WO2022156135A1 - 半导体结构的制造方法及半导体结构 - Google Patents

半导体结构的制造方法及半导体结构 Download PDF

Info

Publication number
WO2022156135A1
WO2022156135A1 PCT/CN2021/101488 CN2021101488W WO2022156135A1 WO 2022156135 A1 WO2022156135 A1 WO 2022156135A1 CN 2021101488 W CN2021101488 W CN 2021101488W WO 2022156135 A1 WO2022156135 A1 WO 2022156135A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor structure
metal wiring
manufacturing
wiring layer
Prior art date
Application number
PCT/CN2021/101488
Other languages
English (en)
French (fr)
Inventor
曹新满
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/442,291 priority Critical patent/US20230059733A1/en
Publication of WO2022156135A1 publication Critical patent/WO2022156135A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4864—Cleaning, e.g. removing of solder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
  • a semiconductor structure is formed on a semiconductor substrate by processes such as photolithography, etching, deposition, etc., for example, dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM), the formed dynamic random access memory usually includes a core.
  • the storage area and the peripheral circuit area wherein the core storage area is used to set up a plurality of memory cells for storing data information, the peripheral circuit area usually includes a plurality of metal wiring layers, and the plurality of metal wiring layers are used to electrically connect with the memory cells. connection, so that the storage unit completes the storage or reading of data information.
  • the conductive substances in the metal wiring layer are easily corroded, which reduces the electrical conductivity of the metal wiring layer, thereby reducing the performance of the semiconductor structure.
  • embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure for preventing corrosion of conductive substances in a metal wiring layer, ensuring the conductivity of the metal wiring layer, and improving the performance of the semiconductor structure.
  • a first aspect of the embodiments of the present application provides a method for manufacturing a semiconductor structure, which includes:
  • a metal wiring layer is formed on the substrate, and the surface of the metal wiring layer has positive charges.
  • a reactive gas is supplied to the metal wiring layer, and the reactive gas is used to neutralize the positive charges.
  • the metal wiring layer after neutralization of the positive charges is cleaned to remove impurities remaining on the metal wiring layer.
  • a second aspect of the embodiments of the present application provides a semiconductor structure including a substrate and a metal wiring layer disposed on the substrate.
  • the metal wiring layer is produced by the manufacturing method of the semiconductor structure as described above.
  • the reactive gas is dissociated, and the electrons generated after the dissociation are neutralized with the positive charges on the surface of the metal wiring layer. reaction, thereby reducing the reaction rate of the metal galvanic cell reaction, thereby avoiding the formation of structural defects in the metal wiring layer after cleaning the metal wiring layer by using the cleaning solution, and improving the performance of the semiconductor structure.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present application
  • FIG. 2 is a flowchart of forming a metal wiring layer on a substrate according to an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of forming a dielectric layer and a conductive layer in the manufacturing method of the semiconductor structure provided by the embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of forming a barrier layer and a transition layer in the manufacturing method of the semiconductor structure provided by the embodiment of the present application;
  • FIG. 5 is a flowchart of forming an isolation trench that penetrates the conductive layer and extends into the dielectric layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 6 is a schematic structural diagram of forming a photoresist layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of forming an isolation trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram one of forming an isolation layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 9 is a second structural schematic diagram of forming an isolation layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of providing a reactive gas to a metal wiring layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 11 is a schematic structural diagram of neutralizing positive charges in the manufacturing method of the semiconductor structure provided by the embodiment of the present application.
  • a dielectric layer and a conductive layer are sequentially formed on the substrate, and the conductive layer is patterned through a patterning process to form a metal wiring. layer, and then the surface of the metal wiring layer needs to be cleaned to remove impurities remaining on the surface of the metal wiring layer.
  • the substrate When forming the metal wiring layer, the substrate is fixed in the etching equipment by electrostatic adsorption, so that the surface of the formed metal wiring layer will carry positive charges.
  • a cleaning process is usually used to neutralize the metal wiring layer. Part of the positive charge on the surface causes the surface of the metal wiring layer to still have positive charges. The positive charge easily reacts with the cleaning solution to corrode the metal wiring layer during the cleaning phase, reducing the electrical conductivity of the metal wiring layer, thereby reducing the performance of the semiconductor structure.
  • embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure.
  • the reactive gas is dissociated, and the electrons generated after the dissociation are connected to the surface of the metal wiring layer.
  • the positive charge of the ions is neutralized, thereby reducing the reaction rate of the metal galvanic cell reaction, thereby avoiding the formation of structural defects in the metal wiring layer after cleaning the metal wiring layer by using the cleaning solution, and improving the performance of the semiconductor structure.
  • This embodiment does not limit the semiconductor structure.
  • the following will take the semiconductor structure as a dynamic random access memory (DRAM) as an example for introduction, but this embodiment is not limited to this, and the semiconductor structure in this embodiment may also be other Structure.
  • DRAM dynamic random access memory
  • an embodiment of the present application provides a method for manufacturing a semiconductor structure, including the following steps:
  • the substrate is used as a supporting part of the semiconductor structure to support other components arranged thereon, wherein the substrate can be made of semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compound and silicon-carbon compound kind.
  • S210 sequentially forming a dielectric layer and a conductive layer on the substrate.
  • an atomic layer deposition process or a chemical vapor deposition process may be used to form a dielectric layer 21 with a certain thickness on the upper surface of the substrate 10 , wherein the material of the dielectric layer 21 may include an insulating material such as silicon nitride, etc.
  • the insulating arrangement between the substrate 10 and the conductive layer 22 is ensured.
  • the material of the conductive layer 22 may include a conductive material such as tungsten to ensure the conductivity of the metal wiring layer.
  • a barrier layer 30 may be formed on the dielectric layer 21 , and the barrier layer 30 can block the conductive material in the conductive layer 22 from penetrating into the dielectric layer 21 .
  • the conductivity of the conductive layer 22 is ensured, thereby improving the yield of the semiconductor structure.
  • the material of the barrier layer 30 may include a conductive material such as titanium nitride. While preventing the penetration between the conductive layer 22 and the dielectric layer 21, it can also realize the electrical connection between the conductive layer 22 and the bit line structure and the peripheral circuit area. connect.
  • a conductive material such as titanium nitride. While preventing the penetration between the conductive layer 22 and the dielectric layer 21, it can also realize the electrical connection between the conductive layer 22 and the bit line structure and the peripheral circuit area. connect.
  • the step of forming the barrier layer on the dielectric layer further includes:
  • a transition layer 40 is formed on the dielectric layer 21. Specifically, an atomic deposition process or a chemical vapor deposition process can be used to form a transition layer 40 with a certain thickness on the dielectric layer 21. The transition layer 40 is used to increase the distance between the dielectric layer 21 and the barrier layer 30. The bonding force between the dielectric layer 21 and the barrier layer 30 is prevented from being separated.
  • the material of the transition layer 40 may include a conductive material such as titanium. While increasing the bonding force between the dielectric layer 21 and the barrier layer 30 , the connection between the conductive layer 22 and the bit line structure and the peripheral circuit area can also be realized. electrical connection.
  • S221 forming a photoresist layer on the side of the conductive layer away from the substrate, the structure of which is shown in FIG. 6 .
  • the photoresist layer 50 can be patterned by means of masking, exposing, developing or etching, etc.
  • a chemical treatment is performed to form a pattern on the photoresist layer 50 , wherein the pattern may include a plurality of opening regions 51 arranged at intervals, and blocking regions between adjacent opening regions 51 .
  • the conductive layer 22 and part of the dielectric layer 21 in the opening region 51 are etched away by using an etching solution or an etching gas to form the isolation trench 60 in the conductive layer 22 and the dielectric layer 21 .
  • a filling layer 70 is formed in the isolation trench 60 and on the surface of the conductive layer 22.
  • a chemical vapor deposition process can be used to form the filling layer 70 in the isolation trench 60, and the filling layer 70 also extends to the outside of the isolation trench 60 and cover the surface of the conductive layer 22 .
  • the filling layer 70 located on the surface of the conductive layer 22 is etched back, and the filling layer 70 located in the isolation trench 60 is reserved, so that the remaining filling layer 70 forms the isolation layer 71 , and the top surface of the isolation layer 71 is It can be lower than the top surface of the conductive layer 20.
  • the entire conductive layer 22 is divided into several conductive strips arranged at intervals through the setting of the isolation layer 71, so as to select some conductive strips and semiconductor structures according to the actual situation.
  • the mid-bit line structure is connected, or all the conductive strips are connected to the bit line structure in the semiconductor structure.
  • the material of the filling layer 70 may include an insulating material such as silicon nitride, so as to realize the insulating arrangement between the conductive layers 22 located on both sides of the isolation trench 60 .
  • the manufacturing method of the semiconductor structure further includes:
  • the photoresist layer 50 is removed, specifically, the photoresist layer 50 on the conductive layer 22 may be removed by cleaning to expose the conductive layer 22 and the isolation trenches 60 so as to form the isolation layer 71 in the isolation trenches 60 .
  • the reaction gas can be supplied into the reaction chamber of the etching equipment, and the positive charge can be neutralized by the reaction gas, wherein the reaction gas can be Oxygen or ozone, the following examples all take oxygen as an example for detailed description.
  • the temperature in the reaction chamber is 20-40 °C
  • the pressure in the reaction chamber is 10-30 mtorr .
  • oxygen is introduced into the reaction chamber as a reaction gas, specifically, oxygen is introduced into the reaction chamber at a rate of 20 to 50 sccm, and the power is 50 to 200 W of radio frequency.
  • oxygen is excited to form negative oxygen ions, positive oxygen ions, free radicals and electrons.
  • the metal wiring layer 20 is fixed in the reaction chamber by electrostatic adsorption.
  • electrons are generated by exciting oxygen gas, and the electrons react with positive charges, thereby reducing the positive charges on the surface of the metal wiring layer.
  • the rate of reaction with electrons in the cleaning solution is slowed down, thereby reducing the reaction rate of the metal galvanic cell reaction, thereby reducing the risk of metal tungsten being corroded, and improving the conductivity of the metal wiring layer and the performance of the semiconductor structure.
  • the negative oxygen ions can form an oxide film with the conductive material on the surface of the metal wiring layer.
  • the oxide film can be a tungsten oxide film formed by negative oxygen ions and metal tungsten, and the oxide film can be used as a protective film. During the cleaning process, the conductive layer can be protected from being damaged, thereby ensuring the performance of the semiconductor structure.
  • a fluorine-containing gas is usually used as the etching gas in the process of etching the dielectric layer and the conductive layer, a polymer containing fluorine ions will be formed on the surface of the metal wiring layer 20.
  • the semiconductor structure needs to be ashed to remove the fluoride ion-containing polymer remaining on the surface of the metal wiring layer due to etching, so as to ensure the subsequent cleaning effect.
  • the ashing process is carried out in the reaction chamber. Therefore, it is necessary to adjust the pressure in the reaction chamber so that the reaction chamber can reach the conditions of the ashing process. For example, adjust the pressure in the reaction chamber to make When it is between 200 and 500 mtorr, it can prevent the pressure in the reaction chamber from being too low to affect the effect of ashing treatment, and at the same time, it can also prevent the pressure in the reaction chamber from being too high and increase the production cost of preparing the semiconductor structure.
  • the temperature in the reaction chamber is 250°C.
  • a certain amount of fluorine-containing gas is introduced into the reaction chamber as the gas for ashing treatment.
  • the semiconductor structure is ashed to remove the fluorine ion-containing polymer remaining on the surface of the metal wiring layer due to etching.
  • the fluorine-containing gas may include CF4, CHF3 or a mixed gas of CF4 and CHF3.
  • the semiconductor structure is cleaned with a cleaning liquid to remove impurities remaining on the metal wiring layer, thereby ensuring the cleanliness of the metal wiring layer.
  • the electrons decomposed by oxygen are used to neutralize the positive charges remaining on the metal wiring layer, which can reduce the amount of positive charges on the metal wiring layer, and the free negative charges between the metal wiring layer and the cleaning solution will not A galvanic cell is formed, thereby reducing corrosion to the metal wiring layer and ensuring the electrical conductivity of the metal wiring layer.
  • oxygen will also decompose negative oxygen ions, and the negative oxygen ions can form a tungsten oxide film with metal tungsten on the surface of the metal wiring layer.
  • the tungsten oxide film can be used as a protective film, which can protect the electrical conductivity during cleaning The layers are not destroyed, thereby ensuring the performance of the semiconductor structure.
  • the embodiments of the present application further provide a semiconductor structure, as shown in FIG. 9 , which includes a substrate 10 and a metal wiring layer 20 disposed on the substrate 10 , wherein the metal wiring layer 20 is the semiconductor structure provided by any of the above embodiments produced by the manufacturing method.
  • the reactive gas dissociates, and the electrons generated after the dissociation undergo a neutralization reaction with the positive charges on the surface of the metal wiring layer, thereby reducing the metal wiring layer.
  • the reaction rate of the galvanic cell reaction further avoids the formation of structural defects after cleaning the metal wiring layer by using the cleaning solution, and improves the performance of the semiconductor structure.
  • the reactive gas can form an oxide film with the conductive material on the surface of the metal wiring layer, and the oxide film can be used as a protective film to protect the conductive layer from being damaged in the subsequent cleaning process, thereby ensuring the performance of the semiconductor structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本申请提供一种半导体结构的制造方法及半导体结构，涉及半导体技术领域，该半导体结构的制造方法包括提供基底；在所述基底上形成金属布线层，所述金属布线层的表面上具有正电荷；向所述金属布线层提供反应气体，该反应气体发生解离，解离后产生的电子与金属布线层表面的正电荷发生中和反应，从而降低了金属原电池反应的反应速率，进而避免了利用清洗液在清洗金属布线层后金属布线层形成结构缺陷，提高了半导体结构的性能。

Description

半导体结构的制造方法及半导体结构
本申请要求于2021年01月25日提交中国专利局、申请号为202110098156.8、申请名称为“半导体结构的制造方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构的制造方法及半导体结构。
背景技术
在半导体制造工艺中，通过光刻、刻蚀、沉积等工艺在半导体基底上形成半导体结构，例如，动态随机存储器((Dynamic Random Access Memory，简称DRAM))，所形成的动态随机存储器通常包括核心存储区和外围电路区，其中，核心存储区用于设置多个存储单元，用于对数据信息进行存储，外围电路区通常包括多个金属布线层，多个金属布线层用于与存储单元电连接，以使得存储单元完成对数据信息的存储或者读取。
但是，在外围电路区的制造过程中，金属布线层中导电物质容易被腐蚀，降低金属布线层的导电能力，进而降低半导体结构的性能。
发明内容
鉴于上述问题，本申请实施例提供一种半导体结构的制造方法及半导体结构，用于防止金属布线层中的导电物质被腐蚀，保证金属布线层的导电能力，进而提高半导体结构的性能。
为了实现上述目的，本申请实施例提供如下技术方案：
本申请实施例的第一方面提供一种半导体结构的制造方法，其包括：
提供基底。
在所述基底上形成金属布线层，所述金属布线层的表面上具有正电荷。
向所述金属布线层提供反应气体，所述反应气体用于中和所述正电荷。
对中和所述正电荷后的所述金属布线层进行清洗，以去除残留在所述金属布线层上的杂质。
本申请实施例的第二方面提供一种半导体结构，其包括基底以及设置在所述基底上的金属布线层。
所述金属布线层通过如上所述的半导体结构的制造方法制得。
本申请实施例所提供的半导体结构的制造方法及半导体结构中，通过向金属布线层提供反应气体，该反应气体发生解离，解离后产生的电子与金属布线层表面的正电荷发生中和反应，从而降低了金属原电池反应的反应速率，进而避免了利用清洗液在清洗金属布线层后金属布线层形成结构缺陷，提高了半导体结构的性能。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的半导体结构的制造方法及半导体结构所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
图1为本申请实施例提供的半导体结构的制造方法的流程图；
图2为本申请实施例提供的在基底上形成金属布线层的流程图；
图3为本申请实施例提供的半导体结构的制造方法中形成介质层和导电层的结构示意图；
图4为本申请实施例提供的半导体结构的制造方法中形成阻挡层和过渡层的结构示意图；
图5为本申请实施例提供的半导体结构的制造方法中形成贯穿导电层并延伸至介质层内的隔离槽的流程图；
图6为本申请实施例提供的半导体结构的制造方法中形成光刻胶层的结构示意图；
图7为本申请实施例提供的半导体结构的制造方法中形成隔离槽的结构示意图；
图8为本申请实施例提供的半导体结构的制造方法中形成隔离层的结 构示意图一；
图9为本申请实施例提供的半导体结构的制造方法中形成隔离层的结构示意图二；
图10为本申请实施例提供的半导体结构的制造方法中向金属布线层提供反应气体的示意图；
图11为本申请实施例提供的半导体结构的制造方法中中和正电荷的结构示意图。
附图标记：
10：基底；
20：金属布线层；
21：介质层；
22：导电层；
30：阻挡层；
40：过渡层；
50：光刻胶层；
51：开口区；
60：隔离槽；
70：填充层；
71：隔离层。
具体实施方式
本公开的发明人在实际工作中发现，在半导体结构的外围电路的制造过程，通常是在基底上依次形成层叠设置的介质层和导电层，通过构图工艺，图形化导电层，以形成金属布线层，之后需要对金属布线层的表面进行清洗，以清除金属布线层表面残留的杂质。
在形成金属布线层时，基底是利用静电吸附的方式固定在刻蚀设备内，致使所形成的金属布线层的表面会携带正电荷，相关技术中，通常会采用清除工艺中和掉金属布线层表面上部分正电荷，致使金属布线层的表面仍然会存在正电荷，该正电荷在清洗阶段容易与清洗液发生反应腐蚀金属布线层，降低金属布线层的导电能力，进而降低半导体结构的性能。
针对上述的技术问题，本申请实施例提供了一种半导体结构的制造方 法及半导体结构，通过向金属布线层提供反应气体，该反应气体发生解离，解离后产生的电子与金属布线层表面的正电荷发生中和反应，从而降低了金属原电池反应的反应速率，进而避免了利用清洗液在清洗金属布线层后金属布线层形成结构缺陷，提高了半导体结构的性能。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存取存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
下面结合图1至图11对半导体结构的制造方法进行介绍。
如图1所示，本申请实施例提供了一种半导体结构的制造方法，包括如下的步骤：
S100：提供基底。
基底作为半导体结构的支撑部件，用于支撑设在其上的其他部件，其中，基底可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
S200：在基底上形成金属布线层，金属布线层的表面上具有正电荷，其工艺流程图如图2所示。
示例性地，S210：在基底上依次形成介质层和导电层。
如图3所示，可以先采用原子层沉积工艺或者化学气相沉积工艺在基底10的上表面上形成一定厚度的介质层21，其中，介质层21的材质可以包括氮化硅等绝缘材质，以保证基底10与导电层22之间的绝缘设置。
然后再利用原子层沉积工艺或者化学气相沉积工艺在基底上形成一定厚度的导电层22，导电层22的材质可以包括钨等导电材质，以保证金属布线层的导电性能。
进一步地，如图4所示，为了避免导电层22中的导电材料渗透至介质层21内，可以在介质层21上形成阻挡层30，阻挡层30能够阻挡导电层 22中的导电材料渗透至介质层内，保证了导电层22的导电性能，进而提高了半导体结构的良率。
示例性地，阻挡层30的材质可以包括氮化钛等导电材质，在阻止导电层22与介质层21之间发生渗透的同时，也可以实现导电层22与位线结构以及外围电路区的电连接。
进一步地，在介质层上形成阻挡层的步骤之前还包括：
于介质层21上形成过渡层40，具体地，可以采用原子沉积工艺或者化学气相沉积工艺在介质层21上形成一定厚度的过渡层40，过渡层40用于增加介质层21和阻挡层30之间的结合力，防止介质层21与阻挡层30之间发生分离。
在本实施例中，过渡层40的材质可以包括钛等导电材质，在增加介质层21和阻挡层30之间的结合力的同时，也可以实现导电层22与位线结构以及外围电路区的电连接。
S220：形成贯穿导电层并延伸至介质层内的隔离槽，其工艺流程图如图5所示。
具体地，S221：在导电层背离基底的一侧上形成光刻胶层，其结构如图6所示。
S222：图形化光刻胶层，以在光刻胶层内形成多个间隔设置的开口区，也就是说，可以通过掩膜、曝光、显影或者蚀刻等方式，对光刻胶层50进行图形化处理，以在光刻胶层50上形成图案，其中图案可以包括多个间隔设置开口区51，以及位于相邻开口区51之间的遮挡区。
S223：去除位于开口内的导电层以及部分介质层，以形成隔离槽，其结构图7所示。
即，利用刻蚀液或者刻蚀气体，蚀刻掉位于开口区51内的导电层22和部分介质层21，以在导电层22和介质层21内形成隔离槽60。
S230：在隔离槽内形成隔离层，隔离层和未被去除的导电层构成金属布线层，其结构如图8和图9所示。
示例性地，如图8所示，在隔离槽60内以及导电层22的表面形成填充层70，具体地，可以采用化学气相沉积工艺在隔离槽60内形成填充层70，填充层70还延伸至隔离槽60外，并覆盖在导电层22的表面。
如图9所示，回刻位于导电层22表面上的填充层70，保留位于隔离槽60内的填充层70，以使被保留的填充层70形成隔离层71，且隔离层71的顶面可以低于导电层20的顶面，本实施例通过隔离层71的设置，将整面的导电层22分割为若干个间隔设置的导电条，以便于根据实际情况，选择部分导电条与半导体结构中位线结构连接，还是全部导电条与半导体结构中的位线结构连接。
在本实施例中，填充层70的材质可以包括氮化硅等绝缘材质，以实现位于隔离槽60两侧的导电层22之间的绝缘设置。
在隔离槽内以及导电层的表面形成填充层的步骤之后，半导体结构的制造方法还包括：
去除光刻胶层50，具体地，可以通过清洗的方式去除位于导电层22上的光刻胶层50，暴露出导电层22和隔离槽60，以便于在隔离槽60内形成隔离层71。
S300：向金属布线层提供反应气体，反应气体用于中和正电荷，其过程如图10和图11所示。
具体地，由于在制造半导体结构时，通常在刻蚀设备的反应腔室内进行，因此，可以向刻蚀设备的反应腔室内提供反应气体，利用反应气体来中和正电荷，其中，反应气体可以为氧气或者臭氧，以下实施例均以氧气为例进行详细的叙述。在此步骤中，需要预先调节反应腔室的温度以及压力，以使反应腔室内具备激发反应气体的条件，例如，反应腔室内的温度为20～40℃，反应腔室内的压力为10～30mtorr。
待反应腔室内满足上述的条件之后，向反应腔室内通入一定量的氧气作为反应气体，具体地，以20～50sccm的速率向反应腔室内通入氧气，并在功率为50～200W的射频源作用下，激发氧气，以使氧气形成负氧离子、正氧离子、自由基以及电子。
如图10所示，由于相关技术中，金属布线层20是通过静电吸附的方式固定在反应腔室内，在静电吸附的过程中，金属布线层的表面的金属钨会失去电子形成带正电的钨离子，如W-ne -＝W n+，在后续清洗金属布线层的过程，正电荷会与清洗液形成原电池反应，致使金属布线层形成缺陷。
本实施例通过激发氧气产生电子，该电子与正电荷发生中和反应，降 低了金属布线层表面的正电荷，如图11所示，由于金属布线层表面的正电荷的量减少，使得正电荷和清洗液中电子反应的速率减慢，从而降低了金属原电池反应的反应速率，进而降低了金属钨被腐蚀的风险，提高了金属布线层的导电能力以及半导体结构的性能。
此外，负氧离子能够与金属布线层表面的导电材料形成氧化物薄膜，示例性地，氧化物薄膜可以为负氧离子与金属钨形成的氧化钨薄膜，氧化物薄膜可以作为保护膜，在后续的清洗过程中可以保护导电层不被破坏，进而保证了半导体结构的性能。
S400：对半导体结构进行灰化处理，去除因刻蚀残留在金属布线层表面的含氟离子的聚合物。
由于在刻蚀介质层和导电层的过程通常是采用含氟的气体作为刻蚀气体，这样在金属布线层20的表面会形成含氟离子的聚合物，为了消除含氟离子的聚合物，通常需要对半导体结构进行灰化处理，以去除因刻蚀残留在金属布线层表面的含氟离子的聚合物，进而保证后续的清洗效果。
在此过程中，灰化处理是在反应腔室内进行的，因此，需要对反应腔室内的压力进行调节，以使反应腔室内达到灰化处理的条件，例如，调节反应腔室内的压力，使之处于200～500mtorr之间，可以防止反应腔室内的压力过低而影响灰化处理的效果，同时，也可以防止反应腔室内的压力过大而增加制备半导体结构的生产成本。
同时，也需要对反应腔室内的温度进行调节，以使反应腔室内达到灰化处理的条件，例如，灰化处理的温度为250℃。
待反应腔室内满足上述的条件之后，向反应腔室内通入一定量的含氟气体作为灰化处理的气体，具体地，以500～3000sccm的速率向反应腔室内通入含氟气体，并在功率为500～800W高频的射频电源的功率下，对半导体结构进行灰化处理，以去除因刻蚀残留在金属布线层表面的含氟离子的聚合物。
在本实施例中含氟气体可以包括CF4、CHF3或者CF4和CHF3的混合气体。
S500：对中和正电荷后的金属布线层进行清洗，以去除残留于金属布线层上的杂质。
示例性地，利用清洗液对半导体结构进行清洗，以去除残留于金属布 线层上的杂质，进而保证金属布线层的清洁度。
由于在上述工艺步骤中，通过氧气分解出来的电子来中和金属布线层上残留的正电荷，可以减少金属布线层上的正电荷的量，金属布线层与清洗液的游离的负电荷不会形成原电池，进而降低了对金属布线层的腐蚀，保证了金属布线层的导电性能。
另外，在上述工艺步骤中，氧气还会分解出来负氧离子，负氧离子能够与金属布线层表面的金属钨形成的氧化钨薄膜，氧化钨薄膜可以作为保护膜，在清洗过程中可以保护导电层不被破坏，进而保证了半导体结构的性能。
本申请实施例还提供了一种半导体结构，如图9所示，其包括基底10以及设置在基底10上的金属布线层20，其中，金属布线层20通过上述任一实施例提供的半导体结构的制造方法制得。
本实施例在制备金属布线层的过程，通过向金属布线层提供反应气体，该反应气体发生解离，解离后产生的电子与金属布线层表面的正电荷发生中和反应，从而降低了金属原电池反应的反应速率进而避免了利用清洗液在清洗金属布线层后形成结构缺陷，提高了半导体结构的性能。
另外，该反应气体能够与金属布线层表面的导电材料形成氧化物薄膜，氧化物薄膜可以作为保护膜，在后续的清洗过程中可以保护导电层不被破坏，进而保证了半导体结构的性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的 普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种半导体结构的制造方法，其特征在于，包括如下步骤：
    提供基底；
    在所述基底上形成金属布线层，所述金属布线层的表面上具有正电荷；
    向所述金属布线层提供反应气体，所述反应气体用于中和所述正电荷；
    对中和所述正电荷后的所述金属布线层进行清洗，以去除残留在所述金属布线层上的杂质。
  2. 根据权利要求1所述的半导体结构的制造方法，其特征在于，向所述金属布线层提供反应气体，所述反应气体用于中和所述正电荷的步骤包括：
    提供氧气作为所述反应气体；
    激发所述氧气，形成负氧离子、正氧离子、自由基以及电子，所述电子中和所述正电荷，所述负氧离子与所述金属布线层表面的导电材料形成氧化物薄膜。
  3. 根据权利要求2所述的半导体结构的制造方法，其特征在于，在所述基底上形成金属布线层的步骤包括：
    在所述基底上依次形成介质层和导电层；
    形成贯穿所述导电层并延伸至所述介质层内的隔离槽；
    在所述隔离槽内形成隔离层，所述隔离层和未被去除的所述导电层构成所述金属布线层。
  4. 根据权利要求3所述的半导体结构的制造方法，其特征在于，形成贯穿所述导电层并延伸至所述介质层内的隔离槽的步骤包括：
    在所述导电层上形成光刻胶层；
    图形化所述光刻胶层，以在所述光刻胶层内形成多个间隔设置的开口区；
    去除位于所述开口内的所述导电层以及部分所述介质层，以形成所述隔离槽。
  5. 根据权利要求4所述的半导体结构的制造方法，其特征在于，在所述隔离槽内形成隔离层的步骤包括：
    在所述隔离槽内以及所述导电层的表面形成填充层；
    去除位于所述导电层表面上的填充层，以形成所述隔离层。
  6. 根据权利要求5所述的半导体结构的制造方法，其特征在于，在去除位于所述开口内的所述导电层以及部分所述介质层的步骤之前，在所述隔离槽内以及所述导电层的表面形成填充层的步骤之后，所述方法还包括：
    去除光刻胶层，以暴露出所述导电层和所述隔离槽。
  7. 根据权利要求6所述的半导体结构的制造方法，其特征在于，在所述基底上依次形成介质层和导电层的步骤包括：
    于所述介质层上形成阻挡层，所述阻挡层用于阻挡所述导电层中导电材料渗透至所述介质层内。
  8. 根据权利要求7所述的半导体结构的制造方法，其特征在于，所述阻挡层的材质为氮化钛。
  9. 根据权利要求8所述的半导体结构的制造方法，其特征在于，于所述介质层上形成阻挡层的步骤之前还包括：
    于所述介质层上形成过渡层，所述过渡层用于增加所述介质层和所述阻挡层的结合力。
  10. 根据权利要求9所述的半导体结构的制造方法，其特征在于，所述过渡层的材质为钛。
  11. 根据权利要求1所述的半导体结构的制造方法，其特征在于，对中和所述正电荷后的所述金属布线层进行清洗，以去除残留于所述金属布线层上的杂质的步骤包括：
    通过清洗液对所述半导体结构进行清洗，以去除残留于所述金属布线层上的杂质。
  12. 根据权利要求11所述的半导体结构的制造方法，其特征在于，在通过清洗液对所述半导体结构进行清洗的步骤之前，向所述金属布线层提供反应气体的步骤之后，所述方法还包括：
    对所述半导体结构进行灰化处理，去除因刻蚀残留在所述金属布线层表面的含氟离子的聚合物。
  13. 根据权利要求12所述的半导体结构的制造方法，其特征在于，所述灰化处理的温度为250℃，所述灰化处理的高频的射频电源的功率为500～800W。
  14. 根据权利要求12所述的半导体结构的制造方法，其特征在于，所 述灰化处理使用的气体为含氟气体，所述含氟气体的流量为500～3000sccm，所述灰化处理在反应腔室中进行，所述反应腔室的压力为200～500mtorr。
  15. 根据权利要求3所述的半导体结构的制造方法，其特征在于，所述导电层的材质为钨。
  16. 一种半导体结构，其特征在于，包括基底以及设置在所述基底上的金属布线层；
    所述金属布线层通过如权利要求1-15任一项所述的半导体结构的制造方法制得。
PCT/CN2021/101488 2021-01-25 2021-06-22 半导体结构的制造方法及半导体结构 WO2022156135A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/442,291 US20230059733A1 (en) 2021-01-25 2021-06-22 Method for manufacturing semiconductor structure and semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110098156.8A CN112908861B (zh) 2021-01-25 2021-01-25 半导体结构的制造方法及半导体结构
CN202110098156.8 2021-01-25

Publications (1)

Publication Number Publication Date
WO2022156135A1 true WO2022156135A1 (zh) 2022-07-28

Family

ID=76119775

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/101488 WO2022156135A1 (zh) 2021-01-25 2021-06-22 半导体结构的制造方法及半导体结构

Country Status (3)

Country Link
US (1) US20230059733A1 (zh)
CN (1) CN112908861B (zh)
WO (1) WO2022156135A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112908861B (zh) * 2021-01-25 2022-03-08 长鑫存储技术有限公司 半导体结构的制造方法及半导体结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101207046A (zh) * 2006-12-18 2008-06-25 中芯国际集成电路制造(上海)有限公司 凸点的形成方法
US20080226824A1 (en) * 2007-03-13 2008-09-18 Stephen Mazur Topographically selective oxidation
CN103730351A (zh) * 2014-01-07 2014-04-16 上海华虹宏力半导体制造有限公司 刻蚀后的灰化方法及磁传感器的形成方法
CN106373919A (zh) * 2015-07-20 2017-02-01 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
CN112908861A (zh) * 2021-01-25 2021-06-04 长鑫存储技术有限公司 半导体结构的制造方法及半导体结构

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6132564A (en) * 1997-11-17 2000-10-17 Tokyo Electron Limited In-situ pre-metallization clean and metallization of semiconductor wafers
JP4033957B2 (ja) * 1997-12-04 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
US6093658A (en) * 1997-12-22 2000-07-25 Philips Electronics North America Corporation Method for making reliable interconnect structures
JP3536649B2 (ja) * 1998-02-20 2004-06-14 信越半導体株式会社 半導体ウエーハ中の重金属不純物を除去する方法およびこの工程を有する半導体ウエーハの製造方法
US6143653A (en) * 1998-10-04 2000-11-07 Promos Technologies, Inc. Method of forming tungsten interconnect with tungsten oxidation to prevent tungsten loss
KR20010004997A (ko) * 1999-06-30 2001-01-15 김영환 반도체 소자의 금속 배선 형성 방법
JP3686325B2 (ja) * 2000-10-26 2005-08-24 松下電器産業株式会社 半導体装置及びその製造方法
DE10203838B4 (de) * 2002-01-31 2006-12-28 Infineon Technologies Ag Fluorhaltiger Fotoresist mit Reaktionsankern für eine chemische Nachverstärkung und verbesserten Copolymerisationseigenschaften
JP2005183738A (ja) * 2003-12-19 2005-07-07 Sharp Corp 化学機械研磨方法及び化学機械研磨装置
KR20060077837A (ko) * 2004-12-31 2006-07-05 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선층 형성 방법
WO2006097977A1 (ja) * 2005-03-11 2006-09-21 Fujitsu Limited 半導体装置及びその製造方法
DE102005046976B4 (de) * 2005-09-30 2011-12-08 Advanced Micro Devices, Inc. Verfahren zur Herstellung einer Wolframverbindungsstruktur mit verbesserter Seitenwandbedeckung der Barrierenschicht
CN101330035B (zh) * 2007-06-18 2010-05-19 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构及其制造方法
JP5231977B2 (ja) * 2008-12-25 2013-07-10 国立大学法人名古屋大学 金属ドットの製造方法およびそれを用いた半導体メモリの製造方法
CN108701645B (zh) * 2016-03-30 2023-10-10 太浩研究有限公司 减成图案化的互连下方的自对准通孔
US11189499B2 (en) * 2019-03-28 2021-11-30 Tokyo Electron Limited Atomic layer etch (ALE) of tungsten or other metal layers
CN112530773B (zh) * 2020-11-27 2023-11-14 北京北方华创微电子装备有限公司 半导体工艺设备
US20240057312A1 (en) * 2022-08-09 2024-02-15 Changxin Memory Technologies, Inc. Array structure, semiconductor structure, and method for manufacturing semiconductor structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101207046A (zh) * 2006-12-18 2008-06-25 中芯国际集成电路制造(上海)有限公司 凸点的形成方法
US20080226824A1 (en) * 2007-03-13 2008-09-18 Stephen Mazur Topographically selective oxidation
CN103730351A (zh) * 2014-01-07 2014-04-16 上海华虹宏力半导体制造有限公司 刻蚀后的灰化方法及磁传感器的形成方法
CN106373919A (zh) * 2015-07-20 2017-02-01 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
CN112908861A (zh) * 2021-01-25 2021-06-04 长鑫存储技术有限公司 半导体结构的制造方法及半导体结构

Also Published As

Publication number Publication date
CN112908861A (zh) 2021-06-04
US20230059733A1 (en) 2023-02-23
CN112908861B (zh) 2022-03-08

Similar Documents

Publication Publication Date Title
TWI235484B (en) Flash memory cell and method of manufacturing the same
CN100541718C (zh) 形成半导体器件精细图形的方法及用其形成接触的方法
TWI251296B (en) Method for fabricating semiconductor device capable of preventing damage by wet cleaning process
KR100505044B1 (ko) 세정액 및 이를 이용한 반도체 장치의 세정방법
WO2022156135A1 (zh) 半导体结构的制造方法及半导体结构
JPH04250623A (ja) ドライエッチング方法
KR20060131519A (ko) 반도체 구조물의 처리 방법 및 이를 이용한 반도체커패시터의 제조 방법
US6784068B2 (en) Capacitor fabrication method
CN109659222B (zh) 半导体装置的形成方法
JP2006339616A (ja) キャパシタの製造方法
KR100489657B1 (ko) 반도체 장치의 패턴 형성 방법 및 이를 이용한 반도체장치의 제조방법
KR100505175B1 (ko) 규화 루테늄 처리방법
KR100799129B1 (ko) 반도체 메모리 소자의 캐패시터 제조방법
US20030045113A1 (en) Fabrication method of semiconductor integrated circuit device
KR20060133606A (ko) 콘택홀 세정방법 및 이를 이용한 반도체 소자의 제조방법
KR100666380B1 (ko) 포토레지스트 제거방법 및 이를 이용한 반도체 소자의 제조방법.
US7052956B2 (en) Method for forming capacitor of semiconductor device
US20110189828A1 (en) Method for forming silicon layer and method for manufacturing semiconductor device
US20230043874A1 (en) Semiconductor structure and manufacturing method thereof
KR20130037519A (ko) 캐패시터 및 그 제조 방법
US7651907B2 (en) Method for fabricating semiconductor device
JP2003332465A (ja) 半導体メモリデバイスの製造方法
KR100567068B1 (ko) 반도체소자의 제조방법
KR100507364B1 (ko) 반도체소자의 캐패시터 제조방법
CN104051322A (zh) 一种制作半导体器件的方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21920516

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21920516

Country of ref document: EP

Kind code of ref document: A1