WO2022151717A1 - 封装后的内存修复方法及装置、存储介质、电子设备 - Google Patents

封装后的内存修复方法及装置、存储介质、电子设备 Download PDF

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WO2022151717A1
WO2022151717A1 PCT/CN2021/110385 CN2021110385W WO2022151717A1 WO 2022151717 A1 WO2022151717 A1 WO 2022151717A1 CN 2021110385 W CN2021110385 W CN 2021110385W WO 2022151717 A1 WO2022151717 A1 WO 2022151717A1
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memory
failed
lines
address
failure information
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PCT/CN2021/110385
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English (en)
French (fr)
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瞿振林
张文喜
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长鑫存储技术有限公司
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Priority to US17/669,538 priority Critical patent/US20220223222A1/en
Publication of WO2022151717A1 publication Critical patent/WO2022151717A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation

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  • the present disclosure relates to the technical field of integrated circuits, and in particular, to a packaged memory repair method and device, a computer-readable storage medium, and an electronic device.
  • a computer system generally consists of five parts: a processor, a memory, an input device, an output device, and a bus.
  • the memory is used to store the instructions and data required for the processor to run.
  • Memory is generally implemented with dynamic random access memory (DRAM) of semiconductor technology.
  • DRAM dynamic random access memory
  • DRAM typically includes one or more arrays of memory cells, each array of memory cells including memory cells arranged in a matrix of rows and columns. DRAMs also typically include redundant memory cells that can be used to functionally replace failed memory cells in an array of memory cells.
  • a method for repairing a packaged memory includes: during a memory test process, writing failure information of the memory into an SPD, where the failure information includes a failure address; After the device is powered on, it reads the failed address from the SPD, and determines the number of failed lines where the failed address is located; when the number of the failed lines is less than or equal to the number of redundant lines, the redundant line is used. The remaining lines repair the failed lines; when the number of the failed lines is greater than the number of the redundant lines, the failure information is loaded into the register.
  • an encapsulated memory repair device includes: a writing module for writing failure information of the memory into an SPD during a memory test process, and the failure The information includes a failed address; a reading module is used to read the failed address from the SPD after the device is turned on, and determine the number of failed lines where the failed address is located; the first repair module is used to When the number of the failed lines is less than or equal to the number of redundant lines, use the redundant lines to repair the failed lines; the second repair module is used for when the number of the failed lines is greater than the number of the redundant lines When the number of failures is reached, the failure information is loaded into the register.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above-mentioned encapsulated memory repair method is implemented.
  • an electronic device comprising: a processor; and a memory for storing one or more programs that, when executed by the processor, cause the processor to Implement the above encapsulated memory repair method.
  • the packaged memory repair method and device, computer-readable storage medium, and electronic device in the exemplary embodiments of the present disclosure on the one hand, by writing the invalid address of the memory into the SPD, after the device is powered on, it can directly access the SPD from the SPD. Read the failed address in the middle of the system, and determine the number of failed lines, repair the failed line according to the number of failed lines, or load the failure information into the register, so that it can be called directly when it needs to be used, thus realizing the failure address. all fixes.
  • the failure information during the memory test process, and repairing the failed address when the machine is turned on, a method of repairing the failed address from the software level is realized, thus providing an implementation for the repair of the memory after encapsulation.
  • the solution reduces the failure rate of the memory and prolongs the service life of the memory.
  • FIG. 1 schematically shows a block diagram of a post-package repair control circuit memory system according to an exemplary embodiment of the present disclosure
  • FIG. 2 schematically shows a schematic structural diagram of an integrated circuit according to an exemplary embodiment of the present disclosure
  • FIG. 3 schematically shows a flow chart of steps of a method for repairing a memory after encapsulation according to an exemplary embodiment of the present disclosure
  • FIG. 4 schematically shows a schematic diagram of a memory repair process after encapsulation according to an exemplary embodiment of the present disclosure
  • FIG. 5 schematically shows a block diagram of a packaged memory repair apparatus according to an exemplary embodiment of the present disclosure
  • FIG. 6 schematically shows a block diagram of an electronic device in an exemplary embodiment according to the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • a typical dynamic random access memory chip has as many as 64 million memory cells, which can be arranged in a main array in rows and columns for easy search by word and bit lines. site.
  • a chip 100 generally includes a normal cell area 110 and a spare cell area 120 .
  • the normal cell area 110 contains many cells, and the normal cell area Region 110 includes two orthogonal lines: word lines 111 and bit lines 112, wherein word lines 111 are column lines and bit lines 112 are row lines.
  • the chip 100 is also provided with a spare unit area 120 including spare units.
  • the spare unit area 120 includes two orthogonal straight lines: the spare word line 121 (Redundancy Word-Line, RWL) and a spare bit line 122 (Redundancy Bit-Line, RBL), wherein the spare word line 121 is a column line for repairing the failed address on the word line 111; the spare bit line 122 is a row line for repairing on the bit line 112 the invalid address.
  • the spare word line 121 is a column line for repairing the failed address on the word line 111
  • the spare bit line 122 is a row line for repairing on the bit line 112 the invalid address.
  • the present exemplary embodiment provides a method for repairing memory after encapsulation.
  • FIG. 1 a block diagram of a post-package repair control circuit memory system according to an exemplary embodiment of the present disclosure is shown.
  • the memory system 200 performs at least a write operation and a read operation in response to various input/output (I/O) requests received from the host 50 .
  • Memory system 200 generally includes memory controller 201 and memory device 202 .
  • the host 50 may be an electronic device, for example, a computer, a laptop, a tablet, a smart phone, a smart TV, and the like. Host 50 may access memory system 200 in conjunction with execution of one or more applications 52 running one or more operating systems 51 .
  • memory system 200 may provide post-package repair commands and associated fail addresses from memory controller 201 to memory device 202 .
  • the repair process includes replacing the failed portion with redundant resources.
  • the method of replacing the failed part with redundant resources is called PPR (Post Package Repair) method, which includes hPPR (hard Post Package Repair, repair after hard packaging) and sPPR (soft Post Package Repair, repair after soft packaging) .
  • Post-package soft repair sPPR is a quick but temporary method to repair elements in the memory array, while post-package hard repair hPPR takes longer, but it is a permanent repair of elements in the memory array.
  • FIG. 3 schematically shows a flow chart of steps of a method for repairing a memory after encapsulation according to some embodiments of the present disclosure.
  • the encapsulated memory repair method may include the following steps:
  • Step S310 in the memory test process, write the failure information of the memory into SPD (Serial Presence Detect, serial detection), and the failure information includes the failure address;
  • SPD Serial Presence Detect, serial detection
  • Step S320 after the device is powered on, read the failed address from the SPD, and determine the number of failed lines where the failed address is located;
  • Step S330 when the number of failed lines is less than or equal to the number of redundant lines, use redundant lines to repair the failed lines;
  • Step S340 when the number of failed lines is greater than the number of redundant lines, load the failure information into the register.
  • the failed address of the memory into the SPD by writing the failed address of the memory into the SPD, after the device is powered on, the failed address can be directly read from the SPD, and the number of failed lines can be determined, Repair the failed lines according to the number of failed lines, or load the failure information into the register, so that it can be called directly when it needs to be used, thus realizing the process of repairing all the failed addresses.
  • the failure information during the memory test process and repairing the failed address when the machine is turned on, a method of repairing the failed address from the software level is realized, thus providing an implementation for the repair of the memory after encapsulation.
  • the solution reduces the failure rate of the memory and prolongs the service life of the memory.
  • step S310 during the memory test process, the failure information of the memory is written into the SPD, and the failure information includes the failure address.
  • SPD is a set of configuration information about memory modules, such as the number of P-Banks (Physical Bank, physical layer), the number of row addresses/column addresses, bit width, various main operation timings, etc. These information are stored in a capacity It is a 256-byte EEPROM (Electrically Erasable Programmable Read Only Memory), that is, the timing information in the SPD is written by the module manufacturer according to the characteristics of the memory chip used and written to the EEPROM , the EEPROM is stored in the memory. That is, the failure information can be written into the SPD of the EEPROM.
  • P-Banks Physical Bank, physical layer
  • EEPROM Electrical Erasable Programmable Read Only Memory
  • EEPROM The main purpose of EEPROM is to assist the Northbridge chip to accurately adjust the physical/timing parameters of the memory to achieve the best use effect. If the memory setting option is set to "By SPD" in the BIOS (Basic Input Output System). Then when starting up, the North Bridge will automatically configure the corresponding memory timing and control registers according to the parameter information in the SPD, so as to avoid faults caused by human adjustment errors.
  • BIOS Basic Input Output System
  • the memory test is first performed. This process is completed before the memory module leaves the factory.
  • the memory manufacturer uses its test software to realize the memory read and write test. And write its failure information into the SPD of the memory, as shown in Table 1, the definition of SPD is 512Kb.
  • Byte (byte) 384 to 511 is defined by the user, and the content defined from Byte384 is shown in Table 2.
  • the invalid addresses are written down in sequence according to this content format, as shown in Table 2.
  • Byte information 384 The location and rank of the first failed particle in the memory stick 385 Bank/Bank Group corresponding to the first failed particle in the memory module 396 The row address corresponding to the first failed particle in the memory module 397 The column address of the first failed chip in the memory module 398 The position and rank of the second failed particle in the memory stick 399 Bank/Bank Group corresponding to the second failed particle in the memory module 400 The row address corresponding to the second failed particle in the memory module 401 The column address of the second failed chip in the memory module
  • the failure information such as the failure position of all failed particles, the Rank of the failed particles, the Bank/Bank Group (storage bank group), the row address and the column address can be written into the user-defined word of the memory.
  • Rank refers to the memory block on the memory module; the array used for addressing in the memory chip is called the bank of the memory chip.
  • the memory information may be written into the user-defined bytes in the order of the failure information in Table 2, and may also be written in another order, which is not limited in this exemplary embodiment.
  • step S320 after the device is powered on, the failed address is read from the SPD, and the number of failed lines where the failed address is located is determined.
  • the CPU Central Processing Unit, central processing unit
  • the above-mentioned determining the number of the failed lines where the failed addresses are located may include: determining the number of the failed lines in the same memory bank group. The number of dead lines where the dead address is located.
  • step S330 when the number of failed lines is less than or equal to the number of redundant lines, the redundant lines are used to repair the failed lines; in step S340, when the number of failed lines is greater than the number of redundant lines, Information is loaded into registers.
  • a specific repair scheme is determined by comparing the number of failed lines and the number of redundant lines. In the case where the number of failed lines is less than or equal to the number of redundant lines, a pair of redundant lines can be directly used Repair the faulty line.
  • the repair here may be hPPR or sPPR repair.
  • the hPPR command is used for repair; when the failed line is stored in the volatile memory, the sPPR command is used for repair.
  • hPPR belongs to the method of permanent repair. After repairing with hPPR, the redundant line permanently replaces the failed line.
  • the failure information is directly loaded into the register to temporarily store the failure information. So that in the process of reading and writing access to the memory, if the invalid address is accessed, the information corresponding to the invalid address can be directly read and written from the register. Avoid failure due to direct access to invalid addresses.
  • the memory can be repaired after each boot, so as to implement a method for repairing from the software level, so that the user can repair the memory during the use of the memory. , reduce the failure rate during the use of the memory, so as to improve the user experience.
  • step S401 a memory test is performed to obtain an invalid address of the memory;
  • step S402 the invalid address is written into the SPD;
  • step S403, the device is powered on;
  • step S404 the invalid address is read from the SPD;
  • step S405, the judgment condition is entered, that is, the invalid line where the invalid address is located is judged Whether the number of redundant lines is less than or equal to the number of redundant lines; if the judgment condition is met, step S406 is executed, and PPR is used to repair; if the judgment condition is not met, step S407 is executed, and the failure information is loaded into the register; complete all invalid addresses
  • step S408 is executed again to start the system normally, and in the process of reading and writing access to the memory, if the invalid address is accessed, the information corresponding to the invalid address is directly read and written
  • the packaged memory repairing device 500 may include: a writing module 510 , a reading module 520 , a first repairing module 530 and a second repairing module 540 , wherein,
  • the writing module 510 is configured to write the failure information of the memory into the SPD during the memory test process, where the failure information includes the failure address.
  • the reading module 520 is configured to read the failed address from the SPD after the device is powered on, and determine the number of failed lines where the failed address is located.
  • the first repairing module 530 is configured to use redundant lines to repair the failed lines when the number of failed lines is less than or equal to the number of redundant lines.
  • the second repair module 540 is configured to load the failure information into the register when the number of failure lines is greater than the number of redundant lines.
  • the writing module 510 can write the failure information such as the failure positions of all failed particles, the Rank of the failed particles, the Bank/Bank Group (memory bank group), the row address and the column address in the memory module into the memory module. in user-defined bytes of memory. The above memory information can be sequentially written into user-defined bytes.
  • the reading module 520 is used to first read the SPD in the EEPROM after the system of the device is powered on, and determine the number of failed lines where the failed address is located according to the failed address recorded in the SPD, and according to the number of different failed lines to identify different repair options.
  • the above-mentioned determining the number of the failed lines where the failed addresses are located may include: determining the number of the failed lines in the same memory bank group. The number of dead lines where the dead address is located.
  • the first repair module 530 or the second repair module 540 is used to repair.
  • the first repair module 530 directly uses redundant lines to repair the failed lines.
  • the repair here may be hPPR or sPPR repair.
  • the second repair module 540 directly loads the failure information into the register to temporarily store the failure information. So that in the process of reading and writing access to the memory, if the invalid address is accessed, the information corresponding to the invalid address can be directly read and written from the register. Avoid failure due to direct access to invalid addresses.
  • the memory can be repaired after each boot, so as to realize a software-level operation
  • the repair method is convenient for the user to repair the memory in the process of using the memory, reducing the failure rate in the process of using the memory, so as to improve the user experience.
  • modules or units of the packaged memory repair apparatus are mentioned in the above detailed description, such division is not mandatory. Indeed, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units to be embodied.
  • an electronic device capable of implementing the above method is also provided.
  • aspects of the present invention may be implemented as a system, method or program product. Therefore, various aspects of the present invention can be embodied in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, which may be collectively referred to herein as implementations "circuit", “module” or "system”.
  • FIG. 6 An electronic device 600 according to this embodiment of the present invention is described below with reference to FIG. 6 .
  • the electronic device 600 shown in FIG. 6 is only an example, and should not impose any limitation on the function and scope of use of the embodiments of the present invention.
  • electronic device 600 takes the form of a general-purpose computing device.
  • Components of the electronic device 600 may include, but are not limited to: the above-mentioned at least one processing unit 610 , the above-mentioned at least one storage unit 620 , a bus 630 connecting different system components (including the storage unit 620 and the processing unit 610 ), and a display unit 640 .
  • the storage unit 620 stores program codes, which can be executed by the processing unit 610, so that the processing unit 610 executes various examples according to the present invention described in the above-mentioned “Exemplary Methods” section of this specification steps of sexual implementation.
  • the processing unit 610 may perform step S310 as shown in FIG.
  • step S320 after the device is powered on, Read the failed address from the SPD, and determine the number of failed lines where the failed address is located; Step S330, when the number of failed lines is less than or equal to the number of redundant lines, use redundant lines to repair the failed line; Step S340, When the number of failed lines is greater than the number of redundant lines, the failure information is loaded into the register.
  • the storage unit 620 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 6201 and/or a cache storage unit 6202 , and may further include a read only storage unit (ROM) 6203 .
  • RAM random access storage unit
  • ROM read only storage unit
  • the storage unit 620 may also include a program/utility 6204 having a set (at least one) of program modules 6205 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, An implementation of a network environment may be included in each or some combination of these examples.
  • the bus 630 may be representative of one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local area using any of a variety of bus structures bus.
  • the electronic device 600 may also communicate with one or more external devices 670 (eg, keyboards, pointing devices, Bluetooth devices, etc.), with one or more devices that enable a user to interact with the electronic device 600, and/or with Any device (eg, router, modem, etc.) that enables the electronic device 600 to communicate with one or more other computing devices. Such communication may occur through input/output (I/O) interface 650 . Also, the electronic device 600 may communicate with one or more networks (eg, a local area network (LAN), a wide area network (WAN), and/or a public network such as the Internet) through a network adapter 660 . As shown, network adapter 660 communicates with other modules of electronic device 600 via bus 630 . It should be appreciated that, although not shown, other hardware and/or software modules may be used in conjunction with electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives and data backup storage systems.
  • the exemplary embodiments described herein may be implemented by software, or may be implemented by software combined with necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure may be embodied in the form of software products, and the software products may be stored in a non-volatile storage medium (which may be CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to cause a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to an embodiment of the present disclosure.
  • a computing device which may be a personal computer, a server, a terminal device, or a network device, etc.
  • a computer-readable storage medium on which a program product capable of implementing the above-described method of the present specification is stored.
  • aspects of the present invention can also be implemented in the form of a program product comprising program code for enabling the program product to run on a terminal device The terminal device performs the steps according to various exemplary embodiments of the present invention described in the "Example Method" section above in this specification.
  • the program product for implementing the above method according to an embodiment of the present invention may adopt a portable compact disc read only memory (CD-ROM), and include program codes, and may be executed on a terminal device such as a personal computer.
  • a readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
  • the program product may employ any combination of one or more readable media.
  • the readable medium may be a readable signal medium or a readable storage medium.
  • the readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or a combination of any of the above. More specific examples (non-exhaustive list) of readable storage media include: electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, portable compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
  • a computer readable signal medium may include a propagated data signal in baseband or as part of a carrier wave with readable program code embodied thereon. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a readable signal medium can also be any readable medium, other than a readable storage medium, that can transmit, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
  • Program code embodied on a readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
  • Program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages—such as Java, C++, etc., as well as conventional procedural Programming Language - such as the "C" language or similar programming language.
  • the program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server execute on.
  • the remote computing device may be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (eg, using an Internet service provider business via an Internet connection).
  • LAN local area network
  • WAN wide area network
  • an external computing device eg, using an Internet service provider business via an Internet connection

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Abstract

一种封装后的内存修复方法及装置、计算机可读存储介质、电子设备，所述方法包括：在内存测试过程中，将所述内存的失效信息写入到SPD中，所述失效信息包括失效地址；在设备开机后，从所述SPD中读取所述失效地址，并确定所述失效地址所在的失效线路的数量；在所述失效线路的数量小于或等于冗余线路的数量时，使用所述冗余线路对所述失效线路进行修复；在所述失效线路的数量大于所述冗余线路的数量时，将所述失效信息加载到寄存器中。实现了对失效地址的全部修复。

Description

封装后的内存修复方法及装置、存储介质、电子设备
相关申请的交叉引用
本公开要求于2021年01月12日提交的申请号为202110033504.3名称为“封装后的内存修复方法及装置、存储介质、电子设备”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种封装后的内存修复方法及装置、计算机可读存储介质、电子设备。
背景技术
计算机系统一般由处理器、内存、输入设备、输出设备和总线五部分组成，其中，内存用来保存处理器运行所需的指令和数据。内存一般是用半导体工艺的动态随机存储器(Dynamic Random Access Memory，DRAM)实现的。
DRAM通常包括一个或多个存储单元陈列，每个存储单元阵列包括以行和列的矩阵布置的存储单元。DRAM通常还包括冗余存储单元，其可用于在功能上替换存储单元阵列中的失效存储单元。
然而，由于在封装后，每个存储体组中可用的冗余存储单元有限，无法实现失效存储单元的全部修复操作。
发明内容
根据本公开的一方面，提供一种封装后的内存修复方法，所述方法包括：在内存测试过程中，将所述内存的失效信息写入到SPD中，所述失效信息包括失效地址；在设备开机后，从所述SPD中读取所述失效地址，并确定所述失效地址所在的失效线路的数量；在所述失效线路的数量小于或等于冗余线路的数量时，使用所述冗余线路对所述失效线路进行修复；在所述失效线路的数量大于所述冗余线路的数量时，将所述失效信息加载到寄存器中。
根据本公开的一方面，提供一种封装后的内存修复装置，所述装置包括：写入模块，用于在内存测试过程中，将所述内存的失效信息写入到SPD中，所述失效信息包括失效地址；读取模块，用于在设备开机后，从所述SPD中读取所述失效地址，并确定所述失效地址所在的失效线路的数量；第一修复模块，用于在所述失效线路的数量小于或等于冗余线路的数量时，使用所述冗余线路对所述失效线路进行修复；第二修复模块，用于在所述失效线路的数量大于所述冗余线路的数量时，将所述失效信息加载到寄存器中。
根据本公开的一方面，提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现上述的封装后的内存修复方法。
根据本公开的一方面，提供一种电子设备，包括：处理器；存储器，用于存储一个或多个程序，当所述一个或多个程序被所述处理器执行时，使得所述处理器实现上述的封装后的内存修复方法。
本公开提供的技术方案可以包括以下有益效果：
本公开的示例性实施例中的封装后的内存修复方法及装置、计算机可读存储介质、电子设备，一方面，通过将内存的失效地址写入到SPD中，设备开机后，可以直接从SPD中读取失效地址，并确定失效线路的数量，根据失效线路的数量对失效线路进行修复，或者将失效信息加载到寄存器中，以在需要使用的时候，可以直接调用，从而实现了对失效地址的全部修复。另一方面，通过在内存测试过程中，记录失效信息，并在开机的时候对失效地址进行修复，实现了一种从软件的层面修复失效地址，从而为内存的封装后修复提供了一种实现方案，减少了内存的故障率，延长了内存的使用寿命。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性示出了根据本公开的示例性实施方式的一种封装后修复控制电路存储器系统的框图；
图2示意性示出了根据本公开的示例性实施方式的一种集成电路的结构示意图；
图3示意性示出了根据本公开的示例性实施方式的封装后的内存修复方法的步骤流程图；
图4示意性示出了根据本公开的示例性实施方式的封装后的内存修复流程示意图；
图5示意性示出了根据本公开的示例性实施方式的一种封装后的内存修复装置的框图；
图6示意性示出了根据本公开的示例性实施方式中的电子设备的模块示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相 同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成区分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成区分/等之外还可存在另外的要素/组成区分/等。
在一个芯片中，通常包含有多个单元。举例来说，一个典型的动态随机存取存储器芯片有多达6千4百万个存储单元，这些存储单元可以按行和列的方式排列成主阵列，以便于通过字线和位线来寻址。
在典型的动态随机存取存储器芯片的制造过程中，可能会发生主阵列中一百万甚至数百万个单元存在着缺陷，即所谓的失效地址。为了提高芯片的成品率，通常会在芯片上制作冗余线路，这些冗余线路可以替代有缺陷的失效地址所在的失效线路，从而旁路这些有缺陷的失效地址并使存储电路可以正常使用。
参照图1，示出了根据本公开的示例性实施方式的一个芯片的结构示意图，一个芯片100通常包括正常单元区110和备用单元区120，正常单元区110中含有较多的单元，正常单元区110包括两种正交的线路：字线111和位线112，其中，字线111为列线路，位线112为行线路。同时，在正常单元区110之外，芯片100上还设置有包含备用单元的备用单元区120，备用单元区120包括两种正交的笔直线路：备用字线121(Redundancy Word-Line，RWL)和备用位线122(Redundancy Bit-Line，RBL)，其中，备用字线121为列线路，用于修补字线111上的失效地址；备用位线122为行线路，用于修补位线112上的失效地址。
然而，对于封装后的存储器，当存储器中的失效线路多于冗余线路的时候，存在着无法修复失效线路而导致无法读取失效地址的信息，导致程序无法正常运行的情况发生。基于此，本示例性实施方式中提供了一种封装后的内存修复方法。
参照图2，示出了根据本公开的示例性实施方式的一种封装后修复控制电路存储器系统的框图。如图1所示，存储器系统200响应于从主机50接收的各种输入/输出(I/O)请求，执行至少写入操作和读取操作。存储器系统200通常包括存储器控制器201和存储器设备202。
主机50可以是电子设备，例如，计算机、笔记本电脑、平板电脑、智能电话、智能电视等。主机50可结合运行一个或多个操作系统51的一个或多个应用52的执行，来访问存储器系统200。
在响应于主机请求的读取/写入操作或其它存储器访问操作的执行期间，存储器系统200可以从存储器控制器201向存储器设备202提供封装后修复命令和相关联的失效地址。
一旦识别出集成电路的失效部分，修复过程包括用冗余资源替换失效部分。用冗余资源替换失效部分的方法称为PPR(Post Package Repair，包装后修复)方法，该PPR包括hPPR(hard Post Package Repair，硬包装后修复)和sPPR(soft Post Package Repair，软包装后修复)。封装后软修复sPPR是一种快速但临时地修复内存阵列中元素的方法，而封装后硬修复hPPR则需要更长的时间，但它是对内存阵列中元素进行永久修复。
在实际应用中，对于sPPR或是hPPR而言，在同一个存储体组中，通常只有一个备用线路(备用位线或备用字线)可以进行修复操作。
图3示意性示出了根据本公开的一些实施例的封装后的内存修复方法的步骤流程图。参考图3，该封装后的内存修复方法可以包括以下步骤：
步骤S310，在内存测试过程中，将内存的失效信息写入到SPD(Serial Presence Detect，串行检测)中，失效信息包括失效地址；
步骤S320，在设备开机后，从SPD中读取失效地址，并确定失效地址所在的失效线路的数量；
步骤S330，在失效线路的数量小于或等于冗余线路的数量时，使用冗余线路对失效线路进行修复；
步骤S340，在失效线路的数量大于冗余线路的数量时，将失效信息加载到寄存器中。
根据本示例实施例中的封装后的内存修复方法，一方面，通过将内存的失效地址写入到SPD中，设备开机后，可以直接从SPD中读取失效地址，并确定失效线路的数量，根据失效线路的数量对失效线路进行修复，或者将失效信息加载到寄存器中，以在需要使用的时候，可以直接调用，从而实现了对失效地址进行全部修复的过程。另一方面，通过在内存测试过程中，记录失效信息，并在开机的时候对失效地址进行修复，实现了一种从软件的层面修复失效地址，从而为内存的封装后修复提供了一种实现方案，减少了内存的故障率，延长了内存的使用寿命。
下面，将对本示例实施例中的封装后的内存修复方法进行进一步的说明。
在步骤S310中，在内存测试过程中，将内存的失效信息写入到SPD中，失效信息包括失效地址。
SPD是一组关于内存模组的配置信息，如P-Bank(Physical Bank，物理层)数量、行地址/列地址数量、位宽、各种主要操作时序等信息，这些信息都存放在一个容量为256字节的EEPROM(Electrically Erasable Programmable Read Only Memory，电擦除可编程只读存储器)中，即SPD内的时序信息由模组生产商根据所使用的内存芯片的特点编写并写入至EEPROM，所述EEPROM存放在内存中。也就是说，失效信息可以写入到EEPROM的SPD中。
EEPROM的主要用途就是协助北桥芯片精确调整内存的物理/时序参数，以达到最佳 的使用效果。如果在BIOS(Basic Input Output System，基本输入输出系统)中将内存设置选项定为“By SPD”。那么在开机时，北桥会根据SPD中的参数信息来自动配置相应的内存时序与控制寄存器，避免人为出现调校错误而引起故障。
在内存访问测试过程中，首先进行内存的测试，这一过程是在内存条出厂前的完成，内存厂家用其测试软件实现内存的读写测试。并将其失效信息写入到内存的SPD中，如表1所示，SPD的定义为512Kb。其中Byte(字节)384～511由用户自定义，从Byte384开始定义的内容如表2所示。失效地址依次按照此内容格式往下写入，如表2所示。
表1
Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7
Byte8 Byte9 Byte10 Byte11 Byte12 Byte13 Byte14 Byte15
               
               
               
               
Byte496 Byte497 Byte498 Byte499 Byte500 Byte501 Byte502 Byte 503
Byte504 Byte505 Byte506 Byte507 Byte508 Byte509 Byte510 Byte 511
表2
Byte 信息
384 内存条中第1颗失效颗粒的位置及Rank
385 内存条中第1颗失效颗粒对应的Bank/Bank Group
396 内存条中第1颗失效颗粒对应的行地址
397 内存条中第1颗失效颗粒的列地址
398 内存条中第2颗失效颗粒的位置及Rank
399 内存条中第2颗失效颗粒对应的Bank/Bank Group
400 内存条中第2颗失效颗粒对应的行地址
401 内存条中第2颗失效颗粒的列地址
在表2中，可以将内存条中的所有失效颗粒的失效位置、失效颗粒的Rank、Bank/Bank Group(存储体组)、行地址和列地址等失效信息写入到内存的用户自定义字节中，其中，Rank指的是在内存模组上的内存区块；内存芯片中用于寻址的阵列称为内存芯片的Bank。
在实际应用中，可以将内存信息按照表2的失效信息顺序写入到用户自定义字节中，也可以按照其他顺序来写入，本示例性实施方式对此不作限定。
在步骤S320中，在设备开机后，从SPD中读取失效地址，并确定失效地址所在的失效线路的数量。
本示例性实施方式中，在内存厂家完成对失效信息的写入步骤之后，在设备的系统开机，例如，用户使用过程中，操作系统的CPU(Central Processing Unit，中央处理器)会首先对内存中的SPD进行读取，并根据SPD中记录的失效地址，确定失效地址所在的失效线路的数量，并根据不同的失效线路的数量来确定不同的修复方案。
由于同一个存储体组中的冗余线路只能对其所在的存储体组中的失效线路进行修复，因此，上述确定失效地址所在的失效线路的数量可以包括：确定同一个存储体组中的失效地址所在的失效线路的数量。
在步骤S330中，在失效线路的数量小于或等于冗余线路的数量时，使用冗余线路对失效线路进行修复；在步骤S340中，在失效线路的数量大于冗余线路的数量时，将失效信息加载到寄存器中。
本示例性实施方式中，通过比较失效线路的数量和冗余线路的数量，来确定具体的修复方案，对于失效线路的数量小于或等于冗余线路的数量的情况，可以直接使用冗余线路对失效线路进行修复。此处的修复有可能是hPPR，也可能是sPPR修复。
具体的，当失效线路存储在非易失性存储器中的时候，使用的是hPPR命令进行修复；当失效线路存储在易失性存储器中的时候，使用的是sPPR命令进行修复。其中，hPPR属于永久修复的方法，使用hPPR修复后，冗余线路即永久替换了失效线路。
而对于失效线路的数量大于冗余线路的数量的情况，直接将失效信息加载到寄存器中，以暂时存放失效信息。以便于在对内存进行读写访问过程中，如果访问到失效地址，则直接从寄存器中读写失效地址对应的信息。避免直接访问到失效地址而出现故障。
同样需要说明的是，上述冗余线路的数量也指的是同一个存储体组中的冗余线路的数量。
在本示例性实施方式中，通过上述步骤S320-S340，可以在每次开机后对内存进行修复，从而实现一种从软件层面进行修复的方法，以便于用户在使用存储器过程中对内存进行修复，减少存储器使用过程中的故障率，从而可以提升用户体验。
参照图4，示意性示出了根据本公开的示例性实施方式的封装后的内存修复流程示意图，如图4所示，在步骤S401中，进行内存测试，以获得内存的失效地址；在步骤S402中，将失效地址写入到SPD中；在步骤S403中，设备开机；在步骤S404中，从SPD中读取失效地址；在步骤S405中，进入判断条件，即判断失效地址所在的失效线路的数量是否小于或等于冗余线路的数量；如果满足判断条件，则执行步骤S406，使用PPR进行修复；如果不满足判断条件，则执行步骤S407，将失效信息加载到寄存器中；完成所有失效地址的修复后，再执行步骤S408，正常启动系统，并且在对内存进行读写访问过程中，如果访问到失效地址，则直接从寄存器中读写失效地址对应的信息。
需要说明的是，尽管在附图中以特定顺序描述了本发明中方法的各个步骤，但是，这 并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
此外，在本示例实施例中，还提供了一种封装后的内存修复装置。参考图5，该封装后的内存修复装置500可以包括：写入模块510、读取模块520、第一修复模块530和第二修复模块540，其中，
写入模块510，用于在内存测试过程中，将内存的失效信息写入到SPD中，失效信息包括失效地址。
读取模块520，用于在设备开机后，从SPD中读取失效地址，并确定失效地址所在的失效线路的数量。
第一修复模块530，用于在失效线路的数量小于或等于冗余线路的数量时，使用冗余线路对失效线路进行修复。
第二修复模块540，用于在失效线路的数量大于冗余线路的数量时，将失效信息加载到寄存器中。
本示例性实施方式中，写入模块510可以将内存条中的所有失效颗粒的失效位置、失效颗粒的Rank、Bank/Bank Group(存储体组)、行地址和列地址等失效信息写入到内存的用户自定义字节中。可以将上述内存信息顺序写入到用户自定义字节中。
读取模块520用于在设备的系统开机后，首先对EEPROM中的SPD进行读取，并根据SPD中记录的失效地址，确定失效地址所在的失效线路的数量，并根据不同的失效线路的数量来确定不同的修复方案。
由于同一个存储体组中的冗余线路只能对其所在的存储体组中的失效线路进行修复，因此，上述确定失效地址所在的失效线路的数量可以包括：确定同一个存储体组中的失效地址所在的失效线路的数量。
通过比较同一个存储体组中的失效线路的数量和冗余线路的数量，使用第一修复模块530或第二修复模块540进行修复。对于失效线路的数量小于或等于冗余线路的数量的情况，通过第一修复模块530直接使用冗余线路对失效线路进行修复。此处的修复有可能是hPPR，也可能是sPPR修复。
而对于失效线路的数量大于冗余线路的数量的情况，则通过第二修复模块540直接将失效信息加载到寄存器中，以暂时存放失效信息。以便于在对内存进行读写访问过程中，如果访问到失效地址，则直接从寄存器中读写失效地址对应的信息。避免直接访问到失效地址而出现故障。
在本示例性实施方式中，通过写入模块510、读取模块520、第一修复模530和第二修复模块540，可以在每次开机后对内存进行修复，从而实现一种从软件层面进行修复的方法，以便于用户在使用存储器过程中对内存进行修复，减少存储器使用过程中的故障率，从而可以提升用户体验。
应当注意，尽管在上文详细描述中提及了封装后的内存修复装置的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
此外，上述附图仅是根据本发明示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
在本公开的示例性实施例中，还提供了一种能够实现上述方法的电子设备。
所属技术领域的技术人员能够理解，本发明的各个方面可以实现为系统、方法或程序产品。因此，本发明的各个方面可以具体实现为以下形式，即：完全的硬件实施方式、完全的软件实施方式(包括固件、微代码等)，或硬件和软件方面结合的实施方式，这里可以统称为“电路”、“模块”或“系统”。
下面参照图6来描述根据本发明的这种实施方式的电子设备600。图6显示的电子设备600仅仅是一个示例，不应对本发明实施例的功能和使用范围带来任何限制。
如图6所示，电子设备600以通用计算设备的形式表现。电子设备600的组件可以包括但不限于：上述至少一个处理单元610、上述至少一个存储单元620、连接不同系统组件(包括存储单元620和处理单元610)的总线630、显示单元640。
其中，所述存储单元620存储有程序代码，所述程序代码可以被所述处理单元610执行，使得所述处理单元610执行本说明书上述“示例性方法”部分中描述的根据本发明各种示例性实施方式的步骤。例如，所述处理单元610可以执行如图3中所示的步骤S310，在内存测试过程中，将内存的失效信息写入到SPD中，失效信息包括失效地址；步骤S320，在设备开机后，从SPD中读取失效地址，并确定失效地址所在的失效线路的数量；步骤S330，在失效线路的数量小于或等于冗余线路的数量时，使用冗余线路对失效线路进行修复；步骤S340，在失效线路的数量大于冗余线路的数量时，将失效信息加载到寄存器中。
存储单元620可以包括易失性存储单元形式的可读介质，例如随机存取存储单元(RAM)6201和/或高速缓存存储单元6202，还可以进一步包括只读存储单元(ROM)6203。
存储单元620还可以包括具有一组(至少一个)程序模块6205的程序/实用工具6204，这样的程序模块6205包括但不限于：操作系统、一个或者多个应用程序、其它程序模块以及程序数据，这些示例中的每一个或某种组合中可能包括网络环境的实现。
总线630可以为表示几类总线结构中的一种或多种，包括存储单元总线或者存储单元控制器、外围总线、图形加速端口、处理单元或者使用多种总线结构中的任意总线结构的局域总线。
电子设备600也可以与一个或多个外部设备670(例如键盘、指向设备、蓝牙设备等)通信，还可与一个或者多个使得用户能与该电子设备600交互的设备通信，和/或与使得 该电子设备600能与一个或多个其它计算设备进行通信的任何设备(例如路由器、调制解调器等等)通信。这种通信可以通过输入/输出(I/O)接口650进行。并且，电子设备600还可以通过网络适配器660与一个或者多个网络(例如局域网(LAN)，广域网(WAN)和/或公共网络，例如因特网)通信。如图所示，网络适配器660通过总线630与电子设备600的其它模块通信。应当明白，尽管图中未示出，可以结合电子设备600使用其它硬件和/或软件模块，包括但不限于：微代码、设备驱动器、冗余处理单元、外部磁盘驱动阵列、RAID系统、磁带驱动器以及数据备份存储系统等。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、终端装置、或者网络设备等)执行根据本公开实施方式的方法。
在本公开的示例性实施例中，还提供了一种计算机可读存储介质，其上存储有能够实现本说明书上述方法的程序产品。在一些可能的实施方式中，本发明的各个方面还可以实现为一种程序产品的形式，其包括程序代码，当所述程序产品在终端设备上运行时，所述程序代码用于使所述终端设备执行本说明书上述“示例性方法”部分中描述的根据本发明各种示例性实施方式的步骤。
根据本发明的实施方式的用于实现上述方法的程序产品可以采用便携式紧凑盘只读存储器(CD-ROM)，并包括程序代码，并可以在终端设备，例如个人电脑上运行。然而，本发明的程序产品不限于此，在本文件中，可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
所述程序产品可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以为但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了可读程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。可读信号介质还可以是可读存储介质以外的任何可读介质，该可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于无线、有线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言的任意组合来编写用于执行本发明操作的程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、C++等，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。在涉及远程计算设备的情形中，远程计算设备可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算设备，或者，可以连接到外部计算设备(例如利用因特网服务提供商来通过因特网连接)。
此外，上述附图仅是根据本发明示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (16)

  1. 一种封装后的内存修复方法，所述方法包括：
    在内存测试过程中，将所述内存的失效信息写入到SPD中，所述失效信息包括失效地址；
    在设备开机后，从所述SPD中读取所述失效地址，并确定所述失效地址所在的失效线路的数量；
    在所述失效线路的数量小于或等于冗余线路的数量时，使用所述冗余线路对所述失效线路进行修复；
    在所述失效线路的数量大于所述冗余线路的数量时，将所述失效信息加载到寄存器中。
  2. 根据权利要求1所述的方法，其中，将所述内存的失效信息写入到内存中包括：
    将所述失效信息写入到EEPROM的所述SPD中。
  3. 根据权利要求1所述的方法，其中，确定所述失效地址所在的失效线路的数量包括：
    确定同一个存储体组中所述失效地址所在的所述失效线路的数量。
  4. 根据权利要求3所述的方法，其中，所述冗余线路的数量是同一个所述存储体组中的冗余线路的数量。
  5. 根据权利要求1-4任一项所述的方法，其中，所述方法还包括：
    在对所述内存进行读写访问过程中，如果访问到所述失效地址，则直接从所述寄存器中读写所述失效地址对应的信息。
  6. 根据权利要求1所述的方法，其中，在内存测试过程中，将所述内存的失效信息写入到内存中包括：
    在所述内存测试过程中，将所述失效信息写入到所述内存的用户自定义字节中。
  7. 根据权利要求1或6所述的方法，其中，所述失效信息还包括失效位置、失效颗粒的Rank、Bank/Bank Group、行地址和列地址；
    将所述失效信息写入到所述内存的用户自定义字节中包括：
    将所述失效信息顺序写入到所述用户自定义字节中。
  8. 一种封装后的内存修复装置，所述装置包括：
    写入模块，用于在内存测试过程中，将所述内存的失效信息写入到SPD中，所述失效信息包括失效地址；
    读取模块，用于在设备开机后，从所述SPD中读取所述失效地址，并确定所述失效地址所在的失效线路的数量；
    第一修复模块，用于在所述失效线路的数量小于或等于冗余线路的数量时，使用所述冗余线路对所述失效线路进行修复；
    第二修复模块，用于在所述失效线路的数量大于所述冗余线路的数量时，将所述失效信息加载到寄存器中。
  9. 根据权利要求8所述的装置，其中，将所述内存的失效信息写入到内存中包括：
    将所述失效信息写入到EEPROM的所述SPD中。
  10. 根据权利要求8所述的装置，其中，确定所述失效地址所在的失效线路的数量包括：
    确定同一个存储体组中所述失效地址所在的所述失效线路的数量。
  11. 根据权利要求10所述的装置，其中，所述冗余线路的数量是同一个所述存储体组中的冗余线路的数量。
  12. 根据权利要求8-11任一项所述的装置，其中，所述装置还包括：
    读写模块，用于在对所述内存进行读写访问过程中，如果访问到所述失效地址，则直接从所述寄存器中读写所述失效地址对应的信息。
  13. 根据权利要求8所述的装置，其中，在内存测试过程中，将所述内存的失效信息写入到内存中包括：
    在所述内存测试过程中，将所述失效信息写入到所述内存的用户自定义字节中。
  14. 根据权利要求8或13所述的装置，其中，所述失效信息还包括失效颗粒的Rank、Bank/Bank Group、行地址和列地址；
    将所述失效信息写入到所述内存的用户自定义字节中包括：
    将所述失效信息顺序写入到所述用户自定义字节中。
  15. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1-7中任一项所述的封装后的内存修复方法。
  16. 一种电子设备，包括：
    处理器；
    存储器，用于存储一个或多个程序，当所述一个或多个程序被所述处理器执行时，使得所述处理器实现如权利要求1-7中任一项所述的封装后的内存修复方法。
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