WO2022110858A1 - 备用电路修补位置确定方法及装置、集成电路修补方法 - Google Patents

备用电路修补位置确定方法及装置、集成电路修补方法 Download PDF

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Publication number
WO2022110858A1
WO2022110858A1 PCT/CN2021/109067 CN2021109067W WO2022110858A1 WO 2022110858 A1 WO2022110858 A1 WO 2022110858A1 CN 2021109067 W CN2021109067 W CN 2021109067W WO 2022110858 A1 WO2022110858 A1 WO 2022110858A1
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Prior art keywords
failure
repair
determining
line
location
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PCT/CN2021/109067
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English (en)
French (fr)
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仰蕾
陈予郎
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长鑫存储技术有限公司
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Priority to US17/649,192 priority Critical patent/US11842788B2/en
Publication of WO2022110858A1 publication Critical patent/WO2022110858A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G11C29/765—Masking faults in memories by using spares or by reconfiguring using address translation or modifications in solid state disks

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular, to a method and device for determining a repair position of a spare circuit, and a method for repairing an integrated circuit.
  • the assigned repair positions of all backup circuits are obtained, and based on the aforementioned repair positions, the failure positions are repaired.
  • a method for determining a repair position of a backup circuit comprising:
  • a final repair position of the backup circuit is determined according to the failure position and the predicted repair position.
  • an apparatus for determining a repair position of a backup circuit comprising:
  • a first determination module used for determining the failure position of the chip to be repaired
  • a second determining module configured to assign an initial repair position of the backup circuit according to the failure position
  • a third determining module configured to determine a potential failure line according to the initial repair position
  • a fourth determining module configured to determine a predicted repair position according to the potential failure line
  • a fifth determination module configured to determine a final repair position of the backup circuit according to the failure position and the predicted repair position.
  • an electronic device comprising:
  • a memory for storing one or more programs, which, when executed by the processor, enables the processor to implement the above-mentioned method for determining a repair position of a spare circuit.
  • FIG. 1 schematically shows a schematic structural diagram of a chip according to an exemplary embodiment of the present disclosure
  • FIG. 2 schematically shows a schematic flowchart of a method for determining a repair position of a spare circuit according to an exemplary embodiment of the present disclosure
  • FIG. 3 schematically shows a schematic diagram of an initial repair position of a backup circuit according to an exemplary embodiment of the present disclosure
  • FIG. 4 schematically shows a first position diagram of determining a potential failure line by the attribute of the number and distance of initial repair positions according to an exemplary embodiment of the present disclosure
  • FIG. 5 schematically shows a second schematic diagram of the location of a potential failure line determined by the number and distance attributes of initial repair locations according to an exemplary embodiment of the present disclosure
  • FIG. 6 schematically shows a schematic diagram 1 of a position of a potential failure line determined by a failure position attribute according to an exemplary embodiment of the present disclosure
  • FIG. 7 schematically shows a second schematic diagram of the location of a potential failure line determined by a failure location attribute according to an exemplary embodiment of the present disclosure
  • FIG. 8 is a schematic diagram showing the cumulative number of failures at the location of the potential failure line in FIG. 4;
  • FIG. 9 shows a schematic diagram of the predicted repair location determined by the potential failure line in FIG. 4;
  • FIG. 10 schematically shows a schematic diagram of another predicted repair location determined by a potential failure line according to an exemplary embodiment of the present disclosure
  • FIG. 11 schematically shows a schematic diagram of yet another predicted repair location determined by a potential failure line according to an exemplary embodiment of the present disclosure
  • FIG. 12 schematically shows a block diagram of an apparatus for determining a position of a backup circuit repair according to an exemplary embodiment of the present disclosure
  • FIG. 13 schematically shows a flow chart of a method for repairing an integrated circuit according to an exemplary embodiment of the present disclosure
  • FIG. 14 schematically shows a block diagram of an electronic device in an exemplary embodiment according to the present disclosure
  • FIG. 15 schematically shows a schematic diagram of a program product in an exemplary embodiment according to the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • a typical dynamic random access memory chip has as many as 64 million cells, which can be arranged in a main array in rows and columns to facilitate addressing by wordlines and bitlines.
  • all the failure positions can be detected by the circuit probe testing technology, and the backup circuits in the chip can be allocated through the backup circuit analysis step to repair the above-mentioned failure positions.
  • the present exemplary embodiment provides a method and apparatus for determining a repairing position of a spare circuit, and a method for repairing an integrated circuit.
  • a chip 100 generally includes a normal cell area 110 and a spare cell area 120 .
  • the normal cell area 110 contains many cells, and the normal cell area Region 110 includes two orthogonal lines: word lines 111 and bit lines 112, wherein word lines 111 are column lines and bit lines 112 are row lines.
  • the chip 100 is also provided with a spare unit area 120 including spare units.
  • the spare unit area 120 includes two orthogonal straight lines: the spare word line 121 (Redundancy Word-Line, RWL) and a spare bit line 122 (Redundancy Bit-Line, RBL), wherein the spare word line 121 is a column line for repairing the failure position on the word line 111; the spare bit line 122 is a row line for repairing on the bit line 112 the failure location.
  • the spare word line 121 is a column line for repairing the failure position on the word line 111
  • the spare bit line 122 is a row line for repairing on the bit line 112 the failure location.
  • FIG. 2 schematically shows a flow chart of a method for determining a repair position of a spare circuit according to some embodiments of the present disclosure.
  • the method for determining the repair position of the spare circuit may include the following steps:
  • Step S210 determining the failure position of the chip to be repaired.
  • Step S220 assigning the initial repair position of the backup circuit according to the failure position.
  • Step S230 determining a potential failure line according to the initial repair position.
  • Step S240 determining the predicted repair position according to the potential failure line.
  • Step S250 Determine the final repair position of the backup circuit according to the failure position and the predicted repair position.
  • the failure position of the chip to be repaired can be determined, and the initial repair position of the spare circuit can be preliminarily assigned according to the failure position, and the potential failure can be determined according to the initial repair position.
  • the predicted repair position can be determined according to the potential failure circuit, wherein the predicted repair position is the position where the above-mentioned more probable new failure position occurs, and then the final repair position of the standby circuit can be determined according to the failure position and the predicted repair position, so that The failure position and the predicted repair position where a new failure position may appear can be determined as the repair position that needs to be repaired at the same time, so that the new failure position can be repaired before it appears, so that the probability of the new failure position can be reduced. Improving the process yield of the chip can also improve the quality of the chip, reduce the cost of after-sales warranty, and improve the user experience.
  • the failure position and the position where a new failure position may appear can be repaired at one time at the same time, thereby saving repair man-hours and repair costs.
  • the above-mentioned repairing solution for the failure position can improve the probability that the failure position is completely repaired after one repair is performed, and reduce the probability that the repair cannot be carried out, thereby effectively improving the process yield of the chip and reducing the occurrence of chip scrapping. .
  • step S210 the failure position of the chip to be repaired is determined.
  • the fail position 113 is a position in the normal cell region 110, and the fail position 113 is on the word line 111 or the bit line 112, so it can pass through the spare word line 121 replaces the word line 111 to repair the failed position 113, or alternatively, the spare bit line 122 can be used to replace the bit line 112 to repair the failed position 113.
  • the specific repair scheme can be determined with reference to the existing spare circuit repair scheme.
  • step S220 the initial repair position of the backup circuit is assigned according to the failure position.
  • the initial repair position of the spare circuit is preliminarily determined according to the existing spare circuit repair scheme to determine whether the failure position on the chip 100 to be repaired is repaired by the spare word line 121 or the spare bit line 122 .
  • FIG. 3 schematically shows a schematic diagram of an initial repair position of a backup circuit.
  • the normal cell area 110 is divided into a plurality of areas, for example, area one 210, area two 220, area three 230, and, for example, if there is no failure position in area one 210; There are three failure positions, and one of the bit lines 221 in the second region 220 contains three failure points (Fail Bit, FB for short), and the specific test items (Bin for short) are a and h, and the three failure points are respectively test items.
  • There are four failure points when any two of the four failure points are adjacent to each other, that is, the failure points are arranged in a linear shape, and the initial repair position is determined according to the above-mentioned multiple failure positions, and the spare word line 121 is allocated to the word line 222.
  • the bit line 122 is assigned to the bit line 221; there is a failure position in the region three 230, and the failure position is on the bit line 231, and the bit line 231 contains a failure point, wherein the test item is a, and the failure point is a single point arrangement , thus assigning spare bit line 122 to bit line 231 as the initial patch location.
  • the initial repair position of the spare circuit determined here does not mean that the allocated spare word line 121 or the allocated spare bit line 122 will eventually be used to repair the failure positions listed above.
  • step S230 a potential failure line is determined according to the initial repair position.
  • a potential failure line refers to a line in which a new failure position may appear if the failure position in the chip 100 is repaired according to the initial repair position determined in step S220.
  • determining the potential failure line it is possible to predict the position where the new failure position will appear, so that the potential failure line can also be repaired when the repair is formally carried out, thereby reducing the probability of the occurrence of the new failure position and improving the The process yield of the chip.
  • the potential failure line is determined according to the historical data of the new failure positions of the scrapped chips in the past.
  • the potential failure line determined by this method The dispersion is relatively large, and data statistics need to be carried out for each line, which requires a large amount of data support.
  • the step of determining a potentially failed line according to an initial repair location may include determining a potentially failed line according to a repair location attribute of the initial repair location.
  • the repair position of each allocated spare circuit usually has a lot of information, such as product combination category, spare circuit type, number of failure points, test items, failure position arrangement shape and other repair position attributes.
  • the spare circuit types refer to spare word lines 121 and spare bit lines 122 .
  • the number of fail points refers to the number of fail points present in the allocated spare word line 121 or the allocated spare bit line 122 .
  • the test item refers to that when the circuit probe tests the failure position, it includes multiple test items. These test items will sequentially test each unit that has not been tested or has passed the previous test to determine whether the position is the failure position.
  • the failure position arrangement shape includes a line shape and a single point, wherein a line shape refers to a shape with consecutive adjacent failure positions, and a single point refers to a shape without consecutive adjacent failure positions.
  • repair location attributes associated with the above-mentioned location information are proposed: a quantity and distance attribute, and a failure location attribute.
  • the potential failure line may be determined according to the above-mentioned attribute of the number and distance of the initial repair positions, or the potentially failed line may be determined according to the failure position attribute of the above-mentioned initial repair position.
  • the step of determining the potential failure position according to the number and distance attribute of the above-mentioned initial repair positions may specifically include: for the initial repair positions that are both word lines or bit lines, the number of initial repair positions is greater than or equal to two, and When the distance between two adjacent initial repair positions is less than or equal to three cells, the word line or bit line adjacent to the initial repair position is determined as a potential failure line.
  • the word adjacent to the initial repair position determines whether the initial repair position is adjacent to The bit line is a potential failure line.
  • FIG. 4 schematically shows a schematic diagram 1 of the location of a potential failure line determined by the attributes of the number and distance of initial repair locations.
  • Figure 4 contains initial patch locations (allocated alternate circuit locations) determined by two spare word lines: an initial patch location one 410 and an initial patch location two 420; both an initial patch location one 410 and an initial patch location two 420 are word lines , and the distance L1 is three units.
  • the two word lines adjacent to the initial repair position one 410 are potential failure lines, and are marked as potential failure position one 430 and potential failure position two 440 respectively.
  • the two word lines adjacent to the initial repair position two 420 are potential failure positions, and are respectively marked as potential failure position three 450 and potential failure position four 460 .
  • FIG. 5 schematically shows a second schematic diagram of the location of a potential failure line determined by attributes of the number and distance of initial repair locations.
  • Figure 5 contains the initial repair positions determined by two spare bit lines: the initial repair position three 510 and the initial repair position four 520; the initial repair position three 510 and the initial repair position four 520 are both bit lines and are located in two phases respectively. In adjacent regions, the distance L2 is one unit. At this time, the three bit lines adjacent to the initial repair position 3 510 are all potential failure positions. Similarly, the three bit lines adjacent to the initial repair position four 520 are also potential failure positions.
  • the step of determining the potential failure line according to the failure position attribute of the initial repair position may specifically include: determining the failure position in the initial repair position and the line where the position adjacent to the position of the unassigned spare circuit is located as the potential failure line.
  • FIG. 6 schematically shows a schematic diagram 1 of the location of a potential failure line determined by the failure location attribute.
  • 6 contains an initial repair position 610 determined by a spare word line, the initial repair position 610 contains three failure points 620, and each failure point 620 and its adjacent points of the unassigned spare circuit form a bit line 630, then the bit line 630 Line 630 is determined to be a potentially failed line.
  • FIG. 7 schematically shows a second schematic diagram of the location of a potential failure line determined by the failure location attribute.
  • 7 contains an initial repair position 710 determined by a spare bit line, the initial repair position 710 contains two failure points 720, and each failure point 720 and its adjacent points of unassigned spare circuits form a word line 730, then the word Line 730 is determined to be a potentially failed line.
  • FIGS. 4 to 7 are only examples of determining the potential failure line according to the location attribute of the initial repair location, and other initial repair location conditions may be referred to and executed, which are not listed one by one in this exemplary embodiment.
  • step S240 the predicted repair position is determined according to the potential failure line.
  • a predicted repair position may be determined on the basis of the potential failure line, so as to determine a repair position with a higher probability of a new failure position.
  • the predicted repair location can be determined according to the cumulative failure probability of the potentially failed line, and the cumulative failure probability of the potentially failed line can be determined according to the historical test data of the same chip, that is, the potential failure probability can be determined according to the historical test data of the same chip.
  • the cumulative failure times of the failed lines and then determine the cumulative failure probability according to the cumulative failure times, and when the cumulative failure probability is greater than the preset value, determine the potential failure line as the predicted repair position; that is, when the cumulative failure times account for the cumulative chip When the proportion of the total number of failures is greater than the preset value, determine the potential failure line as the predicted repair location.
  • FIG. 8 shows the cumulative number of failures at the location of the potential failure line in FIG. 4 , wherein the test item Bin of the initial repair position 1 410 is a or i; the number of failure points of the initial repair position 2 420 is greater than or equal to 2, and multiple failure points are arranged linearly, and the test item Bin is h.
  • the potential failure position 1 occurred 1 time
  • the potential failure position 2 440 occurred 100 times
  • the potential failure position 3 450 occurred 130 times
  • the potential failure position 4 460 occurred. It happened 15 times, that is to say, the probability of occurrence of potential failure position one 430 is 0.008%
  • the probability of occurrence of potential failure position two 440 is 0.799%
  • the probability of occurrence of potential failure position three 450 is 1.038%
  • the probability of potential failure position four 460 is 1.038%.
  • the probability of occurrence is 0.120%.
  • the determination of the preset value can be determined according to the actual situation.
  • the preset value can be 0.5%-1%.
  • the potential failure position 2 440 and the potential failure position 3 450 are larger than the above-mentioned preset value range. , therefore, as shown in FIG. 9 , potential failure position two 440 and potential failure position three 450 are determined as predicted repair positions.
  • This exemplary embodiment does not specifically limit the specific value of the preset value.
  • the product combination category is DDR4 (Double Data Rate SDRAM4, double-rate SDRAM4), wherein, SDRAM is Synchronous Dynamic Random Access Memory Synchronous Dynamic Random Access Access memory; the type of spare circuit is spare word line, and the number of spare circuits is two; the number of failure points on each assigned spare word line is greater than or equal to 1, and the test items include multiple, such as a, i or h; Failure position arrangement shape: the failure points on one of the allocated spare word lines are in an arbitrary shape, and the failure points on the other allocated spare word line are arranged in a line.
  • the two backup circuits are separated by three points, and the predicted repair position is the line between the two backup circuits, that is, the potential failure position two 440 and the potential failure position three 450 .
  • FIG. 10 schematically shows a schematic diagram of another predicted repair location determined by a potentially failed line.
  • the attributes of the chip to be repaired as shown in FIG. 10 are: the product combination type is DDR4; the type of the spare circuit is the allocated spare bit line 1010 , and the number of spare circuits is one; the number of failure points on the allocated spare bit line is greater than or equal to 1 , such as two, the test item contains multiple, such as ⁇ a,i ⁇ , which contains a or i; the failure position arrangement shape is a single point, that is, the distance L3 between the two failure positions is greater than 1 unit.
  • the line at which the two fail positions are located and the line at which the position adjacent to the unassigned spare circuit is located is determined as a potential fail line 1020 .
  • the predicted repair location is two potential failure lines 1020 , and the test item of the failure location belongs to the line of the test item ⁇ a,i ⁇ in the attribute, that is, the potential failure line five 1030 of Bin ⁇ a,i ⁇ .
  • FIG. 11 schematically shows a schematic diagram of yet another predicted repair location determined by a potentially failed line.
  • the attributes of the chip to be repaired as shown in Figure 11 are: the product combination type is DDR4; the type of spare circuit is spare bit line 1110, the number of spare circuits is 1; the number of failure points on the allocated spare bit line is greater than or equal to 2, for example Two, the test items belong to ⁇ a ⁇ , that is, one a;
  • the lines where the two failure positions are located and the positions where the adjacent unassigned backup circuits are located are determined as potential failure lines 1120 and 1130, and in the potential failure line 1120, the test item of the failure position does not belong to ⁇ a ⁇ , and in the potential failure line 1120 In the line 1130, the test item of the failure position belongs to ⁇ a ⁇ . But no matter whether the test item belongs to ⁇ a ⁇ , the potential failure lines 1120 and 1130 are predicted repair positions, that is, the lines of any test item are predicted repair positions.
  • step S250 the final repair position of the backup circuit is determined according to the failure position and the predicted repair position.
  • the failure position and the predicted repair position can be determined as the final repair position of the standby circuit at the same time, so that the failure position and the position where a new failure position may appear can be repaired at the same time during repair, so as to Repair new failure locations before they appear, which can reduce the probability of new failure locations, improve the process yield of the chip, improve the quality of the chip, reduce the cost of after-sales warranty, and improve the user experience.
  • an apparatus for determining a repair position of a backup circuit may include: a first determination module 1210, a second determination module 1220, a third determination module 1230, a fourth determination module 1240, and a fifth determination module 1250, wherein:
  • the first determining module 1210 can be used to determine the failure position of the chip to be repaired
  • the second determining module 1220 can be configured to assign the initial repair position of the backup circuit according to the failure position
  • the third determining module 1230 can be configured to determine the potential failure line according to the initial repair position
  • a fourth determining module 1240 which can be used to determine the predicted repair location according to the potential failure line;
  • the fifth determination module 1250 may be used to determine the final repair position of the backup circuit according to the failure position and the predicted repair position.
  • modules or units of the backup circuit repair position determination device are mentioned in the above detailed description, this division is not mandatory. Indeed, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units to be embodied.
  • the integrated circuit repair method may include the following steps:
  • Step S1310 determining the final repairing position of the backup circuit according to the above-mentioned method for determining the repairing position of the backup circuit;
  • step S1320 the chip to be repaired is repaired according to the final repair position.
  • a final repairing position including a failure position and a predicted repairing position where a new failure position may occur is determined by the standby circuit repairing position determination method, and treatment is performed according to the final repairing position. Repairing the chip can reduce the probability of new failure locations, improve the process yield of the chip, improve the quality of the chip, reduce the cost of after-sales warranty, and improve the user experience. On the other hand, by determining the predicted repair position before repairing, the failure position and the position where a new failure position may appear can be repaired at one time at the same time, thereby saving repair man-hours and repair costs.
  • the above-mentioned repairing solution for the failure position can improve the probability that the failure position is completely repaired after one repair is performed, and reduce the probability that the repair cannot be carried out, thereby effectively improving the process yield of the chip and reducing the occurrence of chip scrapping. .
  • an electronic device capable of implementing the above method is also provided.
  • various aspects of the embodiments of the present disclosure may be implemented as a system, method or program product. Therefore, various aspects of the embodiments of the present disclosure may be embodied in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, where May be collectively referred to as a "circuit,” “module,” or “system.”
  • FIG. 14 An electronic device 1400 according to this embodiment of the present disclosure is described below with reference to FIG. 14 .
  • the electronic device 1400 shown in FIG. 14 is only an example, and should not impose any limitation on the function and scope of use of the embodiments of the present disclosure.
  • electronic device 1400 takes the form of a general-purpose computing device.
  • Components of the electronic device 1400 may include, but are not limited to: the above-mentioned at least one processing unit 1410 , the above-mentioned at least one storage unit 1420 , a bus 1430 connecting different system components (including the storage unit 1420 and the processing unit 1410 ), and a display unit 1440 .
  • the storage unit 1420 stores program codes, and the program codes can be executed by the processing unit 1410, so that the processing unit 1410 executes various methods according to the present disclosure described in the above-mentioned “Exemplary Methods” section of this specification. Steps of an exemplary embodiment.
  • the processing unit 1410 may perform step S210 as shown in FIG.
  • step S220 assign the initial repair position of the backup circuit according to the failure position
  • step S230 assign to the initial repair position
  • the repair position determines the potential failure line
  • Step S240 determines the predicted repair position according to the potential failure line
  • Step S250 determines the final repair position of the backup circuit according to the failure position and the predicted repair position
  • Step S1320 according to the final repair position
  • the patch position is to patch the chip to be patched.
  • the storage unit 1420 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 14201 and/or a cache storage unit 14202 , and may further include a read only storage unit (ROM) 14203 .
  • RAM random access storage unit
  • ROM read only storage unit
  • the storage unit 1420 may also include a program/utility 14204 having a set (at least one) of program modules 14205 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, An implementation of a network environment may be included in each or some combination of these examples.
  • the bus 1430 may be representative of one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local area using any of a variety of bus structures bus.
  • the electronic device 1400 may also communicate with one or more external devices 1470 (eg, keyboards, pointing devices, Bluetooth devices, etc.), with one or more devices that enable a user to interact with the electronic device 1400, and/or with Any device (eg, router, modem, etc.) that enables the electronic device 1400 to communicate with one or more other computing devices. Such communication may occur through input/output (I/O) interface 1450 . Also, the electronic device 1400 may communicate with one or more networks (eg, a local area network (LAN), a wide area network (WAN), and/or a public network such as the Internet) through a network adapter 1460 . As shown, network adapter 1460 communicates with other modules of electronic device 1400 via bus 1430. It should be understood that, although not shown, other hardware and/or software modules may be used in conjunction with electronic device 1400, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives and data backup storage systems.
  • the exemplary embodiments described herein may be implemented by software, or by a combination of software and necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure may be embodied in the form of software products, and the software products may be stored in a non-volatile storage medium (which may be CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to cause a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to an embodiment of the present disclosure.
  • a computing device which may be a personal computer, a server, a terminal device, or a network device, etc.
  • a computer-readable storage medium on which a program product capable of implementing the above-described method of the present specification is stored.
  • various aspects of the embodiments of the present disclosure may also be implemented in the form of a program product, which includes program code for, when the program product runs on a terminal device, the program code for The terminal device is caused to perform the steps according to various exemplary embodiments of the present disclosure described in the above-mentioned "Example Method" section of this specification.
  • a program product 1500 for implementing the above-described method is described according to an implementation of an embodiment of the present disclosure, which may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be stored in run on end devices such as personal computers.
  • CD-ROM portable compact disc read only memory
  • the program product of the embodiments of the present disclosure is not limited thereto, and in this document, a readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device .
  • the program product may employ any combination of one or more readable media.
  • the readable medium may be a readable signal medium or a readable storage medium.
  • the readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or a combination of any of the above. More specific examples (non-exhaustive list) of readable storage media include: electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, portable compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
  • a computer readable signal medium may include a propagated data signal in baseband or as part of a carrier wave with readable program code embodied thereon. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a readable signal medium can also be any readable medium other than a readable storage medium that can transmit, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
  • Program code embodied on a readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
  • Program code for performing the operations of embodiments of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages—such as Java, C++, etc., as well as conventional procedural programming language - such as "C" language or similar programming language.
  • the program code may execute entirely on the user computing device, partly on the user device, as a stand-alone software package, partly on the user computing device and partly on a remote computing device, or entirely on the remote computing device or server execute on.
  • the remote computing device may be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (eg, using an Internet service provider business via an Internet connection).
  • LAN local area network
  • WAN wide area network

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Abstract

一种备用电路修补位置确定方法及装置、集成电路修补方法，通过确定待修补芯片的失效位置，并根据该失效位置可以初步分派备用电路的初始修补位置，而根据初始修补位置可以确定潜在失效线路，再根据潜在失效线路可以确定预测修补位置，其中该预测修补位置就是上述较多概率出现新的失效位置的位置，再根据失效位置和预测修补位置可以确定出备用电路的最终修补位置，从而可以将失效位置和可能出现新的失效位置的预测修补位置同时确定为需要修补的修补位置，以在新的失效位置出现之前即对其进行修补。 (图2)

Description

备用电路修补位置确定方法及装置、集成电路修补方法
相关申请的交叉引用
本公开要求于2020年11月26日提交的申请号为202011350461.3名称为“备用电路修补位置确定方法及装置、集成电路修补方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种备用电路修补位置确定方法及装置、集成电路修补方法。
背景技术
随着计算机技术的快速发展，集成电路芯片在人们的生产生活中发挥的作用越来越大。然而，芯片在研制、生产和使用过程中产生的失效问题不可避免，通常可以采用备用电路对芯片中的失效位置进行修补处理。
现有技术，通常是通过备用电路分析步骤，获得所有备用电路的分派修补位置，基于上述修补位置以对失效位置进行修补。
然而，根据上述修补位置对失效位置进行熔断修补之后，时常会出现新的失效位置，而这些新的失效位置往往由于无法再进行修补而导致芯片报废，降低了芯片的制程良率。
发明内容
根据本公开的一方面，提供一种备用电路修补位置确定方法，所述方法包括：
确定待修补芯片的失效位置；
根据所述失效位置分派备用电路的初始修补位置；
根据所述初始修补位置确定潜在失效线路；
根据所述潜在失效线路确定预测修补位置；
根据所述失效位置和所述预测修补位置确定所述备用电路的最终修补位置。
根据本公开的一方面，提供一种备用电路修补位置确定装置，所述装置包括：
第一确定模块，用于确定待修补芯片的失效位置；
第二确定模块，用于根据所述失效位置分派备用电路的初始修补位置；
第三确定模块，用于根据所述初始修补位置确定潜在失效线路；
第四确定模块，用于根据所述潜在失效线路确定预测修补位置；
第五确定模块，用于根据所述失效位置和所述预测修补位置确定所述备用电路的最终修补位置。
根据本公开的一方面，提供一种电子设备，包括：
处理器；
存储器，用于存储一个或多个程序，当所述一个或多个程序被所述处理器执行时，使得所述处理器实现上述的备用电路修补位置确定方法。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性示出了根据本公开的示例性实施方式的一个芯片的结构示意图；
图2示意性示出了根据本公开的示例性实施方式的备用电路修补位置确定方法的流程示意图；
图3示意性示出了根据本公开的示例性实施方式的一种备用电路的初始修补位置示意图；
图4示意性示出了根据本公开的示例性实施方式的一种由初始修补位置的数量与距离属性确定潜在失效线路的位置示意图一；
图5示意性示出了根据本公开的示例性实施方式的一种由初始修补位置的数量与距离属性确定潜在失效线路的位置示意图二；
图6示意性示出了根据本公开的示例性实施方式的一种由失效位置属性确定潜在失效线路的位置示意图一；
图7示意性示出了根据本公开的示例性实施方式的一种由失效位置属性确定潜在失效线路的位置示意图二；
图8示出了图4中的潜在失效线路所在位置累计发生失效次数的示意图；
图9示出了图4中的由潜在失效线路确定的预测修补位置的示意图；
图10示意性示出了根据本公开的示例性实施方式的另一种由潜在失效线路确定的预测修补位置的示意图；
图11示意性示出了根据本公开的示例性实施方式的再一种由潜在失效线路确定的预测修补位置的示意图；
图12示意性示出了根据本公开的示例性实施方式的一种备用电路修补位置确定装置的框图；
图13示意性示出了根据本公开的示例性实施方式的一种集成电路修补方法的流程 示意图；
图14示意性示出了根据本公开的示例性实施方式中的电子设备的模块示意图；
图15示意性示出了根据本公开的示例性实施方式中的程序产品示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成区分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成区分/等之外还可存在另外的要素/组成区分/等。
在一个芯片中，通常包含有多个单元。举例来说，一个典型的动态随机存取存储器芯片有多达6千4百万个单元，这些单元可以按行和列的方式排列成主阵列，以便于通过字线和位线来寻址。
在典型的动态随机存取存储器芯片的制造过程中，可能会发生主阵列中一百万甚至数百万个单元存在着缺陷，即所谓的失效位置。为了提高芯片的成品率，通常会在芯片上制作备用电路，这些备用电路可以替代有缺陷的失效位置所在的字线或位线，从而旁路这些有缺陷的失效位置并使存储电路可以正常使用。
通常，芯片在研制、生产和使用过程中产生失效位置后，可以通过电路探针测试技术检测到所有的失效位置，通过备用电路分析步骤可以对芯片中的备用电路进行分派以修补上述的失效位置。
然而，通过熔断技术使用分派好的备用电路对上述失效位置进行修补之后，会出现新的失效位置，而这些新的失效位置在上述的电路探针测试技术检测的时候是有效位置。如果这些新的失效位置在出货前的最后产品测试中检测出来，则会直接将含有新的失效位置的芯片报废掉，如此则会降低产品的制程良率；如果这些新的失效位置在出货前未检出，有可能导致芯片在使用过程中发生故障，降低产品的品质，并且提高了售后保固成本，降低用户体验。
基于此，本示例性实施方式中提供了一种备用电路修补位置确定方法及装置、集成电路修补方法。
参照图1，示出了根据本公开的示例性实施方式的一个芯片的结构示意图，一个芯片100通常包括正常单元区110和备用单元区120，正常单元区110中含有较多的单元，正常单元区110包括两种正交的线路：字线111和位线112，其中，字线111为列线路，位线112为行线路。同时，在正常单元区110之外，芯片100上还设置有包含备用单元的备用单元区120，备用单元区120包括两种正交的笔直线路：备用字线121(Redundancy Word-Line，RWL)和备用位线122(Redundancy Bit-Line，RBL)，其中，备用字线121为列线路，用于修补字线111上的失效位置；备用位线122为行线路，用于修补位线112上的失效位置。
图2示意性示出了根据本公开的一些实施例的备用电路修补位置确定方法的流程示意图。参考图2，该备用电路修补位置确定方法可以包括以下步骤：
步骤S210，确定待修补芯片的失效位置。
步骤S220，根据失效位置分派备用电路的初始修补位置。
步骤S230，根据初始修补位置确定潜在失效线路。
步骤S240，根据潜在失效线路确定预测修补位置。
步骤S250，根据失效位置和预测修补位置确定备用电路的最终修补位置。
根据本示例实施例中的备用电路修补位置确定方法，一方面，通过确定待修补芯片的失效位置，并根据该失效位置可以初步分派备用电路的初始修补位置，而根据初始修补位置可以确定潜在失效线路，再根据潜在失效线路可以确定预测修补位置，其中该预测修补位置就是上述较多概率出现新的失效位置的位置，再根据失效位置和预测修补位置可以确定出备用电路的最终修补位置，从而可以将失效位置和可能出现新的失效位置的预测修补位置同时确定为需要修补的修补位置，以在新的失效位置出现之前即对其进行修补，从而可以减小新的失效位置出现的概率，提高芯片的制程良率，也可以提高芯片的品质，降低售后保固的成本，提升用户体验。另一方面，通过在进行修补之前即确定出预测修补位置，可以对失效位置和可能出现新的失效位置的位置同时进行一次性修补，从而可以节省修补工时，节约修补成本。又一方面，上述失效位置修补方案在执行一次修补后，可以提升失效位置被完全修补的概率，减少无法进行修补的情况发生的概率，进而有效提高芯片的制程良率，减少芯片报废的情况发生。
下面，将对本示例实施例中的备用电路修补位置确定方法进行进一步的说明。
在步骤S210中，确定待修补芯片的失效位置。
在本公开的一些示例性实施方式中，如图1所示，失效位置113是正常单元区110中的位置，而且该失效位置113在字线111或者位线112上，所以可以通过备用字线121替换字线111来对失效位置113进行修补，或者，也可以通过备用位线122替换位线112来对失效位置113进行修补，具体的修补方案可以参考现有的备用电路修补方案来确定。
在步骤S220中，根据失效位置分派备用电路的初始修补位置。
在实际应用中，对于多个失效位置位于同一个字线111上的情况，可以只需要一个备用字线121来修补，对于多个失效位置位于同一个位线112上的情况，可以只需要一个备用位线122来修补。
根据现有的备用电路修补方案初步确定出备用电路的初始修补位置，以确定待修补芯片100上的失效位置是由备用字线121来修补，还是由备用位线122来修补。作为一种示例，图3示意性示出了一种备用电路的初始修补位置示意图。参考图3，将正常单元区110划分为多个区域，例如，区域一210、区域二220、区域三230，并且，示例性地，假如区域一210中没有失效位置；区域二220中有多个失效位置，且在区域二220的其中一个位线221上含有3个失效点(Fail Bit，简称FB)、具体测试项目(简称Bin)为a、h，其中三个失效点分别为测试项目为a的一个失效点，测试项目为h的二个失效点，且三个失效点位置不相邻(Bin＝a，2h)，即失效点排列形状为单点；在区域二220的其中一个字线222上含有四个失效点，测试项目为a、b和i，其中四个失效点分别为测试项目为a的一个失效点，测试项目为b的一个失效点及测试项目为i的二个失效点，当四个是失效点中任意二个失效点相邻即失效点排列形状成线形，根据上述多个失效位置确定初始修补位置并将备用字线121分派给字线222、将备用位线122分派给位线221；区域三230中有一个失效位置，且该失效位置在位线231上，该位线231含有一个失效点，其中测试项目为a，该失效点为单点排列，因此分派了备用位线122至位线231并作为初始修补位置。
需要说明的是，此处确定的备用电路的初始修补位置不代表最终会用该已分派备用字线121或已分派备用位线122来修补上述列举的失效位置。
在步骤S230中，根据初始修补位置确定潜在失效线路。
在本公开的一些示例性实施方式中，潜在失效线路指的是如果按照步骤S220确定的初始修补位置对芯片100中的失效位置进行修补之后，可能出现新的失效位置的线路。本公开实施例通过确定潜在失效线路可以对新的失效位置出现的位置进行预测，以便于在正式进行修补的时候对潜在失效线路也进行修补，从而可以减小新的失效位置出现的概率，提高芯片的制程良率。
在实际应用中，根据初始修补位置确定潜在失效线路的方法可以有多种，例如，根据以往被报废芯片出现新的失效位置的历史数据来确定潜在失效线路，但是这种方法确定的潜在失效线路的分散性较大，且需要对每个线路进行数据统计，需要大量的数据支持。
可选的，在本公开的一些示例性实施方式中，根据初始修补位置确定潜在失效线路的步骤可以包括根据初始修补位置的修补位置属性确定潜在失效线路。通过根据初始修补位置的位置属性来确定潜在失效线路，无需以往的大量数据支持即可确定出新的失效位置可能出现的位置，从而可以提高潜在失效线路确定的效率。
在实际应用中，每一条已分派的备用电路的修补位置通常拥有许多信息，例如，产品组合类别、备用电路种类、失效点的数量、测试项目、失效位置排列形状等修补位置属性。
由于不同类别的芯片，产生新的失效位置的因素也有差异，因此需要按照芯片的属性对芯片进行分类，以按照类别对产品归类，确定产品组合类别。备用电路种类指的是备用字线121和备用位线122。失效点的数量指的是已分派备用字线121或已分派备用位线122中存在的失效点的数量。测试项目指的是在电路探针测试失效位置的时候，包含有多个测试项目，这些测试项目会依序检测每一个未检测或已通过上一个检测的单元，以确定该位置是否为失效位置。失效位置排列形状包括线形和单点，其中，线形指的是具有连续相邻的失效位置的形状，单点指的是无连续相邻的失效位置的形状。
在本公开的一些示例性实施方式中，提出了两种与上述位置信息相关联的修补位置属性：数量与距离属性、以及失效位置属性。其中，可以根据上述的初始修补位置的数量与距离属性确定潜在失效线路，也可以根据上述的初始修补位置的失效位置属性确定潜在失效线路。
其中，根据上述的初始修补位置的数量与距离属性确定潜在失效位置的步骤具体可以包括：对于同为字线或同为位线的初始修补位置，初始修补位置的数量大于或等于两条，且相邻的两条初始修补位置的距离小于或等于三个单元时，确定初始修补位置邻近的字线或位线为潜在失效线路。
也就是说，对于含有至少两个同为字线的备用字线121来修补的初始修补位置，相邻的两个初始修补位置的距离小于或等于三个单元时，确定初始修补位置邻近的字线为潜在失效线路；对于含有至少两个同为位线的备用位线122来修补的初始修补位置，相邻的两条初始修补位置的距离小于或等于三个单元时，确定初始修补位置邻近的位线为潜在失效线路。
作为一种示例，图4示意性示出了一种由初始修补位置的数量与距离属性确定潜在失效线路的位置示意图一。图4中含有由两个备用字线确定的初始修补位置(已分派备用电路位置)：初始修补位置一410和初始修补位置二420；初始修补位置一410和初始修补位置二420均为字线，且相距的距离L1为三个单元，此时，初始修补位置一410邻近的两个字线均为潜在失效线路，且分别标记为：潜在失效位置一430和潜在失效位置二440。同样的，初始修补位置二420邻近的两个字线均为潜在失效位置，且分别标记为：潜在失效位置三450和潜在失效位置四460。
作为一种示例，图5示意性示出了一种由初始修补位置的数量与距离属性确定潜在失效线路的位置示意图二。图5中含有由两个备用位线确定的初始修补位置：初始修补位置三510和初始修补位置四520；初始修补位置三510和初始修补位置四520均为位线，且分别位于两个相邻的区域，相距的距离L2为一个单元，此时，初始修补位置三510邻近的三个位线均为潜在失效位置。同样的，初始修补位置四520邻近的三个位线也均为潜在失效位置。
其中，根据上述的初始修补位置的失效位置属性确定潜在失效线路的步骤具体可以包括：将初始修补位置中的失效位置及其邻近未分派备用电路的位置所在的线路确定为潜在 失效线路。
作为一种示例，图6示意性示出了一种由失效位置属性确定潜在失效线路的位置示意图一。图6中含有一个由备用字线确定的初始修补位置610，该初始修补位置610中含有三个失效点620，每个失效点620与其邻近未分派备用电路的点构成一条位线630，则位线630被确定为潜在失效线路。
作为一种示例，图7示意性示出了一种由失效位置属性确定潜在失效线路的位置示意图二。图7中含有一个由备用位线确定的初始修补位置710，该初始修补位置710中含有两个失效点720，每个失效点720与其邻近未分派备用电路的点构成一条字线730，则字线730被确定为潜在失效线路。
上述的图4-图7只是根据初始修补位置的位置属性确定潜在失效线路的一种示例，其他的初始修补位置情况参照执行即可，本示例性实施方式对此不再一一列举。
在步骤S240中，根据潜在失效线路确定预测修补位置。
在本公开的一些示例性实施方式中，通过步骤S230获得潜在失效线路之后，可以在潜在失效线路的基础上再确定出预测修补位置，以确定出现新的失效位置概率较高的修补位置。
在本示例性实施方式中，可以根据潜在失效线路的累计失效概率确定预测修补位置，潜在失效线路的累计失效概率可以根据同类芯片的历史测试数据来确定，即根据同类芯片的历史测试数据确定潜在失效线路的累计失效次数，再根据累计失效次数确定累计失效概率，在累计失效概率大于预设值时，确定所述潜在失效线路为所述预测修补位置；即，在累计失效次数占芯片的累计失效总次数的比例大于预设值时，确定潜在失效线路为预测修补位置。
例如，图8示出了图4中的潜在失效线路所在位置累计发生失效的次数，其中，初始修补位置一410的测试项目Bin为a或i；初始修补位置二420的失效点的数量大于等于2，且多个失效点成线性排列，测试项目Bin为h。
图8中，在累计总发生12521次失效的情况下，潜在失效位置一430发生了1次、潜在失效位置二440发生了100次、潜在失效位置三450发生了130次、潜在失效位置四460发生了15次，也就是说，潜在失效位置一430发生的概率为0.008％，潜在失效位置二440发生的概率为0.799％，潜在失效位置三450发生的概率为1.038％，潜在失效位置四460发生的概率为0.120％。
在实际应用中，预设值的确定可以根据实际情况来确定，例如，预设值可以为0.5％-1％，此时，潜在失效位置二440和潜在失效位置三450大于上述预设值范围，因此，如图9所示将潜在失效位置二440和潜在失效位置三450确定为预测修补位置。本示例性实施方式对于预设值的具体取值不作特殊限定。
在本公开的一些示例性实施方式中，图9所示的待修补芯片中，产品组合类别为DDR4(Double Data Rate SDRAM4，双倍速率SDRAM4)，其中，SDRAM为Synchronous Dynamic  Random Access Memory同步动态随机存取内存；备用电路种类为备用字线，备用电路的数量为两个；每个已分派备用字线上的失效点的数量大于等于1、测试项目包含多个，例如a、i或h；失效位置排列形状：其中一个已分派备用字线上的失效点为任意形状，另一个已分派备用字线上的失效点成线形排列。两个备用电路相距三个点，预测修补位置为两个备用电路之间的线路，即潜在失效位置二440和潜在失效位置三450。
在本公开的一些示例性实施方式中，图10示意性示出了另一种由潜在失效线路确定的预测修补位置的示意图。图10所示的待修补芯片的属性是：产品组合类别为DDR4；备用电路种类为已分派备用位线1010，备用电路的数量为一个；已分派备用位线上的失效点的数量大于等于1，例如两个、测试项目包含多个，例如{a,i}，即包含a或i；失效位置排列形状为单点，也就是两个失效位置的间距L3大于1个单元。两个失效位置所在的位置及其邻近未分派备用电路的位置所在的线路确定为潜在失效线路1020。预测修补位置为两个潜在失效线路1020中，失效位置的测试项目属于属性中的测试项目{a,i}的线路，即Bin∈{a,i}的潜在失效线路五1030。
在本公开的一些示例性实施方式中，图11示意性示出了再一种由潜在失效线路确定的预测修补位置的示意图。图11所示的待修补芯片的属性是：产品组合类别为DDR4；备用电路种类为备用位线1110，备用电路的数量为1；已分派备用位线上的失效点的数量大于等于2，例如两个、测试项目属于{a}，即包含一个a；失效位置排列形状为线形，即两个失效位置的间距L4为1个单元点。两个失效位置所在的位置及其邻近未分派备用电路的位置所在的线路确定为潜在失效线路1120和1130，并且在潜在失效线路1120中，失效位置的测试项目不属于{a}，在潜在失效线路1130中，失效位置的测试项目属于{a}。但无论测试项目是否属于{a}，潜在失效线路1120和1130均为预测修补位置，即任意的测试项目的线路为预测修补位置。
在步骤S250中，根据失效位置和预测修补位置确定备用电路的最终修补位置。
在确定预测修补位置之后，可以将失效位置和预测修补位置同时确定为备用电路的最终修补位置，以在修补的时候即可同时对失效位置和可能出现新的失效位置的位置同时进行修补，以在新的失效位置出现之前即对其进行修补，从而可以减小新的失效位置出现的概率，提高芯片的制程良率，也可以提高芯片的品质，降低售后保固的成本，提升用户体验。
需要说明的是，尽管在附图中以特定顺序描述了本公开的实施例中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
此外，在本示例实施例中，还提供了一种备用电路修补位置确定装置。参考图12，该备用电路修补位置确定装置1200可以包括：第一确定模块1210、第二确定模块1220、第三确定模块1230、第四确定模块1240和第五确定模块1250，其中：
第一确定模块1210，可以用于确定待修补芯片的失效位置；
第二确定模块1220，可以用于根据失效位置分派备用电路的初始修补位置；
第三确定模块1230，可以用于根据初始修补位置确定潜在失效线路；
第四确定模块1240，可以用于根据潜在失效线路确定预测修补位置；
第五确定模块1250，可以用于根据失效位置和预测修补位置确定备用电路的最终修补位置。
上述中各备用电路修补位置确定装置1200的虚拟模块的具体细节已经在对应的备用电路修补位置确定方法中进行了详细的描述，因此此处不再赘述。
应当注意，尽管在上文详细描述中提及了备用电路修补位置确定装置的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
此外，上述附图仅是根据本公开的示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
此外，在本示例实施例中，还提供了一种集成电路修补方法。参考图13，该集成电路修补方法可以包括以下步骤：
步骤S1310，根据上述的备用电路修补位置确定方法确定备用电路的最终修补位置；
步骤S1320，根据最终修补位置对待修补芯片进行修补。
根据本示例实施例中的集成电路修补方法，一方面，通过备用电路修补位置确定方法确定出包含失效位置和可能出现新的失效位置的预测修补位置的最终修补位置，并根据该最终修补位置对待修补芯片进行修补，从而可以减小新的失效位置出现的概率，提高芯片的制程良率，也可以提高芯片的品质，降低售后保固的成本，提升用户体验。另一方面，通过在进行修补之前即确定出预测修补位置，可以对失效位置和可能出现新的失效位置的位置同时进行一次性修补，从而可以节省修补工时，节约修补成本。又一方面，上述失效位置修补方案在执行一次修补后，可以提升失效位置被完全修补的概率，减少无法进行修补的情况发生的概率，进而有效提高芯片的制程良率，减少芯片报废的情况发生。
在本公开的示例性实施例中，还提供了一种能够实现上述方法的电子设备。
所属技术领域的技术人员能够理解，本公开的实施例的各个方面可以实现为系统、方法或程序产品。因此，本公开的实施例的各个方面可以具体实现为以下形式，即：完全的硬件实施方式、完全的软件实施方式(包括固件、微代码等)，或硬件和软件方面结合的实施方式，这里可以统称为“电路”、“模块”或“系统”。
下面参照图14来描述根据本公开的这种实施方式的电子设备1400。图14显示的电子设备1400仅仅是一个示例，不应对本公开的实施例实施例的功能和使用范围带来任何限制。
如图14所示，电子设备1400以通用计算设备的形式表现。电子设备1400的组件可以包括但不限于：上述至少一个处理单元1410、上述至少一个存储单元1420、连接不同系统组件(包括存储单元1420和处理单元1410)的总线1430、显示单元1440。
其中，所述存储单元1420存储有程序代码，所述程序代码可以被所述处理单元1410执行，使得所述处理单元1410执行本说明书上述“示例性方法”部分中描述的根据本公开的各种示例性实施方式的步骤。例如，所述处理单元1410可以执行如图4中所示的步骤S210，确定待修补芯片的失效位置；步骤S220，根据所述失效位置分派备用电路的初始修补位置；步骤S230，根据所述初始修补位置确定潜在失效线路；步骤S240，根据所述潜在失效线路确定预测修补位置；步骤S250，根据所述失效位置和所述预测修补位置确定所述备用电路的最终修补位置；步骤S1320，根据最终修补位置对待修补芯片进行修补。
存储单元1420可以包括易失性存储单元形式的可读介质，例如随机存取存储单元(RAM)14201和/或高速缓存存储单元14202，还可以进一步包括只读存储单元(ROM)14203。
存储单元1420还可以包括具有一组(至少一个)程序模块14205的程序/实用工具14204，这样的程序模块14205包括但不限于：操作系统、一个或者多个应用程序、其它程序模块以及程序数据，这些示例中的每一个或某种组合中可能包括网络环境的实现。
总线1430可以为表示几类总线结构中的一种或多种，包括存储单元总线或者存储单元控制器、外围总线、图形加速端口、处理单元或者使用多种总线结构中的任意总线结构的局域总线。
电子设备1400也可以与一个或多个外部设备1470(例如键盘、指向设备、蓝牙设备等)通信，还可与一个或者多个使得用户能与该电子设备1400交互的设备通信，和/或与使得该电子设备1400能与一个或多个其它计算设备进行通信的任何设备(例如路由器、调制解调器等等)通信。这种通信可以通过输入/输出(I/O)接口1450进行。并且，电子设备1400还可以通过网络适配器1460与一个或者多个网络(例如局域网(LAN)，广域网(WAN)和/或公共网络，例如因特网)通信。如图所示，网络适配器1460通过总线1430与电子设备1400的其它模块通信。应当明白，尽管图中未示出，可以结合电子设备1400使用其它硬件和/或软件模块，包括但不限于：微代码、设备驱动器、冗余处理单元、外部磁盘驱动阵列、RAID系统、磁带驱动器以及数据备份存储系统等。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、终端装置、或者网络设备等)执行根据本公开实施方式的方法。
在本公开的示例性实施例中，还提供了一种计算机可读存储介质，其上存储有能够实现本说明书上述方法的程序产品。在一些可能的实施方式中，本公开的实施例的各个方面还可以实现为一种程序产品的形式，其包括程序代码，当所述程序产品在终端设备上运行时，所述程序代码用于使所述终端设备执行本说明书上述“示例性方法”部分中描述的根据本公开的各种示例性实施方式的步骤。
参考图15所示，描述了根据本公开的实施例的实施方式的用于实现上述方法的程序产品1500，其可以采用便携式紧凑盘只读存储器(CD-ROM)并包括程序代码，并可以在终端设备，例如个人电脑上运行。然而，本公开的实施例的程序产品不限于此，在本文件中，可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
所述程序产品可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以为但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了可读程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。可读信号介质还可以是可读存储介质以外的任何可读介质，该可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于无线、有线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言的任意组合来编写用于执行本公开的实施例操作的程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、C++等，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。在涉及远程计算设备的情形中，远程计算设备可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算设备，或者，可以连接到外部计算设备(例如利用因特网服务提供商来通过因特网连接)。
此外，上述附图仅是根据本公开的示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实 施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (16)

  1. 一种备用电路修补位置确定方法，所述方法包括：
    确定待修补芯片的失效位置；
    根据所述失效位置分派备用电路的初始修补位置；
    根据所述初始修补位置确定潜在失效线路；
    根据所述潜在失效线路确定预测修补位置；
    根据所述失效位置和所述预测修补位置确定所述备用电路的最终修补位置。
  2. 根据权利要求1所述的备用电路修补位置确定方法，其中，所述根据所述初始修补位置确定潜在失效线路的步骤，包括：
    根据所述初始修补位置的位置属性确定所述潜在失效线路。
  3. 根据权利要求2所述的备用电路修补位置确定方法，其中，所述根据所述初始修补位置的位置属性确定所述潜在失效线路的步骤，包括：
    根据所述初始修补位置的数量与距离属性和/或失效位置属性确定所述潜在失效线路。
  4. 根据权利要求3所述的备用电路修补位置确定方法，其中，所述根据所述初始修补位置的数量与距离属性确定所述潜在失效线路的步骤，包括：
    对于同为字线或同为位线的初始修补位置，所述初始修补位置的数量大于或等于两条，且相邻的两条所述初始修补位置的距离小于或等于三个单元时，确定所述初始修补位置邻近的字线或位线为所述潜在失效线路。
  5. 根据权利要求3所述的备用电路修补位置确定方法，其中，所述根据所述初始修补位置的失效位置属性确定所述潜在失效线路的步骤，包括：
    将所述初始修补位置中的失效位置及其邻近未分派备用电路的位置所在的线路确定为所述潜在失效线路。
  6. 根据权利要求1所述的备用电路修补位置确定方法，其中，所述根据所述潜在失效线路确定预测修补位置的步骤，包括；
    根据所述潜在失效线路的累计失效概率确定所述预测修补位置。
  7. 根据权利要求6所述的备用电路修补位置确定方法，其中，所述根据所述潜在失效线路的累计失效概率确定预测修补位置的步骤，包括：
    根据同类所述芯片的历史测试数据确定所述潜在失效线路的所述累计失效次数；
    在所述累计失效次数占所述芯片的累计失效总次数的比例大于预设值时，确定所述潜在失效线路为所述预测修补位置。
  8. 根据权利要求2所述的备用电路修补位置确定方法，其中，所述位置属性包括：产品组合类别、备用电路种类、失效点的数量、测试项目、失效位置排列形状。
  9. 根据权利要求8所述的备用电路修补位置确定方法，其中，所述根据所述初始修补位置的位置属性确定所述潜在失效线路的步骤，包括：
    在所述产品组合类别为DDR4、所述备用电路种类为备用位线，所述失效点的数量大于等于1、所述测试项目包含多个、所述失效位置排列形状为单点的时候，将所述失效位置所在的位置及其邻近未分派备用电路的位置所在的线路确定为所述潜在失效线路。
  10. 根据权利要求9所述的备用电路修补位置确定方法，其中，所述根据所述潜在失效线路确定预测修补位置的步骤，包括；
    所述预测修补位置为所述潜在失效线路的测试项目属于所述初始修补位置的测试项目的线路。
  11. 根据权利要求8所述的备用电路修补位置确定方法，其中，所述根据所述初始修补位置的位置属性确定所述潜在失效线路的步骤，包括：
    在所述产品组合类别为DDR4、所述备用电路种类为备用位线，所述失效点的数量为1、所述测试项目为一个、所述失效位置排列形状为线形的时候，将所述失效位置所在的位置及其邻近未分派备用电路的位置所在的线路确定为所述潜在失效线路。
  12. 根据权利要求11所述的备用电路修补位置确定方法，其中，所述根据所述潜在失效线路确定预测修补位置的步骤，包括；
    所述预测修补位置为所述潜在失效线路的测试项目属于任意测试项目的线路。
  13. 一种备用电路修补位置确定装置，所述装置包括：
    第一确定模块，用于确定待修补芯片的失效位置；
    第二确定模块，用于根据所述失效位置分派备用电路的初始修补位置；
    第三确定模块，用于根据所述初始修补位置确定潜在失效线路；
    第四确定模块，用于根据所述潜在失效线路确定预测修补位置；
    第五确定模块，用于根据所述失效位置和所述预测修补位置确定所述备用电路的最终修补位置。
  14. 一种集成电路修补方法，所述方法包括：
    根据权利要求1所述的备用电路修补位置确定方法确定所述备用电路的最终修补位置；
    根据所述最终修补位置对待修补芯片进行修补。
  15. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1所述的备用电路修补位置确定方法。
  16. 一种电子设备，，包括：
    处理器；
    存储器，用于存储一个或多个程序，当所述一个或多个程序被所述处理器执行时，使得所述处理器实现如权利要求1所述的备用电路修补位置确定方法。
PCT/CN2021/109067 2020-11-26 2021-07-28 备用电路修补位置确定方法及装置、集成电路修补方法 WO2022110858A1 (zh)

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