WO2022041956A1 - 一种晶圆探测数据的处理方法和计算机可读存储介质 - Google Patents

一种晶圆探测数据的处理方法和计算机可读存储介质 Download PDF

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WO2022041956A1
WO2022041956A1 PCT/CN2021/100627 CN2021100627W WO2022041956A1 WO 2022041956 A1 WO2022041956 A1 WO 2022041956A1 CN 2021100627 W CN2021100627 W CN 2021100627W WO 2022041956 A1 WO2022041956 A1 WO 2022041956A1
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bit
information
failed
repair
bits
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PCT/CN2021/100627
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English (en)
French (fr)
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仰蕾
陈予郎
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长鑫存储技术有限公司
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Priority to US17/455,913 priority Critical patent/US11837309B2/en
Publication of WO2022041956A1 publication Critical patent/WO2022041956A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
    • G06F18/20—Analysing
    • G06F18/24—Classification techniques
    • G06F18/241—Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/14—Details relating to CAD techniques related to nanotechnology

Definitions

  • the present disclosure relates to the technical field of wafer manufacturing, and in particular, to a method for processing wafer detection data and a computer-readable storage medium.
  • Fail Bits In the wafer probing (circuit probing) stage, all the locations of Fail Bits (Fail Bits, hereinafter referred to as FBs) are repaired, and the present disclosure refers to the repair of such FBs as "general repair".
  • non-FBs positions may also be repaired.
  • new failed bits may appear in non-FBs positions. Therefore, these non-FBs positions will be patched together after general patching, which is called “predictive patching”.
  • the purpose of the present disclosure is to provide a method for processing wafer detection data and a computer-readable storage medium, to at least to a certain extent overcome the problem of low detection efficiency of failed bits of wafers in the related art.
  • a method for processing wafer probing data including: determining a new failed bit generated in a completed wafer probing process; obtaining a repair record of the newly failed bit, and the new failed bit repair records of adjacent bits of At least one of the following; classifying and learning according to the attribute information to obtain a failed bit prediction model; and predicting the failed bit to be probed on the wafer through the failed bit prediction model.
  • parsing the patch record to determine the attribute information of the newly failed bit and the attribute information of the adjacent bit includes: parsing the patch record to detect whether the newly failed bit has been repaired, and detecting adjacent Whether the bit has been repaired; if it is determined according to the repair record that the new failed bit has not been repaired, and it is determined according to the repair record that the adjacent bit has not been repaired, the position information and crystal of the newly failed bit in the attribute information are obtained. Circle detection process.
  • performing classification learning according to attribute information to obtain a failed bit prediction model includes: performing a correlation analysis on the position information of the newly failed bit and the wafer detection process; or, performing an analysis on the unit of the newly failed bit Perform mining and analysis on the graph; or, perform a wafer map classification analysis on the wafer to which the new failed bit belongs; and obtain a failed bit prediction model according to the analysis result.
  • parsing the repair record to determine the attribute information of the newly failed bit and the attribute information of the adjacent bit further includes: parsing the repair record to detect whether the newly failed bit has been repaired; If the record determines that the new failed bit is repaired, the location information of the new failed bit in the attribute information and the spare circuit information for repairing the new failed bit are determined.
  • performing classification learning according to the attribute information to obtain a prediction model for a failed bit further includes: performing a backup circuit selection analysis on the position information of the newly failed bit and the backup circuit information for repairing the newly failed bit ; Obtain the failure bit prediction model according to the analysis result.
  • parsing the patch record to determine the attribute information of the newly failed bit and the attribute information of the adjacent bit further includes: parsing the patch record to detect whether the newly failed bit has been repaired, and detecting the corresponding Whether the adjacent bit has been repaired; if it is determined according to the repair record that the newly failed bit has not been repaired, and it is determined according to the repair record that the adjacent bit has been repaired, then determine the location information and usage of the adjacent bit in the attribute information. Spare circuit information for repairing adjacent bits.
  • performing classification learning according to the attribute information to obtain a prediction model for a failed bit further includes: comparing the position information of the failed bit and the repair position in the spare circuit information for repairing adjacent bits associated probability analysis, or mining analysis of repair processing rules; obtain the failure bit prediction model according to the analysis results.
  • the location information includes at least one of coordinate information of bits, number information of bits, and types of wafer products.
  • the spare circuit information includes at least one of a spare circuit version, a repair location, a repair detection item, a repair bit number, and a spare circuit information version.
  • the method for processing wafer detection data further includes: creating a reference coordinate system with a coordinate of a bit at the lower left corner of the wafer as an origin coordinate; determining the new failure according to the reference coordinate system
  • the abscissa of the row where the bit is located is x
  • the ordinate position of the column where the new invalid bit is determined is y
  • the x and the y are both positive integers; it is determined that all the columns whose abscissa is x-1 are The bits and all bits of the column whose abscissa is determined to be x+1 are the adjacent bits.
  • the method for processing wafer detection data further includes: creating a reference coordinate system with a coordinate of a bit at the lower left corner of the wafer as an origin coordinate; determining the new failure according to the reference coordinate system
  • the abscissa of the row where the bit is located is x
  • the ordinate position of the column where the new invalid bit is determined is y
  • the x and the y are both positive integers
  • determine the block to which the new invalid bit belongs The sequence number is N
  • the abscissa of the left boundary bit of the block to which the new invalid bit belongs is determined as
  • the abscissa of the right boundary bit of the block to which the new invalid bit belongs is determined as Determine that the ordinate is y-1 and the abscissa is to All bits of , and the ordinate is y+1 and the abscissa is to All bits of are the adjacent bits.
  • the method for processing wafer detection data further includes: creating a reference coordinate system with a coordinate of a bit at the lower left corner of the wafer as an origin coordinate; determining the new failure according to the reference coordinate system
  • the abscissa of the row where the bit is located is x
  • the ordinate position of the column where the new invalid bit is determined is y
  • the x and the y are both positive integers; determine the block to which the new invalid bit belongs
  • the sequence number of the left side block is N-1; it is determined that the sequence number of the right side block of the block to which the new invalid bit belongs is N+1; the abscissa of the left boundary bit of the left side block is determined determined as The abscissa of the right boundary bit of the left block is determined as The abscissa of the left boundary bit of the right block is determined as The abscissa of the right boundary bit of the right block is determined as Determine that the ordinate is y and the abscissa is to
  • predicting a failed bit to be probed on a wafer by using a failed bit prediction model includes: collecting first repair information of a repaired new failed bit and the repaired new failed bit The second repair information of the adjacent bits of the cell; the first repair information and the second repair information are parsed and input to the failure bit prediction model for prediction; determined according to the output result of the failure bit prediction model Invalid bit information.
  • parsing the first patch information and the second patch information to be input into the failed bit prediction model for prediction includes: parsing both the first patch information and the second patch information If it is not repaired, the output result of the failure bit prediction model is a test process phenomenon; if the first repair information is analyzed as being repaired by the backup circuit, and the second repair information is not repaired, then the failure bit prediction model is The output result of is a failure bit phenomenon; if the first repair information is not repaired, and the second repair information is repaired by a backup circuit, the output result of the failure bit prediction model is a repair phenomenon.
  • determining the failure bit information according to the output result of the failure bit prediction model includes: parsing the output result; if parsing the output result includes the test process phenomenon, The first correspondence between the pre-stored test process phenomenon and the failed bits determines the information of the failed bits, and the test process phenomenon includes the phenomenon that the wafer fails after the test process is performed; if the output result is parsed If the failure bit phenomenon is included, then the failure bit information is determined according to a preset second correspondence between the failure bit phenomenon and the failure bit, and the failure bit phenomenon includes the wafer passing through the backup circuit.
  • the repaired bit has a phenomenon of failure; if the analysis output result includes the repair phenomenon, the failed bit information is determined according to the preset third correspondence between the repair phenomenon and the failed bit, and the repaired Phenomena include failures of adjacent bits of the wafer repaired by the spare circuit.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements any one of the above methods for processing wafer detection data.
  • the wafer detection data processing solution provided by the embodiments of the present disclosure obtains the repair records of the new failed bits and adjacent bits generated during the wafer detection process, and performs classification learning based on the above two types of repair records to The failed bits are predicted according to the results of classification learning, so as to improve the efficiency, wafer yield and yield of failed bit detection of wafers, that is, an efficient and highly reliable processing solution for wafer detection data is provided.
  • FIG. 1A shows a schematic diagram of a wafer probing process in an embodiment of the present disclosure
  • FIG. 1B shows a schematic diagram of another wafer probing process in an embodiment of the present disclosure
  • FIG. 1C shows a schematic diagram of another wafer probing process in an embodiment of the present disclosure
  • FIG. 2 shows a schematic flowchart of a method for processing wafer detection data in an embodiment of the present disclosure
  • FIG. 3 shows a schematic flowchart of another method for processing wafer detection data in an embodiment of the present disclosure
  • FIG. 4 shows a schematic flowchart of another method for processing wafer detection data in an embodiment of the present disclosure
  • FIG. 5 shows a schematic flowchart of another method for processing wafer detection data in an embodiment of the present disclosure
  • FIG. 6 shows a schematic flowchart of another method for processing wafer detection data in an embodiment of the present disclosure
  • FIG. 7 shows a schematic flowchart of another method for processing wafer detection data in an embodiment of the present disclosure
  • FIG. 8 shows a schematic flowchart of another method for processing wafer detection data in an embodiment of the present disclosure
  • FIG. 9 shows a schematic flowchart of another method for processing wafer detection data in an embodiment of the present disclosure.
  • FIG. 10 shows a schematic block diagram of another apparatus for processing wafer detection data in an embodiment of the present disclosure
  • FIG. 11 shows a schematic block diagram of an electronic device in an embodiment of the present disclosure.
  • FIG. 12 shows a schematic diagram of a computer-readable storage medium in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • the repair records of the new failed bits and the adjacent bits generated during the wafer detection process are obtained, and classification learning is performed based on the above two types of repair records, so as to classify the failed bits according to the results of classification learning.
  • the prediction is to improve the efficiency, wafer yield and yield of failed bit detection of wafers, that is, to provide an efficient and highly reliable processing solution for wafer detection data.
  • the wafer detection data processing solution provided by the embodiments of the present disclosure involves technologies such as wafer detection and classification learning, and is specifically described by the following embodiments.
  • grooves 106 are arranged between the functional areas on each wafer for partitioning, and are divided into a plurality of sections (Sections).
  • Other valid bits, causing other valid bits to become new fail bits (New Fail Bit, NFBs) can be called ONFB (Observed NFB, observed NFB).
  • the NFBs may be caused by patching, or may be caused by a failed bit in the original patching location 108 .
  • These bits which may affect other valid bits to become new invalid bits after being repaired, are referred to in the present disclosure as "relevant bits 104".
  • the position of the new failed bit 102 is represented by (x, y), and the relevant bit 104 is mainly determined according to the new failed bit 102 and the repaired position 108 Bits, specifically, relevant bits 104 include the following positions:
  • the step of determining an adjacent bit as the relevant bit 104 includes: taking the coordinate of a bit at the lower left corner of the wafer as the origin coordinate, creating a reference coordinate According to the reference coordinate system, it is determined that the abscissa of the row where the new invalid bit is located is x, and the ordinate position of the column where the new invalid bit is determined to be y, and the x and the y are both positive integers; It is determined that all the bits of the column whose abscissa is x-1 and all the bits of the column whose abscissa is x+1 are the adjacent bits.
  • the step of determining an adjacent bit as the relevant bit 104 includes: using the coordinates of a bit at the lower left corner of the wafer as the origin coordinates, creating a reference Coordinate system; according to the reference coordinate system, it is determined that the abscissa of the row where the new invalid bit is located is x, and the ordinate position of the column where the new invalid bit is located is y, and both the x and the y are positive integers ; Determine that the sequence number of the block to which the new failure bit belongs is N; The abscissa of the left boundary bit of the block to which the new failure bit belongs is determined as The abscissa of the right boundary bit of the block to which the new invalid bit belongs is determined as Determine that the ordinate is y-1 and the abscissa is to All bits of , and the ordinate is y+1 and the abscissa is to All bits of are the adjacent bits.
  • the step of determining the adjacent bit as the relevant bit 104 includes: taking the coordinate of a bit at the lower left corner of the wafer as the origin coordinate, creating a reference Coordinate system; according to the reference coordinate system, it is determined that the abscissa of the row where the new invalid bit is located is x, and the ordinate position of the column where the new invalid bit is located is y, and both the x and the y are positive integers Determine that the sequence number of the left block of the block to which the new invalid bit belongs is N-1; Determine that the sequence number of the right block of the block to which the new invalid bit belongs is N+1; The abscissa of the left boundary bit of the left block is determined as The abscissa of the right boundary bit of the left block is determined as The abscissa of the left boundary bit of the right block is determined as The abscissa of the right boundary bit of the right block is determined as Determine that the ordinate is
  • the origin of the xy-axis is determined by the reference of the lower left corner of the wafer, and N is an integer greater than 1. It is assumed that the new invalid bit 102 is in Section N, and y max refers to the highest position in the y direction of the Section where the new invalid bit 102 is located, refers to the lowest position in the x direction in Section N, Refers to the highest position in the x direction in Section N.
  • the processing method of wafer probing data according to this embodiment of the present disclosure will be described below with reference to FIG. 2 .
  • the processing method of wafer probing data shown in FIG. 2 is only an example, and should not impose any limitation on the function and scope of use of the embodiments of the present disclosure.
  • the method for processing wafer detection data of the present disclosure includes:
  • Step S202 determining a new invalid bit generated in the completed wafer probing process.
  • step S204 the repair record of the newly failed bit and the repair record of the adjacent bits of the newly failed bit are acquired.
  • the repair records include but are not limited to the following:
  • Bin A collection of test items.
  • Fail Bit Count The number of failed bits repaired.
  • Redundant ID the spare circuit number.
  • Step S206 parse the repair record to determine the attribute information of the newly failed bit and the attribute information of the adjacent bit, the attribute information includes the position information, the spare circuit information, the cell pattern of the newly failed bit, and at least one of the wafer detection processes. A sort of.
  • the location data includes but is not limited to the following:
  • id the number of the NFB.
  • Chip location The (x, y) position of the chip bit.
  • Bank id bank number. Inside the chip, the data in the memory is written into a large matrix in units of bits.
  • the matrix contains multiple functional units (cells), which are represented by row coordinates (x-axis) and The column coordinate (y-axis) is used for addressing, and this matrix is the logical bank of the chip.
  • step S208 classification learning is performed according to the attribute information to obtain a failure bit prediction model.
  • Step S210 predicting the failed bits to be probed on the wafer by the failed bit prediction model.
  • the adjacent bits of the newly expired bits are related bits
  • the detection data is classified by the repair records of the newly aged bits and the repair records of the adjacent bits, and based on the classified data Model training is performed, and the trained model is used to predict new failed bits, which is beneficial to improve detection efficiency, reliability, yield and yield.
  • parsing the repair record to determine the attribute information of the newly failed bit and the attribute information of the adjacent bit includes:
  • Step S3062 parsing the repair record to detect whether the newly failed bit has been repaired, and whether the adjacent bit has been repaired.
  • step S3064 if it is determined according to the repair record that the newly failed bit has not been repaired, and it is determined that the adjacent bit has not been repaired according to the repair record, the position information of the newly failed bit in the attribute information and the wafer detection process are obtained.
  • this detection result is defined as phenomenon 1
  • the failure causes are classified and learned from the perspective of position information and wafer detection process, so as to Predicting the location of new failed bits based on the wafer probing process is beneficial to improve the efficiency and reliability of wafer probing.
  • the classification learning is performed according to the attribute information to obtain the failure bit prediction model including:
  • Step S4082 perform correlation analysis on the position information of the newly failed bit and the wafer detection process.
  • Step S4084 mining and analyzing the cell graph of the newly failed bit.
  • step S4086 a wafer map classification analysis is performed on the wafer to which the newly failed bit belongs.
  • Step S4088 obtaining a failure bit prediction model according to the analysis result.
  • steps S4082, S4084 and S4086 are three independent classification learning processes, that is, analysis is performed based on position information and wafer detection process, cell pattern and wafer pattern classification, respectively, to obtain failure bit predictions
  • the model in the subsequent wafer detection process, can predict new failed bits based on position information, wafer detection process, cell pattern and wafer map classification, so as to improve the reliability and accuracy of wafer detection efficiency, which is conducive to improving the Yield and yield of wafer products.
  • parsing the repair record to determine the attribute information of the newly failed bit and the attribute information of the adjacent bit also includes:
  • Step S5062 parsing the repair record to detect whether the new invalid bit has been repaired.
  • Step S5064 if it is determined according to the repair record that the new failed bit has been repaired, determine the location information of the new failed bit in the attribute information and the spare circuit information for repairing the new failed bit.
  • the inventor analyzes that the main reason for the occurrence of the new failed bit may be the introduction of a backup circuit to repair the new failed bit , so the spare circuit information for patching new failed bits is obtained for analysis.
  • performing classification learning according to the attribute information to obtain the failure bit prediction model further includes:
  • Step S6082 performing a backup circuit selection analysis on the position information of the newly failed bit and the backup circuit information for repairing the newly failed bit.
  • Step S6084 obtaining the failure bit prediction model according to the analysis result.
  • the characteristics of the backup circuit that are more likely to cause the occurrence of the new failed bit can be determined, so as to improve the backup circuit. Improve overall wafer reliability.
  • the information of the backup circuit is input into the prediction model to predict the position where a new failed bit may occur, thereby improving the reliability and accuracy of wafer detection, and increasing the wafer yield and yield.
  • parsing the repair record to determine the attribute information of the newly failed bit and the attribute information of the adjacent bit also includes:
  • Step S7062 parsing the repair record to detect whether the new failed bit has been repaired, and whether the adjacent bit has been repaired.
  • Step S7064 if it is determined according to the repair record that the new failed bit has not been repaired, and it is determined that the adjacent bit has been repaired according to the repair record, then determine the position information of the adjacent bit in the attribute information and the information used for the repair. Spare circuit information for patching adjacent bits.
  • this detection result is defined as phenomenon 3
  • the inventor analyzes that the main reason for the generation of adjacent bits is that the introduction of The spare circuit repairs adjacent bits, therefore, the spare circuit information is obtained for analysis.
  • performing classification learning according to the attribute information to obtain the failure bit prediction model further includes:
  • Step S8082 analyze the association probability between the position information of the adjacent bit and the repair position in the spare circuit information for repairing the adjacent bit, or perform mining analysis of the repair processing rule.
  • Step S8084 obtaining the failure bit prediction model according to the analysis result.
  • the characteristics of the spare circuit that are more likely to cause the occurrence of adjacent bits can be determined, so as to improve the spare circuit and improve the wafer overall reliability of the chip.
  • the spare circuit information is input into the prediction model to predict the position where adjacent bits may appear, thereby improving the reliability and accuracy of wafer detection and increasing wafer yield and yield.
  • the location information includes at least one of coordinate information of bits, number information of bits, and wafer product types.
  • the spare circuit information includes at least one of a spare circuit version, a repair location, a repair detection item, a repair bit number, and a spare circuit information version.
  • predicting a failed bit to be probed on a wafer by using a failed bit prediction model includes: collecting first repair information of a repaired new failed bit and the repaired new failed bit The second repair information of the adjacent bits of the cell; the first repair information and the second repair information are parsed and input to the failure bit prediction model for prediction; determined according to the output result of the failure bit prediction model Invalid bit information.
  • parsing the first patch information and the second patch information to be input into the failed bit prediction model for prediction includes: parsing both the first patch information and the second patch information If it is not repaired, the output result of the failure bit prediction model is a test process phenomenon; if the first repair information is analyzed as being repaired by the backup circuit, and the second repair information is not repaired, then the failure bit prediction model is The output result of is a failure bit phenomenon; if the first repair information is not repaired, and the second repair information is repaired by a backup circuit, the output result of the failure bit prediction model is a repair phenomenon.
  • determining the failure bit information according to the output result of the failure bit prediction model includes: parsing the output result; if parsing the output result includes the test process phenomenon, The first correspondence between the pre-stored test process phenomenon and the failed bits determines the information of the failed bits, and the test process phenomenon includes the phenomenon that the wafer fails after the test process is performed; if the output result is parsed If the failure bit phenomenon is included, then the failure bit information is determined according to a preset second correspondence between the failure bit phenomenon and the failure bit, and the failure bit phenomenon includes the wafer passing through the backup circuit.
  • the repaired bit has a phenomenon of failure; if the analysis output result includes the repair phenomenon, the failed bit information is determined according to the preset third correspondence between the repair phenomenon and the failed bit, and the repaired Phenomena include failures of adjacent bits of the wafer repaired by the spare circuit.
  • the processing scheme of wafer probing data includes but is not limited to the following data processing, writing and reading processes:
  • the source data includes NFB Data (new failed bit data) and FU Data (full repair record data), but is not limited to this.
  • Step S902 acquiring an NFB.
  • Step S904 retrieving repair information.
  • step S906 it is judged whether the phenomenon 1 is met. If yes, go to step S910, if not, go to step S908.
  • step S908 it is judged whether the phenomenon 2 is met. If yes, go to step S912, if not, go to step S914.
  • Step S910 outputting the sample data of the test process phenomenon.
  • Step S912 outputting the sample data of the failure bit phenomenon.
  • Step S914 outputting the repair phenomenon sample data.
  • Step S916 it is judged whether it is the last NFB on the wafer, if so, the process ends, and if not, step S902 is executed.
  • Valid sample analysis includes: the test process phenomenon sample data, that is, the new invalid bit data NFB Data that conforms to phenomenon 1; Record data FU Data; repair phenomenon sample data, that is, the new invalid bit metadata NFB Data conforming to phenomenon 3 and the corresponding repair record data FU Data.
  • Machine learning system correlation analysis between test process and failed bits; image mining analysis of failed bit cells; wafer map classification analysis.
  • the core processing steps of the wafer detection data processing solution according to the present disclosure are as follows:
  • Output test process phenomenon sample data output ONFB information to the test process phenomenon sample database.
  • Outputting the repairing phenomenon sample data outputting information such as ONFB information, the repairing information of the relevant bit position and the spare circuit number used for the repairing and other information to the repairing phenomenon sample database.
  • the processing apparatus 1000 for wafer probing data according to this embodiment of the present disclosure will be described below with reference to FIG. 10 .
  • the apparatus 1000 for processing wafer probing data shown in FIG. 10 is only an example, and should not impose any limitations on the functions and scope of use of the embodiments of the present disclosure.
  • the apparatus 1000 for processing wafer detection data includes: an acquisition module 1002 , an analysis module 1004 and a prediction module 1006 .
  • the acquiring module 1002 is used for determining the new invalid bits generated in the completed wafer probing process.
  • the obtaining module 1002 is further configured to obtain the repair record of the newly failed bit and the repair record of the adjacent bits of the newly failed bit.
  • the parsing module 1004 is used for parsing the repair record to determine the attribute information of the newly failed bit and the attribute information of the adjacent bit, where the attribute information includes position information, spare circuit information, the cell pattern of the newly failed bit and the wafer detection process at least one of them.
  • the parsing module 1004 is further configured to perform classification learning according to the attribute information to obtain a failure bit prediction model.
  • the prediction module 1006 is used for predicting the failed bits to be probed on the wafer by using the failed bit prediction model.
  • the electronic device 1100 according to this embodiment of the present disclosure is described below with reference to FIG. 11 .
  • the electronic device 1100 shown in FIG. 11 is only an example, and should not impose any limitation on the function and scope of use of the embodiments of the present disclosure.
  • electronic device 1100 takes the form of a general-purpose computing device.
  • Components of the electronic device 1100 may include, but are not limited to, the above-described processing unit 1110, the above-described storage unit 1120, and a bus 1130 connecting components of different wafer probing data processing systems (including the storage unit 1120 and the processing unit 1110).
  • the storage unit stores program codes, which can be executed by the processing unit 1110, so that the processing unit 1110 performs the steps according to various exemplary embodiments of the present disclosure described in the above-mentioned "Exemplary Methods" section of this specification.
  • the processing unit 1110 may perform all the steps shown in FIGS. 2 to 8 , as well as other steps defined in the method for processing wafer probing data of the present disclosure.
  • the storage unit 1120 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 11201 and/or a cache storage unit 11202 , and may further include a read only storage unit (ROM) 11203 .
  • RAM random access storage unit
  • ROM read only storage unit
  • the storage unit 1120 may also include a program/utility 11204 having a set of program modules 11205 including, but not limited to, a processing system that manipulates wafer probing data, one or more application programs, other program modules, and programs Data, each or some combination of these examples may include an implementation of a network environment.
  • a program/utility 11204 having a set of program modules 11205 including, but not limited to, a processing system that manipulates wafer probing data, one or more application programs, other program modules, and programs Data, each or some combination of these examples may include an implementation of a network environment.
  • the bus 1130 may be representative of one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local area using any of a variety of bus structures bus.
  • the electronic device 1100 may also communicate with one or more external devices 1140 (eg, keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device, and/or The electronic device 1100 can communicate with any device (eg, router, modem, etc.) that communicates with one or more other computing devices. Such communication may occur through input/output (I/O) interface 1150 .
  • external devices 1140 eg, keyboards, pointing devices, Bluetooth devices, etc.
  • I/O input/output
  • the electronic device 1100 may communicate with one or more networks (eg, a local area network (LAN), a wide area network (WAN), and/or a public network such as the Internet) through a network adapter 1160 .
  • network adapter 1160 communicates with other modules of electronic device 1100 via bus 1130 .
  • other hardware and/or software modules may be used in conjunction with the electronics, including but not limited to: microcode, device drivers, redundant processing units, arrays of external disk drives, RAID for wafer probing data Processing systems, tape drives, and data backup processing systems that store wafer probing data, etc.
  • the exemplary embodiments described herein may be implemented by software, or may be implemented by software combined with necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure may be embodied in the form of software products, and the software products may be stored in a non-volatile storage medium (which may be CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to cause a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to an embodiment of the present disclosure.
  • a computing device which may be a personal computer, a server, a terminal device, or a network device, etc.
  • a computer-readable storage medium on which a program product capable of implementing the above-described method of the present specification is stored.
  • various aspects of the present disclosure can also be implemented in the form of a program product, which includes program code, when the program product is run on a terminal device, the program code is used to cause the terminal device to execute the above-mentioned instructions in this specification. Steps according to various exemplary embodiments of the present disclosure are described in the "Example Methods" section.
  • a computer program 1200 for implementing the above method according to an embodiment of the present disclosure is described, which can adopt a portable compact disk read only memory (CD-ROM) and include program codes, and can be used in a terminal device, For example running on a personal computer.
  • CD-ROM compact disk read only memory
  • the program product of the present disclosure is not limited thereto, and in this document, a readable storage medium may be any tangible medium that contains or stores a program that can be used by a processing system, apparatus, or device instructing the execution of wafer probing data or used in conjunction with it.
  • a computer readable signal medium may include a propagated data signal in baseband or as part of a carrier wave with readable program code embodied thereon. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a readable signal medium can also be any readable medium other than a readable storage medium that can transmit, propagate, or transmit for use by or in conjunction with a processing system, apparatus, or device that executes instructions to execute wafer probing data. program.
  • Program code embodied on a readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
  • Program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages—such as Java, C++, etc., as well as conventional procedural Programming Language - such as the "C" language or similar programming language.
  • the program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server execute on.
  • the remote computing device may be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (eg, using an Internet service provider business via an Internet connection).
  • LAN local area network
  • WAN wide area network
  • an external computing device eg, using an Internet service provider business via an Internet connection
  • modules or units of the apparatus for action performance are mentioned in the above detailed description, this division is not mandatory. Indeed, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units to be embodied.
  • the exemplary embodiments described herein may be implemented by software, or may be implemented by software combined with necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure may be embodied in the form of software products, and the software products may be stored in a non-volatile storage medium (which may be CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to cause a computing device (which may be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to an embodiment of the present disclosure.
  • a computing device which may be a personal computer, a server, a mobile terminal, or a network device, etc.
  • the repair records of the new failed bits and the adjacent bits generated during the wafer detection process are obtained, and classification learning is performed based on the above two types of repair records, so as to classify the failed bits according to the results of classification learning.
  • the prediction is to improve the efficiency, wafer yield and yield of failed bit detection of wafers, that is, to provide an efficient and highly reliable processing solution for wafer detection data.

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Abstract

提供了一种晶圆探测数据的处理方法和计算机可读存储介质，涉及晶片制造技术领域。其中，晶圆探测数据的处理方法包括：确定已完成的晶圆探测过程中产生的新失效位元(S202)；获取新失效位元的修补记录，以及新失效位元的相邻位元的修补记录(S204)；解析修补记录，以确定新失效位元和相邻位元的属性信息(S206)，属性信息包括位置信息、备用电路信息、新失效位元的单元图形和晶圆探测流程中的至少一种；根据属性信息进行分类学习，以获取失效位元预测模型(S208)；通过失效位元预测模型对待进行晶圆探测的失效位元进行预测(S210)。提高了预测失效位元的可靠性，有利于提升晶圆产品的成品率。

Description

一种晶圆探测数据的处理方法和计算机可读存储介质
交叉引用
本公开要求于2020年08月28日提交的申请号为202010883139.0、名称为“晶圆探测数据的处理方法和计算机可读存储介质”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及晶片制造技术领域，尤其涉及一种晶圆探测数据的处理方法和计算机可读存储介质。
背景技术
在晶圆探测(circuit probing)阶段，会将所有的失效位元(Fail Bits，后文记作FBs)位置进行修补，本公开称这种FBs的修补为“一般修补”。
此外，部分非FBs位置亦可能被进行修补，在“一般修补”后的多道测试程序中，非FBs位置很可能会出现新的失效位元。因此，在一般修补后会将这些非FBs位置一并修补，称为“预测修补”。
晶圆上的电路布线大都是微米级或纳米级，通过人工筛查或探针逐个单元排除来确定失效位元，不仅会导致晶圆探测效率低下，影响晶圆产品的产量，也可能由于探测流程导致新的失效元件产生，影响晶圆产品的良品率。
发明内容
本公开的目的在于提供一种晶圆探测数据的处理方法和计算机可读存储介质，至少在一定程度上克服由于相关技术中晶圆的失效位元的检测效率低下的问题。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
根据本公开的一个方面，提供一种晶圆探测数据的处理方法，包括：确定已完成的晶圆探测过程中产生的新失效位元；获取新失效位元的修补记录，以及新失效位元的相邻位元的修补记录；解析修补记录，以确定新失效位元和相邻位元的属性信息，属性信息包括位置信息、备用电路信息、新失效位元的单元图形和晶圆探测流程中的至少一种；根据属性信息进行分类学习，以获取失效位元预测模型；通过失效位元预测模型对待进行晶圆探测的失效位元进行预测。
根据本公开的一个实施例，解析修补记录，以确定新失效位元的属性信息和相邻位元的属性信息包括：解析修补记录，以检测新失效位元是否经修补处理，以及检测相邻位元是否经修补处理；若根据修补记录确定新失效位元未经修补处理，且根据修补记录确定相 邻位元未经修补处理，则获取属性信息中的新失效位元的位置信息和晶圆探测流程。
根据本公开的一个实施例，根据属性信息进行分类学习，以获取失效位元预测模型包括：对新失效位元的位置信息和晶圆探测流程进行关联分析；或，对新失效位元的单元图形进行挖掘分析；或，对新失效位元所属晶圆进行晶圆图分类分析；根据分析的结果获取失效位元预测模型。
根据本公开的一个实施例，解析修补记录，以确定新失效位元的属性信息和相邻位元的属性信息还包括：解析修补记录，以检测新失效位元是否经修补处理；若根据修补记录确定新失效位元经修补处理，则确定属性信息中的新失效位元的位置信息和用于修补新失效位元的备用电路信息。
根据本公开的一个实施例，根据属性信息进行分类学习，以获取失效位元预测模型还包括：对新失效位元的位置信息和用于修补新失效位元的备用电路信息进行备用电路选择分析；根据分析的结果获取失效位元预测模型。
根据本公开的一个实施例，解析修补记录，以确定新失效位元的属性信息和相邻位元的属性信息还包括：解析修补记录，以检测新失效位元是否经修补处理，以及检测相邻位元是否经修补处理；若根据修补记录确定新失效位元未经修补处理，且根据修补记录确定相邻位元经修补处理，则确定属性信息中的相邻位元的位置信息和用于修补相邻位元的备用电路信息。
根据本公开的一个实施例，根据属性信息进行分类学习，以获取失效位元预测模型还包括：对失效位元的位置信息与用于修补相邻位元的备用电路信息中的修补位置之间的关联概率分析，或进行修补处理规则的挖掘分析；根据分析的结果获取失效位元预测模型。
根据本公开的一个实施例，位置信息包括位元的坐标信息、位元的编号信息和晶圆产品种类中的至少一种。
根据本公开的一个实施例，备用电路信息包括备用电路版本、修补位置、修补检测项目、修补位元数量和备用电路信息版本中的至少一种。
根据本公开的一个实施例，晶圆探测数据的处理方法还包括：以所述晶圆的左下角的一个位元的坐标为原点坐标，创建参考坐标系；根据参考坐标系确定所述新失效位元所在行的横坐标为x，以及确定所述新失效位元所在列的纵坐标位置为y，所述x和所述y均为正整数；确定横坐标为x-1的列的所有位元和确定横坐标为x+1的列的所有位元为所述相邻位元。
根据本公开的一个实施例，晶圆探测数据的处理方法还包括：以所述晶圆的左下角的一个位元的坐标为原点坐标，创建参考坐标系；根据参考坐标系确定所述新失效位元所在行的横坐标为x，以及确定所述新失效位元所在列的纵坐标位置为y，所述x和所述y均为正整数；确定所述新失效位元所属的区块的序号为N；将所述新失效位元所属的区块的左边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000001
将所述新失效位元所属的区块的右边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000002
确定纵坐标为y-1且横坐标为
Figure PCTCN2021100627-appb-000003
至
Figure PCTCN2021100627-appb-000004
的所有位元，以及纵坐标为y+1且横 坐标为
Figure PCTCN2021100627-appb-000005
至
Figure PCTCN2021100627-appb-000006
的所有位元为所述相邻位元。
根据本公开的一个实施例，晶圆探测数据的处理方法还包括：以所述晶圆的左下角的一个位元的坐标为原点坐标，创建参考坐标系；根据参考坐标系确定所述新失效位元所在行的横坐标为x，以及确定所述新失效位元所在列的纵坐标位置为y，所述x和所述y均为正整数；确定所述新失效位元所属的区块的左侧区块的序号为N-1；确定所述新失效位元所属的区块的右侧区块的序号为N+1；将所述左侧区块的左边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000007
将所述左侧区块的右边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000008
将所述右侧区块的左边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000009
将所述右侧区块的右边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000010
确定纵坐标为y且横坐标为
Figure PCTCN2021100627-appb-000011
至
Figure PCTCN2021100627-appb-000012
的所有位元，以及横坐标为
Figure PCTCN2021100627-appb-000013
至
Figure PCTCN2021100627-appb-000014
的所有位元为所述相邻位元。
根据本公开的一个实施例，通过失效位元预测模型对待进行晶圆探测的失效位元进行预测包括：采集一个修补后的新失效位元的第一修补信息和所述修补后的新失效位元的相邻位元的第二修补信息；解析所述第一修补信息和所述第二修补信息输入至所述失效位元预测模型进行预测；根据所述失效位元预测模型的输出结果确定失效位元信息。
根据本公开的一个实施例，解析所述第一修补信息和所述第二修补信息输入至所述失效位元预测模型进行预测包括：解析所述第一修补信息和所述第二修补信息均为未经修补，则失效位元预测模型的输出结果为测试流程现象；解析所述第一修补信息为经备用电路修补，且所述第二修补信息为未经修补，则失效位元预测模型的输出结果为失效位元现象；解析所述第一修补信息为未经修补，且所述第二修补信息为经备用电路修补，则失效位元预测模型的输出结果为修补现象。
根据本公开的一个实施例，根据所述失效位元预测模型的输出结果确定失效位元信息包括：对所述输出结果进行解析处理；若解析所述输出结果包括所述测试流程现象，则根据预存的测试流程现象与失效位元之间的第一对应关系确定所述失效位元信息，所述测试流程现象包括对所述晶圆进行测试流程后出现失效的现象；若解析所述输出结果包括所述失效位元现象，则根据预设的失效位元现象与失效位元之间的第二对应关系确定所述失效位元信息，所述失效位元现象包括所述晶圆经备用电路修补的位元出现失效的现象；若解析所述输出结果包括所述修补现象，则根据预设的修补现象与失效位元之间的第三对应关系确定所述失效位元信息，所述修补现象包括对所述晶圆经备用电路修补的位元的相邻位元出现失效的现象。
根据本公开的又一个方面，提供一种计算机可读存储介质，其上存储有计算机程序，计算机程序被处理器执行时实现上述任意一项的晶圆探测数据的处理方法。
本公开的实施例所提供的晶圆探测数据的处理方案，通过获取晶圆探测过程中产生的新失效位元和相邻位元的修补记录，并基于上述两类修补记录进行分类学习，以根据分类学习的结果对失效位元进行预测，以提高晶圆的失效位元检测的效率、晶圆产量和良率，也即提供了一种高效且高可靠性的晶圆探测数据的处理方案。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A示出本公开实施例中的一个晶圆探测过程的示意图；
图1B示出本公开实施例中的另一个晶圆探测过程的示意图；
图1C示出本公开实施例中的另一个晶圆探测过程的示意图；
图2示出本公开实施例中的一个晶圆探测数据的处理方法的流程示意图；
图3示出本公开实施例中的另一个晶圆探测数据的处理方法的流程示意图；
图4示出本公开实施例中的另一个晶圆探测数据的处理方法的流程示意图；
图5示出本公开实施例中的另一个晶圆探测数据的处理方法的流程示意图；
图6示出本公开实施例中的另一个晶圆探测数据的处理方法的流程示意图；
图7示出本公开实施例中的另一个晶圆探测数据的处理方法的流程示意图；
图8示出本公开实施例的中的另一个晶圆探测数据的处理方法的流程示意图；
图9示出本公开实施例的中的另一个晶圆探测数据的处理方法的流程示意图；
图10示出本公开实施例的中的另一个晶圆探测数据的处理装置的示意框图；
图11示出本公开实施例的中一个电子设备的示意框图；和
图12示出本公开实施例的中一个计算机可读存储介质的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
本公开提供的方案，通过获取晶圆探测过程中产生的新失效位元和相邻位元的修补记录，并基于上述两类修补记录进行分类学习，以根据分类学习的结果对失效位元进行预 测，以提高晶圆的失效位元检测的效率、晶圆产量和良率，也即提供了一种高效且高可靠性的晶圆探测数据的处理方案。
本公开实施例提供的晶圆探测数据的处理方案涉及晶圆探测和分类学习等技术，具体通过如下实施例进行说明。
结合图1A、图1B和图1C所示，各个晶圆上的功能区之间设置有沟槽106进行分区，划分为多个区块(Section)，有些位置经过备用电路修补后，会影响到其他有效位元，导致其他有效位元变成新失效位元(New Fail Bit，NFBs)，在图1A、图1B和图1C中将新失效位元之一的新失效位元102作为对象进行分析，新失效位元102可称为ONFB(Observed NFB，受观察的NFB)。
NFBs出现的原因有可能是修补所导致，亦可能为原本修补位置108中的失效元位所导致。这些受到修补后可能影响其他有效位元变成新失效位元的位元，本公开称其为“相关位元104”。
(1)如图1A、图1B和图1C所示所示，新失效位元102的位置以(x,y)表示，相关位元104主要是根据新失效位元102和修补位置108确定的位元，具体地，相关位元104包括如下位置：
如图1A所示，本公开的一个实施例中确定将相邻位元确定为相关位元104的步骤包括：以所述晶圆的左下角的一个位元的坐标为原点坐标，创建参考坐标系；根据参考坐标系确定所述新失效位元所在行的横坐标为x，以及确定所述新失效位元所在列的纵坐标位置为y，所述x和所述y均为正整数；确定横坐标为x-1的列的所有位元和确定横坐标为x+1的列的所有位元为所述相邻位元。
如图1A所示，位置(x-1,0)与位置(x-1,y max)之间的所有位元位置、位置(x+1,0)与位置(x+1,y max)之间的所有位元位置。
如图1B所示，本公开的另一个实施例中确定将相邻位元确定为相关位元104的步骤包括：以所述晶圆的左下角的一个位元的坐标为原点坐标，创建参考坐标系；根据参考坐标系确定所述新失效位元所在行的横坐标为x，以及确定所述新失效位元所在列的纵坐标位置为y，所述x和所述y均为正整数；确定所述新失效位元所属的区块的序号为N；将所述新失效位元所属的区块的左边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000015
将所述新失效位元所属的区块的右边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000016
确定纵坐标为y-1且横坐标为
Figure PCTCN2021100627-appb-000017
至
Figure PCTCN2021100627-appb-000018
的所有位元，以及纵坐标为y+1且横坐标为
Figure PCTCN2021100627-appb-000019
至
Figure PCTCN2021100627-appb-000020
的所有位元为所述相邻位元。
如图1B所示，位置
Figure PCTCN2021100627-appb-000021
与位置
Figure PCTCN2021100627-appb-000022
之间的所有位元位置、位置
Figure PCTCN2021100627-appb-000023
与位置
Figure PCTCN2021100627-appb-000024
之间的所有位元位置。
如图1C所示，本公开的另一个实施例中确定将相邻位元确定为相关位元104的步骤包括：以所述晶圆的左下角的一个位元的坐标为原点坐标，创建参考坐标系；根据参考坐标系确定所述新失效位元所在行的横坐标为x，以及确定所述新失效位元所在列的纵坐标位置为y，所述x和所述y均为正整数；确定所述新失效位元所属的区块的左侧区块的序号为N-1；确定所述新失效位元所属的区块的右侧区块的序号为N+1；将所述左侧区块的左边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000025
将所述左侧区块的右边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000026
将所述右侧区块的左边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000027
将所述右侧区块的右边界位元的横坐标确定为
Figure PCTCN2021100627-appb-000028
确定纵坐标为y且横坐标为
Figure PCTCN2021100627-appb-000029
至
Figure PCTCN2021100627-appb-000030
的所有位元，以及横坐标为
Figure PCTCN2021100627-appb-000031
至
Figure PCTCN2021100627-appb-000032
的所有位元为所述相邻位元。
如图1C所示，位置
Figure PCTCN2021100627-appb-000033
与位置
Figure PCTCN2021100627-appb-000034
之间的所有位元位置、位置
Figure PCTCN2021100627-appb-000035
与位置
Figure PCTCN2021100627-appb-000036
之间的所有位元位置。
其中，x-y轴的原点由晶圆的左下角位元参考确定，N为大于1的整数。设定新失效位元102处于Section N，y max是指新失效位元102位置所在的Section其y方向的最高位置，
Figure PCTCN2021100627-appb-000037
是指Section N中x方向的最低位置，
Figure PCTCN2021100627-appb-000038
是指Section N中x方向的最高位置。
下面参照图2来描述根据本公开的这种实施方式的晶圆探测数据的处理方法。图2所示的晶圆探测数据的处理方法仅仅是一个示例，不应对本公开实施例的功能和使用范围带来任何限制。
如图2所示，本公开的晶圆探测数据的处理方法包括：
步骤S202，确定已完成的晶圆探测过程中产生的新失效位元。
步骤S204，获取新失效位元的修补记录，以及新失效位元的相邻位元的修补记录。
在上述实施例中，修补记录包括但不限于以下内容：
(1)Version：备用电路修补的版本。
(2)Repaired Address：修补的位置。
(2.1)Chip location：芯片位的(x,y)位置。
(2.2)Region：Bank位置。
(2.3)Subdomain：数据线的位置。
(2.4)Row address：数据线中的x轴位置。
(2.5)Column address：数据线中的y轴位置。
(3)Bin：测试项的集合。
(4)Fail Bit Count：修补的失效位元数量。
(5)Redundant ID：备用电路编号。
步骤S206，解析修补记录，以确定新失效位元的属性信息和相邻位元的属性信息，属性信息包括位置信息、备用电路信息、新失效位元的单元图形和晶圆探测流程中的至少一种。
在上述实施例中，位置数据包括但不限于以下内容：
(1)id：NFB的编号。
(2)product id：产品的种类编号。
(3)Fail Bit Address：失效位元的位置。
(3.1)Lot ID：晶圆批号。
(3.2)Wafer No：晶圆编号。
(3.3)Channel id：通道编号。
(3.4)Chip location：芯片位的(x,y)位置。
(3.5)Bank id：bank编号，在芯片内部，内存的数据以bit(位)为单位写入一张大的矩阵中，矩阵中包含多个功能单元(cell)，以行坐标(x轴)和列坐标(y轴)进行寻址，这个矩阵就是芯片的逻辑bank。
(3.6)Row address：数据线中的x轴位置。
(3.7)Column address：数据线中的y轴位置。
(3.8)DQ address：数据线位置。
步骤S208，根据属性信息进行分类学习，以获取失效位元预测模型。
步骤S210，通过失效位元预测模型对待进行晶圆探测的失效位元进行预测。
在上述实施例中，新失效位元的相邻位元即相关位元，通过对新时效位元的修补记录和相邻位元的修补记录，对探测数据进行分类，并基于分类后的数据进行模型训练，训练后的模型用于新失效位元的预测，有利于提高探测效率、可靠性、产量和良率。
基于图2所示的方法步骤，如图3所示，解析修补记录，以确定新失效位元的属性信息和相邻位元的属性信息包括：
步骤S3062，解析修补记录，以检测新失效位元是否经修补处理，以及检测相邻位元是否经修补处理。
步骤S3064，若根据修补记录确定新失效位元未经修补处理，且根据修补记录确定相邻位元未经修补处理，则获取属性信息中的新失效位元的位置信息和晶圆探测流程。
在上述实施例中，通过确定新失效位元和相邻位元均未经修补处理(此检测结果定义为现象1)，从位置信息和晶圆探测流程的角度对失效原因进行分类学习，以便基于晶圆探测流程预测新失效位元的位置，有利于提高晶圆探测的效率和可靠性。
基于图2和图3所示的方法步骤，如图4所示，根据属性信息进行分类学习，以获取失效位元预测模型包括：
步骤S4082，对新失效位元的位置信息和晶圆探测流程进行关联分析。
步骤S4084，对新失效位元的单元图形进行挖掘分析。
步骤S4086，对新失效位元所属晶圆进行晶圆图分类分析。
步骤S4088，根据分析的结果获取失效位元预测模型。
在上述实施例中，步骤S4082、S4084和S4086是三个相互独立的分类学习过程，也即分别基于位置信息和晶圆探测流程、单元图形和晶圆图分类进行分析，以获得失效位元预测模型，在后续晶圆探测过程中，可以基于位置信息、晶圆探测流程、单元图形和晶圆图分类进行新失效位元预测，以提高晶圆探测效率的可靠性和准确性，有利于提升晶圆产品的产量和良率。
基于图2所示的方法步骤，如图5所示，解析修补记录，以确定新失效位元的属性信息和相邻位元的属性信息还包括：
步骤S5062，解析修补记录，以检测新失效位元是否经修补处理。
步骤S5064，若根据修补记录确定新失效位元经修补处理，则确定属性信息中的新失 效位元的位置信息和用于修补新失效位元的备用电路信息。
在上述实施例中，在确定新失效位元经修补处理(此检测结果定义为现象2)后，发明人分析新失效位元产生的主要原因可能是引入了备用电路对新失效位元进行修补，因此，获取用于修补新失效位元的备用电路信息进行分析。
基于图2和图5所示的方法步骤，如图6所示，根据属性信息进行分类学习，以获取失效位元预测模型还包括：
步骤S6082，对新失效位元的位置信息和用于修补所述新失效位元的备用电路信息进行备用电路选择分析。
步骤S6084，根据分析的结果获取失效位元预测模型。
在上述实施例中，通过对用于修补新失效位元的备用电路选择进行分析，一方面，可以确定更可能导致新失效位元出现的备用电路的特征，以对备用电路进行改进，总而提升晶圆片的整体可靠性。另一方面，在下次采用备用电路进行修补处理时，将备用电路信息输入预测模型，以预测可能出现新失效位元的位置，进而提升晶圆探测的可靠性和准确性，以及提高晶圆产量和良率。
基于图2所示的方法步骤，如图7所示，解析修补记录，以确定新失效位元的属性信息和相邻位元的属性信息还包括：
步骤S7062，解析修补记录，以检测所述新失效位元是否经修补处理，以及检测相邻位元是否经修补处理。
步骤S7064，若根据所述修补记录确定所述新失效位元未经修补处理，且根据修补记录确定相邻位元经修补处理，则确定属性信息中的相邻位元的位置信息和用于修补相邻位元的备用电路信息。
在上述实施例中，在确定新失效位元未经修补处理，且相邻位元经修补处理(此检测结果定义为现象3)后，发明人分析相邻位元产生的主要原因是引入了备用电路对相邻位元进行修补，因此，获取备用电路信息进行分析。
基于图2和图7所示的方法步骤，如图8所示，根据属性信息进行分类学习，以获取失效位元预测模型还包括：
步骤S8082，对相邻位元的位置信息与用于修补相邻位元的备用电路信息中的修补位置之间的关联概率分析，或进行修补处理规则的挖掘分析。
步骤S8084，根据分析的结果获取失效位元预测模型。
在上述实施例中，通过对相邻位元的备用电路选择进行分析，一方面，可以确定更可能导致相邻位元出现的备用电路的特征，以对备用电路进行改进，总而提升晶圆片的整体可靠性。另一方面，在下次采用备用电路进行修补处理时，将备用电路信息输入预测模型，以预测可能出现相邻位元的位置，进而提升晶圆探测的可靠性和准确性，以及提高晶圆产量和良率。
根据本公开的一个实施例，位置信息包括位元的坐标信息、位元的编号信息和晶圆产 品种类中的至少一种。
根据本公开的一个实施例，备用电路信息包括备用电路版本、修补位置、修补检测项目、修补位元数量和备用电路信息版本中的至少一种。
根据本公开的一个实施例，通过失效位元预测模型对待进行晶圆探测的失效位元进行预测包括：采集一个修补后的新失效位元的第一修补信息和所述修补后的新失效位元的相邻位元的第二修补信息；解析所述第一修补信息和所述第二修补信息输入至所述失效位元预测模型进行预测；根据所述失效位元预测模型的输出结果确定失效位元信息。
根据本公开的一个实施例，解析所述第一修补信息和所述第二修补信息输入至所述失效位元预测模型进行预测包括：解析所述第一修补信息和所述第二修补信息均为未经修补，则失效位元预测模型的输出结果为测试流程现象；解析所述第一修补信息为经备用电路修补，且所述第二修补信息为未经修补，则失效位元预测模型的输出结果为失效位元现象；解析所述第一修补信息为未经修补，且所述第二修补信息为经备用电路修补，则失效位元预测模型的输出结果为修补现象。
根据本公开的一个实施例，根据所述失效位元预测模型的输出结果确定失效位元信息包括：对所述输出结果进行解析处理；若解析所述输出结果包括所述测试流程现象，则根据预存的测试流程现象与失效位元之间的第一对应关系确定所述失效位元信息，所述测试流程现象包括对所述晶圆进行测试流程后出现失效的现象；若解析所述输出结果包括所述失效位元现象，则根据预设的失效位元现象与失效位元之间的第二对应关系确定所述失效位元信息，所述失效位元现象包括所述晶圆经备用电路修补的位元出现失效的现象；若解析所述输出结果包括所述修补现象，则根据预设的修补现象与失效位元之间的第三对应关系确定所述失效位元信息，所述修补现象包括对所述晶圆经备用电路修补的位元的相邻位元出现失效的现象。
如图9所示，根据本公开的晶圆探测数据的处理方案包括但不限于以下数据处理、写入和读出过程：
(1)来源数据包括NFB Data(新失效位元数据)和FU Data(全部的修补记录数据)，但不限于此。
(2)系统流程主要用于执行数据处理步骤，具体包括：
步骤S902，获取一个NFB。
步骤S904，撷取修补信息。
步骤S906，判断是否符合现象1，若是，则执行步骤S910，若否，则执行步骤S908。
步骤S908，判断是否符合现象2，若是，则执行步骤S912，若否，则执行步骤S914。
步骤S910，输出测试流程现象样本数据。
步骤S912，输出失效位元现象样本数据。
步骤S914，输出修补现象样本数据。
步骤S916，判断是否为晶圆片上最后一个NFB，若是，则结束，若否，则执行步骤 S902。
(3)有效样本分析包括：测试流程现象样本数据，即符合现象1的新失效位元数据NFB Data；失效位元现象样本数据，即符合现象2的新失效位元数据NFB Data和相应的修补记录数据FU Data；修补现象样本数据，即符合现象3的新失效位元数据NFB Data和相应的修补记录数据FU Data。
(4)机器学习系统：测试流程与失效位元的关联分析；失效位元单元图形挖掘分析；晶圆图分类分析。
综上，根据本公开的晶圆探测数据的处理方案的核心处理步骤如下：
(1)获得一个NFB：从来源数据FB data中，循序取得一个NFB信息。最近一次取得的NFB即为ONFB。
(2)撷取修补信息：取得ONFB的修补位元位置与其相关位元位置的修补信息，并取得使用修补的备用电路编号。
(3)输出测试流程现象样本数据：将ONFB的信息输出至测试流程现象样本数据库。
(4)输出失效位元现象样本数据：将ONFB的信息、ONFB修补位元位置信息与其使用备补的备用电路编号等信息输出至失效位元现象样本数据库。
(5)输出修补现象样本数据：将ONFB的信息、相关位元位置的修补信息与与其使用备补的备用电路编号等信息输出至修补现象样本数据库。
下面参照图10来描述根据本公开的这种实施方式的晶圆探测数据的处理装置1000。图10所示的晶圆探测数据的处理装置1000仅仅是一个示例，不应对本公开实施例的功能和使用范围带来任何限制。
如图10所示，晶圆探测数据的处理装置1000包括：获取模块1002、解析模块1004和预测模块1006。
获取模块1002用于，确定已完成的晶圆探测过程中产生的新失效位元。
获取模块1002还用于，获取新失效位元的修补记录，以及新失效位元的相邻位元的修补记录。
解析模块1004用于，解析修补记录，以确定新失效位元的属性信息和相邻位元的属性信息，属性信息包括位置信息、备用电路信息、新失效位元的单元图形和晶圆探测流程中的至少一种。
解析模块1004还用于，根据属性信息进行分类学习，以获取失效位元预测模型。
预测模块1006用于，通过失效位元预测模型对待进行晶圆探测的失效位元进行预测。
下面参照图11来描述根据本公开的这种实施方式的电子设备1100。图11所示的电子设备1100仅仅是一个示例，不应对本公开实施例的功能和使用范围带来任何限制。
如图11所示，电子设备1100以通用计算设备的形式表现。电子设备1100的组件可以包括但不限于：上述处理单元1110、上述存储单元1120、连接不同晶圆探测数据的处理系统的组件(包括存储单元1120和处理单元1110)的总线1130。
其中，存储单元存储有程序代码，程序代码可以被处理单元1110执行，使得处理单元1110执行本说明书上述“示例性方法”部分中描述的根据本公开各种示例性实施方式的步骤。例如，处理单元1110可以执行如图2至图8中所示的全部步骤，以及本公开的晶圆探测数据的处理方法中限定的其他步骤。
存储单元1120可以包括易失性存储单元形式的可读介质，例如随机存取存储单元(RAM)11201和/或高速缓存存储单元11202，还可以进一步包括只读存储单元(ROM)11203。
存储单元1120还可以包括具有一组程序模块11205的程序/实用工具11204，这样的程序模块11205包括但不限于：操作晶圆探测数据的处理系统、一个或者多个应用程序、其它程序模块以及程序数据，这些示例中的每一个或某种组合中可能包括网络环境的实现。
总线1130可以为表示几类总线结构中的一种或多种，包括存储单元总线或者存储单元控制器、外围总线、图形加速端口、处理单元或者使用多种总线结构中的任意总线结构的局域总线。
电子设备1100也可以与一个或多个外部设备1140(例如键盘、指向设备、蓝牙设备等)通信，还可与一个或者多个使得用户能与该电子设备交互的设备通信，和/或与使得该电子设备1100能与一个或多个其它计算设备进行通信的任何设备(例如路由器、调制解调器等等)通信。这种通信可以通过输入/输出(I/O)接口1150进行。
并且，电子设备1100还可以通过网络适配器1160与一个或者多个网络(例如局域网(LAN)，广域网(WAN)和/或公共网络，例如因特网)通信。如图所示，网络适配器1160通过总线1130与电子设备1100的其它模块通信。应当明白，尽管图中未示出，可以结合电子设备使用其它硬件和/或软件模块，包括但不限于：微代码、设备驱动器、冗余处理单元、外部磁盘驱动阵列、RAID晶圆探测数据的处理系统、磁带驱动器以及数据备份存储晶圆探测数据的处理系统等。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、终端装置、或者网络设备等)执行根据本公开实施方式的方法。
在本公开的示例性实施例中，还提供了一种计算机可读存储介质，其上存储有能够实现本说明书上述方法的程序产品。在一些可能的实施方式中，本公开的各个方面还可以实现为一种程序产品的形式，其包括程序代码，当程序产品在终端设备上运行时，程序代码用于使终端设备执行本说明书上述“示例性方法”部分中描述的根据本公开各种示例性实施方式的步骤。
参考图12所示，描述了根据本公开的实施方式的用于实现上述方法的计算机程序1200，其可以采用便携式紧凑盘只读存储器(CD-ROM)并包括程序代码，并可以在终端设备，例如个人电脑上运行。然而，本公开的程序产品不限于此，在本文件中，可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行晶圆探测数据的处理系统、装置或者器件使用或者与其结合使用。
计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了可读程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。可读信号介质还可以是可读存储介质以外的任何可读介质，该可读介质可以发送、传播或者传输用于由指令执行晶圆探测数据的处理系统、装置或者器件使用或者与其结合使用的程序。
可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于无线、有线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言的任意组合来编写用于执行本公开操作的程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、C++等，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。在涉及远程计算设备的情形中，远程计算设备可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算设备，或者，可以连接到外部计算设备(例如利用因特网服务提供商来通过因特网连接)。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示按照该特定顺序来执行这些步骤，或是执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、移动终端、或者网络设备等)执行根据本公开实施方式的方法。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或 者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。
工业实用性
本公开提供的方案，通过获取晶圆探测过程中产生的新失效位元和相邻位元的修补记录，并基于上述两类修补记录进行分类学习，以根据分类学习的结果对失效位元进行预测，以提高晶圆的失效位元检测的效率、晶圆产量和良率，也即提供了一种高效且高可靠性的晶圆探测数据的处理方案。

Claims (16)

  1. 一种晶圆探测数据的处理方法，其特征在于，包括：
    确定已完成的晶圆探测过程中产生的新失效位元；
    获取所述新失效位元的修补记录，以及所述新失效位元的相邻位元的修补记录；
    解析所述修补记录，以确定所述新失效位元和所述相邻位元的属性信息，所述属性信息包括位置信息、备用电路信息、新失效位元的单元图形和晶圆探测流程中的至少一种；
    根据所述属性信息进行分类学习，以获取失效位元预测模型；
    通过失效位元预测模型对待进行晶圆探测的失效位元进行预测。
  2. 根据权利要求1所述的晶圆探测数据的处理方法，其特征在于，解析所述修补记录，以确定所述新失效位元的属性信息和所述相邻位元的属性信息包括：
    解析所述修补记录，以检测所述新失效位元是否经修补处理，以及检测所述相邻位元是否经修补处理；
    若根据所述修补记录确定所述新失效位元未经修补处理，且根据所述修补记录确定所述相邻位元未经修补处理，则获取所述属性信息中的新失效位元的位置信息和晶圆探测流程。
  3. 根据权利要求2所述的晶圆探测数据的处理方法，其特征在于，根据所述属性信息进行分类学习，以获取失效位元预测模型包括：
    对所述新失效位元的位置信息和所述晶圆探测流程进行关联分析；
    或，对所述新失效位元的单元图形进行挖掘分析；
    或，对所述新失效位元所属晶圆进行晶圆图分类分析；
    根据所述分析的结果获取所述失效位元预测模型。
  4. 根据权利要求1所述的晶圆探测数据的处理方法，其特征在于，解析所述修补记录，以确定所述新失效位元的属性信息和所述相邻位元的属性信息还包括：
    解析所述修补记录，以检测所述新失效位元是否经修补处理；
    若根据所述修补记录确定所述新失效位元经修补处理，则确定所述属性信息中的新失效位元的位置信息和用于修补所述新失效位元的备用电路信息。
  5. 根据权利要求4所述的晶圆探测数据的处理方法，其特征在于，根据所述属性信息进行分类学习，以获取失效位元预测模型还包括：
    对所述新失效位元的位置信息和用于修补所述新失效位元的备用电路信息进行备用电路选择分析；
    根据所述分析的结果获取所述失效位元预测模型。
  6. 根据权利要求1所述的晶圆探测数据的处理方法，其特征在于，解析所述修补记录，以确定所述新失效位元的属性信息和所述相邻位元的属性信息还包括：
    解析所述修补记录，以检测所述新失效位元是否经修补处理，以及检测所述相邻位元是否经修补处理；
    若根据所述修补记录确定所述新失效位元未经修补处理，且根据所述修补记录确定所述相邻位元经修补处理，则确定所述属性信息中的相邻位元的位置信息和用于修补所述相邻位元的备用电路信息。
  7. 根据权利要求6所述的晶圆探测数据的处理方法，其特征在于，根据所述属性信息进行分类学习，以获取失效位元预测模型还包括：
    对所述相邻位元的位置信息与用于修补所述相邻位元的备用电路信息中的修补位置之间的关联概率分析，或进行修补处理规则的挖掘分析；
    根据所述分析的结果获取所述失效位元预测模型。
  8. 根据权利要求1-7中任一项所述的晶圆探测数据的处理方法，其特征在于，
    所述位置信息包括位元的坐标信息、位元的编号信息和晶圆产品种类中的至少一种。
  9. 根据权利要求1-7中任一项所述的晶圆探测数据的处理方法，其特征在于，
    所述备用电路信息包括备用电路版本、修补位置、修补检测项目、修补位元数量和备用电路信息版本中的至少一种。
  10. 根据权利要求1-7中任一项所述的晶圆探测数据的处理方法，其特征在于，还包括：
    以所述晶圆的左下角的一个位元的坐标为原点坐标，创建参考坐标系；
    根据参考坐标系确定所述新失效位元所在行的横坐标为x，以及确定所述新失效位元所在列的纵坐标位置为y，所述x和所述y均为正整数；
    确定横坐标为x-1的列的所有位元和确定横坐标为x+1的列的所有位元为所述相邻位元。
  11. 根据权利要求1-7中任一项所述的晶圆探测数据的处理方法，其特征在于，还包括：
    以所述晶圆的左下角的一个位元的坐标为原点坐标，创建参考坐标系；
    根据参考坐标系确定所述新失效位元所在行的横坐标为x，以及确定所述新失效位元所在列的纵坐标位置为y，所述x和所述y均为正整数；
    确定所述新失效位元所属的区块的序号为N；
    将所述新失效位元所属的区块的左边界位元的横坐标确定为
    Figure PCTCN2021100627-appb-100001
    将所述新失效位元所属的区块的右边界位元的横坐标确定为
    Figure PCTCN2021100627-appb-100002
    确定纵坐标为y-1且横坐标为
    Figure PCTCN2021100627-appb-100003
    至
    Figure PCTCN2021100627-appb-100004
    的所有位元，以及纵坐标为y+1且横坐标为
    Figure PCTCN2021100627-appb-100005
    至
    Figure PCTCN2021100627-appb-100006
    的所有位元为所述相邻位元。
  12. 根据权利要求1-7中任一项所述的晶圆探测数据的处理方法，其特征在于，还包括：
    以所述晶圆的左下角的一个位元的坐标为原点坐标，创建参考坐标系；
    根据参考坐标系确定所述新失效位元所在行的横坐标为x，以及确定所述新失效位元所在列的纵坐标位置为y，所述x和所述y均为正整数；
    确定所述新失效位元所属的区块的左侧区块的序号为N-1；
    确定所述新失效位元所属的区块的右侧区块的序号为N+1；
    将所述左侧区块的左边界位元的横坐标确定为
    Figure PCTCN2021100627-appb-100007
    将所述左侧区块的右边界位元的横坐标确定为
    Figure PCTCN2021100627-appb-100008
    将所述右侧区块的左边界位元的横坐标确定为
    Figure PCTCN2021100627-appb-100009
    将所述右侧区块的右边界位元的横坐标确定为
    Figure PCTCN2021100627-appb-100010
    确定纵坐标为y且横坐标为
    Figure PCTCN2021100627-appb-100011
    至
    Figure PCTCN2021100627-appb-100012
    的所有位元，以及横坐标为
    Figure PCTCN2021100627-appb-100013
    至
    Figure PCTCN2021100627-appb-100014
    的所有位元为所述相邻位元。
  13. 根据权利要求1-7中任一项所述的晶圆探测数据的处理方法，其特征在于，通过失效位元预测模型对待进行晶圆探测的失效位元进行预测包括：
    采集一个修补后的新失效位元的第一修补信息和所述修补后的新失效位元的相邻位元的第二修补信息；
    解析所述第一修补信息和所述第二修补信息输入至所述失效位元预测模型进行预测；
    根据所述失效位元预测模型的输出结果确定失效位元信息。
  14. 根据权利要求13所述的晶圆探测数据的处理方法，其特征在于，解析所述第一修补信息和所述第二修补信息输入至所述失效位元预测模型进行预测包括：
    解析所述第一修补信息和所述第二修补信息均为未经修补，则失效位元预测模型的输出结果为测试流程现象；
    解析所述第一修补信息为经备用电路修补，且所述第二修补信息为未经修补，则失效位元预测模型的输出结果为失效位元现象；
    解析所述第一修补信息为未经修补，且所述第二修补信息为经备用电路修补，则失效位元预测模型的输出结果为修补现象。
  15. 根据权利要求14所述的晶圆探测数据的处理方法，其特征在于，根据所述失效位元预测模型的输出结果确定失效位元信息包括：
    对所述输出结果进行解析处理；
    若解析所述输出结果包括所述测试流程现象，则根据预存的测试流程现象与失效位元之间的第一对应关系确定所述失效位元信息，所述测试流程现象包括对所述晶圆进行测试流程后出现失效的现象；
    若解析所述输出结果包括所述失效位元现象，则根据预设的失效位元现象与失效位元之间的第二对应关系确定所述失效位元信息，所述失效位元现象包括所述晶圆经备用电路修补的位元出现失效的现象；
    若解析所述输出结果包括所述修补现象，则根据预设的修补现象与失效位元之间的第三对应关系确定所述失效位元信息，所述修补现象包括对所述晶圆经备用电路修补的位元的相邻位元出现失效的现象。
  16. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，
    所述计算机程序被处理器执行时实现权利要求1-15中任一项所述的晶圆探测数据的处理方法。
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Publication number Priority date Publication date Assignee Title
CN114968652A (zh) * 2022-07-09 2022-08-30 超聚变数字技术有限公司 故障处理方法及计算设备
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CN115798559B (zh) * 2023-02-10 2023-07-04 长鑫存储技术有限公司 失效单元预测方法、装置、设备及存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130231769A1 (en) * 2012-03-01 2013-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Defect Management Systems and Methods
CN107039074A (zh) * 2016-02-03 2017-08-11 株式会社东芝 半导体存储装置
US20190267072A1 (en) * 2017-10-05 2019-08-29 Gyrfalcon Technology Inc. Method of self-testing and reusing of reference cells in a memory architecture
CN110968985A (zh) * 2018-09-30 2020-04-07 长鑫存储技术有限公司 集成电路修补算法确定方法及装置、存储介质、电子设备
CN110991124A (zh) * 2018-09-29 2020-04-10 长鑫存储技术有限公司 集成电路修补方法及装置、存储介质、电子设备

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7570796B2 (en) * 2005-11-18 2009-08-04 Kla-Tencor Technologies Corp. Methods and systems for utilizing design data in combination with inspection data
US20140282327A1 (en) 2013-03-14 2014-09-18 Nvidia Corporation Cutter in diagnosis (cid) a method to improve the throughput of the yield ramp up process
CN105845592B (zh) 2015-01-16 2018-11-16 中芯国际集成电路制造(上海)有限公司 用于失效分析的方法
KR102449196B1 (ko) * 2016-01-15 2022-09-29 삼성전자주식회사 비휘발성 메모리 장치 및 비휘발성 메모리 장치의 프로그램 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130231769A1 (en) * 2012-03-01 2013-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Defect Management Systems and Methods
CN107039074A (zh) * 2016-02-03 2017-08-11 株式会社东芝 半导体存储装置
US20190267072A1 (en) * 2017-10-05 2019-08-29 Gyrfalcon Technology Inc. Method of self-testing and reusing of reference cells in a memory architecture
CN110991124A (zh) * 2018-09-29 2020-04-10 长鑫存储技术有限公司 集成电路修补方法及装置、存储介质、电子设备
CN110968985A (zh) * 2018-09-30 2020-04-07 长鑫存储技术有限公司 集成电路修补算法确定方法及装置、存储介质、电子设备

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