WO2022147955A1 - 时序控制器、时钟复位方法及显示面板 - Google Patents

时序控制器、时钟复位方法及显示面板 Download PDF

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Publication number
WO2022147955A1
WO2022147955A1 PCT/CN2021/097292 CN2021097292W WO2022147955A1 WO 2022147955 A1 WO2022147955 A1 WO 2022147955A1 CN 2021097292 W CN2021097292 W CN 2021097292W WO 2022147955 A1 WO2022147955 A1 WO 2022147955A1
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WIPO (PCT)
Prior art keywords
reset
control signal
clock
timing controller
reset control
Prior art date
Application number
PCT/CN2021/097292
Other languages
English (en)
French (fr)
Inventor
刘金风
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/434,005 priority Critical patent/US11804159B2/en
Publication of WO2022147955A1 publication Critical patent/WO2022147955A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present application relates to the field of display technology, and in particular, to a timing controller, a clock reset method and a display panel.
  • the timing controller of the display panel needs to be restarted when an error or abnormality is detected in the system, and the clock of the timing controller needs to be restored each time it is activated, so as to retrain the link and synchronize the clock of the entire system. Therefore, whether the timing controller can normally complete the clock data recovery operation during restart plays a crucial role in the stability and reliability of the timing controller and the display panel.
  • embodiments of the present application provide a timing controller, a clock reset method, and a display panel.
  • an embodiment of the present application provides a timing controller, the timing controller includes a detection module, a processing module and a clock data recovery module connected in sequence; the detection module is used to respond to the normal operation of the timing controller output the reset control signal of the initial state in response to the abnormal working condition of the timing controller, and output the reset control signal of the transition state in response to the abnormal working condition of the timing controller; the processing module is used for the reset control according to the transition state The signal generates a clock reset pulse signal, and in response to the end of the pulse of the clock reset pulse signal, the reset control signal is restored from the jump state to the initial state; the clock data recovery module is used for according to the clock reset pulse. The signal recovers the clock of the timing controller.
  • the detection module includes a detection unit and a reset unit connected to each other; the detection unit is used to detect the working state of the timing controller, and output an initial output when the timing controller is in a normal working condition The reset control signal of the state; the reset unit is configured to convert the reset control signal from an initial state to a transition state when the detection unit detects that the timing controller has an abnormal working condition.
  • the processing module includes a processing unit, a delay inversion unit, and a logic gate unit, an input terminal of the processing unit is connected to an output terminal of the detection module, and an output terminal of the processing unit is respectively connected to the output terminal of the detection module.
  • the input end of the delay inversion unit is connected to the first input end of the logic gate unit, and the second input end of the logic gate unit is connected to the output end of the delay inversion unit; wherein: the processing unit is used for Detect the state of the reset control signal and the clock reset pulse signal, and reset the reset control signal after the pulse of the clock reset pulse signal ends and before the reset control signal is restored from the transition state to the initial state The control signal is restored from the jumping state to the initial state; the delay inversion unit is used for delaying the reset control signal for a preset time length and performing inversion operation to obtain the delayed inversion and repositioning control signal; the logic gate unit uses performing a corresponding logical operation according to the reset control signal and the delay fetching and repositioning control signal and outputting the clock reset pulse signal, wherein the pulse width of the clock reset pulse signal is the preset duration.
  • the initial state of the reset control signal is a high level
  • the transition state of the reset control signal is a low level
  • the logic gate unit is an OR gate
  • the initial state of the reset control signal is a low level
  • the transition state of the reset control signal is a high level
  • the logic gate unit is an AND gate
  • an embodiment of the present application further provides a clock reset method for a timing controller, where the timing controller includes a detection module, a processing module, and a clock data recovery module connected in sequence; the clock reset method includes:
  • the detection module outputs the reset control signal in the initial state in response to the normal working condition of the timing controller, and outputs the reset control signal in the transition state in response to the abnormal working condition of the timing controller.
  • the processing module generates a clock reset pulse signal according to the reset control signal of the transition state, and restores the reset control signal from the transition state to the initial state in response to the end of the pulse of the clock reset pulse signal.
  • the clock of the timing controller is recovered by the clock data recovery module according to the clock reset pulse signal.
  • the processing module includes a processing unit, a delay inversion unit, and a logic gate unit, an input terminal of the processing unit is connected to an output terminal of the detection module, and an output terminal of the processing unit is respectively connected to the output terminal of the detection module.
  • the input end of the delay inversion unit is connected to the first input end of the logic gate unit, and the second input end of the logic gate unit is connected to the output end of the delay inversion unit.
  • the generating of the clock reset pulse signal by the processing module according to the reset control signal of the transition state specifically includes:
  • the reset control signal is output by the processing unit.
  • the reset control signal is delayed for a preset period of time by the delay inversion unit and an inversion operation is performed to obtain a delayed inversion and repositioning control signal.
  • the logic gate unit performs corresponding logical operations according to the reset control signal and the delay-replacement control signal, and outputs the clock reset pulse signal when the reset control signal is converted from an initial state to a transition state ; wherein, the pulse width of the clock reset pulse signal is the preset duration.
  • the processing unit includes a detection subunit and a recovery subunit that are interconnected.
  • restoring the reset control signal from the jump state to the initial state by the processing module in response to the end of the pulse of the clock reset pulse signal specifically includes:
  • the reset control signal is changed from The transition state is restored to the initial state.
  • the initial state of the reset control signal is a high level
  • the transition state of the reset control signal is a low level
  • the logic gate unit is an OR gate
  • the initial state of the reset control signal is a low level
  • the transition state of the reset control signal is a high level
  • the logic gate unit is an AND gate
  • an embodiment of the present application further provides a display panel, the display panel includes at least one timing controller, and the timing controller includes a detection module, a processing module, and a clock data recovery module connected in sequence; wherein:
  • the detection module is configured to output the reset control signal of the initial state in response to the normal working condition of the timing controller, and output the reset control signal of the transition state in response to the abnormal working condition of the timing controller Signal;
  • the processing module is configured to generate a clock reset pulse signal according to the reset control signal of the transition state, and restore the reset control signal from the transition state to the initial state in response to the end of the pulse of the clock reset pulse signal state;
  • the clock data recovery module is configured to recover the clock of the timing controller according to the clock reset pulse signal.
  • the detection module includes an interconnected detection unit and a reset unit; wherein:
  • the detection unit configured to detect the working state of the timing controller, and output the reset control signal of the initial state when the timing controller is in a normal working condition
  • the reset unit is configured to convert the reset control signal from an initial state to a transition state when the detection unit detects that the timing controller has an abnormal working condition.
  • the processing module includes a processing unit, a delay inversion unit, and a logic gate unit, an input terminal of the processing unit is connected to an output terminal of the detection module, and an output terminal of the processing unit is respectively connected to the output terminal of the detection module.
  • the input end of the delay inversion unit is connected to the first input end of the logic gate unit, and the second input end of the logic gate unit is connected to the output end of the delay inversion unit;
  • the processing unit is used to detect the state of the reset control signal and the clock reset pulse signal, and after the pulse of the clock reset pulse signal ends and the reset control signal is restored from the jump state to the initial state Before, restoring the reset control signal from the transition state to the initial state;
  • the delay inversion unit is used for delaying the reset control signal for a preset duration and performing an inversion operation to obtain a delay-inversion and repositioning control signal;
  • the logic gate unit is configured to perform a corresponding logical operation according to the reset control signal and the delay fetching and repositioning control signal and output the clock reset pulse signal, wherein the pulse width of the clock reset pulse signal is the preset duration.
  • the processing unit includes an interconnected detection subunit and a recovery subunit; wherein:
  • the detection subunit is used to detect the state of the reset control signal and the clock reset pulse signal
  • the restoration subunit is used for restoring the reset control signal after the detection subunit detects that the pulse of the clock reset pulse signal ends and before the reset control signal is restored from the jump state to the initial state Return to the initial state from the transition state.
  • the initial state of the reset control signal is a high level
  • the transition state of the reset control signal is a low level
  • the logic gate unit is an OR gate
  • the initial state of the reset control signal is a low level
  • the transition state of the reset control signal is a high level
  • the logic gate unit is an AND gate
  • Embodiments of the present application provide a timing controller, a clock resetting method, and a display panel.
  • the timing controller outputs a reset control signal in an initial state through a detection module when the timing controller is in a normal working state, and when the timing controller works abnormally
  • the reset control signal of the transition state is output in the case of the state, and then the clock reset pulse signal is output from the initial state to the transition state through the processing module according to the reset control signal, and the reset control signal is immediately after the pulse of the clock reset pulse signal ends.
  • the signal is restored from the transition state to the initial state, and finally the clock of the timing controller is restored according to the clock reset pulse signal through the clock data recovery module.
  • the timing controller can immediately restore the reset control signal from the jump state to the initial state by the processing module in advance after the pulse of the clock reset pulse signal output by the processing module ends, so that every time the timing controller has an abnormal working condition,
  • the clock reset pulse signal is output normally and the clock of the timing controller is restored through the clock data recovery module, thereby avoiding abnormal working conditions of the timing controller during the transition stage when the reset control signal is restored from the transition state to the initial state.
  • the processing module cannot output the clock reset pulse signal normally, and the clock data recovery module cannot restore the clock of the sequential controller normally, resulting in the problem that the clocks of the sequential controller cannot be synchronized, which improves the reliability of the sequential controller.
  • FIG. 1 is a schematic structural diagram of a clock data recovery circuit of a timing controller in the prior art.
  • FIG. 2 is a timing diagram of a clock data recovery circuit of a timing controller in the prior art.
  • FIG. 3 is a schematic structural diagram of a timing controller provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a detection module of a timing controller according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a processing module of a timing controller according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a processing unit of a processing module of a timing controller according to an embodiment of the present application.
  • FIG. 7( a ) is a schematic diagram of a first specific structure of a processing module of a timing controller according to an embodiment of the present application.
  • FIG. 7( b ) is a schematic diagram of a first timing sequence of the sequence controller provided by the embodiment of the present application.
  • FIG. 8( a ) is a schematic diagram of a second specific structure of a processing module of a timing controller provided by an embodiment of the present application.
  • FIG. 8( b ) is a second timing diagram of the timing controller provided by the embodiment of the present application.
  • FIG. 9 is a schematic flowchart of a method for resetting a clock of a timing controller according to an embodiment of the present application.
  • the main function of the clock data recovery operation is to extract the data sequence from the received signal, and restore the clock timing signal corresponding to the data sequence, so as to restore the received specific information, thereby making the timing sequence
  • the controller's clock is synchronized with the system.
  • 1 is a schematic structural diagram of a clock data recovery circuit of a prior art timing controller
  • FIG. 2 is a timing diagram of a clock data recovery circuit of a prior art timing controller.
  • the current timing The clock data recovery mechanism of the controller is: detect the working state of the timing controller through the detection module and output the reset control signal Reset of the initial state when the timing controller is working normally, and then delay the reset control signal Reset and the reset control signal Reset and take it.
  • the delay obtained after inversion is fetched and the bit control signal Delay is ORed, thereby outputting the clock reset pulse signal CDR reset, thereby informing the clock data recovery module to restore the clock of the timing controller to retrain the link so that the clock of the timing controller is synchronized with the system.
  • the detection module detects that the timing controller resumes normal operation (usually after the clock reset pulse signal CDR After the reset pulse ends), the reset control signal Reset will be restored from the low level to the high level of the initial state, so as to wait for the normal output of the clock reset pulse signal CDR reset during the next restart, so as to restore the clock of the timing controller normally. That is, every time an abnormality is detected, the reset control signal Reset is switched from the high potential in the initial state to the low potential.
  • the sequence controller has abnormal working conditions or starts two consecutive times under human control, that is, there is an abnormal start between the first normal start (phase t1) and the second normal start (phase t3). (t2 stage), it may be because the time interval between the second normal start (t3 stage) and the first normal start (t1 stage) is very short, so the reset control signal Reset has not been activated by the first low level.
  • the reset control signal Reset In the case of returning to the high potential of the initial state (t2 stage), during the abnormal startup (t2 stage), the reset control signal Reset is in the transition stage from low potential to high potential, which will cause the clock reset pulse signal CDR The reset cannot be output normally (the CDR reset signal cannot be output in the t2 stage), thus causing the clock data recovery operation to fail, which may cause the clock of the sequence controller to be out of sync with the system, making the state of the sequence controller unstable, resulting in the display panel.
  • the screen is abnormal.
  • FIG. 3 is a schematic structural diagram of a timing controller provided by an embodiment of the present application.
  • the timing controller includes a detection module 301, a processing module 302, and a clock data recovery module 303 that are connected in sequence. modules are described in detail.
  • the detection module 301 is used for outputting the reset control signal Reset of the initial state in response to the normal working condition of the timing controller, and outputting the reset control signal Reset of the transition state in response to the abnormal working condition of the timing controller.
  • the abnormal working condition of the timing controller refers to a situation in which abnormal data transmission occurs in the timing controller and the abnormal data transmission lasts for a certain period of time.
  • the working state of the timing controller is detected by the detection module 301, and the reset control signal Reset of the initial state is output when the timing controller is working normally. If the working state of the timing controller is normal, the reset control signal output by the detection module 301 is output. Reset remains in the initial state; when the timing controller has an abnormal working condition, the detection module 301 converts the reset control signal Reset from the initial state to the jumping state.
  • the processing module 302 is configured to generate a clock reset pulse signal CDR reset according to the reset control signal Reset of the transition state, and, in response to the clock reset pulse signal CDR The reset pulse ends and the reset control signal Reset is restored from the transition state to the initial state.
  • the processing module 302 monitors the state of the reset control signal Reset, and outputs the clock reset pulse signal CDR when the reset control signal Reset changes from the initial state to the transition state reset.
  • the reset control signal Reset output by the detection module 301 needs a certain self-recovery duration to recover from the transition state to the initial state, and the processing module 302 can also advance the reset control signal Reset from the transition state within this self-recovery duration.
  • the clock reset pulse signal CDR The problem that reset cannot output normally.
  • the processing module 302 restores the reset control signal Reset from the jump state to the initial state in advance, and needs to be in the clock reset pulse signal CDR. After the reset pulse ends, the processing module 302 is reset after the clock signal CDR After the reset pulse ends, the reset control signal Reset is restored from the transition state to the initial state.
  • the clock data recovery module 303 is configured to recover the clock of the timing controller according to the clock reset pulse signal CDR reset.
  • the clock data recovery module 303 is a module for recovering the clock of the timing controller, and the timing controller restores the clock of the timing controller through the clock data recovery module 303 to keep the clock of the timing controller synchronized with the system.
  • the processing module 302 does not output the clock reset pulse signal CDR reset, the clock data recovery module 303 does not perform the clock data recovery operation.
  • the timing controller provided by the embodiment of the present application can reset the clock signal CDR output by the processing module 302 Immediately after the reset pulse ends, the reset control signal Reset output by the detection module 301 is restored from the jumping state to the initial state, so that the clock reset pulse signal CDR reset can be output normally every time an abnormal working condition occurs in the timing controller, and the clock reset pulse signal CDR reset can be outputted normally.
  • the data recovery module 303 recovers the clock of the timing controller, thereby preventing the timing controller from having an abnormal working condition during the transitional stage (self-recovery duration) when the reset control signal Reset returns from the transition state to the initial state, due to the reset control signal.
  • the processing module 302 cannot normally output the clock reset pulse signal CDR reset, and the clock data recovery module 303 cannot normally restore the clock of the timing controller, which leads to the problem that the clocks of the timing controller cannot be synchronized, and improves the performance of the timing controller. reliability.
  • FIG. 4 is a schematic structural diagram of a detection module 301 of a timing controller provided by an embodiment of the present application.
  • the detection module 301 includes a detection unit 3011 and a reset unit 3012 that are connected to each other, wherein:
  • the detection unit 3011 is configured to detect the working state of the timing controller and output the reset control signal Reset of the initial state when the timing controller is working normally.
  • the reset unit 3012 is configured to convert the reset control signal Reset from the initial state to the jump state when the detection unit 3011 detects that the timing controller has an abnormal working condition.
  • the working process of the detection module 301 is as follows: the detection unit 3011 detects the working state of the timing controller, including whether there is an abnormal data transmission in the timing controller, and the duration of the abnormal data transmission.
  • the reset control signal Reset of the initial state is output; when the detection unit 3011 detects that the data transmission is abnormal in the timing controller and the abnormal data transmission lasts for a certain period of time, it is determined that the timing controller has an abnormal working condition, At this time, the reset control signal Reset of the initial state output by the detection unit 3011 is converted into a transition state by the reset unit 3012 and then output.
  • the detection unit 3011 detects that the timing controller has been in a normal working state without abnormal working conditions, it will always output the reset control signal Reset of the initial state. In the working state, even if the timing controller changes from an abnormal state to a normal working state, it will output the reset control signal Reset of the initial state. At this time, the reset unit 3012 does not perform any operation on the reset control signal Reset, but directly outputs the reset control signal Reset. .
  • FIG. 5 is a schematic structural diagram of a processing module of a timing controller provided by an embodiment of the present application.
  • the processing module 302 includes a processing unit 3021 , a delay inversion unit 3022 and a logic gate unit 3023 , and the processing unit 3021
  • the input end of ⁇ is connected to the output end of the detection module 301, the output end of the processing unit 3021 is respectively connected to the input end of the delay inversion unit 3022 and the first input end of the logic gate unit 3023, and the second input end of the logic gate unit 3023 is connected The output of the delay inversion unit 3022; wherein:
  • the processing unit 3021 is used to detect the state of the reset control signal Reset and the clock reset pulse signal CDR reset, and after the pulse of the clock reset pulse signal CDR reset ends and before the reset control signal Reset returns from the jump state to the initial state, The reset control signal Reset returns from the transition state to the initial state.
  • the delay and inversion unit 3022 is configured to delay the reset control signal Reset by a preset time period and perform an inversion operation to obtain the delayed and inversion bit control signal CDR reset.
  • the logic gate unit 3023 is used to perform corresponding logic operations according to the reset control signal Reset and the delay and fetch and repeat the bit control signal Delay and output the clock reset pulse signal CDR reset, wherein the pulse width of the clock reset pulse signal CDR reset is a preset duration.
  • the working process of the processing module 302 is as follows: using the processing unit 3021 to process the reset control signal Reset and output it, and then delay the reset control signal Reset by the delay inversion unit 3022 for a preset duration and perform an inversion operation to obtain the delay Take the repeated bit control signal Delay, and finally use the logic gate unit 3023 to perform a logic operation on the reset control signal Reset and the delay take and repeat bit control signal Delay to obtain the clock reset pulse signal CDR reset.
  • the pulse width of the clock reset pulse signal CDR reset is the preset time period by which the reset control signal Reset is delayed by the delay fetching and repositioning control signal Delay.
  • the processing process of the reset control signal Reset by the processing unit 3021 is specifically: if the processing unit 3021 detects that after the pulse of the clock reset pulse signal CDR reset ends and the reset control signal Reset has not been restored from the jump state to the initial state, The reset control signal Reset is restored from the transition state to the initial state. It can be understood that when the processing unit 3021 does not detect the clock reset pulse signal CDR After the reset pulse ends and the reset control signal Reset has not been restored from the transition state to the initial state, the reset control signal Reset is directly output without changing the reset control signal Reset.
  • the processing unit 3021 includes a detection subunit 30211 and a recovery subunit 30212. in:
  • the detection sub-unit 30211 is used to detect the state of the reset control signal Reset and the clock reset pulse signal CDR reset.
  • the recovery subunit 30212 is used to reset the reset control signal Reset from the transition state after the detection subunit 30211 detects the end of the pulse of the clock reset pulse signal CDR reset and before the reset control signal Reset is restored from the transition state to the initial state return to the original state.
  • FIG. 7( a ) is a schematic diagram of the first specific structure of the processing module of the timing controller provided by the embodiment of the present application
  • FIG. 7( b ) is In the first timing diagram of the timing controller provided by the embodiment of the present application, in the embodiment of the present application, the potential of the initial state of the reset control signal Reset is a high potential, and the potential of the jump state is a low potential. Accordingly, the processing module 302
  • the logic gate unit is an OR gate.
  • the T1 stage in FIG. 7(b) represents the normal startup of the timing controller when an abnormal working condition occurs for the first time
  • the A1 stage represents the processing module 302 in the clock reset pulse After the pulse of the signal CDR reset ends and before the reset control signal Reset returns from the jump state to the initial state, the reset control signal Reset is restored from the jump state to the initial state.
  • Stage T2 indicates the second abnormality of the timing controller Normal startup under working conditions (ie, abnormal startup in Figure 2).
  • the timing controller outputs the reset control signal Reset, the delay fetching and repositioning control signal Delay and the clock reset pulse signal CDR
  • the specific process of reset working is as follows:
  • the processing module 302 delays the reset control signal Reset for a preset time period and performs an inversion operation to obtain the delayed inversion bit.
  • the processing module 302 restores the reset control signal Reset from the low level to the high level in advance in the stage when the reset control signal Reset ends after the clock reset pulse signal CDR reset and the detection module 301 has not restored the low level to the high level.
  • potential (A1 stage) which can prevent the processing module 302 from being unable to output the clock reset pulse signal CDR reset normally due to the reset control signal Reset is still at a low potential when the timing controller has an abnormal working condition at this stage, so that the clock data recovery module 303 The clock of the timing controller cannot be recovered normally.
  • FIG. 8( a ) is a schematic diagram of a second specific structure of the processing module of the timing controller provided by the embodiment of the application
  • FIG. 8( b ) is an implementation of the application.
  • the potential of the initial state of the reset control signal Reset is a low potential
  • the potential of the jump state is a high potential.
  • the logic gate of the processing module 302 The unit is an AND gate.
  • the specific working process of the timing controller is similar to the above-mentioned embodiment, and details are not repeated here.
  • the clock reset pulse signal in Figure 8(b) The start time of the rising edge of CDR reset is the end time of the rising edge of the reset control signal Reset, and the clock reset pulse signal CDR The start time of the falling edge of reset is the end time of the falling edge of the delay fetching bit control signal Delay.
  • FIG. 9 is a schematic flowchart of a method for resetting a clock of a timing controller according to an embodiment of the present application.
  • the timing controller includes a detection module 301, a processing module 302, and a clock data connected in sequence.
  • Recovery module 303; the clock reset method includes the following steps:
  • the detection module 301 outputs the reset control signal Reset of the initial state in response to the normal working condition of the timing controller, and outputs the reset control signal Reset of the transition state in response to the abnormal working condition of the timing controller.
  • the processing module 302 generates a clock reset pulse signal CDR reset according to the reset control signal Reset of the transition state, and responds to the clock reset pulse signal CDR The reset pulse ends and the reset control signal Reset is restored from the transition state to the initial state.
  • the clock of the timing controller is recovered by the clock data recovery module 303 according to the clock reset pulse signal CDR reset.
  • the clock reset method of the timing controller provided by the embodiment of the present application can immediately restore the reset control signal Reset from the jump state to the initial state after each clock reset pulse signal CDR reset is output, thereby avoiding the timing controller.
  • the reset control signal Reset returns from the transition state to the initial state when an abnormal working condition occurs, the clock reset pulse signal CDR reset cannot be output normally, so that the clock of the sequence controller cannot be restored normally, that is, the sequence
  • the controller can be applied to the case of continuous multiple starts, and the clock reset pulse signal CDR is normally output after each continuous multiple starts. reset, thereby recovering the clock of the timing controller, and improving the reliability of the clock data recovery operation of the timing controller.
  • the processing module 302 includes a processing unit 3021 , a delay inversion unit 3022 and a logic gate unit 3023 , the input terminal of the processing unit 3021 is connected to the output terminal of the detection module 301 , and the output terminals of the processing unit 3021 are respectively be connected to the input end of the delay inversion unit 3022 and the first input end of the logic gate unit 3023, and the second input end of the logic gate unit 3023 is connected to the output end of the delay inversion unit 3022;
  • the processing module 302 outputs the clock reset pulse signal CDR when the reset control signal is converted from the initial state to the transition state reset, including:
  • the reset control signal Reset is output through the processing unit 3021 .
  • the reset control signal Reset is delayed by a preset period of time through the delay inversion unit 3022 and an inversion operation is performed to obtain the delay inversion and reposition control signal Delay.
  • the logic gate unit 3023 performs corresponding logical operations according to the reset control signal Reset and the delay fetching and repositioning control signal Delay, and outputs the clock reset pulse signal CDR when the reset control signal changes from the initial state to the transition state reset; wherein, the pulse width of the clock reset pulse signal CDR reset is a preset duration.
  • the processing unit 3021 includes a detection sub-unit 30211 and a recovery sub-unit 30212 which are connected to each other;
  • the reset control signal Reset is restored from the jump state to the initial state, including:
  • the state of the reset control signal Reset and the state of the clock reset pulse signal CDR reset are detected by the detection unit 30211 .
  • the reset control signal Reset is restored from the transition state by the restoration sub-unit 30212 is the initial state.
  • an embodiment of the present application further provides a display panel, the display panel includes at least one timing controller described in any one of the foregoing embodiments.
  • the display panel has the same structure and beneficial effects as the timing controller. Since the timing controller has been described in detail in the above embodiments, it will not be repeated here.
  • timing controller The chip can no longer meet the demand, so more than two timing controller chips are often used. Whether the clock system of the timing controller is synchronized is particularly important for the stability and reliability of the display panel. Therefore, for one or more timing controllers included in the display panel, as long as the clock of one of the timing controllers is not synchronized with the system , then it is necessary to restore the clock of the sequence controller, so that the clocks of all the sequence controllers are kept synchronized.

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Abstract

本申请提供一种时序控制器、时钟复位方法及显示面板，避免了在复位控制信号由跳变状态恢复为初始状态的过渡阶段出现异常工作状况，由于复位控制信号处于跳变状态，处理模块无法正常输出时钟复位脉冲信号，时钟数据恢复模块无法正常恢复时序控制器的时钟，导致时序控制器的时钟无法同步的问题，提高了时序控制器的可靠性。

Description

时序控制器、时钟复位方法及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种时序控制器、时钟复位方法及显示面板。
 背景技术
显示面板的时序控制器在侦测到系统出现错误或异常时需要重新启动，每次启动需要恢复时序控制器的时钟，以重新对链路进行训练，使得整个系统的时钟同步。因此，时序控制器是否能在重新启动时正常地完成时钟数据恢复操作，对于时序控制器以及显示面板的稳定性和可靠性起到至关重要的作用。
目前的时序控制器在出现异常工作状况导致发生连续多次启动时，存在无法正常输出时钟复位脉冲信号，从而无法正常恢复时序控制器的时钟，导致显示面板出现画面异常的现象。
因此，有必要提出一种新的时序控制器，以及时序控制器的时钟复位方法，以在时序控制器发生多次连续启动时，每次启动都能正常输出时钟恢复信号，以使整个系统的时钟同步。
 技术问题
目前的时序控制器在出现异常工作状况导致发生连续多次启动时，存在无法正常输出时钟复位脉冲信号，从而无法正常恢复时序控制器的时钟，导致显示面板出现画面异常的现象。
 技术解决方案
为了解决上述问题，本申请实施例提供一种时序控制器、时钟复位方法及显示面板。
第一方面，本申请实施例提供一种时序控制器，该时序控制器包括依次连接的检测模块、处理模块和时钟数据恢复模块；所述检测模块用于响应于所述时序控制器的正常工作状况而输出初始状态的复位控制信号，以及，响应于所述时序控制器的异常工作状况而输出跳变状态的所述复位控制信号；所述处理模块用于根据跳变状态的所述复位控制信号生成时钟复位脉冲信号，以及，响应于所述时钟复位脉冲信号的脉冲结束而将所述复位控制信号由跳变状态恢复为初始状态；所述时钟数据恢复模块用于根据所述时钟复位脉冲信号恢复所述时序控制器的时钟。
在一些实施例中，所述检测模块包括互相连接的检测单元和复位单元；所述检测单元用于检测所述时序控制器的工作状态，并在所述时序控制器处于正常工作状况时输出初始状态的所述复位控制信号；所述复位单元用于在所述检测单元检测到所述时序控制器出现异常工作状况时，将所述复位控制信号由初始状态转换为跳变状态。
在一些实施例中，所述处理模块包括处理单元、延迟取反单元和逻辑门单元，所述处理单元的输入端与所述检测模块的输出端连接，所述处理单元的输出端分别与所述延迟取反单元的输入端和所述逻辑门单元的第一输入端连接，所述逻辑门单元的第二输入端连接所述延迟取反单元的输出端；其中：所述处理单元用于侦测所述复位控制信号和所述时钟复位脉冲信号的状态，并在所述时钟复位脉冲信号的脉冲结束之后且在所述复位控制信号由跳变状态恢复为初始状态之前，将所述复位控制信号由跳变状态恢复为初始状态；所述延迟取反单元用于将所述复位控制信号延迟预设时长并进行取反运算，以获得延迟取反复位控制信号；所述逻辑门单元用于根据所述复位控制信号和所述延迟取反复位控制信号进行相应的逻辑运算并输出所述时钟复位脉冲信号，其中，所述时钟复位脉冲信号的脉冲宽度为所述预设时长。
在一些实施例中，所述复位控制信号的初始状态为高电位，所述复位控制信号的跳变状态为低电位，以及所述逻辑门单元为或门。
在一些实施例中，所述复位控制信号的初始状态为低电位，所述复位控制信号的跳变状态为高电位，以及所述逻辑门单元为与门。
第二方面，本申请实施例还提供一种时序控制器的时钟复位方法，所述时序控制器包括依次连接的检测模块、处理模块和时钟数据恢复模块；所述时钟复位方法包括：
通过所述检测模块响应于所述时序控制器的正常工作状况而输出初始状态的复位控制信号，以及，响应于所述时序控制器的异常工作状况而输出跳变状态的所述复位控制信号。
通过所述处理模块根据跳变状态的所述复位控制信号生成时钟复位脉冲信号，以及，响应于所述时钟复位脉冲信号的脉冲结束而将所述复位控制信号由跳变状态恢复为初始状态。
通过所述时钟数据恢复模块根据所述时钟复位脉冲信号恢复所述时序控制器的时钟。
在一些实施例中，所述处理模块包括处理单元、延迟取反单元和逻辑门单元，所述处理单元的输入端与所述检测模块的输出端连接，所述处理单元的输出端分别与所述延迟取反单元的输入端和所述逻辑门单元的第一输入端连接，所述逻辑门单元的第二输入端连接所述延迟取反单元的输出端。
相应地，所述通过所述处理模块根据跳变状态的所述复位控制信号生成时钟复位脉冲信号，具体包括：
通过所述处理单元输出所述复位控制信号。
通过所述延迟取反单元将所述复位控制信号延迟预设时长并进行取反运算，以获得延迟取反复位控制信号。
通过所述逻辑门单元根据所述复位控制信号和所述延迟取反复位控制信号进行相应的逻辑运算，并在所述复位控制信号由初始状态转换为跳变状态时输出所述时钟复位脉冲信号；其中，所述时钟复位脉冲信号的脉冲宽度为所述预设时长。
在一些实施例中，所述处理单元包括互相连接的侦测子单元和恢复子单元。
相应地，所述通过所述处理模块响应于所述时钟复位脉冲信号的脉冲结束而将所述复位控制信号由跳变状态恢复为初始状态，具体包括：
通过所述侦测单元侦测所述复位控制信号的状态和所述时钟复位脉冲信号的状态；
通过所述恢复子单元在所述侦测子单元侦测到所述时钟复位脉冲信号的脉冲结束之后且在所述复位控制信号由跳变状态恢复为初始状态之前，将所述复位控制信号由跳变状态恢复为初始状态。
在一些实施例中，所述复位控制信号的初始状态为高电位，所述复位控制信号的跳变状态为低电位，以及所述逻辑门单元为或门。
在一些实施例中，所述复位控制信号的初始状态为低电位，所述复位控制信号的跳变状态为高电位，以及所述逻辑门单元为与门。
第三方面，本申请实施例还提供一种显示面板，该显示面板包括至少一个时序控制器，所述时序控制器包括依次连接的检测模块、处理模块和时钟数据恢复模块；其中：
所述检测模块，用于响应于所述时序控制器的正常工作状况而输出初始状态的复位控制信号，以及，响应于所述时序控制器的异常工作状况而输出跳变状态的所述复位控制信号；
所述处理模块，用于根据跳变状态的所述复位控制信号生成时钟复位脉冲信号，以及，响应于所述时钟复位脉冲信号的脉冲结束而将所述复位控制信号由跳变状态恢复为初始状态；
所述时钟数据恢复模块，用于根据所述时钟复位脉冲信号恢复所述时序控制器的时钟。
在一些实施例中，所述检测模块包括互相连接的检测单元和复位单元；其中：
所述检测单元，用于检测所述时序控制器的工作状态，并在所述时序控制器处于正常工作状况时输出初始状态的所述复位控制信号；
所述复位单元，用于在所述检测单元检测到所述时序控制器出现异常工作状况时，将所述复位控制信号由初始状态转换为跳变状态。
在一些实施例中，所述处理模块包括处理单元、延迟取反单元和逻辑门单元，所述处理单元的输入端与所述检测模块的输出端连接，所述处理单元的输出端分别与所述延迟取反单元的输入端和所述逻辑门单元的第一输入端连接，所述逻辑门单元的第二输入端连接所述延迟取反单元的输出端；其中：
所述处理单元用于侦测所述复位控制信号和所述时钟复位脉冲信号的状态，并在所述时钟复位脉冲信号的脉冲结束之后且在所述复位控制信号由跳变状态恢复为初始状态之前，将所述复位控制信号由跳变状态恢复为初始状态；
所述延迟取反单元用于将所述复位控制信号延迟预设时长并进行取反运算，以获得延迟取反复位控制信号；
所述逻辑门单元用于根据所述复位控制信号和所述延迟取反复位控制信号进行相应的逻辑运算并输出所述时钟复位脉冲信号，其中，所述时钟复位脉冲信号的脉冲宽度为所述预设时长。
在一些实施例中，所述处理单元包括互相连接的侦测子单元和恢复子单元；其中：
所述侦测子单元用于侦测所述复位控制信号和所述时钟复位脉冲信号的状态；
所述恢复子单元用于在所述侦测子单元侦测到所述时钟复位脉冲信号的脉冲结束之后且在所述复位控制信号由跳变状态恢复为初始状态之前，将所述复位控制信号由跳变状态恢复为初始状态。
在一些实施例中，所述复位控制信号的初始状态为高电位，所述复位控制信号的跳变状态为低电位，以及所述逻辑门单元为或门。
在一些实施例中，所述复位控制信号的初始状态为低电位，所述复位控制信号的跳变状态为高电位，以及所述逻辑门单元为与门。
 有益效果
本申请实施例提供一种时序控制器、时钟复位方法及显示面板，该时序控制器通过检测模块在时序控制器处于正常工作状况时输出初始状态的复位控制信号，而在时序控制器出现异常工作状况时输出跳变状态的复位控制信号，然后通过处理模块根据复位控制信号由初始状态转变为跳变状态输出时钟复位脉冲信号，并且，在所述时钟复位脉冲信号的脉冲结束之后立即将复位控制信号由跳变状态恢复为初始状态，最后通过时钟数据恢复模块根据时钟复位脉冲信号恢复时序控制器的时钟。
该时序控制器能在处理模块输出的时钟复位脉冲信号的脉冲结束之后，立即由处理模块提前将复位控制信号由跳变状态恢复为初始状态，从而能在时序控制器每次出现异常工作状况都正常输出时钟复位脉冲信号并通过时钟数据恢复模块恢复时序控制器的时钟，由此避免了时序控制器在复位控制信号由跳变状态恢复为初始状态的过渡阶段出现异常工作状况，由于复位控制信号处于跳变状态，处理模块无法正常输出时钟复位脉冲信号，时钟数据恢复模块无法正常恢复时序控制器的时钟，导致时序控制器的时钟无法同步的问题，提高了时序控制器的可靠性。
 附图说明
图1为现有技术的时序控制器的时钟数据恢复电路的结构示意图。
图2为现有技术的时序控制器的时钟数据恢复电路的时序图。
图3为本申请实施例提供的时序控制器的结构示意图。
图4为本申请实施例提供的时序控制器的检测模块的结构示意图。
图5为本申请实施例提供的时序控制器的处理模块的结构示意图。
图6为本申请实施例提供的时序控制器的处理模块的处理单元的结构示意图。
图7（a）为本申请实施例提供的时序控制器的处理模块的第一种具体结构示意图。
图7（b）为本申请实施例提供的时序控制器的第一种时序示意图。
图8（a）为本申请实施例提供的时序控制器的处理模块的第二种具体结构示意图。
图8（b）为本申请实施例提供的时序控制器的第二种时序示意图。
图9为本申请实施例提供的时序控制器的时钟复位方法的流程示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
在时序控制器中，时钟数据恢复操作的主要作用是从接收到的信号中提取出数据序列，并且恢复出与数据序列相对应的时钟时序信号，从而还原接收到的具体信息，由此使得时序控制器的时钟与系统保持同步。图1为现有技术的时序控制器的时钟数据恢复电路的结构示意图，图2为现有技术的时序控制器的时钟数据恢复电路的时序图，如图1和图2所示，目前的时序控制器的时钟数据恢复机制是：通过检测模块检测时序控制器的工作状态并在时序控制器正常工作时输出初始状态的复位控制信号Reset，然后将复位控制信号Reset与复位控制信号Reset延迟且取反后得到的延迟取反复位控制信号Delay进行或运算，从而输出时钟复位脉冲信号CDR reset，由此通知时钟数据恢复模块恢复时序控制器的时钟，以重新对链路进行训练，使得时序控制器的时钟与系统同步。然后，检测模块在检测到时序控制器恢复正常工作之后（一般在时钟复位脉冲信号CDR reset的脉冲结束之后），会将复位控制信号Reset由低电位恢复到初始状态的高电位，以等待下一次重新启动时正常输出时钟复位脉冲信号CDR reset，从而正常恢复时序控制器的时钟。即，每次检测到异常时，复位控制信号Reset都是由初始状态的高电位转换为低电位。
但是，如果时序控制器出现异常工作状况或者在人为控制下连续两次启动，即，在第一次正常启动（t1阶段）和第二次正常启动（t3阶段）之间还存在一次非正常启动（t2阶段），则可能由于第二次正常启动（t3阶段）距离第一次正常启动（t1阶段）的时间间隔很短，因此复位控制信号Reset存在还没有由第一次启动后的低电位恢复到初始状态的高电位的情况（t2阶段），在非正常启动（t2阶段）的过程中，复位控制信号Reset处于由低电位转换为高电位的过渡阶段，这样会导致时钟复位脉冲信号CDR reset无法正常输出（t2阶段无法输出CDR reset信号），由此使得时钟数据恢复操作失败，这样可能会使得时序控制器的时钟未与系统同步，使得时序控制器的状态不稳定，从而导致显示面板出现画面异常的现象。
为了解决上述问题，参阅图3，图3为本申请实施例提供的时序控制器的结构示意图，该时序控制器包括依次连接的检测模块301、处理模块302和时钟数据恢复模块303，以下对各个模块进行详细说明。
检测模块301，用于响应于时序控制器的正常工作状况而输出初始状态的复位控制信号Reset，以及，响应于时序控制器的异常工作状况而输出跳变状态的复位控制信号Reset。
其中，时序控制器的异常工作状况是指时序控制器中出现数据传输异常的情况且数据传输异常的情况持续一定时间。
具体地，通过检测模块301检测时序控制器的工作状态，并在时序控制器正常工作时输出初始状态的复位控制信号Reset，若时序控制器的工作状态正常，则检测模块301输出的复位控制信号Reset保持为初始状态；当时序控制器出现异常工作状况时，检测模块301将复位控制信号Reset由初始状态转换为跳变状态。
处理模块302，用于根据跳变状态的复位控制信号Reset生成时钟复位脉冲信号CDR reset，以及，响应于时钟复位脉冲信号CDR reset的脉冲结束而将复位控制信号Reset由跳变状态恢复为初始状态。
具体地，通过处理模块302监测复位控制信号Reset的状态，并在当复位控制信号Reset由初始状态转换为跳变状态时，输出时钟复位脉冲信号CDR reset。
进一步地，检测模块301输出的复位控制信号Reset由跳变状态恢复为初始状态需要一定的自恢复时长，处理模块302还能够在这段自恢复时长内，将复位控制信号Reset提前由跳变状态恢复为初始状态，以防止时序控制器在这段自恢复时长内再次出现异常工作状况时，时钟复位脉冲信号CDR reset无法正常输出的问题。
需要注意的是，为了不对前一次异常状况时输出的时钟复位脉冲信号CDR reset输出干扰，处理模块302将复位控制信号Reset提前由跳变状态恢复为初始状态的操作，需要在时钟复位脉冲信号CDR reset的脉冲结束之后再进行，即，处理模块302是在时钟复位脉冲信号CDR reset的脉冲结束之后，将复位控制信号Reset由跳变状态恢复为初始状态。
可以理解的是，如果检测模块301输出的复位控制信号Reset一直为初始状态，而没有由初始状态转换为跳变状态，则处理模块302不对复位控制信号Reset进行任何操作，也不会输出时钟复位脉冲信号CDR reset。
时钟数据恢复模块303，用于根据时钟复位脉冲信号CDR reset恢复时序控制器的时钟。
具体地，时钟数据恢复模块303是恢复时序控制器的时钟的模块，时序控制器通过时钟数据恢复模块303恢复时序控制器的时钟而使得时序控制器的时钟与系统保持同步。
可以理解的是，如果处理模块302不输出时钟复位脉冲信号CDR reset，则时钟数据恢复模块303不进行时钟数据恢复操作。
本申请实施例提供的时序控制器，能在处理模块302输出的时钟复位脉冲信号CDR reset的脉冲结束之后立即将检测模块301输出的复位控制信号Reset由跳变状态恢复为初始状态，从而能在时序控制器每次出现异常工作状况都正常输出时钟复位脉冲信号CDR reset，并通过时钟数据恢复模块303恢复时序控制器的时钟，由此避免了时序控制器在复位控制信号Reset由跳变状态恢复为初始状态的过渡阶段（自恢复时长）内出现异常工作状况时，由于复位控制信号Reset处于跳变状态，处理模块302无法正常输出时钟复位脉冲信号CDR reset，时钟数据恢复模块303无法正常恢复时序控制器的时钟，从而导致时序控制器的时钟无法同步的问题，提高了时序控制器的可靠性。
基于上述实施例，参阅图4，图4为本申请实施例提供的时序控制器的检测模块301的结构示意图，检测模块301包括互相连接的检测单元3011和复位单元3012，其中：
检测单元3011，用于检测时序控制器的工作状态并在时序控制器正常工作时输出初始状态的复位控制信号Reset。
复位单元3012，用于在检测单元3011检测到时序控制器出现异常工作状况时，将复位控制信号Reset由初始状态转换为跳变状态。
具体地，检测模块301的工作过程为：通过检测单元3011检测时序控制器的工作状态，包括时序控制器中是否出现数据传输异常的情况，以及数据传输异常的情况持续的时间，并在时序控制器正常工作时输出初始状态的复位控制信号Reset；在检测单元3011检测到时序控制器中出现数据传输异常的情况且数据传输异常的情况持续一定时间时，则判定时序控制器出现异常工作状况，此时通过复位单元3012将检测单元3011输出的初始状态的复位控制信号Reset转换为跳变状态再输出。
可以理解的是，如果检测单元3011检测到时序控制器一直处于正常工作状态而未出现异常工作状况，则一直输出初始状态的复位控制信号Reset，换言之，检测单元3011只要检测到时序控制器处于正常工作状态，即使时序控制器是由异常状况转变为正常工作状态，就会输出初始状态的复位控制信号Reset，此时，复位单元3012不对复位控制信号Reset进行任何操作而直接将复位控制信号Reset输出。
基于上述实施例，参阅图5，图5为本申请实施例提供的时序控制器的处理模块的结构示意图，处理模块302包括处理单元3021、延迟取反单元3022和逻辑门单元3023，处理单元3021的输入端与检测模块301的输出端连接，处理单元3021的输出端分别与延迟取反单元3022的输入端和逻辑门单元3023的第一输入端连接，逻辑门单元3023的第二输入端连接延迟取反单元3022的输出端；其中：
处理单元3021用于侦测复位控制信号Reset和时钟复位脉冲信号CDR reset的状态，并在时钟复位脉冲信号CDR reset的脉冲结束之后且在复位控制信号Reset由跳变状态恢复为初始状态之前，将复位控制信号Reset由跳变状态恢复为初始状态。
延迟取反单元3022用于将复位控制信号Reset延迟预设时长并进行取反运算，以获得延迟取反复位控制信号CDR reset。
逻辑门单元3023用于根据复位控制信号Reset和延迟取反复位控制信号Delay进行相应的逻辑运算并输出时钟复位脉冲信号CDR reset，其中，时钟复位脉冲信号CDR reset的脉冲宽度为预设时长。
具体地，处理模块302的工作过程为：利用处理单元3021将复位控制信号Reset经过处理后输出，然后通过延迟取反单元3022将复位控制信号Reset延迟预设时长并进行取反运算后得到延时取反复位控制信号Delay，最后利用逻辑门单元3023将复位控制信号Reset和延时取反复位控制信号Delay进行逻辑运算后得到时钟复位脉冲信号CDR reset。可以理解的是，时钟复位脉冲信号CDR reset的脉冲宽度即为延时取反复位控制信号Delay将复位控制信号Reset所延迟的预设时长。
其中，处理单元3021对复位控制信号Reset的处理过程具体为：若处理单元3021侦测到时钟复位脉冲信号CDR reset的脉冲结束之后且复位控制信号Reset还未由跳变状态恢复为初始状态时，将复位控制信号Reset由跳变状态恢复为初始状态。可以理解的是，当处理单元3021未侦测到时钟复位脉冲信号CDR reset的脉冲结束之后且复位控制信号Reset还未由跳变状态恢复为初始状态这一触发条件时，则不改变复位控制信号Reset而将复位控制信号Reset直接输出。
基于上述实施例，参阅图6，图6为本申请实施例提供的时序控制器的处理模块的处理单元的结构示意图，处理单元3021包括侦测子单元30211和恢复子单元30212。其中：
侦测子单元30211用于侦测复位控制信号Reset和时钟复位脉冲信号CDR reset的状态。
恢复子单元30212用于在侦测子单元30211侦测到时钟复位脉冲信号CDR reset的脉冲结束之后且在复位控制信号Reset由跳变状态恢复为初始状态之前，将复位控制信号Reset由跳变状态恢复为初始状态。
基于上述实施例，参阅图7（a）和图7（b），图7（a）为本申请实施例提供的时序控制器的处理模块的第一种具体结构示意图，图7（b）为本申请实施例提供的时序控制器的第一种时序示意图，本申请实施例中复位控制信号Reset的初始状态的电位为高电位，且跳变状态的电位为低电位，相应地，处理模块302的逻辑门单元为或门。
其中，对照参阅图3和图7（b），图7（b）中的T1阶段表示时序控制器第一次出现异常工作状况时的正常启动，A1阶段表示处理模块302在所述时钟复位脉冲信号CDR reset的脉冲结束之后且在复位控制信号Reset由跳变状态恢复为初始状态之前，将复位控制信号Reset由跳变状态恢复为初始状态的阶段，T2阶段表示时序控制器第二次出现异常工作状况时的正常启动（即图2中的非正常启动）。
具体地，时序控制器基于检测模块301、处理模块302和时钟数据恢复模块303输出复位控制信号Reset、延时取反复位控制信号Delay和时钟复位脉冲信号CDR reset进行工作的具体过程为：
当检测模块301输出的复位控制信号Reset由初始状态的高电位转换为跳变状态的低电位时，处理模块302将复位控制信号Reset延迟预设时长并进行取反运算后得到延时取反复位控制信号Delay，并将复位控制信号Reset和延时取反复位控制信号Delay进行或运算，则在复位控制信号Reset由高电位转换为低电位时，延时取反复位控制信号Delay仍为低电位，此刻开始输出低电位的时钟复位脉冲信号CDR reset；在延时取反复位控制信号Delay由低电位转换为高电位时，时钟复位脉冲信号CDR reset由低电位转换为高电位，即时钟复位脉冲信号CDR reset结束，因此时钟复位脉冲信号CDR reset的脉冲宽度即为延时取反复位控制信号Delay将复位控制信号Reset所延迟的预设时长。然后，处理模块302在复位控制信号Reset在时钟复位脉冲信号CDR reset结束之后且还未由检测模块301将其由低电位恢复为高电位的阶段，提前将复位控制信号Reset由低电位恢复为高电位（A1阶段），这样能防止时序控制器在该阶段出现异常工作状况时由于复位控制信号Reset仍为低电位，导致处理模块302不能正常输出时钟复位脉冲信号CDR reset，从而使时钟数据恢复模块303不能正常恢复时序控制器的时钟。
或者，参阅图8（a）和图8（b），图8（a）为本申请实施例提供的时序控制器的处理模块的第二种具体结构示意图，图8（b）为本申请实施例提供的时序控制器的第二种时序示意图，本申请实施例中复位控制信号Reset的初始状态的电位为低电位，且跳变状态的电位为高电位，相应地，处理模块302的逻辑门单元为与门。在本申请实施例中，该时序控制器的具体工作过程与上述实施例类似，此处不再赘述。
需要强调的是，图7（b）和图8（b）中的延时取反复位控制信号Delay为复位控制信号Reset进行延迟得到的，时钟复位脉冲信号CDR reset为复位控制信号Reset和延时取反复位控制信号Delay进行逻辑运算生成的。具体而言，图7（b）对应为时钟复位脉冲信号CDR reset由复位控制信号Reset和延时取反复位控制信号Delay进行“或”运算生成的情况，因此，图7（b）中的时钟复位脉冲信号CDR reset的下降沿的开始时刻为复位控制信号Reset的下降沿的结束时刻，时钟复位脉冲信号CDR reset的上升沿的开始时刻为延时取反复位控制信号Delay的上升沿的结束时刻；图8（b）对应为时钟复位脉冲信号CDR reset由复位控制信号Reset和延时取反复位控制信号Delay进行“与”运算生成的情况，因此，图8（b）中的时钟复位脉冲信号CDR reset的上升沿的开始时刻为复位控制信号Reset的上升沿的结束时刻，时钟复位脉冲信号CDR reset的下降沿的开始时刻为延时取反复位控制信号Delay的下降沿的结束时刻。
基于上述实施例，参阅图3和图9，图9为本申请实施例提供的时序控制器的时钟复位方法的流程示意图，该时序控制器包括依次连接的检测模块301、处理模块302和时钟数据恢复模块303；该时钟复位方法包括以下步骤：
S1、通过检测模块301响应于时序控制器的正常工作状况而输出初始状态的复位控制信号Reset，以及，响应于时序控制器的异常工作状况而输出跳变状态的复位控制信号Reset。
S2、通过处理模块302根据跳变状态的复位控制信号Reset生成时钟复位脉冲信号CDR reset，以及，响应于时钟复位脉冲信号CDR reset的脉冲结束而将复位控制信号Reset由跳变状态恢复为初始状态。
S3、通过时钟数据恢复模块303根据时钟复位脉冲信号CDR reset恢复时序控制器的时钟。
本申请实施例提供的时序控制器的时钟复位方法，能够在每次时钟复位脉冲信号CDR reset输出之后，立即将复位控制信号Reset由跳变状态恢复为初始状态，由此避免了该时序控制器在复位控制信号Reset由跳变状态恢复为初始状态的过渡阶段出现异常工作状况时，时钟复位脉冲信号CDR reset无法正常输出，从而无法正常恢复时序控制器的时钟的问题，也就是说，该时序控制器能够应用于连续多次启动的情况，在连续多次启动的每次启动后都正常输出时钟复位脉冲信号CDR reset，从而恢复时序控制器的时钟，提高了时序控制器的时钟数据恢复操作的可靠性。
基于上述实施例，参阅图5，处理模块302包括处理单元3021、延迟取反单元3022和逻辑门单元3023，处理单元3021的输入端与检测模块301的输出端连接，处理单元3021的输出端分别与延迟取反单元3022的输入端和逻辑门单元3023的第一输入端连接，逻辑门单元3023的第二输入端连接延迟取反单元3022的输出端；
通过处理模块302在复位控制信号由初始状态转换为跳变状态时输出时钟复位脉冲信号CDR reset，具体包括：
通过处理单元3021输出复位控制信号Reset。
通过延迟取反单元3022将复位控制信号Reset延迟预设时长并进行取反运算，以获得延迟取反复位控制信号Delay。
通过逻辑门单元3023根据复位控制信号Reset和延迟取反复位控制信号Delay进行相应的逻辑运算，并在复位控制信号由初始状态转换为跳变状态时输出时钟复位脉冲信号CDR reset；其中，时钟复位脉冲信号CDR reset的脉冲宽度为预设时长。
基于上述实施例，参阅图6，处理单元3021包括互相连接的侦测子单元30211和恢复子单元30212；
在时钟复位脉冲信号CDR reset的脉冲结束之后且在复位控制信号由跳变状态恢复为初始状态之前，将复位控制信号Reset由跳变状态恢复为初始状态，具体包括：
通过侦测单元30211侦测复位控制信号Reset的状态和时钟复位脉冲信号CDR reset的状态。
通过恢复子单元30212在侦测子单元30211侦测到时钟复位脉冲信号CDR reset的脉冲结束之后且在复位控制信号Reset由跳变状态恢复为初始状态之前，将复位控制信号Reset由跳变状态恢复为初始状态。
基于同一发明构思，本申请实施例还提供一种显示面板，该显示面板包括至少一个上述任一实施方式所述的时序控制器。该显示面板与该时序控制器具有相同的结构和有益效果，由于上述各实施例已经对该时序控制器进行了详细的描述，此处不再赘述。
最后需要强调的是，随着消费升级和技术发展，显示面板的尺寸越来越大，规格也越来越高，目前的高阶产品由于高解析度和刷新率的需求，一颗时序控制器芯片已经不能满足需求，因此经常需要用到两颗以上的时序控制器芯片。而时序控制器的时钟系统是否同步，对于显示面板的稳定性和可靠性尤为重要，因此针对显示面板所包括的一个或多个时序控制器，只要其中一个时序控制器的时钟未与系统保持同步，则都需要使其恢复时序控制器的时钟，从而使得所有时序控制器的时钟均保持同步。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (17)

  1. 一种时序控制器，其包括依次连接的检测模块、处理模块和时钟数据恢复模块；
    所述检测模块，用于响应于所述时序控制器的正常工作状况而输出初始状态的复位控制信号，以及，响应于所述时序控制器的异常工作状况而输出跳变状态的所述复位控制信号；
    所述处理模块，用于根据跳变状态的所述复位控制信号生成时钟复位脉冲信号，以及，响应于所述时钟复位脉冲信号的脉冲结束而将所述复位控制信号由跳变状态恢复为初始状态；
    所述时钟数据恢复模块，用于根据所述时钟复位脉冲信号恢复所述时序控制器的时钟。
  2. 如权利要求1所述的一种时序控制器，其中，所述检测模块包括互相连接的检测单元和复位单元；
    所述检测单元，用于检测所述时序控制器的工作状态，并在所述时序控制器处于正常工作状况时输出初始状态的所述复位控制信号；
    所述复位单元，用于在所述检测单元检测到所述时序控制器出现异常工作状况时，将所述复位控制信号由初始状态转换为跳变状态。
  3. 如权利要求1所述的一种时序控制器，其中，所述处理模块包括处理单元、延迟取反单元和逻辑门单元，所述处理单元的输入端与所述检测模块的输出端连接，所述处理单元的输出端分别与所述延迟取反单元的输入端和所述逻辑门单元的第一输入端连接，所述逻辑门单元的第二输入端连接所述延迟取反单元的输出端；其中：
    所述处理单元用于侦测所述复位控制信号和所述时钟复位脉冲信号的状态，并在所述时钟复位脉冲信号的脉冲结束之后且在所述复位控制信号由跳变状态恢复为初始状态之前，将所述复位控制信号由跳变状态恢复为初始状态；
    所述延迟取反单元用于将所述复位控制信号延迟预设时长并进行取反运算，以获得延迟取反复位控制信号；
    所述逻辑门单元用于根据所述复位控制信号和所述延迟取反复位控制信号进行相应的逻辑运算并输出所述时钟复位脉冲信号，其中，所述时钟复位脉冲信号的脉冲宽度为所述预设时长。
  4. 如权利要求3所述的一种时序控制器，其中，所述处理单元包括互相连接的侦测子单元和恢复子单元；
    所述侦测子单元用于侦测所述复位控制信号和所述时钟复位脉冲信号的状态；
    所述恢复子单元用于在所述侦测子单元侦测到所述时钟复位脉冲信号的脉冲结束之后且在所述复位控制信号由跳变状态恢复为初始状态之前，将所述复位控制信号由跳变状态恢复为初始状态。
  5. 如权利要求3所述的一种时序控制器，其中，所述复位控制信号的初始状态为高电位，所述复位控制信号的跳变状态为低电位，以及所述逻辑门单元为或门。
  6. 如权利要求3所述的一种时序控制器，其中，所述复位控制信号的初始状态为低电位，所述复位控制信号的跳变状态为高电位，以及所述逻辑门单元为与门。
  7. 一种时序控制器的时钟复位方法，其中，所述时序控制器包括依次连接的检测模块、处理模块和时钟数据恢复模块；所述时钟复位方法包括：
    通过所述检测模块响应于所述时序控制器的正常工作状况而输出初始状态的复位控制信号，以及，响应于所述时序控制器的异常工作状况而输出跳变状态的所述复位控制信号；
    通过所述处理模块根据跳变状态的所述复位控制信号生成时钟复位脉冲信号，以及，响应于所述时钟复位脉冲信号的脉冲结束而将所述复位控制信号由跳变状态恢复为初始状态；
    通过所述时钟数据恢复模块根据所述时钟复位脉冲信号恢复所述时序控制器的时钟。
  8. 如权利要求7所述的时序控制器的时钟复位方法，其中，所述处理模块包括处理单元、延迟取反单元和逻辑门单元，所述处理单元的输入端与所述检测模块的输出端连接，所述处理单元的输出端分别与所述延迟取反单元的输入端和所述逻辑门单元的第一输入端连接，所述逻辑门单元的第二输入端连接所述延迟取反单元的输出端；
    所述通过所述处理模块根据跳变状态的所述复位控制信号生成时钟复位脉冲信号，具体包括：
    通过所述处理单元输出所述复位控制信号；
    通过所述延迟取反单元将所述复位控制信号延迟预设时长并进行取反运算，以获得延迟取反复位控制信号；
    通过所述逻辑门单元根据所述复位控制信号和所述延迟取反复位控制信号进行相应的逻辑运算，并在所述复位控制信号由初始状态转换为跳变状态时输出所述时钟复位脉冲信号；其中，所述时钟复位脉冲信号的脉冲宽度为所述预设时长。
  9. 如权利要求7所述的时序控制器的时钟复位方法，其中，所述处理单元包括互相连接的侦测子单元和恢复子单元；
    所述通过所述处理模块响应于所述时钟复位脉冲信号的脉冲结束而将所述复位控制信号由跳变状态恢复为初始状态，具体包括：
    通过所述侦测单元侦测所述复位控制信号的状态和所述时钟复位脉冲信号的状态；
    通过所述恢复子单元在所述侦测子单元侦测到所述时钟复位脉冲信号的脉冲结束之后且在所述复位控制信号由跳变状态恢复为初始状态之前，将所述复位控制信号由跳变状态恢复为初始状态。
  10. 如权利要求8所述的时序控制器的时钟复位方法，其中，所述复位控制信号的初始状态为高电位，所述复位控制信号的跳变状态为低电位，以及所述逻辑门单元为或门。
  11. 如权利要求8所述的时序控制器的时钟复位方法，其中，所述复位控制信号的初始状态为低电位，所述复位控制信号的跳变状态为高电位，以及所述逻辑门单元为与门。
  12. 一种显示面板，其包括至少一个时序控制器，所述时序控制器包括依次连接的检测模块、处理模块和时钟数据恢复模块；
    所述检测模块，用于响应于所述时序控制器的正常工作状况而输出初始状态的复位控制信号，以及，响应于所述时序控制器的异常工作状况而输出跳变状态的所述复位控制信号；
    所述处理模块，用于根据跳变状态的所述复位控制信号生成时钟复位脉冲信号，以及，响应于所述时钟复位脉冲信号的脉冲结束而将所述复位控制信号由跳变状态恢复为初始状态；
    所述时钟数据恢复模块，用于根据所述时钟复位脉冲信号恢复所述时序控制器的时钟。
  13. 如权利要求12所述的显示面板，其中，所述检测模块包括互相连接的检测单元和复位单元；
    所述检测单元，用于检测所述时序控制器的工作状态，并在所述时序控制器处于正常工作状况时输出初始状态的所述复位控制信号；
    所述复位单元，用于在所述检测单元检测到所述时序控制器出现异常工作状况时，将所述复位控制信号由初始状态转换为跳变状态。
  14. 如权利要求12所述的显示面板，其中，所述处理模块包括处理单元、延迟取反单元和逻辑门单元，所述处理单元的输入端与所述检测模块的输出端连接，所述处理单元的输出端分别与所述延迟取反单元的输入端和所述逻辑门单元的第一输入端连接，所述逻辑门单元的第二输入端连接所述延迟取反单元的输出端；
    所述处理单元用于侦测所述复位控制信号和所述时钟复位脉冲信号的状态，并在所述时钟复位脉冲信号的脉冲结束之后且在所述复位控制信号由跳变状态恢复为初始状态之前，将所述复位控制信号由跳变状态恢复为初始状态；
    所述延迟取反单元用于将所述复位控制信号延迟预设时长并进行取反运算，以获得延迟取反复位控制信号；
    所述逻辑门单元用于根据所述复位控制信号和所述延迟取反复位控制信号进行相应的逻辑运算并输出所述时钟复位脉冲信号，其中，所述时钟复位脉冲信号的脉冲宽度为所述预设时长。
  15. 如权利要求12所述的显示面板，其中，所述处理单元包括互相连接的侦测子单元和恢复子单元；
    所述侦测子单元用于侦测所述复位控制信号和所述时钟复位脉冲信号的状态；
    所述恢复子单元用于在所述侦测子单元侦测到所述时钟复位脉冲信号的脉冲结束之后且在所述复位控制信号由跳变状态恢复为初始状态之前，将所述复位控制信号由跳变状态恢复为初始状态。
  16. 如权利要求14所述的显示面板，其中，所述复位控制信号的初始状态为高电位，所述复位控制信号的跳变状态为低电位，以及所述逻辑门单元为或门。
  17. 如权利要求14所述的显示面板，其中，所述复位控制信号的初始状态为低电位，所述复位控制信号的跳变状态为高电位，以及所述逻辑门单元为与门。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1975523A (zh) * 2005-11-28 2007-06-06 Lg.菲利浦Lcd株式会社 液晶显示装置及其驱动方法
US20170116954A1 (en) * 2015-10-22 2017-04-27 Samsung Electronics Co., Ltd. Clock and data recovery circuit detecting unlock of output of phase locked loop
CN106782410A (zh) * 2017-02-21 2017-05-31 昆山龙腾光电有限公司 液晶显示装置及其驱动方法
CN111404543A (zh) * 2020-05-27 2020-07-10 深圳市汇顶科技股份有限公司 时钟数据恢复电路、处理芯片及电子设备
CN111986603A (zh) * 2020-08-10 2020-11-24 深圳市华星光电半导体显示技术有限公司 显示装置以及电子设备
CN112837644A (zh) * 2021-01-07 2021-05-25 Tcl华星光电技术有限公司 时序控制器及其时钟复位方法、显示面板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101470501B (zh) * 2007-12-26 2010-12-15 珠海中慧微电子有限公司 一种延时复位控制电路及方法
US8878792B2 (en) * 2009-08-13 2014-11-04 Samsung Electronics Co., Ltd. Clock and data recovery circuit of a source driver and a display device
KR102640827B1 (ko) * 2018-12-03 2024-02-28 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
JPWO2020158524A1 (ja) * 2019-01-30 2021-12-02 パナソニックＩｐマネジメント株式会社 表示システムおよび表示装置の制御方法
KR102626169B1 (ko) * 2019-03-19 2024-01-18 삼성전자주식회사 디스플레이 장치 및 디스플레이 장치의 제어 방법
CN111326098B (zh) * 2020-04-08 2022-10-04 Tcl华星光电技术有限公司 源极驱动控制方法、装置及显示终端

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1975523A (zh) * 2005-11-28 2007-06-06 Lg.菲利浦Lcd株式会社 液晶显示装置及其驱动方法
US20170116954A1 (en) * 2015-10-22 2017-04-27 Samsung Electronics Co., Ltd. Clock and data recovery circuit detecting unlock of output of phase locked loop
CN106782410A (zh) * 2017-02-21 2017-05-31 昆山龙腾光电有限公司 液晶显示装置及其驱动方法
CN111404543A (zh) * 2020-05-27 2020-07-10 深圳市汇顶科技股份有限公司 时钟数据恢复电路、处理芯片及电子设备
CN111986603A (zh) * 2020-08-10 2020-11-24 深圳市华星光电半导体显示技术有限公司 显示装置以及电子设备
CN112837644A (zh) * 2021-01-07 2021-05-25 Tcl华星光电技术有限公司 时序控制器及其时钟复位方法、显示面板

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