WO2022147900A1 - 芯片的电源调节电路及方法 - Google Patents

芯片的电源调节电路及方法 Download PDF

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Publication number
WO2022147900A1
WO2022147900A1 PCT/CN2021/079740 CN2021079740W WO2022147900A1 WO 2022147900 A1 WO2022147900 A1 WO 2022147900A1 CN 2021079740 W CN2021079740 W CN 2021079740W WO 2022147900 A1 WO2022147900 A1 WO 2022147900A1
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WIPO (PCT)
Prior art keywords
chip
circuit
current
power supply
adjustable
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PCT/CN2021/079740
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English (en)
French (fr)
Inventor
陆让天
王先宏
吕鹏方
温长清
梁爱梅
Original Assignee
深圳市紫光同创电子有限公司
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Priority to KR1020237015870A priority Critical patent/KR20230084563A/ko
Publication of WO2022147900A1 publication Critical patent/WO2022147900A1/zh
Priority to US18/344,871 priority patent/US20230341883A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/004—Capacitive coupling circuits not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks

Definitions

  • the present application relates to the technical field of semiconductor integrated circuits, and more particularly, to a chip power regulation circuit and method.
  • the power integrity problem needs to be considered, the purpose is to ensure the performance of the chip.
  • IC integrated Circuit Chip
  • CPU Central Processing Unit
  • FPGA Field Programmable Gate Array
  • the power supply voltage must be guaranteed to be within tolerance, and the DC error, ripple and noise, etc., are all within the allowable range.
  • the resonant frequency of the power supply circuit is usually fixed.
  • the operating frequency of the chip changes, it cannot match the operating frequency of the chip, and the power integrity of the chip cannot be well guaranteed.
  • the present application proposes a chip power regulation circuit and method to solve the above problems.
  • an embodiment of the present application provides a power supply adjustment circuit for a chip, which includes: an LC circuit and an LC correction circuit, wherein: one end of the LC circuit is used for electrical connection with the positive electrode of the chip and the positive electrode of the power supply, respectively, and the LC circuit The other end is used to be electrically connected to the negative pole of the chip and the negative pole of the power supply respectively; the LC correction circuit is electrically connected to the chip and the LC circuit respectively, and is used to adjust the working parameters of the LC circuit according to the current working mode of the chip.
  • an embodiment of the present application provides a power supply adjustment method for a chip, which is applied to the power supply adjustment circuit of the chip in the first aspect.
  • the method includes: acquiring a current working mode of the chip; adjusting based on the current working mode the operating parameters of the LC circuit.
  • the power supply adjustment circuit and method for a chip provided by the embodiments of the present application are composed of an LC circuit and an LC correction circuit.
  • the other end of the circuit is used to be electrically connected to the negative electrode of the chip and the negative electrode of the power supply respectively; the LC correction circuit is electrically connected to the chip and the LC circuit respectively.
  • the LC correction circuit can adjust the working parameters of the LC circuit according to the current working mode of the chip, so as to realize the self-adaptive function of the resonance frequency of the power supply, even if the working frequency of the chip changes due to the change of the working mode It can ensure the power integrity of the chip.
  • FIG. 1 shows a circuit schematic diagram of a chip power supply circuit in the related art provided according to an embodiment of the present application.
  • FIG. 2 shows a circuit schematic diagram of a chip power supply circuit provided according to an embodiment of the present application.
  • FIG. 3 shows a circuit schematic diagram of a chip power supply circuit provided according to another embodiment of the present application.
  • FIG. 4 shows a schematic circuit diagram of a power supply adjustment circuit provided according to an embodiment of the present application.
  • FIG. 5 shows a circuit schematic diagram of a power supply regulation circuit provided according to another embodiment of the present application.
  • FIG. 6 shows a schematic flowchart of a power supply adjustment method provided according to an embodiment of the present application.
  • FIG. 7 shows a schematic flowchart of a power supply adjustment method provided according to another embodiment of the present application.
  • FIG. 8 shows a schematic flowchart of a power supply adjustment method provided according to still another embodiment of the present application.
  • FIG. 9 shows a schematic flowchart of a power supply adjustment method provided according to still another embodiment of the present application.
  • FIG. 10 shows a schematic flowchart of a power supply adjustment method provided according to yet another embodiment of the present application.
  • FIG. 11 shows a functional block diagram of a power conditioning apparatus provided according to an embodiment of the present application.
  • VLSI Very Large Scale Integration
  • the power integrity problem of integrated circuits is closely related to the parasitic RLC parameters of the packaged power circuit.
  • the resistance R in the parasitic RLC will increase the DC error of the power supply, and the LC circuit will increase the power supply ripple and noise interference.
  • RLC parasitic parameters are well suppressed, such as flip-chip packaging. But more advanced packaging means more expensive costs.
  • a decoupling capacitor Cdie is often placed on the chip.
  • this approach does not always provide decoupling and sometimes does more harm than good.
  • the package parasitic inductance Lpkg of the power supply and the chip decoupling capacitor Cdie will form oscillation, which is used to match the resonant frequency of the power supply with the operating frequency of the chip to ensure the integrity of the chip power supply.
  • the resonant frequency of the power supply is also fixed, so when the operating frequency of the chip changes, the resonant frequency of the power supply will no longer match the operating frequency of the chip, resulting in the inability to ensure the integrity of the chip power supply. .
  • the package parasitic inductance Lpkg of the power supply and the on-chip decoupling capacitor Cdie will oscillate, if the oscillation frequency is the same as the operating frequency of the chip, the power supply ripple inside the chip will be so large that it may exceed the power supply voltage capacity of the chip. poor request.
  • an RLC resonant circuit is connected in parallel between the two ends of the decoupling capacitor Cdie.
  • RLC circuit at its resonant frequency
  • providing a zero impedance R0 can prevent the oscillation at this frequency, thereby stabilizing the chip's internal power supply VDD_die.
  • this method still has the defect that it cannot match the different operating frequencies of the chip: it can only stabilize the power supply at a single resonant frequency point, and can only provide a single zero-point impedance; and with process deviation and temperature changes, its frequency point The change is large, and the zero-point impedance is very different from the actual working current, which can easily cause the power supply ripple to be too large and exceed the power supply tolerance requirements. Therefore, this method is limited to applications where the chip operates at a single fixed operating frequency and a single fixed operating current, and the accuracy of the frequency point and zero point impedance is not high, the package design is difficult, and the design cycle is long.
  • the inventor proposes the power supply adjustment circuit and method of the chip in the embodiment of the present application, which can avoid the application limitations of the single fixed operating frequency and single fixed operating current of the chip; , The difference between the zero-point impedance and the actual working current is large, which is easy to cause the problem that the power supply ripple is too large and exceeds the power supply tolerance requirements; and solve the problems of difficult packaging design and long design cycle.
  • FIG. 4 shows a schematic circuit diagram of a power supply adjustment circuit provided by an embodiment of the present application.
  • the power supply adjustment circuit 100 can be applied to the chip 100 in FIG. 4 , and the chip 200 and the power supply 300 form a loop.
  • the power regulation circuit 100 of the chip may include an LC correction circuit 110 and an LC circuit 120 .
  • one end of the LC circuit 120 can be electrically connected to the positive electrode of the chip 200 and the positive electrode of the power supply 300 respectively, and the other end of the LC circuit 120 can be electrically connected to the negative electrode of the chip 200 and the negative electrode of the power supply 300 respectively;
  • the LC correction circuit 110 It can be electrically connected to the chip 200 and the LC circuit 120, respectively, for adjusting the working parameters of the LC circuit 120 according to the current working mode of the chip 200.
  • the power supply 300 can be packaged with a chip decoupling capacitor Cdie and two parasitic inductances Lpkg, that is, the power supply 300 includes a power supply VDC, an on-chip coupling capacitor Cdie and two parasitic inductances Lpkg, wherein the first one of the on-chip coupling capacitor Cdie The terminals are respectively electrically connected to the positive pole of the power supply VDC and the positive pole of the chip 200 , and the second terminal of the on-chip coupling capacitor Cdie is respectively electrically connected to the negative pole of the power supply VDC and the negative pole of the chip.
  • a parasitic inductance Lpkg is connected in series between the on-chip coupling capacitor Cdie and the positive electrode of the power supply VDC.
  • a parasitic inductance Lpkg is connected in series between the on-chip coupling capacitor Cdie and the negative pole of the power supply VDC.
  • the LC calibration circuit 120 can detect the current working mode of the chip 200 , and then adjust the working parameters of the LC circuit 120 according to the current working mode of the chip 200 .
  • a mapping relationship between multiple working modes of the chip 200 and multiple working parameters of the LC circuit 120 may be established in advance, each working mode of the chip 200 corresponds to one working parameter of the LC circuit 120 , and then the LC correction circuit 110 It can be determined whether the current operating parameters of the LC circuit 120 match the current operating mode of the chip 200 , and if not, the current operating parameters of the LC circuit 120 are adjusted to the operating parameters matching the current operating mode of the chip 200 . If it matches, you can do nothing.
  • the LC correction circuit 110 can detect the parameters such as the current value, the working frequency and the voltage value of the chip 200 to determine the chip 200 .
  • the operating parameter of the LC circuit 120 may be the resonance frequency.
  • the power supply adjustment circuit 100 of the chip 200 is formed by the LC circuit 120 and the LC correction circuit 110, wherein: one end of the LC circuit 120 is used to be electrically connected to the positive electrode of the chip 200 and the positive electrode of the power supply 300, respectively, The other end of the LC circuit 120 is used to be electrically connected to the negative electrode of the chip 200 and the negative electrode of the power supply 300 respectively; the LC correction circuit 110 is electrically connected to the chip 200 and the LC circuit 120 respectively.
  • the LC correction circuit 110 can adjust the operating parameters of the LC circuit 120 according to the current operating mode of the chip 200, so as to realize the self-adaptive function of the resonant frequency of the power supply, even if the chip 200 is caused by the change of the operating mode When the operating frequency changes, the power integrity of the chip 200 can also be guaranteed.
  • the LC circuit 120 includes an adjustable capacitor C_M and an adjustable inductor L_M, and one end of the adjustable capacitor C_M and the adjustable inductor L_M connected in series can be electrically connected to the positive electrode of the chip 200 and the positive electrode of the power supply, respectively.
  • the other end of the adjustable capacitor C_M connected in series with the adjustable inductor L_M may be electrically connected to the negative electrode of the chip 200 and the negative electrode of the power supply 300 respectively.
  • the LC correction circuit 110 may be electrically connected to the adjustable capacitor C_M and the adjustable inductor L_M, respectively, for adjusting the inductance value of the adjustable inductor L_M and the capacitance value of the adjustable capacitor C_M according to the current operating mode of the chip 200 .
  • the operating parameter of the LC circuit 120 may be the resonant frequency, which is calculated according to the resonant frequency formula It can be seen that the resonant frequency of the LC circuit 120 can be calculated according to the inductance value of the adjustable inductor L_M and the capacitance value of the adjustable capacitor C_M. Therefore, the LC correction circuit 110 can adjust the inductance value of the adjustable inductor L_M according to the current working mode of the chip 200 and the capacitance value of the adjustable capacitor C_M, so as to realize the adjustment of the resonant frequency of the LC circuit 120 , that is, the adjustment of the working parameters of the LC circuit 120 .
  • the operating frequency of the chip 200 in the current operating mode matches the resonant frequency of the LC circuit 120
  • it can be determined that the operating parameters of the LC circuit 120 match the current operating mode of the chip 200 so it can be determined according to the current operating mode of the chip 200.
  • the inductance value of the adjustable inductor L_M and the capacitance value of the adjustable capacitor C_M are adjusted according to the operating frequency in the mode, so that the adjusted resonant frequency of the LC circuit 120 matches the operating frequency in the current operating mode.
  • the resonance frequency and the working frequency are consistent, it can be determined that the resonance frequency and the working frequency match.
  • the difference between the resonance frequency and the working frequency is within a preset difference range, it may be determined that the resonance frequency and the working frequency match.
  • the LC circuit 120 can also be connected in series with a zero-point impedance to prevent oscillation and avoid the appearance of ripples.
  • the zero-point impedance may be a resistor with a fixed resistance value, or may be an adjustable resistor R_M, which is not limited herein.
  • the LC circuit 120 includes an adjustable capacitor C_M and an adjustable inductor L_M, and one end of the adjustable capacitor C_M and the adjustable inductor L_M connected in series can be electrically connected to the positive electrode of the chip 200 and the positive electrode of the power supply 300, respectively.
  • the other end of the adjustable capacitor C_M connected in series with the adjustable inductor L_M may be electrically connected to the negative electrode of the chip 200 and the negative electrode of the power supply 300 respectively.
  • the LC correction circuit 110 can be electrically connected to the adjustable capacitor C_M and the adjustable inductor L_M respectively, and is used to adjust the inductance value of the adjustable inductor L_M and the capacitance value of the adjustable capacitor C_M according to the current working mode of the chip 200 , so as to be convenient and effective. to adjust the operating parameters of the LC circuit 120.
  • the power conditioning circuit 100 may further include an adjustable resistor R_M and an impedance configuration circuit 130 . in:
  • One end of the adjustable resistor R_M connected in series with the LC circuit 120 can be electrically connected to the positive electrode of the chip 200 and the positive electrode of the power supply 300 respectively, and the other end of the adjustable resistor R_M connected in series with the LC circuit 120 can be connected to the negative electrode of the chip 200 and the power supply 300 respectively. negative electrical connection.
  • the impedance configuration circuit 130 is electrically connected to the chip 200 and the adjustable resistor R_M respectively, and is used for adjusting the resistance value of the adjustable resistor R_M according to the current working mode of the chip 200 .
  • the impedance configuration circuit 130 and the LC correction circuit 110 may be packaged together, or may be provided separately, which is not limited.
  • the impedance configuration circuit 130 can detect the current working mode of the chip 200 , and then adjust the resistance value of the adjustable resistor R_M according to the current working mode of the chip 200 .
  • multiple working modes of the chip 200 can be established in advance With the mapping relationship of multiple resistance values of the adjustable resistor R_M, each working mode of the chip 200 corresponds to a resistance value of the adjustable resistor R_M, and then, the impedance configuration circuit 130 can determine whether the current resistance value of the adjustable resistor R_M is the same as that of the chip.
  • the current working mode of the chip 200 matches, if not, the current resistance value of the adjustable resistor R_M is adjusted to a resistance value matching the current working mode of the chip 200 . If it matches, you can do nothing.
  • the impedance configuration circuit 130 can detect the working current in the current working mode of the chip 200, and then adjust the current resistance value of the adjustable resistor R_M according to the working current.
  • the real-time power supply voltage of the chip 200 is equal to the product of the working current of the chip 200 and the adjustable resistor R_M, when the product of the working current of the chip 200 and the resistance value of the adjustable resistor R_M is between the rated voltage of the chip 200 When the tolerance does not exceed ⁇ 5%, it can be determined that the resistance value of the adjustable resistor R_M matches the current working mode of the chip 200 . This ensures that the power supply voltage of the chip 200 is within the power supply tolerance.
  • the oscillation frequency of the LC circuit is the same as the operating frequency of the chip, the power supply ripple inside the chip will be so large that it may exceed the tolerance requirement.
  • One end of the LC circuit in series can be electrically connected to the positive pole of the chip and the positive pole of the power supply, and the other end of the adjustable resistor connected in series with the LC circuit can be electrically connected to the negative pole of the chip and the negative pole of the power supply respectively, so as to configure the zero impedance to prevent oscillation , to avoid the appearance of ripples.
  • the impedance configuration circuit is used to adjust the resistance value of the adjustable resistor according to the current working mode of the chip, so as to configure the zero-point impedance correspondingly, so as to provide a corresponding configuration with the actual working mode of the chip.
  • Matching zero point impedance avoids the problem of excessive power supply ripple exceeding the power supply tolerance requirements.
  • FIG. 6 shows a schematic flowchart of a power supply adjustment method provided by an embodiment of the present application.
  • the method can be applied to the power supply adjustment circuit shown in FIG. 4 in the above-mentioned embodiment, and can be specifically applied to the LC correction circuit.
  • the method can include:
  • the LC correction circuit can detect the current value, operating frequency, voltage value, power and other parameters of the chip to determine The current operating mode of the chip.
  • the range values of various working parameters of the chip under different working modes can be recorded in advance, as an example, as shown in Table 1:
  • Operating mode Current value mA
  • Operating frequency GHz
  • Voltage value V
  • working mode 1 a1 ⁇ a2 b1 ⁇ b2 c1 ⁇ c2 work mode 2 a3 ⁇ a4 b3 ⁇ b4 c3 ⁇ c4 work mode 3 a5 ⁇ a6 b5 ⁇ b6 c5 ⁇ c6
  • the current working mode of the chip can be obtained by query. For example, when it is detected that the current current value of the chip is A, and A is within the range of a3 to a4, it can be determined that the current working mode of the chip is working mode 2. For another example, when it is detected that the current operating frequency of the chip is B, and B is within the range of b5-b6, it can be determined that the current operating mode of the chip is operating mode 3.
  • the current working mode of the chip can be obtained quickly and effectively according to Table 1.
  • each operating mode of the chip corresponds to an operating parameter of the LC circuit
  • the LC correction circuit can determine whether the current operating parameter of the LC circuit matches the current operating mode of the chip, and if not, the LC circuit
  • the current working parameters of the chip are adjusted to the working parameters matching the current working mode of the chip. If it matches, you can do nothing.
  • the operating parameters of the LC circuit may include the resonant frequency of the LC circuit.
  • the operating parameters of the LC circuit match the current operating mode of the chip, for example, when the resonant frequency of the LC circuit is consistent with the operating frequency in the current operating mode of the chip, the power integrity of the chip can be ensured and the power supply can be guaranteed. It can supply power to the chip stably.
  • the power configuration parameters of the chip can be adaptively adjusted to match the working mode of the chip quickly and effectively, avoiding the need for The problem that the power integrity requirements of the chip cannot be met when the working mode of the chip is changed due to the single constant power configuration parameter.
  • FIG. 7 shows a schematic flowchart of a power supply adjustment method provided by another embodiment of the present application.
  • the method can be applied to the LC correction circuit of the power supply adjustment circuit shown in FIG. 4 in the above-mentioned embodiment.
  • the method may include:
  • S210 can refer to S110, so it is not repeated here.
  • the clock signal of the chip may also refer to the clock frequency of the chip, which is equivalent to the operating frequency of the chip.
  • the operating frequency can be directly determined as the current clock signal of the chip.
  • the LC correction circuit detects that the parameters of the chip do not include the operating frequency, then the current operating mode of the chip can be determined according to Table 1 and other detected parameters of the chip (such as voltage value, current value), and then look up according to Table 1.
  • the operating frequency corresponding to the current operating mode is obtained, thereby obtaining the current clock signal of the chip.
  • the operating frequency corresponding to the current operating mode is in the range value in Table 1
  • the average value of the range value may be used as the current clock signal, or the minimum value of the range value may be used as the current clock signal
  • the maximum value of the range value can be used as the current clock signal, which can be set according to the actual situation.
  • the specific implementation of S230 may be to adjust the inductance value of the adjustable inductor and the capacitance value of the adjustable capacitor based on the current clock signal to adjust the resonant frequency of the LC circuit, wherein the adjusted resonant frequency is the same as the current clock signal match.
  • the current clock signal of the chip is determined according to the current working mode, based on the current clock signal. Adjusting the working parameters of the LC circuit can more quickly and effectively adjust the working parameters of the LC circuit to match the working mode of the chip, thereby ensuring the power integrity of the chip.
  • FIG. 8 shows a schematic flowchart of a power supply adjustment method provided by another embodiment of the present application.
  • the method can be applied to the power supply adjustment circuit shown in FIG. 5 in the above-mentioned embodiment. Specifically, it can be applied to FIG.
  • the LC correction circuit and impedance configuration circuit of 5, the method may include:
  • S310 to S320 can be referred to S110 to S120, so they are not repeated here.
  • an adjustable resistor that is, a zero-point impedance
  • the LC circuit may be connected in series with the LC circuit to prevent the oscillation of the operating frequency fdie of the chip, thereby further stabilizing the power supply VDD_die of the chip. Because the resistance value of the zero-point impedance needs to be matched with the working mode of the chip, so as to avoid the power supply ripple being too large and exceeding the power supply tolerance requirement. Therefore, it is necessary to adjust the resistance value of the adjustable resistor according to the current working mode of the chip.
  • the resistance mapping relationship between different working modes of the chip and different resistance values of the adjustable resistor may be established in advance, and the specific establishment method may refer to the establishment method in Table 1.
  • the impedance configuration circuit can determine the resistance value corresponding to the current working mode according to the mapping relationship of the resistance value and the current working mode of the chip. If the current resistance value of the adjustable resistor is inconsistent with the resistance value corresponding to the current working mode, it can be The current resistance value of the adjustable resistor is adjusted to the resistance value corresponding to the current working mode. If they are consistent, you can do nothing.
  • the working current of the chip will also change. If the zero-point impedance is fixed, it may be very different from the actual working current of the chip, and it is easy to cause the power supply ripple to be too large and exceed the power supply. Tolerance requirements.
  • the resistance value of the adjustable resistor based on the current working mode, it is ensured that when the working mode of the chip changes, the resistance value of the zero-point impedance can also be adjusted adaptively, so as to avoid excessive power supply ripple and cause Exceeding power supply tolerance requirements.
  • FIG. 9 shows a schematic flowchart of a power supply adjustment method provided by still another embodiment of the present application.
  • the method can be applied to the power supply adjustment circuit shown in FIG. 5 in the above embodiment, and the method may include:
  • S410 to S420 can be referred to S110 to S120, so they are not repeated here.
  • the current value corresponding to the current working mode may be obtained by referring to the look-up table 1.
  • the rated voltage value of the chip can be pre-stored in the storage module of the impedance configuration circuit for calling, and the anti-configuration circuit can first identify the identification information such as the model of the chip, and then call from the storage module according to the identification information.
  • the rated voltage corresponding to the identification information wherein the mapping relationship between the identification information of different chips and different rated voltage values may also be pre-stored in the impedance configuration circuit.
  • the product of the resistance value of the adjustable resistor and the current value in the current working mode is consistent with the rated voltage value.
  • the product of the resistance value of the adjustable resistor and the current value in the current working mode is consistent with the rated voltage value. This ensures that the chip's supply voltage is within tolerance.
  • the chip may generate a configuration bus signal M_cfg based on the rated voltage value and current value, and then send the configuration bus signal M_cfg to the impedance configuration circuit to instruct the impedance configuration circuit to adjust the adjustable resistor to adjust its resistance value to match the configuration bus signal.
  • S440 a specific embodiment of adjusting the resistance value of the adjustable resistor based on the rated voltage value and the current value may be, when the difference between the product of the adjusted resistance value and the current value and the rated voltage value is absolute The value does not exceed the specified value, confirm that the product of the adjusted resistance value and the current value matches the rated voltage, and stop the adjustment of the adjustable resistance.
  • the specified value may be 5% of the rated voltage value X of the chip, ie (5%X)V, if the absolute value of the difference between the product of the adjusted resistance value and the current value and the rated voltage value When X is -3%X, it can be determined that the product of the adjusted resistance value and the current value matches the rated voltage, and the adjustment of the adjustable resistance is stopped.
  • the specified value may be related to the performance parameter of the chip, and the specified value corresponding to different chips may be different.
  • the current value of the chip in the current working mode and the rated voltage value of the chip are obtained, and the adjustable resistance is adjusted based on the rated voltage value and current value.
  • the product of the adjusted resistance value and the current value matches the rated voltage, so that the zero-point impedance matching the actual working current can be provided, so as to avoid excessive power supply ripple and exceed the power supply tolerance requirements.
  • FIG. 10 shows a schematic flowchart of a power supply adjustment method provided by still another embodiment of the present application.
  • the method can be applied to the power supply adjustment circuit shown in FIG. 5 in the above embodiment, and the method may include:
  • S510 Receive an enable signal output by the chip.
  • the enable signal may be used to control the working states of the impedance configuration circuit and the LC correction circuit, wherein the working states of the impedance configuration circuit and the LC correction circuit may include an on state, an off state, and the like.
  • an enable signal when the chip switches the working state, an enable signal can be generated, and the enable signal can be sent to the impedance configuration circuit and the LC correction circuit, so as to control the core impedance configuration circuit and the LC correction circuit according to the enable signal.
  • the enable signal may be the configuration bus signal M_cfg in FIG. 5 .
  • the impedance configuration circuit is turned off, and the LC correction circuit is turned off.
  • the impedance configuration circuit and the LC correction circuit receive the enable signal output by the chip, and
  • the enable signal is an enable signal for instructing the impedance configuration circuit and the LC correction circuit to be turned on, so that the impedance configuration circuit can be controlled to be turned on and the LC correction circuit can be controlled to be turned on.
  • S540 Determine the current clock signal of the chip according to the current working mode.
  • S530 to S540 can be referred to S210 to S230, so they are not repeated here.
  • S560 to S570 may refer to S430 to S440, and thus are not repeated here.
  • the working states of the impedance configuration circuit and the LC correction circuit can be adjusted. is turned off to save power consumption.
  • the impedance configuration circuit and the LC correction circuit can be turned on again.
  • the power supply adjustment method in this embodiment may be applied to a chip power supply circuit as shown in FIG. 5 , and the circuit may include a chip decoupling capacitor Cdie, a power supply adjustment circuit, and a chip.
  • One end of the on-chip decoupling capacitor Cdie is connected to the chip internal power supply VDD_die, and the other end is connected to the chip ground wire.
  • One end of the power regulation circuit is connected to the chip's internal power supply VDD_die, the other end is connected to the chip ground wire, and is connected in parallel with the chip decoupling capacitor Cdie.
  • One end of the chip is connected to the internal power supply VDD_die of the chip, and the other end is connected to the ground wire of the chip.
  • the chip is connected to the power conditioning circuit through the chip clock signal fdie, the control bus signal ctrl and the configuration bus signal M_cfg.
  • the power supply adjustment circuit includes an adjustable capacitor C_M, an adjustable inductor L_M, an LC correction circuit, an adjustable resistor R_M, and an impedance configuration circuit.
  • the chip When the chip power supply circuit works, the chip outputs the chip clock signal fdie to the LC correction circuit in the power supply adjustment circuit.
  • the chip can output the corresponding configuration bus signal M_cfg to the impedance configuration circuit in the power supply adjustment circuit according to the working mode and current of the chip, and the impedance configuration circuit provides a zero point that matches the actual working current by adjusting the resistor R_M impedance to avoid excessive power supply ripple beyond the power supply tolerance requirements.
  • the chip can output the control bus signal ctrl to the power supply adjustment circuit, and control the power supply adjustment circuit accordingly.
  • the control bus signal ctrl is equivalent to an enable signal, and can be used to control when the impedance configuration circuit and the LC correction circuit in the power conditioning circuit are turned on and off.
  • the zero-point impedance can be configured accordingly to provide a zero-point impedance that matches the actual working current, so as to avoid excessive power supply ripple and exceed the power supply tolerance requirements.
  • the power supply adjustment method provided in this embodiment can endow the chip with strong versatility, and can be applied to various occasions with different working modes, different working frequencies and different working currents.
  • the self-adaptive function of the resonance frequency is realized, and the zero-point impedance matches the actual working current, which does not change with the change of process deviation or temperature, which significantly reduces the difficulty of packaging design and shortens the design cycle.
  • the packaging solution can use a low-cost wire bonding process, and the packaging substrate does not need to place filter capacitors, which significantly reduces packaging costs.
  • FIG. 11 shows a power supply adjustment device provided by an embodiment of the present application, which is applied to the power supply adjustment circuit of the chip of the above-mentioned embodiment.
  • the device 600 includes: a current working mode acquisition module 610 and a working parameter adjustment module 620 ,in:
  • the current working mode obtaining module 610 is configured to obtain the current working mode of the chip.
  • the working parameter adjustment module 620 is configured to adjust the working parameters of the LC circuit based on the current working mode.
  • the working parameter adjustment module 620 includes:
  • the current clock signal determination sub-module is used to determine the current clock signal of the chip according to the current working mode.
  • the working parameter adjustment sub-module is used to adjust the working parameters of the LC circuit based on the current clock signal.
  • the LC circuit includes an adjustable capacitor and an adjustable inductor connected in series with each other, and a working parameter adjustment sub-module is specifically used to adjust the inductance value of the adjustable inductor and the capacitance value of the adjustable capacitor based on the current clock signal, so as to adjust the LC circuit.
  • the resonant frequency of wherein the adjusted resonant frequency matches the current clock signal.
  • the power supply adjustment circuit of the chip further includes: an adjustable resistor and an impedance configuration circuit, the adjustable resistor is connected in series with the LC circuit, and the impedance configuration circuit is electrically connected to the chip and the adjustable resistor respectively, and the device 600 further includes:
  • the resistance adjustment module is used to adjust the resistance value of the adjustable resistance based on the current working mode.
  • the resistance adjustment module includes:
  • the information acquisition sub-module is used to acquire the current value of the chip in the current working mode and the rated voltage value of the chip.
  • the resistance adjustment sub-module is used for adjusting the resistance value of the adjustable resistance based on the rated voltage value and the current value, wherein the product of the adjusted resistance value and the current value matches the rated voltage.
  • the resistance adjustment sub-module is specifically used to determine the product of the adjusted resistance value and the current value when the absolute value of the difference between the product of the adjusted resistance value and the current value and the rated voltage value does not exceed a specified value. Match the rated voltage and stop adjusting the adjustable resistor.
  • the apparatus 600 further includes:
  • the enable signal receiving module is used for receiving the enable signal output by the chip.
  • the working state control module is used for controlling the working states of the impedance configuration circuit and the LC correction circuit according to the enable signal.
  • the coupling or direct coupling or communication connection between the modules shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or modules may be electrical, mechanical or otherwise.
  • each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist physically alone, or two or more modules may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules.
  • the power supply adjustment circuit and method provided in this embodiment can avoid the application limitations of a single fixed operating frequency and a single fixed operating current of the chip; solve the problem of unstable frequency point, large difference between zero point impedance and actual operating current, It is easy to cause the problem that the power supply ripple is too large and exceed the power supply tolerance requirements; and solve the problems of difficult package design and long design cycle.

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Abstract

提供了一种芯片的电源调节电路及方法，涉及半导体集成电路技术领域。电源调节电路（100）包括：LC电路（120）以及LC校正电路（110），其中， LC电路（120）的一端用于分别与芯片（200）的正极和电源（300）的正极电连接，LC电路（120）的另一端用于分别与芯片（200）的负极和电源（300）的负极电连接；LC校正电路（110），LC校正电路（110）分别与芯片（200）和LC电路（120）电连接，用于根据芯片（200）的当前工作模式调节LC电路（120）的工作参数，从而实现电源的谐振频点自适应功能，即使芯片因工作模式变化而导致工作频率变化时，也能够保证芯片的电源完整性。

Description

芯片的电源调节电路及方法
相关申请的交叉引用
本申请要求于2021年01月06日提交的申请号为202110014731.1的中国申请的优先权，其在此处于所有目的通过引用将其全部内容并入本文。
技术领域
本申请涉及半导体集成电路技术领域，更具体地，涉及一种芯片的电源调节电路及方法。
背景技术
在集成电路设计中，需要考虑电源完整性问题，目的是保证芯片工作性能。比如，对于高性能数字微型电子芯片(Integrated Circuit Chip，IC)，比如中央处理器(Central Processing Unit，CPU)、现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)等，在保证芯片工作时的电源完整性时，必须保证其电源电压处于容差内、以及直流误差、纹波和噪声等都处于允许范围内。
然而，电源电路的谐振频率通常是固定的，当芯片的工作频率发生变化时，则无法与芯片的工作频率匹配，从容导致无法较好地保证芯片的电源完整性。
发明内容
鉴于上述问题，本申请提出了一种芯片的电源调节电路及方法，以解决上述问题。
第一方面，本申请实施例提供了一种芯片的电源调节电路，该包括：LC电路以及LC校正电路，其中：LC电路的一端用于分别与芯片的正极和电源的正极电连接，LC电路的另一端用于分别与芯片的负极和电源的负极电连接；LC校正电路分别与芯片和LC电路电连接，用于根据芯片的当前工作模式调节LC电路的工作参数。
第二方面，本申请实施例提供了一种芯片的电源调节方法，应用于第一方面的芯片的电源调节电路，该方法包括：获取所述芯片的当前工作模式；基于所述当前工作模式调节所述LC电路的工作参数。
本申请实施例提供的芯片的电源调节电路及方法，通过LC电路以及LC校正电路构成的芯片的电源调节电路，其中：LC电路的一端用于分别与芯片的正极和电源的正极电连接，LC电路的另一端用于分别与芯片的负极和电源的负极电连接；LC校正电路分别与芯片和LC电路电连接。当电源对芯片进行供电时，LC校正电路可以根据芯片的当前工作模式调节LC电路的工作参数，从而实现电源的谐振频点自适应功能，即使芯片因工作模式变化而导致工作频率变化时，也能够 保证芯片的电源完整性。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了根据本申请实施例提供的相关技术中芯片电源电路的电路原理图。
图2示出了根据本申请一种实施例提供的芯片电源电路的电路原理图。
图3示出了根据本申请另一种实施例提供的芯片电源电路的电路原理图。
图4示出了根据本申请一种实施例提供的电源调节电路的电路原理图。
图5示出了根据本申请另一种实施例提供的电源调节电路的电路原理图。
图6示出了根据本申请一种实施例提供的电源调节方法的流程示意图。
图7示出了根据本申请另一种实施例提供的电源调节方法的流程示意图。
图8示出了根据本申请又一种实施例提供的电源调节方法的流程示意图。
图9示出了根据本申请再一种实施例提供的电源调节方法的流程示意图。
图10示出了根据本申请又另一种实施例提供的电源调节方法的流程示意图。
图11示出了根据本申请实施例提供的电源调节装置的原理框图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本申请的描述中，需要说明的是，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
在本申请的描述中，还需要说明的是，除非另有明确的规定和限定，术语“设置”、“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然， 所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
现代的超大规模集成电路(Very Large Scale Integration，VLSI)系统，规模越来越大，工作频率越来越高，工作电流越来越大，而电源电压却越来越低，即电源容差要求越来越严苛，从而导致芯片的电源完整性问题变得非常严峻。
集成电路的电源完整性问题，与封装的电源电路的寄生RLC参数息息相关，比如寄生RLC中的电阻R会增加电源直流误差，LC电路则增加电源纹波和噪声干扰。随着封装技术的发展，RLC寄生参数得到很好抑制，比如flip-chip封装形式。但是更先进的封装，代表着更昂贵的成本。
如图1所示，在相关技术中，为了解决电源完整性问题，保证芯片内部电源VDD_die的稳定，往往是在芯片上放置去耦电容Cdie。但是，这种方案并不总能起到去耦作用，有时候甚至弊大于利。通常电源的封装寄生电感Lpkg与片上去耦电容Cdie会形成振荡，用于使电源的谐振频率与芯片的工作频率相匹配，以确保芯片电源的完整性，然而，由于去耦电容Cdie和电感Lpkg的参数是配置好的，导致电源的谐振频率也是固定不变的，所以当芯片的工作频率发生改变时，电源的谐振频率将不在与芯片的工作频率相匹配，导致无法保证芯片电源的完整性。
另外，因为电源的封装寄生电感Lpkg与片上去耦电容Cdie会形成振荡，如果这个振荡频率与芯片工作频率相同，那么芯片内部电源纹波将会很大，以至于可能超过芯片的电源电压的容差要求。
发明人发现，如图2所示，如果在寄生电感Lpkg和芯片的正极之间串联一个电阻Rdie，可以有效阻止振荡，从而避免纹波的出现，但是又增加了直流误差。
发明人继续研究发现，如图3所示，在去耦电容Cdie两端并联一个RLC谐振电路。RLC电路在其谐振频率
Figure PCTCN2021079740-appb-000001
处，提供一个零点阻抗R0，就可以阻止了在这个频率上的振荡，从而把芯片内部电源VDD_die稳定下来。
但是，该方法仍然存在无法匹配芯片的不同工作频率的缺陷：它只能在单一谐振频点上使得电源稳定，也只能提供单一零点阻抗；且随着工艺偏差以及温度变化，它的频点变化很大，而零点阻抗与实际工作电流差异很大，很容易造成电源纹波过大而超过电源容差要求。因此，这种方法，仅局限于芯片在单一固定工作频率和单一固定工作电流的应用场合，且频点和零点阻抗的精度不高，封装设计难度大、设计周期长。
因此，针对于上述问题，发明人提出了本申请实施例中的芯片的电源调节电路及方法，能够实现避免芯片的单一固定工作频率和单一固定工作电流的应用场合局限性；解决频点不稳定、零点阻抗与实际工作电流差异大，容易造成电源纹波过大而超过电源容差要求的问题；以及解决封装设计难度大、设计周期长等问题。
请参阅图4，图4示出了本申请一个实施例提供的电源调节电路的电路原理图，该电源调节电路100可以应用于图4中的芯片100，该芯片200与电源300形成回路。该芯片的电源调节电路100可以包括LC校正电路110以及LC电路120。
在实际应用中，LC电路120的一端可以分别与芯片200的正极和电源300的正极电连接，LC电路120的另一端可以分别与芯片200的负极和电源300的负极电连接；LC校正电路110可以分 别与芯片200和LC电路电120连接，用于根据芯片200的当前工作模式调节LC电路120的工作参数。
在一些实施方式中，电源300中可以封装片上去耦电容Cdie以及两个寄生电感Lpkg，即电源300包括电源VDC、片上耦电容Cdie以及两个寄生电感Lpkg，其中，片上耦电容Cdie的第一端分别与电源VDC的正极和芯片200的正极电连接，片上耦电容Cdie的第二端分别与电源VDC的负极和芯片的负极电连接。其中，片上耦电容Cdie与电源VDC的正极之间串联一个寄生电感Lpkg。片上耦电容Cdie与电源VDC的负极之间串联一个寄生电感Lpkg。
当电源VDC需要对芯片200进行供电时，LC校正电路120可以检测芯片200的当前工作模式，然后根据芯片200的当前工作模式来调节LC电路120的工作参数。作为一种方式，可以预先建立芯片200的多个工作模式与LC电路120的多个工作参数的映射关系，芯片200的每一个工作模式对应LC电路120的一个工作参数，随后，LC校正电路110可以判断LC电路120的当前工作参数是否与芯片200的当前工作模式匹配，若不匹配，则将LC电路120的当前工作参数调节为与该芯片200的当前工作模式匹配的工作参数。若匹配，则可以不做任何处理。可选地，由于芯片200在不同工作模式下的电流值、工作频率、电压值等参数不同，因此LC校正电路110可以检测芯片200的电流值、工作频率、电压值等参数来确定该芯片200的当前工作模式。其中，LC电路120的工作参数可以为谐振频率。
可以理解的是，当LC电路120的当前工作参数与芯片200的当前工作模式匹配时，可以保证芯片200电源VDD_die的稳定、确保芯片200电源的完整性。
可见，在本实施例中，通过LC电路120以及LC校正电路110构成的芯片200的电源调节电路100，其中：LC电路120的一端用于分别与芯片200的正极和电源300的正极电连接，LC电路120的另一端用于分别与芯片200的负极和电源300的负极电连接；LC校正电路110分别与芯片200和LC电路120电连接。当电源300对芯片200进行供电时，LC校正电路110可以根据芯片200的当前工作模式调节LC电路120的工作参数，从而实现电源的谐振频点自适应功能，即使芯片200因工作模式变化而导致工作频率变化时，也能够保证芯片200的电源完整性。
请再次参阅图5，其中，LC电路120包括可调电容C_M和可调电感L_M，可调电容C_M与可调电感L_M串联后的一端可以分别与芯片200的正极和电源的正极电连接，可调电容C_M与可调电感L_M串联后的另一端可以分别与芯片200的负极和电源300的负极电连接。
LC校正电路110可以分别与可调电容C_M和可调电感L_M电连接，用于根据芯片200的当前工作模式调节可调电感L_M的电感值和可调电容C_M的电容值。
在实际应用中，LC电路120的工作参数可以为谐振频率，根据谐振频率计算公式
Figure PCTCN2021079740-appb-000002
Figure PCTCN2021079740-appb-000003
可知，LC电路120的谐振频率可以根据可调电感L_M的电感值和可调电容C_M的电容值计算得到，因此，LC校正电路110可以根据芯片200的当前工作模式调节可调电感L_M的电感值和可调电容C_M的电容值，从而实现对LC电路120的谐振频率的调节，即对LC电路120的工作参数的调节。
可选地，当芯片200在当前工作模式下的工作频率与LC电路120的谐振频率匹配时，可以确定LC电路120的工作参数与芯片200的当前工作模式匹配，因此可以根据芯片200在当前工作模式下的工作 频率来调节可调电感L_M的电感值和可调电容C_M的电容值，使得调节后的LC电路120的谐振频率与当前工作模式下的工作频率匹配。可选地，当谐振频率和工作频率一致时，可以确定谐振频率和工作频率匹配。可选地，当谐振频率和工作频率之间的差值处于预设差值范围内时，可以确定谐振频率和工作频率匹配。
可选地，LC电路120还可以串联一个零点阻抗，阻止振荡，避免纹波的出现。可选地，该零点阻抗可以是固定阻值的电阻，也可以是可调电阻R_M，在此不做限定。
在本实施例中，通过LC电路120包括可调电容C_M和可调电感L_M，可调电容C_M与可调电感L_M串联后的一端可以分别与芯片200的正极和电源300的正极电连接，可调电容C_M与可调电感L_M串联后的另一端可以分别与芯片200的负极和电源300的负极电连接。LC校正电路110可以分别与可调电容C_M和可调电感L_M电连接，用于根据芯片200的当前工作模式调节可调电感L_M的电感值和可调电容C_M的电容值，从而能够方便、有效地调节LC电路120的工作参数。
请参阅图5，在一些实施例中，该电源调节电路100还可以包括：可调电阻R_M以及阻抗配置电路130。其中：
可调电阻R_M与LC电路120串联后的一端可以分别与芯片200的正极和电源300的正极电连接，可调电阻R_M与LC电路120串联后的另一端可以分别与芯片200的负极和电源300的负极电连接。
阻抗配置电路130分别与芯片200和可调电阻R_M电连接，用于根据芯片200的当前工作模式调节可调电阻R_M的电阻值。可选地，阻抗配置电路130和LC校正电路110可以封装在一起，也可以分开设置，对此不作限定。
在实际应用中，阻抗配置电路130可以检测芯片200的当前工作模式，然后根据芯片200的当前工作模式调节可调电阻R_M的电阻值，作为一种方式，可以预先建立芯片200的多个工作模式与可调电阻R_M的多个电阻值的映射关系，芯片200的每一个工作模式对应可调电阻R_M的一个电阻值，随后，阻抗配置电路130可以判断可调电阻R_M的当前电阻值是否与芯片200的当前工作模式匹配，若不匹配，则将可调电阻R_M的当前电阻值调节为与该芯片200的当前工作模式匹配的电阻值。若匹配，则可以不做任何处理。
其中，当可调电阻R_M的当前电阻值与芯片200的当前工作模式匹配时，可以确定芯片200的电源电压在处于电源容差内。具体地，阻抗配置电路130可以检测芯片200的当前工作模式下的工作电流，然后根据工作电流来调节可调电阻R_M的当前电阻值。作为一种示例，由于芯片200的实时电源电压等于芯片200的工作电流与可调电阻R_M的积，当芯片200的工作电流与可调电阻R_M的电阻值的积与芯片200的额定电压之间的容差不超过±5％时，则可以确定可调电阻R_M的电阻值与芯片200的当前工作模式匹配。从而确保芯片200的电源电压处于电源容差内。
考虑到如果LC电路的振荡频率与芯片工作频率相同，那么芯片内部电源纹波将会很大，以至于可能超过容差要求，在本实施例中，通过设置可调电阻，且可调电阻与LC电路串联后的一端可以分别与芯片的正极和电源的正极电连接，可调电阻与LC电路串联后的另一端可以分别与芯片的负极和电源的负极电连接，从而配置零点阻抗以阻止振荡，避免纹波的出现。另外，通过设置阻抗配置电路分别与芯 片和可调电阻电连接，用于根据芯片的当前工作模式调节可调电阻的电阻值，从而对零点阻抗进行相应配置，以提供与芯片的实际工作模式相匹配的零点阻抗，避免造成电源纹波过大而超过电源容差要求的问题。
请参阅图6，图6示出了本申请一个实施例提供的电源调节方法的流程示意图，该方法可以应用于上述实施例中图4所示的电源调节电路，具体可以应用于的LC校正电路，该方法可以包括：
S110，获取芯片的当前工作模式。
在一些实施方式中，由于芯片在不同工作模式下的电流值、工作频率、电压值、功率等参数不同，因此LC校正电路可以检测芯片的电流值、工作频率、电压值、功率等参数来确定该芯片的当前工作模式。具体地，可以预先记录芯片在不同工作模式下的各种工作参数的范围值，作为一种示例，如表1所示：
表1
工作模式 电流值(mA) 工作频率(GHz) 电压值(V)
工作模式1 a1～a2 b1～b2 c1～c2
工作模式2 a3～a4 b3～b4 c3～c4
工作模式3 a5～a6 b5～b6 c5～c6
可见，根据表1和芯片的电流值、工作频率、电压值中任意一个参数或多个参数，可以查询得到芯片的当前工作模式。例如，当检测到芯片的当前电流值为A，A处于a3～a4的范围内，则可以确定芯片的当前工作模式为工作模式2。又例如，当检测到芯片的当前工作频率为B，B处于b5～b6的范围内，则可以确定芯片的当前工作模式为工作模式3。依次类推，可以根据表1快速、有效地获得芯片的当前工作模式。
S120，基于当前工作模式调节LC电路的工作参数。
在一些实施方式中，芯片的每一个工作模式对应LC电路的一个工作参数，随后，LC校正电路可以判断LC电路的当前工作参数是否与芯片的当前工作模式匹配，若不匹配，则将LC电路的当前工作参数调节为与该芯片的当前工作模式匹配的工作参数。若匹配，则可以不做任何处理。其中，LC电路的工作参数可以包括LC电路的谐振频率。
可以理解的是，当LC电路的工作参数与芯片的当前工作模式匹配时，例如，LC电路的谐振频率与芯片的当前工作模式下的工作频率一致时，可以确保芯片的电源完整性，保证电源能够对芯片稳定供电。
在本实施例中，通过获取芯片的当前工作模式，基于当前工作模式调节LC电路的工作参数，能够快捷、有效地将芯片的电源配置参数自适应地调节到与芯片的工作模式匹配，避免了因电源配置参数单一不变，而导致芯片的工作模式改变时，无法满足芯片的电源完整性要求的问题。
请参阅图7，图7示出了本申请另一个实施例提供的电源调节方法的流程示意图，该方法可以应用于上述实施例中图4所示的电源调节电路的LC校正电路，具体可以应用于的LC校正电路，该方法可 以包括：
S210，获取芯片的当前工作模式。
其中，S210的具体实施方式可以参考S110，故不在此赘述。
S220，根据当前工作模式确定芯片的当前时钟信号。
其中，芯片的时钟信号也可以是指芯片的时钟频率，相当于的芯片的工作频率。
承前述实施例的内容，在一些实施方式中，若LC校正电路检测到芯片的参数中包括工作频率，则可以直接将该工作频率确定为芯片的当前时钟信号。
在另一些实施方式中。若LC校正电路检测到芯片的参数中不包括工作频率，那可以根据表1和检测到的芯片的其他参数(如电压值、电流值)确定芯片的当前工作模式，然后再根据表1查找到与该当前工作模式对应的工作频率，从而获得芯片的当前时钟信号。可选地，当该当前工作模式对应的工作频率在表1中时范围值时，可以将该范围值的平均值作为当前时钟信号，也可以将该范围值的最小值作为当前时钟信号，还可以将该范围值的最大值作为当前时钟信号，具体可以根据实际情况设定。
S230，基于当前时钟信号调节LC电路的工作参数。
在一些实施方式中，S230的具体实施方式可以是，基于当前时钟信号调节可调电感的电感值和可调电容的电容值，以调节LC电路的谐振频率，其中，调节后的谐振频率与当前时钟信号匹配。
作为一种示例，该将芯片时钟信号fdie输出到该电源调节电路的LC校正电路。基于谐振频率计算公式
Figure PCTCN2021079740-appb-000004
可知，该LC校正电路可以对可调电容C_M或/和可调电感L_M进行调整，可以实现fr＝fdie，从而把芯片的电源VDD_die稳定下来。同理，当芯片的工作模式发生改变时，其芯片的工作频率也会发生改变，该电源调节电路的谐振频率fr实时根据芯片的工作频率fdie做调整，从而实现自适应功能，不受工艺偏差以及温度变化的影响。
考虑到芯片的时钟信号反映工作频率，而工作频率与电源的谐振频率是否一致为电源完整性的重要指标，在本实施例中，通过根据当前工作模式确定芯片的当前时钟信号，基于当前时钟信号调节LC电路的工作参数，能够更快捷、有效地将LC电路的工作参数调节到与芯片的工作模式匹配，从而确保芯片的电源完整性。
请参阅图8，图8示出了本申请又一个实施例提供的电源调节方法的流程示意图，该方法可以应用于上述实施例中图5所示的电源调节电路，具体地，可以应用于图5中的LC校正电路和阻抗配置电路，该方法可以包括：
S310，获取芯片的当前工作模式。
S320，基于当前工作模式调节LC电路的工作参数。
其中，S310至S320的具体实施方式可以参考S110至S120，故不在此赘述。
S330，基于当前工作模式调节可调电阻的电阻值。
在一些实施方式中，如图5所示，可以在LC电路处串联一个可调电阻，即零点阻抗，阻止芯片的工作频率fdie的振荡，从而进一步把芯片的电源VDD_die稳定下来。因为零点阻抗的阻值需要与芯片的工作模式相匹配，以避免电源纹波过大而超过电源容差要求。所以需要根据芯片的当 前工作模式调节可调电阻的电阻值。
作为一种示例，可以预先建立芯片不同工作模式和可调电阻的不同电阻值之间的阻值映射关系，具体的建立方式可以参考表1的建立方式。阻抗配置电路可以根据该阻值映射关系和芯片的当前工作模式，确定与该当前工作模式对应的电阻值，如果可调电阻的当前电阻值与该当前工作模式对应的电阻值不一致，则可以将可调电阻的当前电阻值调节至与该当前工作模式对应的电阻值。如果一致，则可以不做任何处理。
考虑到当芯片的工作模式改变时，该芯片的工作电流也会发生改变，如果零点阻抗固定不变的话，可能与芯片的实际工作电流差异很大，很容易造成电源纹波过大而超过电源容差要求。在本实施例中，通过基于当前工作模式调节可调电阻的电阻值，从而确保在芯片的工作模式发生改变时，零点阻抗的电阻值也可以适应性地调整，避免造成电源纹波过大而超过电源容差要求的情况。
请参阅图9，图9示出了本申请再一个实施例提供的电源调节方法的流程示意图，该方法可以应用于上述实施例中图5所示的电源调节电路，该方法可以包括：
S410，获取芯片的当前工作模式。
S420，基于当前工作模式调节LC电路的工作参数。
其中，S410至S420的具体实施方式可以参考S110至S120，故不在此赘述。
S430，获取芯片在当前工作模式下的电流值以及芯片的额定电压值。
在一些实施方式中，当芯片的工作模式确定以后，可以参考查询表1的方式，获取与该当前工作模式对应的电流值，即该当前工作模式下的电流值。可选地，芯片的额定电压值可以预先存储在阻抗配置电路的存储模块中以供调用，抗配置电路可以先识别该芯片的型号等标识信息，然后根据该标识信息从存储模块中调用与该标识信息对应的额定电压，其中，不同芯片的标识信息和不同的额定电压值的映射关系也可以预先存储在阻抗配置电路中。
S440，基于额定电压值和电流值调节可调电阻的电阻值，其中，调节后的电阻值和电流值的积与额定电压相匹配。
作为一种示例，可以检测可调电阻的电阻值与当前工作模式下的电流值的积，是否与额定电压值一致，若一致，则可以不做任何处理；若不一致，则可以调节可调电阻的电阻值，使可调电阻的电阻值与当前工作模式下的电流值的积与额定电压值一致。从而保证芯片的电源电压处于容差内。
可选地，芯片可以基于额定电压值和电流值生成配置总线信号M_cfg，然后将配置总线信号M_cfg发送至阻抗配置电路，以指示阻抗配置电路将可调电阻将其电阻值调节至与配置总线信号M_cfg对应的电阻值。
在一些实施方式中，S440，基于额定电压值和电流值调节可调电阻的电阻值的具体实施方式可以是，当调节后的电阻值和电流值的积与额定电压值之间的差值绝对值不超过指定值，确定调节后的电阻值和电流值的积与额定电压相匹配，并停止对可调电阻的调节。
作为一种示例，指定值可以是芯片的额定电压值X的5％，即(5％X)V，若当调节后的电阻值和电流值的积与额定电压值之间的差值绝对值为X 为-3％X时，则可以确定调节后的电阻值和电流值的积与额定电压相匹配，并停止对可调电阻的调节。其中，指定值可以与芯片的性能参数相关，不同的芯片对应的指定值可以不同。
考虑到不同的芯片对应的电源容差有所不同，在本实施例中，通过获取芯片在当前工作模式下的电流值以及芯片的额定电压值，并基于额定电压值和电流值调节可调电阻的电阻值，其中，调节后的电阻值和电流值的积与额定电压相匹配，从而能够提供与实际工作电流相匹配的零点阻抗，避免造成电源纹波过大而超过电源容差要求。
请参阅图10，图10示出了本申请又另一个实施例提供的电源调节方法的流程示意图，该方法可以应用于上述实施例中图5所示的电源调节电路，该方法可以包括：
S510，接收芯片输出的使能信号。
其中，使能信号可以用于控制阻抗配置电路和LC校正电路的工作状态，其中，阻抗配置电路和LC校正电路的工作状态可以包括开启状态、关闭状态等。
在一些实施方式中，当芯片切换工作状态时，可以生成使能信号，并将该使能信号发送给阻抗配置电路和LC校正电路，以根据使能信号控制芯阻抗配置电路和LC校正电路的工作状态。具体地，使能信号具体可以是图5中的配置总线信号M_cfg。
S520，根据使能信号控制阻抗配置电路和LC校正电路的工作状态。
作为一种示例，例如在芯片切换工作状态之前，阻抗配置电路为关闭状态，LC校正电路为关闭状态，当芯片切换工作状态时，阻抗配置电路和LC校正电路接收芯片输出的使能信号，且使能信号是用于指示阻抗配置电路和LC校正电路开启的使能信号，则可以控制阻抗配置电路为开启状态以及控制LC校正电路为开启状态。
S530，获取芯片的当前工作模式。
S540，根据当前工作模式确定芯片的当前时钟信号。
S550，基于当前时钟信号调节LC电路的工作参数。
其中，S530至S540的具体实施方式可以参考S210至S230，故不在此赘述。
S560，获取芯片在当前工作模式下的电流值以及芯片的额定电压值。
S570，基于额定电压值和电流值调节可调电阻的电阻值，其中，调节后的电阻值和电流值的积与额定电压相匹配。
其中，S560至S570的具体实施方式可以参考S430至S440，故不在此赘述。
可选地，当调节后的电阻值和电流值的积与额定电压相匹配，调节后的LC电路的工作参数与芯片的工作模式匹配时，可以将阻抗配置电路和LC校正电路的工作状态调节为关闭，以节省功耗。当检测到芯片下一次切换工作状态时又可以再次开启阻抗配置电路和LC校正电路。
作为一种具体示例，本实施例中的电源调节方法可以应用于如图5所示的芯片供电电路，该电路可以包括片上去耦电容Cdie、电源调节电路以及芯片。该片上去耦电容Cdie一端连接芯片内部电源VDD_die，另一端连接芯片地线。该电源调节电路一端连接芯片内部电源VDD_die，另一端连接芯片地线，与片上去耦电容Cdie并联。该芯片一端连接芯片内部电源VDD_die，另一端连接芯片地线。该芯片通过芯片时钟信号fdie、控制总线信号ctrl以及配置总线信号M_cfg，与该电源调节电路相连接。
该电源调节电路包括：可调电容C_M、可调电感L_M、以及LC校正电路、可调电阻R_M、以及阻抗配置电路。
当该芯片供电电路工作时，该芯片把芯片时钟信号fdie输出到该电源调节电路中的LC校正电路。基于谐振频率计算公式fr＝1/(2Π√(L_M*C_M))可知，该LC校正电路对电容C_M或/和电感L_M进行调整，可以实现fr＝fdie，并在fr处提供一个可调电阻R_M作为零点阻抗，阻止在工作频率fdie的振荡，从而把芯片内部电源VDD_die稳定下来，从而使该电源调节电路的谐振频率fr能够实时地根据芯片的工作频率fdie做调整，实现自适应功能，不受工艺偏差以及温度变化的影响。
其中，该芯片可以根据芯片的工作模式和电流，把相应的配置总线信号M_cfg输出到该电源调节电路中的阻抗配置电路，该阻抗配置电路通过调整电阻R_M，提供与实际工作电流相匹配的零点阻抗，避免造成电源纹波过大而超过电源容差要求。
进一步的，该芯片可以把控制总线信号ctrl输出到该电源调节电路，对该电源调节电路进行相应控制。具体地，控制总线信号ctrl相当于使能信号，可以用于控制电源调节电路中的阻抗配置电路和LC校正电路何时开启，何时关闭。
可见，基于这种方法设计的芯片，根据芯片的工作频率fdie，调整其谐振频率fr，使得fr＝fdie，并在fr处提供一个零点阻抗，阻止在工作频率的振荡，从而把芯片内部电源VDD_die稳定下来。
进一步的，还可以根据芯片的工作模式和电流，对零点阻抗进行相应配置，提供与实际工作电流相匹配的零点阻抗，避免造成电源纹波过大而超过电源容差要求。
可见，本实施例提供的电源调节方法，可以赋予芯片很强的通用性，可以应用于各种不同工作模式、不同工作频率和不同工作电流的场合。实现谐振频点自适应功能，且零点阻抗与实际工作电流相匹配，不随着工艺偏差或温度的变化而变化，显著降低封装设计难度和缩短设计周期。同时封装方案可以使用低成本的绑线工艺，且封装基板无需放置滤波电容，显著降低封装成本。
请参阅图11，图11示出了本申请一个实施例提供的电源调节装置，应用于上述实施例的芯片的电源调节电路，该装置600包括：当前工作模式获取模块610和工作参数调节模块620，其中：
当前工作模式获取模块610，用于获取芯片的当前工作模式。
工作参数调节模块620，用于基于当前工作模式调节LC电路的工作参数。
可选地，工作参数调节模块620，包括：
当前时钟信号确定子模块，用于根据当前工作模式确定芯片的当前时钟信号。
工作参数调节子模块，用于基于当前时钟信号调节LC电路的工作参数。
可选地，LC电路包括相互串联的可调电容和可调电感，工作参数调节子模块，具体用于基于当前时钟信号调节可调电感的电感值和可调电容的电容值，以调节LC电路的谐振频率，其中，调节后的谐振频率与当前时钟信号匹配。
可选地，芯片的电源调节电路，还包括：可调电阻和阻抗配置电路，可调电阻与LC电路串联，阻抗配置电路分别与芯片和可调电阻电连接，该装置600还包括：
电阻调节模块，用于基于当前工作模式调节可调电阻的电阻值。
可选地，电阻调节模块包括：
信息获取子模块，用于获取芯片在当前工作模式下的电流值以及芯片的额定电压值。
电阻调节子模块，用于基于额定电压值和电流值调节可调电阻的电阻值，其中，调节后的电阻值和电流值的积与额定电压相匹配。
可选地，电阻调节子模块，具体用于当调节后的电阻值和电流值的积与额定电压值之间的差值绝对值不超过指定值，确定调节后的电阻值和电流值的积与额定电压相匹配，并停止对可调电阻的调节。
可选地，该装置600还包括：
使能信号接收模块，用于接收芯片输出的使能信号。
工作状态控制模块，用于根据使能信号控制阻抗配置电路和LC校正电路的工作状态。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，所显示或讨论的模块相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
另外，在本申请各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
综上所述，本实施例提供的电源调节电路及方法能够实现避免芯片的单一固定工作频率和单一固定工作电流的应用场合局限性；解决频点不稳定、零点阻抗与实际工作电流差异大，容易造成电源纹波过大而超过电源容差要求的问题；以及解决封装设计难度大、设计周期长等问题。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不驱使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (10)

  1. 一种芯片的电源调节电路，其特征在于，包括：
    LC电路，所述LC电路的一端用于分别与所述芯片的正极和电源的正极电连接，所述LC电路的另一端用于分别与所述芯片的负极和所述电源的负极电连接；以及
    LC校正电路，所述LC校正电路分别与所述芯片和所述LC电路电连接，用于根据所述芯片的当前工作模式调节所述LC电路的工作参数。
  2. 根据权利要求1所述的芯片的电源调节电路，其特征在于，所述LC电路包括可调电容和可调电感，
    所述可调电容与所述可调电感串联后的一端用于分别与所述芯片的正极和所述电源的正极电连接，所述可调电容与所述可调电感串联后的另一端用于分别与所述芯片的负极和所述电源的负极电连接；
    所述LC校正电路分别与所述可调电容和所述可调电感电连接，用于根据所述芯片的当前工作模式调节所述可调电感的电感值和所述可调电容的电容值。
  3. 根据权利要求1或2所述的芯片的电源调节电路，其特征在于，还包括：
    可调电阻，所述可调电阻与所述LC电路串联后的一端用于分别与所述芯片的正极和所述电源的正极电连接，所述可调电阻与所述LC电路串联后的另一端用于分别与所述芯片的负极和所述电源的负极电连接；以及
    阻抗配置电路，所述阻抗配置电路分别与所述芯片和所述可调电阻电连接，用于根据所述芯片的当前工作模式调节所述可调电阻的电阻值。
  4. 一种芯片的电源调节方法，其特征在于，应用于如权利要求1至3任一项所述的芯片的电源调节电路，所述方法包括：
    获取所述芯片的当前工作模式；
    基于所述当前工作模式调节所述LC电路的工作参数。
  5. 根据权利要求4所述的方法，其特征在于，所述基于所述当前工作模式调节所述LC电路的工作参数，包括：
    根据所述当前工作模式确定所述芯片的当前时钟信号；
    基于所述当前时钟信号调节所述LC电路的工作参数。
  6. 根据权利要求5所述的方法，其特征在于，所述LC电路包括相互串联的可调电容和可调电 感，所述基于所述当前时钟信号调节所述LC电路的工作参数，包括：
    基于所述当前时钟信号调节所述可调电感的电感值和所述可调电容的电容值，以调节所述LC电路的谐振频率，其中，调节后的谐振频率与所述当前时钟信号匹配。
  7. 根据权利要求4所述的方法，其特征在于，所述芯片的电源调节电路，还包括：可调电阻和阻抗配置电路，所述可调电阻与所述LC电路串联，所述阻抗配置电路分别与所述芯片和所述可调电阻电连接，所述方法还包括：
    基于所述当前工作模式调节所述可调电阻的电阻值。
  8. 根据权利要求7所述的方法，其特征在于，基于所述当前工作模式调节所述可调电阻的电阻值，包括：
    获取所述芯片在所述当前工作模式下的电流值以及所述芯片的额定电压值；
    基于所述额定电压值和所述电流值调节所述可调电阻的电阻值，其中，调节后的电阻值和所述电流值的积与所述额定电压相匹配。
  9. 根据权利要求8所述的方法，其特征在于，所述基于所述额定电压值和所述电流值调节所述可调电阻的电阻值，包括：
    当调节后的电阻值和所述电流值的积与所述额定电压值之间的差值绝对值不超过指定值，确定调节后的电阻值和所述电流值的积与所述额定电压相匹配，并停止对所述可调电阻的调节。
  10. 根据权利要求7所述的方法，其特征在于，所述方法还包括：
    接收所述芯片输出的使能信号；
    根据所述使能信号控制所述阻抗配置电路和所述LC校正电路的工作状态。
PCT/CN2021/079740 2021-01-06 2021-03-09 芯片的电源调节电路及方法 WO2022147900A1 (zh)

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