WO2022142141A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022142141A1
WO2022142141A1 PCT/CN2021/098923 CN2021098923W WO2022142141A1 WO 2022142141 A1 WO2022142141 A1 WO 2022142141A1 CN 2021098923 W CN2021098923 W CN 2021098923W WO 2022142141 A1 WO2022142141 A1 WO 2022142141A1
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Prior art keywords
pixel
sub
electrode
display substrate
base substrate
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PCT/CN2021/098923
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English (en)
French (fr)
Inventor
张大成
许晨
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to AU2021221904A priority Critical patent/AU2021221904B2/en
Priority to JP2021550245A priority patent/JP2024501390A/ja
Priority to MX2021012016A priority patent/MX2021012016A/es
Priority to US17/605,664 priority patent/US20230363223A1/en
Priority to KR1020217031158A priority patent/KR20230124779A/ko
Priority to EP21743021.4A priority patent/EP4050662B1/en
Publication of WO2022142141A1 publication Critical patent/WO2022142141A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • organic light-emitting diode (OLED) display panels have the characteristics of self-luminescence, high contrast ratio, low energy consumption, wide viewing angle, fast response speed, flexible panels, wide operating temperature range, and simple manufacturing. Prospects.
  • the semiconductor element technology which is the core of the display device, has also been greatly improved.
  • organic light-emitting diode Organic Light-Emitting Diode, OLED for short
  • OLED Organic Light-Emitting Diode
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate and a first conductive structure on the base substrate.
  • the first conductive structure includes a first surface and a second surface facing away from the base substrate, the first surface and the second surface are of the same material; the first surface and the plate of the base substrate The surface has a first included angle, the second surface and the board surface of the base substrate have a second included angle, and the first included angle is different from the second included angle; the first surface is provided with A first surface microstructure, the second surface is provided with a second surface microstructure; the first conductive structure further includes a third surface and a fourth surface close to the base substrate, the third surface and the the first surface is opposite to the second surface, and the fourth surface is opposite to the second surface; the first surface microstructure has a first cross-section perpendicular to the base substrate, and the first cross-section is on the third surface has a first orthographic projection; the length of the first orthographic projection is smaller than the length of the first surface microstructure on the first
  • the distance between the two ends of the first section and the distance between the two ends of the second section are respectively greater than 0.1 micrometer and less than 1 micrometer.
  • the first surface microstructures at least partially overlap the third surface
  • the second surface microstructures at least partially overlap the fourth surface
  • At least one of the third surface and the fourth surface is a flat surface.
  • the area of the orthographic projection of the first surface microstructure on the third surface is smaller than the surface area of the first surface microstructure; the area of the second surface microstructure on the fourth surface The area of the orthographic projection is smaller than the surface area of the second surface microstructure.
  • the minimum thickness of the first conductive structures at the first surface microstructures is less than and greater than 3/5 of the average thickness of the first conductive structures.
  • the first surface microstructure has a first end point, a first intermediate point, and a second end point at the first cross section
  • the second surface microstructure has a first end point at the second surface microstructure
  • Three end points, a second middle point and a fourth end point; the distance between the first middle point and the third surface and the distance between the first end point and the second end point and the third surface are not equal, so The distance between the second intermediate point and the fourth surface and the distance between the third end point and the fourth end point and the fourth surface are not equal.
  • the first included angle is greater than 0 degrees, and the second included angle is equal to 0 degrees.
  • the first surface microstructure has a first endpoint and a second endpoint at the first cross-section
  • the second surface microstructure has a third endpoint and a fourth endpoint at the second cross-section
  • the distance between the first endpoint and the second endpoint is greater than the distance between the third endpoint and the fourth endpoint.
  • the display substrate further includes a first insulating layer on a side of the first conductive structure close to the base substrate, and the first insulating layer includes a third insulating layer that is respectively connected to the first conductive structure.
  • the surface and the fourth surface are in direct contact with a first portion and a second portion, respectively, and the minimum thickness of the first portion is smaller than the minimum thickness of the second portion.
  • the display substrate further includes a second conductive structure on a side of the first insulating layer close to the base substrate, and a first portion of the first insulating layer covers the second conductive structure. At least in part.
  • the first surface microstructure does not overlap the second conductive structure in a direction perpendicular to the base substrate.
  • the first conductive structure is electrically connected to the second conductive structure through a first via passing through the first insulating layer; in a direction perpendicular to the base substrate, the first conductive structure is The surface microstructure overlaps at least a portion of the first via.
  • the first insulating layer includes a stacked first sublayer and a second sublayer, the second sublayer is farther from the base substrate than the first sublayer; the first sublayer a sublayer includes a first side exposed by the first via, the second sublayer includes a second side exposed by the first via, and one of the first side and the second side At least one is in direct contact with the third surface of the first conductive structure.
  • the included angle between the first side surface and the base substrate is greater than the included angle between the second side surface and the base substrate.
  • the second sublayer is denser than the first sublayer.
  • the oxygen content of the first surface is higher than the oxygen content of the third surface.
  • the first surface microstructure has a first end point and a second end point on the first cross section, and a point of the first cross section closest to the third surface and the first end point and The distances of the second endpoints are not equal.
  • first surface microstructures include first concave structures and the second surface microstructures include second concave structures.
  • the display substrate further includes a plurality of sub-pixels on the base substrate, the plurality of sub-pixels are arranged in a plurality of pixel columns and a plurality of pixel rows along a first direction and a second direction, the plurality of sub-pixels The first direction crosses the second direction; each of the plurality of sub-pixels includes a first transistor, a second transistor, a third transistor and a storage capacitor on the base substrate, and the second transistor has a The first electrode is electrically connected with the first capacitor electrode of the storage capacitor and the gate of the first transistor, the second electrode of the second transistor is configured to receive a data signal, and the gate of the second transistor is configured as receiving a first control signal, the second transistor is configured to write the data signal to the gate of the first transistor and the storage capacitor in response to the first control signal, the first transistor of the first transistor The electrode is electrically connected to the second capacitor electrode of the storage capacitor and is configured to be electrically connected to the first electrode of the light-emitting element, the second electrode of the
  • a center distance between an orthographic projection of the first surface microstructure on the base substrate and an orthographic projection of the second surface microstructure on the base substrate is within the first
  • the components of the direction and the second direction are respectively smaller than the average size of each of the plurality of sub-pixels in the first direction and the second direction.
  • the subpixels of each pixel column emit the same color.
  • the first surface microstructure includes a first concave structure
  • the second surface microstructure includes a second concave structure
  • the first concave structure and the second concave structure are electrically conductive along the first
  • the extension directions of the structures are arranged and face the sub-pixels of the same color.
  • the display substrate further includes an extension protruding from the gate of the first transistor, the extension extending from the gate of the first transistor in the second direction and being connected with the first transistor
  • the first electrodes of the two transistors are at least partially overlapped and electrically connected in a direction perpendicular to the base substrate.
  • the active layer of the second transistor includes a first electrode contact region, a second electrode contact region, and a channel region between the first electrode contact region and the second electrode contact region,
  • the first electrode of the second transistor is electrically connected to the first electrode contact region, the extension portion and the first capacitor electrode respectively through a second via hole.
  • the second via extends along the first direction and exposes at least a portion of a surface of the extension and two opposite sides in the first direction.
  • the extension separates the second via into a first recess and a second recess
  • the first electrode of the second transistor fills the first recess and the second recess a groove and covering the two side surfaces of the extension part
  • the first electrode of the second transistor includes a first part, a second part and a third part, the second part covers the surface of the extension part , the first part covers the first groove, the third part covers the second groove; the first part and the third part also cover the two side surfaces of the extension part respectively.
  • the first conductive structure is a first electrode of the second transistor, and both the first surface microstructure and the second surface microstructure are located on the second electrode of the first electrode of the second transistor. three parts.
  • the dimension of the first surface microstructure in the first direction is less than one tenth of the largest dimension of the third portion in the first direction.
  • the size of the first surface microstructure in the first direction is less than ten times the maximum size of the orthographic projection of the second via on the base substrate in the first direction one part.
  • each of the plurality of sub-pixels further includes the light-emitting element
  • the light-emitting element includes a first electrode, a light-emitting layer and a second electrode that are stacked in sequence, and the first electrode is compared to the The second electrode is closer to the base substrate, and the first electrode of the light-emitting element is electrically connected to the first electrode of the first transistor of the sub-pixel to which the light-emitting element belongs through a third via hole.
  • the first electrode of the light emitting element includes a first electrode part, a second electrode part and a third electrode part connected in sequence in the first direction, the first electrode part is used to correspond to the corresponding
  • the first electrode of the first transistor is electrically connected and overlaps with the first electrode of the corresponding first transistor in the direction perpendicular to the base substrate; the third electrode part of the light-emitting element is connected to the first electrode of the light-emitting element
  • the open regions at least partially overlap in a direction perpendicular to the base substrate.
  • the sum of the largest dimension along the first direction and the largest dimension along the second direction of the first electrode portion is smaller than the largest dimension along the first direction and along the third electrode portion.
  • the sum of the largest dimensions of the second direction; the sum of the largest dimensions of the second electrode part along the first direction and the largest dimension of the second direction is smaller than the sum of the largest dimensions of the third electrode part along the first direction.
  • the display substrate includes a plurality of first surface microstructures and a plurality of second surface microstructures, and a portion of the plurality of first surface microstructures and the plurality of second surface microstructures is associated with the first surface microstructures.
  • An electrode part overlaps in a direction perpendicular to the base substrate, and another part of the plurality of first surface microstructures and the plurality of second surface microstructures and the third electrode part are in a direction perpendicular to the base substrate overlapping in the direction; the distribution density of the first surface microstructure and the second surface microstructure overlapping with the first electrode part is greater than the distribution density of the first surface microstructure and the second surface microstructure overlapping with the third electrode part distribution density.
  • the average size of the second electrode portion of the first electrode of the light-emitting element in the second direction is smaller than the average size of the first electrode portion in the second direction, and is also smaller than the third the average size of the electrode portion in the second direction.
  • the plurality of pixel rows include a first pixel row, the first pixel row is divided into a plurality of pixel units, and each pixel unit includes a first sub-pixel, a two sub-pixels and a third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel are respectively configured to emit light of three basic colors;
  • the display substrate further includes A first scan line extending in two directions, the first scan line is electrically connected to the gates of the second transistors in the first sub-pixel, the second sub-pixel and the third sub-pixel to provide the first control signal .
  • the first scan line overlaps with the second electrode portion of the first electrode of the light emitting element of the first subpixel in a direction perpendicular to the base substrate.
  • the display substrate further includes a color filter layer, the color filter layer is located on a side of the first electrode of the light-emitting element close to the base substrate; the color filter layer includes layers corresponding to the A plurality of color filter portions of the first sub-pixel, the second sub-pixel and the third sub-pixel, the lights emitted by the first sub-pixel, the second sub-pixel and the third sub-pixel are respectively The corresponding color filter portion emits the display substrate to form display light.
  • the color filter portion corresponding to the first subpixel, the color filter portion corresponding to the second subpixel, and the second surface microstructure are in a vertical direction. All overlap in the direction of the base substrate.
  • each of the plurality of color filter portions overlaps with the third electrode portion of the first electrode of the light-emitting element of the corresponding sub-pixel, and overlaps with the third electrode portion of the light-emitting element of the corresponding sub-pixel.
  • the first electrode portions of the first electrodes of the light-emitting elements of the corresponding sub-pixels do not overlap.
  • the first scan line is located on a side of the color filter layer close to the base substrate; in a direction perpendicular to the base substrate, the first scan line of the light-emitting element of the first sub-pixel.
  • the portion of the second electrode portion of an electrode overlapping the first scan line also overlaps the color filter portion corresponding to the first sub-pixel.
  • the first scan line includes a first portion and a second portion that are alternately connected, and the second portion is a ring-shaped structure.
  • the first electrode of the light emitting element of the first sub-pixel overlaps with the first portion of the first scan line and overlaps with the first scan line.
  • the second part does not overlap.
  • the display substrate further includes a plurality of first signal lines extending along the first direction, and in a direction perpendicular to the base substrate, the plurality of first signal lines and the first signal lines The second portion of a scan line overlaps to define a plurality of first hollow regions arranged along the second direction.
  • the geometric centers of the plurality of first hollow regions corresponding to each pixel unit are not on a straight line.
  • the color filter portion corresponding to the first sub-pixel overlaps with at least one of the plurality of first hollow regions, and the second sub-pixel corresponds to The color filter portion does not overlap with the plurality of first hollow regions.
  • the color filter portion corresponding to the first sub-pixel overlaps with one of the plurality of first hollow regions and has a first overlapping area
  • the The color filter portion corresponding to the second sub-pixel overlaps with another one of the plurality of first hollow regions and has a second overlapping area; the first overlapping area is different from the second overlapping area.
  • the absolute value of the difference between the first overlapping area and the second overlapping area is greater than (n* ⁇ )2, where ⁇ is the wavelength of light emitted by the first sub-pixel and the second sub-pixel larger value.
  • the display substrate includes a plurality of first surface microstructures and a plurality of second surface microstructures, and a portion of the plurality of first surface microstructures and the plurality of second surface microstructures is associated with the first surface microstructures.
  • a first portion of a scan line overlaps in a direction perpendicular to the base substrate, and another portion of the plurality of first surface microstructures and the plurality of second surface microstructures is perpendicular to the second portion of the first scan line overlapping in the direction of the base substrate; in the direction perpendicular to the base substrate, the distribution density of the first surface microstructure and the second surface microstructure overlapping with the second part of the first scan line is greater than that of the Distribution density of overlapping first surface microstructures and second surface microstructures of the first portion of the first scan line.
  • the first overlapping area is greater than an area of an orthographic projection of each of the plurality of first surface microstructures or the second surface microstructures on the base substrate; the second overlapping The area is greater than an area of an orthographic projection of each of the plurality of first surface microstructures or the second surface microstructures on the base substrate.
  • the pixel unit further includes a fourth sub-pixel, the fourth sub-pixel is configured to emit white light, and the first hollowed-out regions of the plurality of first hollowed-out regions adjacent to the fourth sub-pixel are all the same as the first hollowed-out region.
  • the color filter layers do not overlap in a direction perpendicular to the base substrate.
  • the plurality of first signal lines include a plurality of data lines, and the plurality of data lines are connected to the plurality of pixel columns in a one-to-one correspondence; for the first pixel row, the plurality of data lines are It is divided into a plurality of data line groups corresponding to the plurality of pixel units one-to-one, and each data line group includes a first data line connected to the first subpixel, the second subpixel and the third subpixel respectively, a second data line and a third data line; for each of the pixel units, the first data line, the second data line and the third data line corresponding to the pixel unit are located in the between the first subpixel and the third subpixel.
  • the display substrate further includes a plurality of power supply lines extending along the first direction, the plurality of power supply lines being configured to provide the first power supply voltage for the plurality of sub-pixels, the plurality of power supply lines At least one pixel column is spaced between each of the power lines and any one of the plurality of data lines.
  • the display substrate includes a plurality of first surface microstructures and a plurality of second surface microstructures, and a portion of the plurality of first surface microstructures and the plurality of second surface microstructures are distributed in the a plurality of data lines, another part of the plurality of first surface microstructures and the plurality of second surface microstructures is distributed on the plurality of power lines; the plurality of first surface microstructures and the plurality of The distribution density of the second surface microstructures on the plurality of data lines is greater than the distribution density of the plurality of first surface microstructures and the plurality of second surface microstructures on the plurality of power supply lines.
  • the second subpixel is directly adjacent to the third subpixel
  • the third subpixel has a first side and a second side opposite in the second direction
  • the second subpixel The data line and the third data line are located on the first side of the third subpixel and between the second subpixel and the third subpixel.
  • the second electrode portion of the first electrode of the light-emitting element of the third subpixel is directed away from the second side of the third subpixel relative to the first electrode portion and the third electrode portion thereof. concave.
  • the second data line and the third data line at least partially overlap with the color filter layer, respectively.
  • the pixel unit further includes a fourth subpixel, the fourth subpixel is configured to emit white light, and each data line group further includes a fourth data line connected to the fourth subpixel;
  • the fourth data line does not overlap with the color filter layer.
  • the plurality of pixel rows further include a second pixel row directly adjacent to the first pixel row in the first direction, the second pixel row including The fifth sub-pixel, the sixth sub-pixel and the seventh sub-pixel are arranged in sequence in the second direction, the fifth sub-pixel and the first sub-pixel are located in the same pixel column, and the sixth sub-pixel and the The second sub-pixel is located in the same pixel column, and the seventh sub-pixel and the third sub-pixel are located in the same pixel column.
  • the color filter portion corresponding to the first sub-pixel has a side close to the fifth sub-pixel, and the side is parallel to the second direction.
  • the display substrate further includes a second scan line extending along the second direction, and the second scan line is associated with the fifth sub-pixel, the sixth sub-pixel and the seventh sub-pixel.
  • the gates of the three transistors are electrically connected to provide the second control signal.
  • the second scan line includes a first portion and a second portion that are alternately connected, and the second portion is a ring-shaped structure.
  • the plurality of first signal lines overlap with a second portion of the second scan line to define a plurality of sequentially arranged along the second direction.
  • a second hollow area in a direction perpendicular to the base substrate, the plurality of first signal lines overlap with a second portion of the second scan line to define a plurality of sequentially arranged along the second direction.
  • the first conductive structure is one of the plurality of first signal lines
  • the first surface microstructure and the second surface microstructure are located on the first signal line
  • the The first surface microstructure and the second hollow area corresponding to the first signal line at least partially overlap in a direction perpendicular to the base substrate.
  • the color filter portion corresponding to the first sub-pixel overlaps with one of the plurality of second hollow regions and has a third overlap area
  • the color filter portion corresponding to the second sub-pixel overlaps with another second hollow area among the plurality of second hollow areas and has a fourth overlapping area
  • the color filter portion corresponding to the third sub-pixel overlaps with the second hollow area.
  • Still another one of the plurality of second hollow areas overlaps and has a fifth overlapping area; the third overlapping area, the fourth overlapping area and the fifth overlapping area are all different.
  • the second electrode of the third transistor is electrically connected to the detection part extending along the second direction through a fourth via hole, and the detection part is electrically connected to the detection line extending along the first direction , so that the second electrode of the third transistor is connected to the detection circuit through the detection part and the detection line.
  • the first conductive structure is a second electrode of the third transistor
  • the first surface microstructure and the second surface microstructure are located on the second electrode of the third transistor
  • the first surface microstructure and the fourth via hole at least partially overlap in a direction perpendicular to the base substrate.
  • the active layer of the third transistor includes a first electrode contact region, a second electrode contact region, and a channel region between the first electrode contact region and the second electrode contact region, The first electrode of the third transistor is electrically connected to the first electrode contact area of the third transistor through a fifth via hole.
  • the first conductive structure is a first electrode of the third transistor
  • the first surface microstructure and the second surface microstructure are located on the first electrode of the third transistor
  • the first surface microstructure at least partially overlaps the fifth via in a direction perpendicular to the base substrate.
  • At least one embodiment of the present disclosure further provides a display substrate including a base substrate and a first conductive structure on the base substrate, the first conductive structure including a first surface facing away from the base substrate and a second conductive structure Two surfaces, the first surface and the second surface have the same material; the first surface is provided with a first surface microstructure, and the second surface is provided with a second surface microstructure; the first surface The surface microstructure has a first cross-section perpendicular to the base substrate, the second surface microstructure has a second cross-section perpendicular to the base substrate; the first surface microstructure is on the first cross-section Having a first end point and a second end point, the second surface microstructure has a third end point and a fourth end point on the second section; the middle of the connecting line between the first end point and the second end point The distance between the point and the midpoint of the line connecting the third end point and the fourth end point with respect to the board surface of the base substrate is different.
  • the minimum thickness of the first conductive structures at the first surface microstructures is less than and greater than 3/5 of the average thickness of the first conductive structures.
  • the first conductive structure further includes a third surface and a fourth surface close to the base substrate, and the first surface microstructure is in a direction perpendicular to the base substrate and the The third surface at least partially overlaps and the second surface microstructures at least partially overlap the fourth surface.
  • At least one of the third surface and the fourth surface is a flat surface.
  • the area of the orthographic projection of the first surface microstructure on the third surface is smaller than the surface area of the first surface microstructure; the area of the second surface microstructure on the fourth surface The area of the orthographic projection is smaller than the surface area of the second surface microstructure.
  • the first surface microstructure further has, on the first cross section, a first intermediate point between the first end point and the second end point, the second surface microstructure at The second section also has a second intermediate point between the third end point and the fourth end point; the distance between the first intermediate point and the third surface and the first end point and The distances between the second end point and the third surface are not equal, the distances between the second intermediate point and the fourth surface and the distances between the third end point and the fourth end point and the fourth surface are all equal to each other. not equal.
  • the first surface and the board surface of the base substrate have a first included angle
  • the second surface and the board surface of the base substrate have a second included angle
  • the first sandwiched The angle is different from the second included angle
  • the first included angle is greater than 0 degrees, and the second included angle is equal to zero.
  • the display substrate further includes a first insulating layer on a side of the first conductive structure close to the base substrate, and the first insulating layer includes a third insulating layer that is respectively connected to the first conductive structure.
  • the surface and the fourth surface are in direct contact with a first portion and a second portion, respectively, and the minimum thickness of the first portion is smaller than the minimum thickness of the second portion.
  • the display substrate further includes a second conductive structure on a side of the first insulating layer close to the base substrate, and a first portion of the first insulating layer covers the second conductive structure. At least in part.
  • the first surface microstructure does not overlap the second conductive structure in a direction perpendicular to the base substrate.
  • the first conductive structure is electrically connected to the second conductive structure through a first via passing through the first insulating layer; in a direction perpendicular to the base substrate, the first conductive structure is The surface microstructure overlaps at least a portion of the first via.
  • the first insulating layer includes a stacked first sublayer and a second sublayer, the second sublayer is farther from the base substrate than the first sublayer; the first sublayer a sublayer includes a first side exposed by the first via, the second sublayer includes a second side exposed by the first via, and one of the first side and the second side At least one is in direct contact with the third surface of the first conductive structure.
  • the included angle between the first side surface and the base substrate is greater than the included angle between the second side surface and the base substrate.
  • the second sublayer is denser than the first sublayer.
  • the oxygen content of the first surface is higher than the oxygen content of the third surface.
  • At least one embodiment of the present disclosure further provides a display device including the display substrate provided in any of the above embodiments.
  • FIG. 1A is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 1B is a second schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 2A is a third schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 2B is one of circuit diagrams of pixels in a display substrate provided by at least one embodiment of the present disclosure
  • 2C is a second circuit diagram of a pixel in a display substrate provided by at least one embodiment of the present disclosure
  • 2D-FIG. 2F are signal timing diagrams of a driving method of a pixel circuit according to an embodiment of the present disclosure
  • 3A is a fourth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • Figure 3B is a cross-sectional view of Figure 3A along section line I-I';
  • 3C-3E are schematic diagrams of display substrates provided by other embodiments of the present disclosure.
  • FIG. 4A is a schematic plan view of a first conductive layer in a display substrate according to at least one embodiment of the present disclosure
  • 4B is a schematic plan view of a semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure
  • 4C is a schematic plan view of a second conductive layer in a display substrate provided by at least one embodiment of the present disclosure
  • 4D is a schematic plan view of a third conductive layer in a display substrate according to at least one embodiment of the present disclosure
  • 5A is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure.
  • 5B is a second schematic diagram of a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • display panels are prone to failure due to external stress.
  • the signal lines in the display panel are easily affected by external stress. A fracture occurred, causing the panel to fail.
  • At least one embodiment of the present disclosure provides a display substrate including a base substrate and a first conductive structure on the base substrate, the first conductive structure including a first surface facing away from the base substrate and a second conductive structure
  • the material of the first surface and the second surface is the same; the first surface and the board surface of the base substrate have a first included angle, and the second surface and the board of the base board
  • the surface has a second included angle, and the first included angle is different from the second included angle;
  • the first surface is provided with a first surface microstructure, and the second surface is provided with a second surface microstructure;
  • the first conductive structure further includes a third surface and a fourth surface close to the base substrate, the third surface is opposite to the first surface, and the fourth surface is opposite to the second surface;
  • the The first surface microstructure has a first cross section on a first projection plane, the first projection plane is perpendicular to the board surface of the base substrate; the first cross section has a first orthographic projection on the third surface , the length
  • the first surface microstructure and the second surface microstructure are respectively provided on the first surface and the second surface of the first conductive structure, so that the first conductive structure can be arranged at different angles or different The stress is released in the direction to avoid stress concentration and lead to panel failure.
  • the first surface microstructure and the second surface microstructure in the embodiments of the present disclosure may be implemented as various specific structures, which are not limited in the present disclosure.
  • the first stress structure and the second surface microstructure are grooves, protrusions or through holes, and these structures can effectively increase the surface area of the conductive structure, thereby helping to relieve stress.
  • FIG. 1A shows a schematic diagram of a display substrate 10 provided by at least one embodiment of the present disclosure.
  • the display substrate 10 includes a first conductive structure 110 on a base substrate 101 , and the first conductive structure 110 includes The first surface 111 and the second surface 112 facing away from the base substrate 101 , the first surface 111 and the board surface of the base board 101 have a first included angle ⁇ , and the second surface 112 and the board surface of the base board 101 have a first angle ⁇ .
  • the second included angle, the first included angle is different from the second included angle.
  • the first included angle ⁇ is greater than 0, that is, the first surface 111 is an inclined plane; for example, the second included angle is 0, that is, the second surface 112 is parallel to the board surface of the base substrate.
  • the first surface 111 is provided with first surface microstructures 11
  • the second surface 112 is provided with second surface microstructures 12 .
  • the maximum size of the orthographic projection of the first surface microstructures 11 on the first surface 111 is greater than the maximum size of the orthographic projection of the second surface microstructures 12 on the second surface 112 .
  • the largest dimension of the first surface microstructures 11 in the direction perpendicular to the first surface 111 is larger than the largest dimension of the second surface microstructures 12 in the direction perpendicular to the second surface 112 . Since the first surface 111 is more inclined with respect to the base substrate than the second surface 112, and the stress is more concentrated, setting the size of the first surface microstructure 11 to a larger size helps to release the stress more uniformly.
  • the maximum size of the orthographic projection of the first surface microstructure 11 on the first surface 111 is 0.15-0.35 ⁇ m, for example, 0.22-0.28 ⁇ m; in the direction perpendicular to the first surface 111 , the first The largest dimension of the surface microstructures 11 is in the range of 0.03-0.1 micrometer, eg, 0.05-0.08 micrometer.
  • the line width of the first conductive structure is in the range of 5-30 microns.
  • the largest dimension of the first surface microstructure 11 in the direction perpendicular to the first surface 111 is 5%-20% of the average thickness of the first conductive structure.
  • the largest dimension of the orthographic projection of the second surface microstructure 12 on the second surface 112 is 0.1-0.2 micrometers, for example, 0.12-0.15 micrometers; in the direction perpendicular to the second surface 112, the second surface
  • the largest dimension of the microstructures 12 is in the range of 0.02-0.08 microns, eg, 0.03-0.07 microns.
  • the line width of the first conductive structure ranges from 5 to 30 microns.
  • the largest dimension of the second surface microstructure 12 in a direction perpendicular to the second surface 112 is 5%-20% of the average thickness of the first conductive structure.
  • the first conductive structure 110 further includes a third surface 113 and a fourth surface 114 close to the base substrate 101 , the third surface 113 is opposite to the first surface 111 , and the fourth surface 114 is opposite to the second surface 112 relatively.
  • the first surface microstructure 11 has a first cross section 11a perpendicular to the base substrate, and the second surface microstructure has a second cross section 12a perpendicular to the base substrate.
  • first cross section 11a has a first orthographic projection (C1C2) on the third surface 113, and the length of the first orthographic projection is smaller than the length of the first surface microstructure 11 on the first cross section 11a, that is, the length of the curve A1A2 .
  • the second surface microstructure 12 has a second cross section 12a on the first projection surface, the second cross section 12a has a second orthographic projection ( D1D2 ) on the fourth surface 114 , and the length of the second orthographic projection is smaller than that of the second surface
  • the length of the microstructure 12 on the second section 12a is the length of the curve B1B2.
  • the curve A1A2 or B1B2 can effectively increase the surface area of the first surface microstructure 11 or the second surface microstructure 12 , thereby improving the stress release capability of the first surface microstructure 11 and the second surface microstructure 12 .
  • the curve A1A2 and/or the curve B1B2 includes arcs, thereby making the stress relief more uniform.
  • Both the first section 11a and the second section 12a are projected as linear structures (one-dimensional structures), which are related to the shapes of the third and fourth surfaces.
  • the first orthographic projection and the second orthographic projection are respectively straight lines, as shown in FIG. 1A ; when the third surface and the fourth surface are curved surfaces, the first orthographic projection The orthographic projection and the second orthographic projection are curves, respectively.
  • the orthographic projection of a structure on the projection surface is the projection of the structure on the projection surface along the direction of the normal of each point on the projection surface.
  • the third surface 113 and the fourth surface 114 is a flat surface.
  • the third surface 113 and the fourth surface 114 are both flat surfaces.
  • the first surface microstructure 11 at least partially overlaps the third surface 113
  • the second surface microstructure 12 at least partially overlaps the fourth surface 114 .
  • the flatness of the third surface 113 and the fourth surface 114 is relative to the dimensions of the first surface microstructure 11 or the second surface microstructure 12 , the third surface 113 and the fourth surface
  • the judging scale of the flatness of 114 should be in the same order of magnitude as the scale of the first surface microstructure 11 or the second surface microstructure 12 .
  • the judgment scale in the direction parallel to the third surface 113 or the fourth surface 114 is in the order of 0.1 ⁇ m
  • the judgment scale in the direction perpendicular to the third surface 113 or the fourth surface 114 is in the order of 0.01 ⁇ m class.
  • the third surface 113/fourth surface 114 when there are concave or convex structures in the third surface 113/fourth surface 114 with a size of the order of 0.1 ⁇ m in the parallel direction and a size of 0.01 ⁇ m in the vertical direction, it is determined that the third surface 113/the fourth surface Four surfaces 114 are non-planar surfaces.
  • the area of the orthographic projection of the first surface microstructure 11 on the third surface 113 is smaller than the surface area of the first surface microstructure; the area of the orthographic projection of the second surface microstructure 12 on the fourth surface 114 is less than The surface area of the second surface microstructure.
  • This arrangement increases the surface area of the first conductive structure, thereby facilitating stress relief.
  • the first surface microstructure has a first end point, a first intermediate point and a second end point
  • the second surface microstructure has a third end point, a second intermediate point and a fourth intermediate point
  • the distance between the first intermediate point and the third surface and the distance between the first and second endpoints and the third surface are not equal, and the second intermediate point and the fourth surface are not equal and the distances between the third end point and the fourth end point and the fourth surface are not equal.
  • the first surface microstructure 11 and the second surface microstructure 12 respectively include a first concave structure and a second concave structure, and the first concave structure is relative to the reference plane where the first surface 111 is located.
  • the second concave structure is concave with respect to the reference plane where the second surface 112 is located.
  • the concave structure increases the surface area of the first conductive structure 110 , thereby facilitating stress relief and reducing the risk of stress fracture of the first conductive structure 110 .
  • the first concave structure and the second concave structure are oriented in different directions, for example, the orientation of the first concave structure can be defined as a direction perpendicular to the first surface 111 , and the orientation of the second concave structure It can be defined as the direction perpendicular to the second surface 112 .
  • This helps to disperse the stress on the first conductive structure 110, further reducing the risk of failure.
  • the maximum depth of the concave structure is one-tenth to two-fifths of the thickness of the first conductive structure where the concave structure is located.
  • the minimum thickness of the first conductive structure at the first surface microstructure is less than the average thickness of the first conductive structure and greater than 3/5 of the average thickness of the first conductive structure.
  • the first surface microstructure 11 has a first end point A1 and a second end point A2 on the first section 11a
  • the second surface microstructure 12 has a third end point A2 on the second section 12a
  • the midpoint (not shown) of the line segment between the first endpoint A1 and the second endpoint A2 and the midpoint (not shown) of the line segment between the third endpoint B1 and the fourth endpoint B2 are relative to the base substrate 101
  • the distance between the boards is different. This arrangement enables the first surface microstructures 11 and the second surface microstructures 12 to have different heights relative to the base substrate, which helps to further disperse the stress on the first conductive structure 110 and reduce the risk of defects.
  • the distance L1 between the first end point A1 and the second end point A2 is greater than the distance L2 between the third end point B1 and the fourth end point B2.
  • the largest dimension of the first concave structure in the direction perpendicular to the first surface 111 is greater than the largest dimension of the second concave structure in the direction perpendicular to the second surface 112 .
  • the distance L1 between the first end point A1 and the second end point A2 and the distance L2 between the third end point B1 and the fourth end point B2 are respectively greater than 0.1 micrometer and less than 1 micrometer.
  • the distance L1 between the first end point A1 and the second end point A2 is greater than the distance L2 between the third end point B1 and the fourth end point B2; that is, the length of the first surface microstructure on the inclined surface is longer long.
  • the distance L1 between the first end point A1 and the second end point A2 is 0.15-0.35 ⁇ m, for example, 0.22-0.28 ⁇ m;
  • the largest dimension is 0.03-0.1 microns, for example 0.05-0.08 microns. Within this size range, it is not only ensured that the conductive structure will not be broken, but also the stress can be fully relieved.
  • the distance L2 between the third end point B1 and the fourth end point B2 is 0.1-0.2 ⁇ m, for example, 0.12-0.15 ⁇ m;
  • the size range is 0.02-0.08 microns, for example 0.03-0.07 microns.
  • first surface 111 is more inclined with respect to the base substrate than the second surface 112, and the stress is more concentrated, setting the size of the first concave structure to be larger helps to release the stress more uniformly.
  • first concave structure and the second concave structure it is not only ensured that the conductive structure will not be broken, but also the stress can be fully relieved.
  • the first surface microstructure 11 has a first end point A1 and a second end point A2 on the first cross section 11a, and the second surface microstructure 12 is at the second end point A2.
  • the section 12a has a third endpoint B1 and a fourth endpoint B2; the midpoint of the line connecting the first endpoint A1 and the second endpoint A2 is relative to the midpoint of the line connecting the third endpoint B1 and the fourth endpoint B2.
  • the distances between the surfaces of the base substrate 101 are different.
  • first surface microstructures 11 and the second surface microstructures 12 to have different heights relative to the base substrate, which helps to further disperse the stress on the first conductive structure 110 and reduce the risk of defects.
  • the roughness of the first surface 111 is higher than that of the third surface 113
  • the roughness of the second surface 112 is higher than that of the fourth surface 114 .
  • This arrangement can improve the direct adhesion between the first conductive structure 110 and the insulating layer located thereon, and avoid the peeling of the insulating layer.
  • the surface roughness of the first conductive structure 110 on the side away from the base substrate may be slightly oxidized during the fabrication process to improve the surface roughness, thereby improving the roughness of the first surface and the second surface.
  • the oxygen content of the first surface 111 is higher than that of the third surface 113
  • the oxygen content of the second surface 112 is higher than that of the fourth surface 114 .
  • the display substrate 10 further includes a first insulating layer 103 located on the side of the first conductive structure 110 close to the base substrate 101 , the first insulating layer 103 includes a The third surface 113 and the fourth surface 114 of 110 directly contact the first part 103a and the second part 103b, respectively, and the minimum thickness d1 of the first part 103a is smaller than the minimum thickness d2 of the second part 103b.
  • the thickness here refers to the dimension of the first insulating layer 103 in the direction perpendicular to the surface of the film layer.
  • this arrangement thins the first portion 103 of the first insulating layer 103 , which helps to reduce the difficulty of climbing the first portion 103 a of the first insulating layer 103 , thereby reducing the first conductive structure 110 fracture risk.
  • the closest point of the first surface microstructure to the third surface is not the first end point or the second end point, and the distances from the first end point and the second end point are not equal.
  • the first concave structure includes a smooth curved surface, that is, the angle between the tangent of the curved surface and the base substrate 101 changes continuously; in the direction away from the base substrate 101 , the tangent of the curved surface and the The rate of change of the included angle of the base substrate 101 gradually increases, that is, the first concave structure is asymmetric, and the slope angle in the upstream (the side away from the base substrate) is smaller than that in the downstream (the side close to the base substrate). slope angle.
  • this arrangement enables the first conductive structure to better reflect the light emitted by the light-emitting element located on the side of the first conductive structure away from the base substrate, thereby improving the efficiency of the light. Utilize utilization. This will be described in detail later in conjunction with the specific structure of the display substrate.
  • the second concave structure includes a smooth curved surface, such as a symmetrical structure, that is, the angle between the tangent of the curved surface and the base substrate 101 changes continuously and the change rate remains constant. This arrangement facilitates uniform stress relief across the plane.
  • the display substrate 10 further includes a second conductive structure 120 located on the side of the first insulating layer 103 close to the base substrate, for example, the first insulating layer 103 connects the first conductive structure 110 with the second conductive structure 120 intervals.
  • the first insulating layer 103 is formed on the second conductive structure 102
  • the first surface 111 of the first insulating layer 103 is formed as a slope due to the existence of the second conductive structure 102 .
  • the first surface microstructure 11 and the second conductive structure 120 do not overlap. Since the stress at the first surface microstructure 11 is relatively concentrated, especially concentrated in the deepest part of the first surface microstructure 11, the first surface microstructure 11 is set so as not to overlap the second conductive structure 120, which reduces the amount of stress caused by the first surface microstructure 11. Risk of short circuit between the first conductive structure 110 and the second conductive structure 120 caused by a fracture at a surface microstructure 11 .
  • the display substrate 10 further includes a buffer layer 102 on the side of the second conductive structure 120 close to the base substrate, for example, the buffer layer 102 is in direct contact with the base substrate 101 .
  • the buffer layer 102 helps to improve the flatness of the base substrate 101 and improve the adhesion of the second conductive structure 120 to the base substrate 101 .
  • the buffer layer 102 can also effectively isolate oxygen or moisture from the outside so as to protect the circuit structure on the substrate.
  • FIG. 1B is a schematic diagram of a display substrate according to another embodiment of the present disclosure, and only the first surface microstructure 11 is shown in the figure.
  • the first conductive structure 110 is electrically connected to the second conductive structure 120 through a via hole 130 in the insulating layer 103 , and the via hole 130 and the first surface microstructure 11 are in a direction perpendicular to the base substrate 101 at least partially overlap.
  • the first insulating layer 103 includes a first sub-layer 131 and a second sub-layer 132 arranged in layers, and the second sub-layer 132 is farther from the base substrate 101 than the first sub-layer 131 .
  • the via hole 130 penetrates the first sub-layer 131 and the second sub-layer 132 .
  • the first sub-layer 131 includes a first side surface 131 a exposed by the via hole 130
  • the second sub-layer 132 includes a second side surface 132 a exposed by the via hole 130
  • the first side surface 131 a and the second side surface 132 a At least one of them is in direct contact with the third surface 133 of the first conductive structure 130 .
  • the first side surface 131 a is in direct contact with the third surface 133 of the first conductive structure 130 .
  • the included angle (slope angle) between the first side surface 131a and the base substrate 101 is ⁇ 1
  • the included angle between the second side surface 132a and the base substrate 101 is ⁇ 2
  • ⁇ 1 is smaller than ⁇ 2.
  • the slope of the first insulating layer 103 at the via hole 130 can be slowed down, so as to prevent the risk of wire breakage caused by the via hole being too steep, and on the other hand, it can prevent the via hole from being too flat and causing the via hole Takes up too much space.
  • the first sub-layer 131 may be formed by a high-temperature deposition process
  • the second sub-layer 132 may be formed by a low-temperature deposition process, so that the density of the second sub-layer 132 is higher than that of the first sub-layer 131
  • the first insulating layer is etched by a dry etching process, so that the slope angle of the first sub-layer 131 is smaller than that of the second sub-layer 132 .
  • FIG. 2A is a block diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 10 includes a plurality of sub-pixels 100 arranged in an array, for example, each sub-pixel 100 includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light.
  • the display substrate is an organic light emitting diode (OLED) display substrate, and the light emitting element is an OLED.
  • the display substrate may further include a plurality of scan lines and a plurality of data lines for providing scan signals (control signals) and data signals for the plurality of sub-pixels, so as to drive the plurality of sub-pixels.
  • the display substrate may further include power lines, detection lines, and the like.
  • the pixel circuit includes a driving sub-circuit for driving the light-emitting element to emit light and a detection sub-circuit for detecting the electrical characteristics of the sub-pixel to realize external compensation.
  • the embodiments of the present disclosure do not limit the specific structure of the pixel circuit.
  • FIG. 2B shows a schematic diagram of a 3T1C pixel circuit for the display substrate.
  • the pixel circuit may further include a compensation circuit, a reset circuit, and the like, which are not limited in the embodiments of the present disclosure.
  • the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor Cst.
  • the first electrode of the second transistor T2 is electrically connected to the first capacitor electrode of the storage capacitor Cst and the gate of the first transistor T1, the second electrode of the second transistor T2 is configured to receive the data signal GT, and the second transistor T2 is configured to respond to the
  • the data signal DT is written into the gate of the first transistor T1 and the storage capacitor Cst according to the first control signal G1; the first electrode of the first transistor T1 is electrically connected to the second capacitor electrode of the storage capacitor Cst, and is configured to be connected to the light-emitting
  • the first electrode of the element is electrically connected, the second electrode of the first transistor T1 is configured to receive a first power supply voltage V1 (eg, a high power supply voltage VDD), and the first transistor T1 is configured to be at the voltage of the gate of the first transistor T1.
  • V1 eg, a high power supply voltage
  • the current used to drive the light-emitting element is controlled under control; the first electrode of the third transistor T3 is electrically connected to the first electrode of the first transistor T1 and the second capacitor electrode of the storage capacitor Cst, and the second electrode of the third transistor T3 is configured as Connected to the detection line 230 to be connected to the external detection circuit 21, the third transistor T3 is configured to detect the electrical characteristic of the sub-pixel to which it belongs in response to the second control signal G2 to achieve external compensation; the electrical characteristic includes, for example, the threshold of the first transistor T1 voltage and/or carrier mobility, or threshold voltage, drive current, etc. of the light-emitting element.
  • the external detection circuit 21 is, for example, a conventional circuit including a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and the like, which will not be repeated in the embodiments of the present disclosure.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the thin film transistors are used as examples for description in the embodiments of the present disclosure.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • one pole is directly described as the first pole, and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (eg, 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (eg, 5V, 10V, or other suitable voltages) );
  • the turn-on voltage is a high-level voltage (eg, 5V, 10V, or other suitable voltages)
  • the turn-off voltage is a low-level voltage (eg, 0V, -5V, -10V or other suitable voltages) voltage).
  • the transistor in FIG. 2B is an N-type transistor as an example for illustration, but this is not a limitation of the present disclosure.
  • FIG. 2B shows the working principle of the pixel circuit shown in FIG. 2B , wherein FIG. 2D shows the signal timing diagram of the pixel circuit during the display process, and FIG. 2E and FIG. 2F show The signal timing diagram of the pixel circuit in the detection process is shown.
  • the display process of each frame of image includes data writing and resetting phase 1 and light-emitting phase 2 .
  • Figure 2C shows the timing waveforms of the various signals in each stage.
  • a working process of the 3T1C pixel circuit includes: in data writing and resetting stage 1, the first control signal G1 and the second control signal G2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2, the first switch K1 is turned off, and the analog-to-digital converter writes to the first electrode of the light-emitting element (eg, the anode of the OLED) through the detection line 230 and the third transistor T3
  • the reset signal, the first transistor T1 is turned on and generates a driving current to charge the first electrode of the light-emitting element to the working voltage; in the light-emitting stage 2, the first control signal G1 and the second control signal G2 are both off
  • FIG. 2E shows a signal timing diagram of the pixel circuit when the threshold voltage is detected.
  • a working process of the 3T1C pixel circuit includes: the first control signal G1 and the second control signal G2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to the second transistor T2 through the second transistor T2.
  • FIG. 2F shows a signal timing diagram of the pixel circuit when the carrier mobility is detected.
  • a working process of the 3T1C pixel circuit includes: in the first stage, the first control signal G1 and the second control signal G2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is passed through the second The transistor T2 is transmitted to the gate of the first transistor T1; the first switch K1 is turned off, and the analog-to-digital converter writes a reset signal to the first electrode (node S) of the light-emitting element through the detection line 230 and the third transistor T3; at the second In the stage, the first control signal G1 is an off signal, the second control signal G1 is an on signal, the second transistor T2 is turned off, the third transistor T3 is turned on, and the first switch K1 and the second switch K2 are turned off to detect The line 230 is floating; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains
  • the electrical characteristics of the first transistor T1 can be obtained and a corresponding compensation algorithm can be implemented.
  • the display substrate 10 may further include a data driving circuit 23 and a scan driving circuit 24 .
  • the data driving circuit 23 is configured to send out a data signal, such as the above-mentioned data signal DT, as required (eg, an image signal input to the display device); the pixel circuit of each sub-pixel is also configured to receive the data signal and apply the data signal to the first data signal. gate of a transistor.
  • the scan driving circuit 24 is configured to output various scan signals, for example, including the first control signal G1 and the second control signal G2, which are, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly fabricated on the display substrate. ).
  • the display substrate 10 further includes a control circuit 22 .
  • the control circuit 22 is configured to control the data driving circuit 23 to apply the data signal, and to control the gate driving circuit to apply the scan signal.
  • An example of the control circuit 22 is a timing control circuit (T-con).
  • the control circuit 22 may be in various forms, for example, including a processor 121 and a memory 127, where the memory 121 includes executable code, and the processor 121 executes the executable code to perform the above-described detection method.
  • the processor 121 may be a central processing unit (CPU) or other form of processing device having data processing capabilities and/or instruction execution capabilities, such as may include a microprocessor, a programmable logic controller (PLC), or the like.
  • CPU central processing unit
  • PLC programmable logic controller
  • memory 127 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • Volatile memory may include, for example, random access memory (RAM) and/or cache memory, among others.
  • Non-volatile memory may include, for example, read only memory (ROM), hard disk, flash memory, and the like.
  • One or more computer program instructions may be stored on a computer-readable storage medium, and the processor 121 may execute the functions desired by the program instructions.
  • Various application programs and various data can also be stored in the computer-readable storage medium, for example, the electrical characteristic parameters obtained in the above detection method, and the like.
  • the display substrate 10 includes a base substrate 101 on which a plurality of sub-pixels 100 are located.
  • the plurality of sub-pixels 100 are distributed along the first direction D1 and the second direction D2 as a pixel array, the pixel array includes a plurality of pixel columns and a plurality of pixel rows, the column direction of the pixel array is the first direction D1, and the row direction is the second direction.
  • the direction D2, the first direction D1 and the second direction D2 intersect, for example, orthogonal.
  • each pixel row is divided into a plurality of pixel units, each of which is configured to emit full-color light.
  • One pixel cell is exemplarily shown in FIG. 3A, and implementations of the present disclosure are not limited to this layout;
  • FIG. 3B shows a cross-sectional view of FIG. 3A along section line I-I'. As shown in FIG.
  • the pixel unit includes a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3 arranged in sequence along the second direction D2, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P1
  • the three sub-pixels P3 are respectively used to emit light of three primary colors (RGB); for example, the first sub-pixel P1 is a red sub-pixel, the second sub-pixel P2 is a blue sub-pixel, and the third sub-pixel P3 is a green sub-pixel .
  • the pixel unit may further include a fourth sub-pixel P4, and the fourth sub-pixel P4 is used for emitting white light.
  • the fourth sub-pixel P4 is located between the first sub-pixel P1 and the second sub-pixel P2, however, the embodiment of the present disclosure does not limit the position of the fourth sub-pixel P4.
  • the display substrate 10 includes a first conductive layer 501, a first insulating layer 201, a semiconductor layer 104, a second insulating layer 202, a second conductive layer 502, The third insulating layer 203 and the third conductive layer 503 .
  • T1g, T1s, T1d, T1a are used to represent the gate, first electrode, second electrode and active layer of the first transistor T1 respectively
  • T2g, T2s, T2d, T2a are used to represent the first transistor T1, respectively.
  • the gate, the first electrode, the second electrode and the active layer of the two transistors T2 are represented by T3g, T3s, T3d and T3a, respectively
  • the gate, the first electrode, the second electrode and the active layer of the third transistor T3 are represented by Ca, Cb, and Cc represent the first capacitor electrode, the second capacitor electrode, and the third capacitor electrode of the storage capacitor Cst, respectively.
  • the “same layer arrangement” referred to in the present disclosure refers to two (or more than two) structures formed by the same deposition process and patterned by the same patterning process. Can be the same or different.
  • the “integrated structure” in the present disclosure refers to a structure in which two (or more than two) structures are formed by the same deposition process and patterned by the same patterning process and are connected to each other, and their materials may be the same or different. .
  • the first conductive layer 501 includes a shielding layer 170 , and the orthographic projection of the shielding layer 170 on the base substrate 101 covers the active layer T1a of the first transistor T1 on the base substrate 101 orthographic projection.
  • the first transistor T1 is used as a driving transistor of the pixel circuit, and the stability of its electrical characteristics is very important for the light-emitting characteristics of the light-emitting element.
  • the shielding layer 170 is an opaque layer, which can prevent light from entering the active layer of the first transistor T1 from the back of the base substrate 101 to cause a shift in the threshold voltage of the first transistor T1, so as to avoid affecting the corresponding luminous properties of the light-emitting element.
  • the shielding layer 170 is made of an opaque conductive material, such as a metal or metal alloy material. This arrangement can alleviate the back channel phenomenon caused by the trapped charges of the base substrate 101 .
  • the semiconductor layer 104 includes the active layer T1a of the first transistor T1, the active layer T2a of the second transistor T2, and the active layer T3a of the third transistor T3.
  • the semiconductor layer 104 further includes a first capacitor electrode Ca of the storage capacitor Cst, and the first capacitor electrode Ca is obtained from the semiconductor layer 104 through conducting treatment; that is, the first capacitor electrode Ca and the first transistor T1 have a The active layer T1a, the active layer T2a of the second transistor, and the active layer T3a of the third transistor are arranged in the same layer.
  • the second conductive layer 502 includes the gate T1g of the first transistor T1, the gate T2g of the second transistor T2 and the gate T3g of the third transistor T3.
  • the display substrate 10 adopts a self-alignment process, and uses the second conductive layer 502 as a mask to conduct conductorization treatment (eg, doping treatment) on the semiconductor layer 104, so that the semiconductor layer 104 is not covered by the second conductive layer 502.
  • the covered part is conductorized, so as to obtain the first capacitor electrode Ca, and the parts of the active layer of each transistor located on both sides of the channel region are conductorized to form a first electrode contact region and a second electrode contact region, respectively,
  • the first electrode contact area and the second electrode contact area are used for electrical connection with the first electrode and the second electrode of the transistor, respectively.
  • the third conductive layer 503 includes a first electrode T1s and a second electrode T1d of the first transistor T1, a first electrode T2s and a second electrode T2d of the second transistor T2, and a first electrode T3s and a second electrode of the third transistor T3. Diode T3d.
  • the third conductive layer 503 further includes a second capacitor electrode Cb of the storage capacitor Cst.
  • the second capacitor electrode Cb and the second electrode T1d of the first transistor T1 are provided in the same layer and are connected to each other as a whole.
  • the first capacitor electrode Ca and the second capacitor electrode Cb overlap each other in a direction perpendicular to the base substrate 101 to form a storage capacitor Cst.
  • FIG. 2C shows a circuit diagram of a pixel in a display substrate provided by another embodiment of the present disclosure.
  • the storage capacitor Cst further includes a third capacitor electrode Cc, the third capacitor electrode is located on the side of the first capacitor electrode Ca away from the second capacitor electrode Cb and is connected to the second capacitor electrode Cb through No. 7 shown in FIG. 3A .
  • the holes are electrically connected to each other to form a parallel capacitor structure, increasing the capacitance value of the storage capacitor Cst.
  • the third capacitor electrode Cc, the second capacitor electrode Cb, and the first capacitor electrode Ca all overlap with each other.
  • the third capacitor electrode Cc is located on the first conductive layer 501 .
  • the shielding layer 170 and the second capacitor electrode Cb of the storage capacitor Cst are provided in the same layer and have the same material.
  • the shielding layer 170 and the second capacitor electrode Cb of the storage capacitor Cst are the same electrode block.
  • the shielding layer 170 is connected to the first electrode T3s of the third transistor T3 so as to prevent the shielding layer from being floated and causing a potential change during the display operation to affect the threshold voltage of the transistor.
  • the first transistor T1 and the second transistor T2 are arranged along the second direction D2, and are arranged side by side in the second direction D2.
  • the first transistor T1 and the second transistor T2 are located on the same side of the second capacitor electrode Cb, and are located on opposite sides of the second capacitor electrode Cb with the third transistor T3.
  • the display substrate 10 further includes an extension 180 protruding from the gate T1g of the first transistor T1, the extension 180 extends from the gate T1g of the first transistor T1 along the second direction D2 and is connected with the second transistor T2
  • the first electrode T2s of the second transistor T2 passes through the via hole 800 (an example of the second via hole in the present disclosure), the first electrode contact region Ta1 , the extension portion 180 (that is, the first transistor T1 ) The gate T1g) and the first capacitor electrode Ca are electrically connected.
  • the first electrode T2s of the second transistor T2 is electrically connected to the three parts through a via hole. Compared with the electrical connection to the three parts through a plurality of via holes, the occupied layout space can be reduced and the wiring density can be improved, thereby Increase pixel density. As shown in FIG.
  • the via hole 800 is formed in the third insulating layer 203 , and the extending portion 180 and the portion of the second insulating layer 202 located under the extending portion 180 are located in the via hole 800 and spaced from the via hole 800 .
  • the first electrode T2s of the second transistor T2 is filled in the via hole 800 and covers the first groove V1 and the second groove V2 and has a surface parallel or inclined with respect to the base substrate.
  • the first electrode T2s of the second transistor T2 extends along the first direction D1, spans the extension 180 (crosses the extension 180) and passes through the via 800 (ie, in FIG. 3A ).
  • No. 2 via hole) is electrically connected to the first capacitor electrode Ca.
  • the extension portion 180 has a first side surface and a second side surface opposite in a first direction; for example, the via hole 800 extends along the first direction D1 and exposes the surface of the extension portion 180 and the first side surface and at least a portion of the second side.
  • the first pole T2s of the second transistor T2 includes a first part S1, a second part S2 and a third part S3, the first part S1, the second part S2 and the third part S3 are connected in sequence in the first direction D1.
  • the second portion S2 overlaps the extending portion 180 , the first portion S1 and the third portion S3 are located on both sides of the second portion S2 in the first direction D1 respectively, and the third portion S3 is located close to the second portion S2 One side of the third transistor T3; the first portion S1 fills the first groove V1, and the third portion S3 fills the second groove V2.
  • the first portion S1 is electrically connected to the first electrode contact region T2a1 of the active layer T2a of the second transistor T2, and the second portion S2 is electrically connected to the extension portion 180 in direct contact, which helps In order to increase the contact area and reduce the resistance; the third part S3 is electrically connected to the first capacitor electrode Ca.
  • the first electrode T2s of the second transistor T2 extends along the first direction, and covers the two side surfaces of the extension portion 180 through the via hole 800 , for example, the first portion S1 covers the first side surface, and the third portion S3 Cover the second side.
  • the first electrode T2s of the second transistor T2 and the extension portion 180 have a larger contact area, thereby reducing the contact resistance between the two.
  • the display substrate 10 may further include a connecting portion 720 , which overlaps with the extending portion 180 in a direction perpendicular to the base substrate 101 and is connected to the same layer as the first capacitor electrode Ca
  • the connecting portion 720 is a structure in which the first capacitor electrode Ca is connected to the first electrode contact region T2a1 of the second transistor T2 as a whole.
  • the connecting portion 720 is a portion that is not conductive because it is blocked by the extending portion 180 .
  • the portion 180 and the data signal in the first electrode T2s of the second transistor T2 are turned on, so that the first electrode T2s of the second transistor T2 can be electrically connected to the first capacitor electrode Ca.
  • a dual-channel structure is formed between the first electrode T2s of the second transistor T2 and the first capacitor electrode Ca, which helps to reduce channel resistance.
  • the connecting portion 720 has a structure in which the first capacitor electrode Ca is connected to the first electrode contact region T2a1 of the second transistor T2 as a whole, so as to contact the first electrode of the second transistor T2
  • the region T2a1 is also included in the range of the first capacitive electrode Ca.
  • the first capacitor electrode Ca has a larger area and has a larger overlap area with the third capacitor electrode Cc, thereby increasing the capacitance of the storage capacitor Cst.
  • the third capacitor electrode Cc may at least partially overlap with the first electrode contact region T2a1 of the second transistor T2 in a direction perpendicular to the base substrate, so as to have a larger size with the first capacitor electrode.
  • the overlapping area thus increases the capacitance of the storage capacitor Cst.
  • the third capacitor electrode Cc does not overlap with the channel region T2a0 of the second transistor T2 in a direction perpendicular to the base substrate 101 . This is to prevent the potential on the third capacitor electrode Cc from adversely affecting the operation of the second transistor T2, for example, to prevent the potential on the third capacitor electrode Cc from acting on the channel region T2a0 of the second transistor T2.
  • the second transistor T2 cannot be normally turned off, and the leakage current is relatively large.
  • the display substrate 10 may further include a first scan line 150 and a second scan line 160 corresponding to each pixel row.
  • the first scan line 150 and the second scan line 160 are located in the second conductive layer 502 and extend along the second direction D2.
  • the first scan line 150 is integrated with the gate T2g of the second transistor T2 of the corresponding row of sub-pixels, and the second scan line 160 is respectively connected to the gate T3g of the third transistor T3 of the corresponding row of sub-pixels. an integrated structure.
  • the corresponding first scan line 150 and the second scan line 160 are respectively located on both sides of the first transistor T1 in the row of sub-pixels.
  • each first scan line 150 includes a first portion 151 and a second portion 152 connected alternately, the second portion 152 is a ring structure, and in the first direction D1, the size of the second portion 152 is larger than that of the first portion 151 .
  • each second scan line 160 includes a first portion 161 and a second portion 162 connected alternately, the second portion 162 is a ring structure, and in the first direction D1, the size of the second portion 162 is larger than that of the first portion 161.
  • the display substrate includes a plurality of first surface microstructures and a plurality of second surface microstructures, and a part of the plurality of first surface microstructures and the plurality of second surface microstructures is associated with the first scan line
  • a first portion of the plurality of first surface microstructures and the plurality of second surface microstructures overlap in a direction perpendicular to the base substrate, and another portion of the plurality of first surface microstructures and the second portion of the first scan line are in a direction perpendicular to the overlapping in the direction of the base substrate; in the direction perpendicular to the base substrate, the distribution density of the first surface microstructure and the second surface microstructure overlapping with the second part of the first scan line is greater than that with the first scan line.
  • Distribution density of overlapping first surface microstructures and second surface microstructures for a first portion of a scan line are distributed to the first scan line.
  • the stress relief effect can be improved by the above arrangement.
  • the first overlapping area is greater than an area of the orthographic projection of each of the plurality of first surface microstructures or the second surface microstructures on the base substrate; the second overlapping area is greater than all the area of the orthographic projection of each of the plurality of first surface microstructures or the second surface microstructures on the base substrate.
  • the area of the release structure is too large, it is prone to over-release of stress, resulting in defective panels.
  • the area of the surface microstructure is smaller than the overlapping area, the stress in this area can be fully released to ensure the stability of the panel in this area.
  • the distribution density of surface microstructures in the present disclosure refers to the number of surface microstructures distributed in a unit area of a substrate.
  • the display substrate 10 further includes a plurality of signal lines extending along the first direction D1.
  • the signal lines may be data lines, power lines or auxiliary electrode lines.
  • each second portion 152 intersects with at least one data line in a direction perpendicular to the base substrate 101, thereby defining a plurality of first hollow regions H1 arranged along the second direction D2; each Each of the second portions 162 crosses at least one data line in a direction perpendicular to the base substrate 101, thereby defining a plurality of second hollow regions H2 arranged along the second direction D2.
  • the yield of the device can be effectively improved.
  • the position where the signal lines cross is prone to short-circuit failure due to electrostatic breakdown of parasitic capacitance.
  • the channel can be cut off (for example, by laser cutting), The circuit structure can still work normally through the other channel.
  • the plurality of signal lines include a plurality of data lines DL, and the plurality of data lines DL are connected to each column of sub-pixels in the sub-pixel array in a one-to-one correspondence to provide data signals for the sub-pixels.
  • the plurality of data lines are divided into a plurality of data line groups corresponding to the plurality of pixel units in the pixel row.
  • each data line group includes a first sub-pixel The first data line DL1 connected to P1, the second data line DL2 connected to the second subpixel P2, the third data line DL3 connected to the third subpixel P3, and the fourth data line DL4 connected to the fourth subpixel P4 .
  • the data lines DL1-DL4 connected to the pixel unit are located between the first sub-pixel P1 and the third sub-pixel P3. This setup can provide space for the setup of the detection and power lines.
  • the display substrate 10 further includes a plurality of detection lines 230 extending along the first direction D1, the detection lines 230 are used to connect with the detection sub-circuits (eg, the third transistor T3 ) in the sub-pixel 100, and Connect this detection subcircuit to an external detection circuit.
  • the detection sub-circuits eg, the third transistor T3
  • Connect this detection subcircuit to an external detection circuit.
  • at least one column of the sub-pixels is spaced between each detection line 230 and any one of the plurality of data lines DL; that is, the detection line 230 is not directly adjacent to any data line DL.
  • the first data line DL1 and the fourth data line DL4 are located between the first sub-pixel P1 and the fourth sub-pixel P4, the second data line DL2 and the third data line
  • the DL3 is located between the second sub-pixel P2 and the third sub-pixel P3, and the detection line 230 is located between the fourth sub-pixel P4 and the second sub-pixel P2.
  • the signal delay on the data line caused by the resistance-capacitance load caused by the data line directly adjacent to the detection line is avoided, and the problem of uneven display caused by the delay is further avoided.
  • the signal transmitted on the data line DL is usually a high-frequency signal
  • setting the detection line 230 and the data line DL to not be directly adjacent to each other can prevent the detection line 230 from receiving high-frequency signal crosstalk during the external compensation charging and sampling process, thereby affecting the Sampling accuracy.
  • the four sub-pixels in the pixel unit share one detection line 230 , and the detection line 230 is respectively connected with the third transistor T3 in the four sub-pixels through the detection portion 231 extending along the second direction D2 Diode T3d is electrically connected.
  • the detection line 230 is electrically connected to the detection part 231 through a via hole, and the detection part 231 is electrically connected to the second electrode T3d of the third transistor T3 through a No. 10 via hole.
  • the first electrode T3s of the third transistor T3 is electrically connected to the first electrode contact region T3a1 of the third transistor T3 through the No. 6 via hole, and the second electrode T3d of the third transistor T3 is electrically connected to the third transistor T3 through the No. 5 via hole.
  • the second pole contact region T3a2 is electrically connected.
  • the third transistor T3 and the second capacitor electrode Cb are provided in the same layer and connected as an integral structure.
  • the display substrate 10 further includes a plurality of power supply lines 240 extending along the first direction D1, and the plurality of power supply lines 240 are configured to provide a first power supply voltage for a plurality of sub-pixels, and the power supply voltage is, for example, High supply voltage VDD.
  • the power line 240 is, for example, located in the third conductive layer 503 .
  • at least one pixel column is spaced between each of the plurality of power lines 240 and any one of the plurality of data lines; that is, the power line 240 is not directly adjacent to any data line DL.
  • any power supply line 240 does not overlap with the detection part 231 in the direction perpendicular to the base substrate 101 , that is, the power supply line 240 is provided at the interval corresponding to the adjacent detection parts 231 .
  • This arrangement reduces the overlap of the signal lines, thereby effectively reducing the parasitic capacitance between the signal lines and the signal delay caused thereby.
  • the power supply line 240 is electrically connected to the second electrode T1d of the first transistor T1 of the directly adjacent sub-pixel (eg, the first sub-pixel P1 ) through the No. 3 via hole.
  • the power supply line is connected to The second electrode T1d of the first transistor T1 has an integrated structure.
  • the power supply line 240 is electrically connected to the second electrode T1d of the first transistor T1 of the sub-pixel not directly adjacent to the power supply line 240 through the connection electrode 241 .
  • the connection electrode 241 is electrically connected to the second electrode T1d of the first transistor T1 of the second sub-pixel or the fourth sub-pixel through the No. 11 via hole.
  • the display substrate includes a plurality of first surface microstructures 11 and a plurality of second surface microstructures 12, and a part of the plurality of first surface microstructures and the plurality of second surface microstructures is distributed in the plurality of On a data line DL, another part of the plurality of first surface microstructures and the plurality of second surface microstructures is distributed on the plurality of power lines; the plurality of first surface microstructures and the plurality of The distribution density of the second surface microstructures on the plurality of data lines is greater than the distribution density of the plurality of first surface microstructures and the plurality of second surface microstructures on the plurality of power supply lines.
  • the sensitivity to stress is higher, so setting the distribution density of the surface microstructures on the data line to be higher helps to improve the stability of the panel.
  • connection electrode 241 and the detection part 231 are located in the first conductive layer 501 .
  • connection electrode 241 does not overlap the detection line 230 in the direction perpendicular to the base substrate.
  • the connection electrode 241 is disconnected at a position corresponding to the detection line 230 so as not to overlap with the detection line 230 , which can reduce parasitic capacitance.
  • the first surface microstructure and the second surface microstructure in the present disclosure may be disposed in any signal line or any conductive structure in the display substrate provided by the present disclosure, for example, disposed in the signal line or conductive structure corresponding to the The part at the hole to help relieve the stress of the signal line or the conductive structure at the via hole, thereby reducing the risk of wire breakage.
  • the distance between the first surface microstructure and the second surface microstructure is less than 1/10 of the size of a sub-pixel. This setting can effectively relieve the stress in the range of pixel size.
  • the center distance between the orthographic projection of the first surface microstructure on the base substrate and the orthographic projection of the second surface microstructure on the base substrate is in the first direction and the The components of the second direction are respectively smaller than the average size of each of the plurality of sub-pixels in the first direction and the second direction.
  • the size of one sub-pixel is defined by the signal lines directly adjacent to it and located on both sides respectively.
  • the average size (length) of each sub-pixel in the first direction is the average distance between the corresponding first scan line 150 and the second scan line 160
  • the size of each sub-pixel in the second direction The average size (width) is the average distance between the corresponding data line DL and the detection line 230/power line 240.
  • the length and width of a sub-pixel are respectively 100-500 microns, and the center distance between the orthographic projections of the first surface microstructure 11 and the second surface microstructure 12 on the base substrate is 5-20 microns .
  • first surface microstructures 11 and the second surface microstructures 12 are arranged along the first direction D1, for example, on signal lines (eg, data lines, power lines, detection lines, etc.) extending along the first direction D1.
  • signal lines eg, data lines, power lines, detection lines, etc.
  • the first surface microstructure 11 and the second surface microstructure 12 are located on the same power line 240 , the first surface microstructure 11 includes a first concave structure, and the second surface microstructure 12 includes a second concave surface structure, the first concave structure and the second concave structure face sub-pixels of the same color, for example, the orthographic projection of the normals of the first concave structure and the second concave structure on the base substrate and the first direction D1 sandwich The corners are all acute, that is, point to the same column of sub-pixels.
  • the sub-pixels of each pixel column ie, the sub-pixels located in the same column
  • the concave structure can generate the light back to the light-emitting element (for example, the cathode of the light-emitting element). pixels, thereby avoiding cross-coloring of light from different extended sub-pixels.
  • the display substrate provided by the present disclosure is exemplified below by taking the first electrode T2s of the second transistor T2 as the first conductive structure of the present disclosure as an example, but the embodiments of the present disclosure are not limited thereto.
  • the first surface microstructure 11 is located on the surface of the second pole T2 of the second transistor T2 that is inclined to the base substrate, for example, located on the first part, the second part, the first part, the second part, the second part of the second pole T2 of the second transistor T2
  • the second surface microstructure 12 is located on the surface of the second pole T2s of the second transistor T2 that is parallel to the substrate, for example, on the first part of the second pole T2 of the second transistor T2 , at least one of the second part and the third part.
  • the first surface microstructure 11 is located at the third portion S3 of the second pole T2 of the second transistor T2, and the third portion S3 is filled into the via hole 800 (or the first and second concave holes).
  • the first surface microstructure 11 is located on the slope near the third transistor T3 .
  • the first surface microstructure 11 may be located at the first portion S1 of the second pole T2 of the second transistor T2, and the first portion S1 has a surface relative to the base substrate due to being filled into the via hole 800 .
  • a slope (an example of the first surface of the first conductive structure of the present disclosure), on which the first surface microstructure 11 is located.
  • the second surface microstructure is located on a portion of the third portion S3 that is filled into the second groove and forms a surface parallel to the board surface of the base substrate. Since the conductive structure is subjected to relatively large stress in the groove, disposing the surface microstructure on the part where the third part S3 is filled into the groove can help to relieve the stress.
  • the surfaces of the first portion S1 , the second portion S2 and the third portion S3 of the second electrode T2 of the second transistor T2 are parallel to the board surface of the base substrate (the first conductive structure of the present disclosure).
  • the second surface microstructures 12 are respectively provided on the two surfaces.
  • the first portion S1 of the second electrode T2 of the second transistor T2 includes a portion located in the via hole 800 in direct contact with the semiconductor layer 104 , and the upper surface of the portion can be provided with the second surface microstructure 12 to relieve stress .
  • Fig. 3B shows the recessed structures of the first surface microstructure 11 and the second surface microstructure 12 with blank space.
  • the recessed structures may be at least surrounded by surrounding insulating layers. Filling, for example, all is filled with the fourth insulating layer 204 .
  • the dimension of the first surface microstructure in the first direction is less than one tenth of the largest dimension of the third portion S3 along the first direction.
  • the dimension of the first surface microstructure 11 or the second surface microstructure 12 in the first direction D1 is smaller than that of the via hole 800 in the base substrate
  • One-tenth of the maximum size of the orthographic projection on 101 on the first direction D1 for example, 2%-5%.
  • each sub-pixel further includes a light-emitting element 125 , for example, the light-emitting element is an organic light-emitting diode, including a first electrode 123 , a light-emitting layer 124 and a second electrode 122 that are stacked in sequence.
  • the light-emitting element 125 is a top emission structure
  • the first electrode is reflective
  • the second electrode 122 is transmissive or semi-transmissive.
  • the first electrode 122 is a material with a high work function to serve as an anode, such as an ITO/Ag/ITO stack structure;
  • the second electrode 122 is a material with a low work function to serve as a cathode, such as a semi-transmissive metal or metal alloy material , such as Ag/Mg alloy materials.
  • the display substrate 10 further includes a fourth insulating layer 204 and a fifth insulating layer 205 located between the third conductive layer 503 and the first electrode 123 of the light-emitting element.
  • the fourth insulating layer 204 is a passivation layer, such as an inorganic insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride and other silicon oxides, silicon nitrides or silicon oxynitrides;
  • the insulating layer 205 is an organic insulating material, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA) and other organic insulating materials.
  • the fifth insulating layer 205 is a planarization layer.
  • the display substrate 10 further includes a pixel defining layer 206 located on the first electrode 123 of the light emitting element 125, and the pixel defining layer 206 is an organic insulating material, such as polyimide (PI), acrylate, epoxy resin, Organic insulating materials such as polymethyl methacrylate (PMMA).
  • PI polyimide
  • PMMA polymethyl methacrylate
  • the first electrode 123 of the light-emitting element 125 is electrically connected to the first electrode T1s of the first transistor T1 and the second capacitor electrode Cb through a via hole 700 (namely, the No. 8 via hole in FIG. 3A ), for example, the via hole 700 penetrates through The fourth insulating layer 204 and the fifth insulating layer 205 .
  • the first electrode 123 of the light-emitting element includes a first electrode part 123a, a second electrode part 123b and a third electrode part 123c connected in sequence in the first direction D1, the first electrode part 123a is used to electrically connect with the first electrode T1s of the corresponding first transistor T1 and overlap with the first electrode T1s of the corresponding first transistor T1 in the direction perpendicular to the base substrate 101 .
  • the third electrode portion 123c is used for direct contact with the light-emitting layer 124, and overlaps with the opening area (not shown) of the light-emitting element in a direction perpendicular to the base substrate, that is, the third electrode portion 123c corresponds to the light-emitting element It does not overlap with the via hole 700 in the direction perpendicular to the base substrate, so as to avoid the interface at the via hole 700 from adversely affecting the luminous efficiency of the light-emitting material.
  • the second electrode portion 123b connects the first electrode portion 123a and the third electrode portion 123c.
  • the opening area of the light emitting element is an opening area corresponding to the light emitting element in the pixel defining layer 206, the opening area exposes the first electrode 123 of the light emitting element, and accommodates at least part of the light emitting layer of the light emitting element.
  • the average size of the second electrode portion 123b of the first electrode 123 of the light-emitting element in the second direction D2 is smaller than the average size of the first electrode portion 123a in the second direction D2, and also smaller than the average size of the third electrode portion 123c in the second direction D2.
  • the sum of the largest dimension of the first electrode part along the first direction and the largest dimension along the second direction is smaller than the largest dimension of the third electrode part along the first direction and the largest dimension along the second direction
  • the sum of the largest dimensions of the two directions; the sum of the largest dimension of the second electrode part along the first direction and the largest dimension along the second direction is smaller than the largest dimension of the third electrode part along the first direction
  • the display substrate includes a plurality of first surface microstructures 11 and a plurality of second surface microstructures 12, a part of the plurality of first surface microstructures and the plurality of second surface microstructures and the first electrode part overlapping in a direction perpendicular to the base substrate, and another part of the plurality of first surface microstructures and the plurality of second surface microstructures overlaps the third electrode part in a direction perpendicular to the base substrate ;
  • the distribution density of the first surface microstructure and the second surface microstructure overlapping with the first electrode part is greater than the distribution density of the first surface microstructure and the second surface microstructure overlapping with the third electrode part.
  • the first electrode portion is close to the pixel driving region, for example, at least partially overlapping with the first transistor T1 in the direction perpendicular to the substrate, and the stress in the pixel driving region is more concentrated, the above arrangement can effectively release the stress in the driving region , to improve the performance of the display substrate.
  • the first scan line 150 is located between the first electrode part 123a and the third electrode part 123c, and the second electrode part 123b and the first scan line 150 are perpendicular to the substrate
  • the substrates overlap in the direction, and reducing the size of the second electrode portion 123b in the second direction D2 helps to reduce the overlapping area of the second electrode portion 123b and the first scan line 150 to reduce parasitic capacitance.
  • the second electrode portion 123b overlaps with the first portion 151 of the first scan line 150 in a direction perpendicular to the base substrate 101 , and overlaps with the second portion 152 of the first scan line 150 in a direction perpendicular to the base substrate 101 . direction does not overlap.
  • the second portion 152 of the first scan line 150 overlaps with the signal lines (such as power lines, detection lines, data lines, etc.) along the first direction D1, the second portion 152 is prone to short-circuit and other defects, and needs to be repaired during the repair process. repaired in. Setting the first electrode of the light-emitting element to not overlap with the second portion 152 of the first scan line 150 can reduce the difficulty of repairing at the second portion 152 .
  • the first sub-pixel P1 has a first side and a second side opposite to each other in the second direction D2, the first side is provided with a power line 240, and the second side is provided with a data line DL (No. A data line DL1 and a fourth data line DL4), the second electrode portion 123b is recessed toward the first side relative to the first electrode portion 123a and the third electrode portion 123c, that is, recessed toward the direction away from the second side ; That is, the second electrode portion 123b is closer to the power line than the data line.
  • placing the second electrode portion 123b closer to the power line can prevent the high-frequency signal on the data line DL from affecting the first light-emitting element.
  • the potential on an electrode has an effect, thereby affecting the display gray scale.
  • the second sub-pixel P2 is directly adjacent to the third sub-pixel P3
  • the third sub-pixel P3 has a first side and a second side opposite in the second direction
  • the second data line The DL2 and the third data line DL3 are located on the first side of the third subpixel P3 and between the second subpixel P2 and the third subpixel P3
  • the detection line 230 is located on the second side of the third subpixel P3.
  • the second electrode portion of the first electrode of the light-emitting element of the third subpixel is concave relative to the first electrode portion and the third electrode portion thereof in a direction away from the second side of the third subpixel, that is, the second electrode The portion is closer to the detection line 230 than to the data line.
  • the detection line 230 transmits the low-frequency detection signal
  • the data line DL transmits the high-frequency signal
  • arranging the second electrode part closer to the detection line can prevent the high-frequency signal on the data line DL from affecting the first light-emitting element.
  • the potential on an electrode has an effect, thereby affecting the display gray scale.
  • the light-emitting element OLED in each sub-pixel is configured to emit white light
  • the display substrate 10 further includes a color filter layer
  • the white light is emitted through the color filter layer to realize full-color display.
  • the light-emitting layer 124 can be formed on the entire surface by an Open Mask combined with an evaporation process, so as to avoid using a fine metal mask (Fine Metal Mask, FMM) to pattern the light-emitting layer, thereby avoiding the limitation of the display due to the limited precision of the FMM.
  • FMM Fine Metal Mask
  • the light emitting element of the display substrate 10 may adopt a bottom emission structure.
  • the color filter layer is located on the side of the first electrode of the light-emitting element close to the base substrate 101 , for example, between the fourth insulating layer 204 and the fifth insulating layer 205 .
  • the color filter layer includes a plurality of color filter portions 190 respectively corresponding to a plurality of sub-pixels except the white sub-pixel, that is, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 respectively correspond to a color filter portion 190, the light emitted by the light-emitting elements of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 is emitted through the color filter portion 90 to form display light.
  • the light of the white sub-pixel does not need to pass through the color filter layer, so the fourth sub-pixel P4 does not have a corresponding color filter portion.
  • adjacent color filter portions overlap in a direction perpendicular to the base substrate, and a first surface microstructure or a second surface microstructure is disposed at the corresponding overlap. Due to the non-uniform stress caused by the overlapping of the color filters, the surface microstructure can effectively relieve the stress in this area.
  • the color filter portion corresponding to the first subpixel, the color filter portion corresponding to the second subpixel, and the second surface microstructure are perpendicular to the substrate.
  • the direction of the substrate overlaps.
  • each color filter portion 190 overlaps with the first electrode portion 123a of the first electrode of the light-emitting element of the corresponding sub-pixel, and does not overlap with the third electrode portion 123c of the first electrode of the light-emitting element , because the color filter layer only needs to be arranged corresponding to the light-emitting layer of the light-emitting element.
  • the third electrode portion 123c of the first electrode of the light-emitting element, the light-emitting layer 124 and the color filter portion 190 overlap each other.
  • the overlapping portion of the second electrode portion 123 b of the first electrode of the light-emitting element of the first sub-pixel P1 and the first scan line 150 is also overlapped with the first scanning line 150 .
  • the color filter portions 190 corresponding to the first sub-pixels P1 overlap.
  • the color filter portion 190 is located between the first scan line 150 and the first electrode 123 of the light emitting element in the direction perpendicular to the base substrate, and since the fifth insulating layer 205 on the color filter portion 190 is a planarization layer, therefore The formation of the color filter portion 190 does not affect the height of the fifth insulating layer 205 relative to the base substrate at the color filter portion, that is, does not change the distance between the first electrode of the light-emitting element and the first scan line 150, However, the dielectric constant of the color filter portion 190 is lower than the dielectric constant of the fifth insulating layer 205, so the color filter portion 190 is formed between the second electrode portion 123b and the first scan line 150 and is connected with the two The overlapping helps to further reduce the parasitic capacitance between the first electrode of the light-emitting element and the first scan line.
  • the inventors found that when a plurality of first hollow regions H1 or second hollow regions H2 are regularly arranged along the second direction D2, when a certain regular continuity occurs, a periodic diffraction phenomenon will occur, causing the hollow regions to be different from non-conductive regions.
  • the metal lines in the hollow area have obvious differences in the reflection of ambient light, resulting in uneven display.
  • the geometric centers of the plurality of first hollow regions H1 are not on a straight line, which helps to reduce the regularity of the first hollow regions arranged in the same direction and reduce the cycle time. Display unevenness caused by diffraction.
  • a color filter layer is used to selectively block a plurality of hollow areas located in the same row and corresponding to one pixel unit, thereby breaking the arrangement rule of the hollow areas in the pixel unit and weakening the Diffraction effect, improve display uniformity.
  • the color filter portion corresponding to one pixel row (the first pixel row) is located between the first scan line 150 corresponding to the pixel row and the immediately adjacent next pixel row ( between the second scan lines 160 corresponding to the second pixel row).
  • the second pixel row includes a fifth sub-pixel P5, a sixth sub-pixel P6 and a seventh sub-pixel P7 arranged in sequence along the second direction D2, the fifth sub-pixel P5 and the first sub-pixel P1 are located in the same column, The sixth sub-pixel P6 and the second sub-pixel P2 are located in the same column, and the seventh sub-pixel P7 and the third sub-pixel P3 are located in the same column.
  • sub-pixels located in the same column emit the same color.
  • the first electrode of the light-emitting element of each sub-pixel also extends in the first direction D1 to be perpendicular to the substrate with the second capacitive electrode Cb of the sub-pixel in the adjacent next pixel row The direction of the substrate overlaps.
  • a fourth insulating layer 204 and a fifth insulating layer 205 are spaced between the first electrode of the light-emitting element and the second capacitor electrode Cb of the next row of sub-pixels.
  • a repair hole is formed between the first electrode of the light-emitting element and the second capacitor electrode Cb of the next row of sub-pixels, for example, the fourth insulating layer 204 is removed by laser and the first electrode of the light-emitting element is filled into the repair hole It is electrically connected to the second capacitor electrode Cb of the sub-pixel in the next row, and the second capacitor electrode Cb is electrically connected to the first electrode of the light-emitting element of the sub-pixel to which it belongs.
  • An electrode is electrically connected to the first electrode of the light-emitting element of the sub-pixel in the next row, so that the defective sub-pixel can be repaired.
  • the location of the repair hole is illustrated in FIG. 3A with a No. 9 via hole.
  • the color filter portions 190 corresponding to the first pixel row respectively have sides close to the second pixel row, for example, the sides are straight and parallel to the second direction D2.
  • the color filter portion 190 corresponding to the first sub-pixel P1 overlaps with at least one of the plurality of first hollow regions H1
  • the color filter portion 190 corresponding to the second sub-pixel P2 overlaps with the plurality of first hollow regions H1. None of the first hollow regions H1 overlap.
  • the color filter portion corresponding to the first sub-pixel P1 overlaps with one of the plurality of first hollow regions H1 and has a first overlapping area
  • the color filter portion corresponding to the second sub-pixel P2 The portion overlaps with another one of the plurality of first hollow regions H1 and has a second overlapping area; the first overlapping area is different from the second overlapping area.
  • the absolute value of the difference between the first overlapping area and the second overlapping area is greater than (n* ⁇ )2 (ie, the square of an integer multiple of wavelengths), where ⁇ is the amount of light emitted by the first sub-pixel P1 and the second sub-pixel P2 the larger of the wavelengths.
  • ⁇ is the amount of light emitted by the first sub-pixel P1 and the second sub-pixel P2 the larger of the wavelengths.
  • the color filter portion 190 corresponding to the first sub-pixel P1 overlaps with one of the plurality of first hollow regions H1
  • the color filter portion corresponding to the second sub-pixel P2 190 and the color filter portion 190 corresponding to the third sub-pixel P3 do not overlap with the plurality of first hollow regions H1.
  • the second portion 162 of the second scan line 160 corresponding to the second pixel row overlaps with the power line 240 , the data line DL and the detection line 230 in a direction perpendicular to the base substrate to define a second direction D2 A plurality of second hollow regions H2 arranged in sequence.
  • the color filter portion corresponding to the first sub-pixel P1 overlaps with one of the second hollow regions H2 and has a third overlapping area A3
  • the color filter portion corresponding to the second sub-pixel P2 overlaps with another second hollow area in the plurality of second hollow areas H2 and has a fourth overlapping area A4.
  • the third sub-pixel P3 and the second hollow area in the plurality of second hollow areas H2 Another second hollow area overlaps and has a fifth overlapping area A5; the third overlapping area A3, the fourth overlapping area A4 and the fifth overlapping area A5 are all different.
  • the first hollow regions H1 ′ near the fourth sub-pixel P4 among the plurality of first hollow regions H1 do not overlap with the color filter layer in the direction perpendicular to the base substrate; the plurality of second hollow regions The second hollow regions H2' in H2 close to the fourth sub-pixel P4 do not overlap with the color filter layer in the direction perpendicular to the base substrate.
  • the first hollow area H1 ′′ that is directly adjacent to the first hollow area H1 ′ does not overlap with the color filter layer in the direction perpendicular to the base substrate; in the second direction D2
  • the second hollow area H2 ′′ directly adjacent to the second hollow area H2 ′ does not overlap with the color filter layer in a direction perpendicular to the base substrate.
  • the fourth sub-pixel P4 Since the fourth sub-pixel P4 emits white light, the uniformity of the display due to the diffraction of the white light is small, so the hollow area close to the fourth sub-pixel P4 may not be shielded.
  • the first data line DL1 , the second data line DL2 and the third data line DL3 all overlap with the color filter layer. This setting can avoid the reflection of the light by the data line and the uneven display occurs.
  • the fourth data line DL4 does not overlap with the color filter layer.
  • the detection line 230 overlaps with the color filter layer, and the overlapping area is smaller than any one of the first data line DL1 , the second data line DL2 and the third data line DL3 .
  • the overlapping area of the line and the color filter layer is smaller than any one of the first data line DL1 , the second data line DL2 and the third data line DL3 .
  • the fourth data line DL4 and the detection line 230 are closest to the fourth sub-pixel P4 compared to the first data line DL1, the second data line DL2 and the third data line DL3, and the fourth sub-pixel P4 emits white light, the white light Diffraction has little effect on display uniformity, so the fourth data line DL4 and the detection line 230 have little influence on the reflection of the light emitted by the first sub-pixel P4, and the fourth data line and the detection line may not be shielded.
  • the first surface microstructures 11 and the second surface microstructures 12 are located on the same power line 240 , that is, the power line 240 serves as the first conductive structure;
  • a surface microstructure 11 and the second hollow region H2 corresponding to the power line 240 at least partially overlap in a direction perpendicular to the base substrate.
  • the stress is relatively large, and arranging the first surface microstructure 12 at the power line 240 corresponding to the second hollow area H2 helps to relieve the stress and improve the performance of the power line 240. Rate.
  • the first surface microstructures 11 and the second surface microstructures 12 are located on the second pole T3d of the third transistor T3, that is, the second pole T3d of the third transistor T3 serves as a and the first surface microstructure and the No. 10 via hole (an example of the fourth via hole of the present disclosure) at least partially overlap in a direction perpendicular to the base substrate.
  • the first surface microstructures 11 and the second surface microstructures 12 are located on the first electrode T3s of the third transistor T3, that is, the first electrode T3s of the third transistor T3 serves as the the first conductive structure; and the first surface microstructure and the No. 6 via hole at least partially overlap in a direction perpendicular to the base substrate.
  • first surface microstructure 11 and the second surface microstructure 12 are shown with black dots in both Figures 3D and 3E. Since the gradient of the conductive structure at the first position of the via hole is relatively large, the stress is relatively large, and disposing the first surface microstructure at the position corresponding to the via hole of the first conductive structure can help to release the stress.
  • At least one embodiment of the present disclosure also provides a method for fabricating the above-mentioned display substrate.
  • 3A-3B and FIGS. 4A-4D and taking a sub-pixel as an example, the manufacturing method of the display substrate provided by the embodiment of the present disclosure will be exemplarily described, but the embodiment of the present disclosure is not limited thereto.
  • FIGS. 4A-4D respectively show the patterns of the first conductive layer, the semiconductor layer, the second conductive layer, and the third conductive layer in one sub-pixel (eg, the first sub-pixel P1 ).
  • the manufacturing method includes the following steps S61-S65.
  • Step S61 forming a first conductive material layer, and performing a patterning process on the first conductive material layer to form the first conductive layer 501 as shown in FIG. 4A , that is, the light shielding layer 170 and the third capacitor electrode Cc of the storage capacitor Cst .
  • This patterning process also forms the detection portion 231 and the connection electrode 241 insulated from each other.
  • Step S62 forming a first insulating layer 201 on the first conductive layer 501 and forming a semiconductor material layer on the first insulating layer, and performing a patterning process on the semiconductor material layer to form the semiconductor layer 104 shown in FIG. 4B , that is, the active layer T1a of the first transistor T1, the active layer T2a of the second transistor T2, and the active layer T3a of the third transistor T3 are formed spaced apart from each other.
  • Step S63 forming a second insulating layer 202 on the semiconductor layer 104 and forming a second conductive material layer on the second insulating layer, and performing a patterning process on the second conductive material layer to form a second conductive material as shown in FIG. 4C
  • the layer 502, ie forms the gate T1g of the first transistor T1, the gate T2g of the second transistor T2 and the gate T3g of the third transistor T3, which are insulated from each other.
  • FIG. 4C also shows extension 180 .
  • the second conductive layer 502 further includes the first scan line 150 and the second scan line 160 which are insulated from each other.
  • the line widths of the first scan lines 150 and the second scan lines 160 are in the range of 5-15 microns.
  • the first scan line 150 is integrated with the gate T2g of the second transistor T2 of the corresponding row of sub-pixels, and the second scan line 160 is respectively connected to the gate T3g of the third transistor T3 of the corresponding row of sub-pixels. an integrated structure.
  • Step S64 adopting a self-alignment process, and using the second conductive layer 502 as a mask to conduct conducting treatment (eg, doping treatment) on the semiconductor layer 204 , so that the semiconductor layer 204 is not covered by the second conductive layer 502
  • the part of the transistor is conductorized to obtain the first capacitor electrode Ca, and the part of the active layer of each transistor located on both sides of the channel region is conductorized to form a first electrode contact region and a second electrode contact region, respectively.
  • the first electrode contact area and the second electrode contact area are used for electrical connection with the first electrode and the second electrode of the transistor, respectively.
  • connection 720 is also shown in Figure 4B.
  • an etching process is performed on the second insulating layer 202 before conducting the conductorization treatment on the semiconductor layer 104, so that the entire area of the second insulating layer 202 not covered by the second conductive layer 502 is etched, that is, the first The two insulating layers 103 and the second conductive layer 502 overlap in a direction perpendicular to the base substrate 101 .
  • the implanted ions may not be blocked by the second insulating layer 202 when the semiconductor layer 204 is conductively treated by ion implantation in the region not covered by the second conductive layer 202 .
  • Step S65 forming a third insulating layer 203 on the second conductive layer 502, forming a third conductive material layer on the third insulating layer 203, and performing a patterning process on the third conductive material layer to form as shown in FIG. 4D
  • the third conductive layer 503, that is, the first electrode T1s and the second electrode T1d of the first transistor T1, the first electrode T2s and the second electrode T2d of the second transistor T2, and the first electrode T3s and the second electrode of the third transistor T3 are formed.
  • the second pole T3d is, the first electrode T1s and the second electrode T1d of the first transistor T1, the first electrode T2s and the second electrode T2d of the second transistor T2, and the first electrode T3s and the second electrode of the third transistor T3 are formed.
  • the second pole T3d is, the first electrode T1s and the second electrode T1d of the first transistor T1, the first electrode T2s and the second electrode T2d of the second transistor T2, and the first electrode
  • the third conductive layer 503 further includes a data line DL, a detection line 230 and a power supply line 240 which are insulated from each other.
  • the line width of the data line DL is in the range of 5-15 micrometers
  • the line width of the detection line 230 is in the range of 5-30 micrometers
  • the line width of the power supply line 240 is in the range of 5-30 micrometers.
  • the power supply line 240 and the second electrode T1 d of the first transistor T1 in the sub-pixel directly adjacent thereto have an integrated structure.
  • each data line 110 and the second electrode T2d of the second transistor T2 in the sub-pixel connected thereto are integrated.
  • the materials of the semiconductor material layer include but are not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene, etc.) , polythiophene, etc.).
  • silicon-based materials amorphous silicon a-Si, polycrystalline silicon p-Si, etc.
  • metal oxide semiconductors IGZO, ZnO, AZO, IZTO, etc.
  • organic materials hexathiophene, etc.
  • the first conductive material layer is a light-shielding conductive material, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and An alloy material composed of the above metals.
  • the first conductive material layer may be a molybdenum-titanium alloy, eg, with a thickness of 50-100 nanometers.
  • materials of the second conductive material layer and the third conductive material layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) ) and alloy materials composed of the above metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • the second conductive material layer is a laminated structure of molybdenum-titanium alloy and copper, for example, the thickness of the molybdenum-titanium alloy is 30-50 nanometers, and the thickness of copper is 300-400 nanometers.
  • the third conductive material layer is a laminated structure of molybdenum-titanium alloy and copper, for example, the thickness of the molybdenum-titanium alloy is 30-50 nanometers, and the thickness of copper is 400-700 nanometers.
  • the materials of the semiconductor material layer include but are not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene, etc.) , polythiophene, etc.).
  • silicon-based materials amorphous silicon a-Si, polycrystalline silicon p-Si, etc.
  • metal oxide semiconductors IGZO, ZnO, AZO, IZTO, etc.
  • organic materials hexathiophene, etc.
  • the material of the semiconductor material layer is indium gallium zinc oxide, and the thickness is 30-50 nanometers.
  • the first insulating layer 201 , the second insulating layer 202 , and the third insulating layer 203 are inorganic insulating layers, such as silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, silicon nitrides, or silicon nitrogens. Oxides, or aluminum oxide, titanium nitride, etc., include metal oxynitride insulating materials.
  • these insulating layers may also be organic materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), etc., which are not limited in the embodiment of the present disclosure.
  • the material of the first insulating layer 201 is silicon oxide, and the thickness is 300-500 nanometers.
  • the material of the second insulating layer 202 is silicon oxide, and the thickness is 100-160 nanometers.
  • the material of the third insulating layer is silicon oxide, and the thickness is 400-600 nanometers.
  • a fourth insulating layer 204 , a color filter layer and a fifth insulating layer 205 may be formed in sequence on the third conductive layer 503 , and the first electrode of the light-emitting element may be formed on the fifth insulating layer 205 123, then the pixel defining layer 206 is formed on the first electrode 123, and the light emitting layer 124 and the second electrode 122 are formed in sequence, thus forming the display substrate 10 as shown in FIG. 3A.
  • forming the color filter layer may include first forming a red color filter layer and performing a patterning process on the red color filter layer to form a color filter portion corresponding to the red sub-pixels, and then forming a green color filter layer and patterning the green color filter layer The process forms a color filter portion corresponding to the green sub-pixel, and then forms a blue color film layer and performs a patterning process on the blue color film layer to form a color filter portion corresponding to the blue sub-pixel.
  • the thicknesses of the red color filter layer, the green color filter layer and the blue color filter layer are respectively 2000-3000 nanometers, that is, the thickness of each color filter part is 2000-3000 nanometers.
  • a light shielding portion can be formed between adjacent sub-pixels by overlapping the color filter portions to avoid cross-coloring.
  • the concave structure can be formed by etching the conductive structure or signal line in the display substrate, or the surface of the conductive structure or signal line can be plasma treated to form the above-mentioned first surface microstructure and second surface microstructure .
  • At least one embodiment of the present disclosure further provides a display panel including any one of the above display substrates 10 .
  • the above-mentioned display substrate 10 provided in at least one embodiment of the present disclosure may include the light-emitting element 125 or may not include the light-emitting element 125 , that is, the light-emitting element 125 may be formed in a panel factory after the display substrate 10 is completed.
  • the display panel provided by the embodiment of the present disclosure further includes the light-emitting element 125 in addition to the display substrate 10 .
  • the display panel is an OLED display panel, and correspondingly, the display substrate 10 included in the display panel is an OLED display substrate.
  • the display panel 20 further includes an encapsulation layer 801 and a cover plate 802 disposed on the display substrate 10 , and the encapsulation layer 801 is configured to seal the light-emitting elements on the display substrate 10 to prevent external humidity The penetration of gas and oxygen into the light-emitting element and the driving circuit causes damage to the device.
  • the encapsulation layer 801 includes an organic thin film or a structure in which organic thin films and inorganic thin films are alternately stacked.
  • a water absorbing layer (not shown) may also be disposed between the encapsulation layer 801 and the display substrate 10, which is configured to absorb water vapor or sol remaining in the pre-fabrication process of the light-emitting element.
  • the cover plate 802 is, for example, a glass cover plate.
  • the cover plate 802 and the encapsulation layer 801 may be an integral structure.
  • the display panel includes an adhesive layer 901 and a metal encapsulation layer 902 disposed on the display substrate 10 .
  • the metal encapsulation layer 902 can also support and fix the display substrate 10.
  • the display substrate 10 can be supported to reduce the stress impact on the display substrate 10.
  • the display substrate 10 is a bottom emission structure, and the metal encapsulation layer 902 does not block the display light.
  • At least one embodiment of the present disclosure further provides a display device 30.
  • the display device 30 includes any of the above-mentioned display substrates 10 or display panels 20.
  • the display device in this embodiment may be: a display, an OLED Panels, OLED TVs, electronic paper, mobile phones, tablet computers, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • the above-mentioned patterning process may adopt a conventional photolithography process, for example, including steps of photoresist coating, exposure, development, drying, and etching.

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Abstract

一种显示基板(10)及显示装置(30)。该显示基板(10)包括第一导电结构(110)，该第一导电结构(110)包括相对的第一表面(111)和第三表面(113)以及相对的第二表面(112)和第四表面(114)，该第一表面(111)与第二表面(112)的材料相同，该第一表面(111)和第二表面(112)分别与衬底基板(101)的板面形成不同的夹角；该第一表面(111)上设置有第一表面微结构(11)，该第二表面(112)上设置有第二表面微结构(12)；该第一表面微结构(11)具有与衬底基板(101)垂直的第一截面(11a)，该第一截面(11a)在该第三表面(113)具有第一正投影(C1C2)；该第一正投影(C1C2)的长度小于该第一表面微结构(11)在该第一截面(11a)上的长度；该第二表面微结构(12)具有与衬底基板(101)垂直的第二截面(12a)，该第二截面(12a)在该第四表面(114)上具有第二正投影(D1D2)，该第二正投影(D1D2)的长度小于该第二表面微结构(12)在该第二截面(12a)上的长度。该显示基板(10)可以有效提高良率。

Description

显示基板及显示装置
本申请要求于2021年1月4日递交的中国专利申请第202110000866.2的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
[根据细则91更正 18.06.2021]　
本公开实施例涉及一种显示基板及显示装置。
背景技术
[根据细则91更正 18.06.2021]　
在显示领域，有机发光二极管（OLED）显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。作为显示装置核心的半导体元件技术也随之得到了飞跃性的进步。对于现有的显示装置而言，有机发光二极管(Organic Light-Emitting Diode，简称OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点而越来越多地被应用于高性能显示技术领域当中。
发明内容
本公开至少一实施例提供一种显示基板，包括：衬底基板及位于所述衬底基板上的第一导电结构。所述第一导电结构包括背离所述衬底基板的第一表面和第二表面，所述第一表面和所述第二表面的材料相同；所述第一表面与所述衬底基板的板面具有第一夹角，所述第二表面与所述衬底基板的板面具有第二夹角，所述第一夹角与所述第二夹角不同；所述第一表面上设置有第一表面微结构，所述第二表面上设置有第二表面微结构；所述第一导电结构还包括靠近所述衬底基板的第三表面和第四表面，所述第三表面与所述第一表面相对，所述第四表面与所述第二表面相对；所述第一表面微结构具有与所述衬底基板垂直的第一截面，所述第一截面在所述第三表面具有第一正投影；所述第一正投影的长度小于所述第一表面微结构在所述第一截面上的长度；所述第二表面微结构具有与所述衬底基板垂直的第二截面，所述第二 截面在所述第四表面上具有第二正投影，所述第二正投影的长度小于所述第二表面微结构在所述第二截面上的长度。
在一些示例中，所述第一截面的两端之间的距离和所述第二截面的两端的距离分别大于0.1微米小于1微米。
在一些示例中，在垂直于所述衬底基板的方向上，所述第一表面微结构与所述第三表面至少部分重叠，所述第二表面微结构与所述第四表面至少部分重叠。
在一些示例中，所述第三表面和所述第四表面的至少之一为平坦表面。
在一些示例中，所述第一表面微结构在所述第三表面上的正投影的面积小于所述第一表面微结构的表面积；所述第二表面微结构在所述第四表面上的正投影的面积小于所述第二表面微结构的表面积。
在一些示例中，所述第一导电结构在所述第一表面微结构处的最小厚度小于所述第一导电结构的平均厚度且大于所述第一导电结构的平均厚度的3/5。
在一些示例中，所述第一表面微结构在所述第一截面具有第一端点、第一中间点和第二端点，所述第二表面微结构在所述第二表面微结构具有第三端点、第二中间点和第四端点；所述第一中间点与所述第三表面的距离和所述第一端点及第二端点与所述第三表面的距离均不相等，所述第二中间点与所述第四表面的距离和所述第三端点及所述第四端点与所述第四表面的距离均不相等。
在一些示例中，所述第一夹角大于0度，所述第二夹角等于0度。
在一些示例中，所述第一表面微结构在所述第一截面具有第一端点和第二端点，所述第二表面微结构在所述第二截面具有第三端点和第四端点；所述第一端点和所述第二端点构成的线段的中点与所述第三端点和所述第四端点的构成的线段的中点相对于所述衬底基板的板面的距离不同。
在一些示例中，所述第一端点与所述第二端点之间的距离大于所述第三端点与所述第四端点之间的距离。
在一些示例中，所述显示基板还包括位于所述第一导电结构靠近所述衬底基板一侧的第一绝缘层，所述第一绝缘层包括分别与所述第一导电结构的第三表面和第四表面分别直接接触的第一部分和第二部分，所述第一部分的 最小厚度小于所述第二部分的最小厚度。
在一些示例中，所述显示基板还包括位于所述第一绝缘层靠近所述衬底基板一侧的第二导电结构，所述第一绝缘层的第一部分包覆所述第二导电结构的至少部分。
在一些示例中，在垂直于衬底基板的方向上，所述第一表面微结构与所述第二导电结构不重叠。
在一些示例中，所述第一导电结构通过贯穿所述第一绝缘层的第一过孔与所述第二导电结构电连接；在垂直于所述衬底基板的方向上，所述第一表面微结构与所述第一过孔的至少部分重叠。
在一些示例中，所述第一绝缘层包括层叠设置的第一子层和第二子层，所述第二子层相较于所述第一子层远离所述衬底基板；所述第一子层包括被所述第一过孔暴露的第一侧面，所述第二子层包括被所述第一过孔暴露的第二侧面，所述第一侧面与所述第二侧面中的至少之一与所述第一导电结构的第三表面直接接触。
在一些示例中，所述第一侧面与所述衬底基板的夹角大于所述第二侧面与所述衬底基板的夹角。
在一些示例中，所述第二子层的致密度高于所述第一子层。
在一些示例中，所述第一表面的氧含量高于所述第三表面的氧含量。
在一些示例中，所述第一表面微结构在所述第一截面具有第一端点和第二端点，所述第一截面距离所述第三表面最近的点与所述第一端点和所述第二端点的距离不相等。
在一些示例中，所述第一表面微结构包括第一凹面结构，所述第二表面微结构包括第二凹面结构。
在一些示例中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素沿第一方向和第二方向布置为多个像素列和多个像素行，所述第一方向与所述第二方向交叉；所述多个子像素中的每个包括在所述衬底基板上的第一晶体管、第二晶体管、第三晶体管和存储电容，所述第二晶体管的第一极与所述存储电容的第一电容电极和所述第一晶体管的栅极电连接，所述第二晶体管的第二极配置为接收数据信号，所述第二晶体管的栅极配置为接收第一控制信号，所述第二晶体管配置为响应于所述第一控制信号 将所述数据信号写入所述第一晶体管的栅极和所述存储电容，所述第一晶体管的第一极与所述存储电容的第二电容电极电连接，并配置为与发光元件的第一电极电连接，所述第一晶体管的第二极配置为接收第一电源电压，所述第一晶体管配置为在所述第一晶体管的栅极的电压的控制下控制用于驱动所述发光元件的电流，所述第三晶体管的第一极与所述第一晶体管的第一极以及所述存储电容的第二电容电极电连接，所述第三晶体管的第二极配置为与检测电路连接。
在一些示例中，所述第一表面微结构在所述衬底基板上的正投影与所述第二表面微结构在所述衬底基板上的正投影之间的中心距离在所述第一方向和所述第二方向的分量分别小于所述多个子像素的每个在所述第一方向和所述第二方向的平均尺寸。
在一些示例中，每个像素列的子像素发相同颜色的光。
在一些示例中，所述第一表面微结构包括第一凹面结构，所述第二表面微结构包括第二凹面结构；所述第一凹面结构和所述第二凹面结构沿所述第一导电结构的延伸方向排列，且朝向颜色相同的子像素。
在一些示例中，所述显示基板还包括从所述第一晶体管的栅极突出的延伸部，所述延伸部从所述第一晶体管的栅极沿所述第二方向延伸并与所述第二晶体管的第一极在垂直于所述衬底基板的方向上至少部分重叠且电连接。
在一些示例中，所述第二晶体管的有源层包括第一极接触区、第二极接触区以及位于所述第一极接触区和所述第二极接触区之间的沟道区，所述第二晶体管的第一极通过第二过孔分别与所述第一极接触区、所述延伸部以及所述第一电容电极电连接。
在一些示例中，所述第二过孔沿所述第一方向延伸并暴露出所述延伸部的表面以及在所述第一方向上相对的两个侧面的至少部分。
在一些示例中，所述延伸部将所述第二过孔间隔为第一凹槽和第二凹槽，所述第二晶体管的第一极填充所述第一凹槽和所述第二凹槽并包覆所述延伸部的所述两个侧面；所述第二晶体管的第一极包括第一部分、第二部分以及第三部分，所述第二部分覆盖所述延伸部的所述表面，所述第一部分覆盖所述第一凹槽，所述第三部分覆盖所述第二凹槽；所述第一部分和所述第三部分还分别覆盖所述延伸部的所述两个侧面。
在一些示例中，所述第一导电结构为所述第二晶体管的第一极，所述第一表面微结构和所述第二表面微结构均位于所述第二晶体管的第一极的第三部分。
在一些示例中，所述第一表面微结构在所述第一方向上的尺寸小于所述第三部分沿所述第一方向的最大尺寸的十分之一。
在一些示例中，所述第一表面微结构在所述第一方向上的尺寸小于所述第二过孔在所述衬底基板上的正投影在所述第一方向上的最大尺寸的十分之一。
在一些示例中，所述多个子像素的每个还包括所述发光元件，所述发光元件包括依次层叠设置的第一电极、发光层和第二电极，所述第一电极相较于所述第二电极更靠近所述衬底基板，所述发光元件的第一电极通过第三过孔与所述发光元件所属的子像素的第一晶体管的第一极电连接。
在一些示例中，所述发光元件的第一电极包括在所述第一方向上依次连接的第一电极部、第二电极部和第三电极部，所述第一电极部用于与对应的第一晶体管的第一极电连接且在垂直于所述衬底基板的方向上与所述对应的第一晶体管的第一极重叠；所述发光元件的第三电极部与所述发光元件的开口区在垂直于所述衬底基板的方向上至少部分重叠。
在一些示例中，所述第一电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺寸之和小于所述第三电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺寸之和；所述第二电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺寸之和小于所述第三电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺寸之和。
在一些示例中，所述显示基板包括多个第一表面微结构和多个第二表面微结构，所述多个第一表面微结构和多个第二表面微结构中的一部分与所述第一电极部在垂直于衬底基板的方向上重叠，所述多个第一表面微结构和多个第二表面微结构的另一部分与所述第三电极部在垂直于所述衬底基板的方向上重叠；与所述第一电极部重叠的第一表面微结构和第二表面微结构的分布密度大于与所述第三电极部的重叠的第一表面微结构和第二表面微结构的分布密度。
在一些示例中，所述发光元件的第一电极的第二电极部在所述第二方向 的平均尺寸小于所述第一电极部在所述第二方向的平均尺寸，也小于所述第三电极部在所述第二方向的平均尺寸。
在一些示例中，所述多个像素行包括第一像素行，所述第一像素行划分为多个像素单元，每个像素单元包括沿所述第二方向依次布置的第一子像素、第二子像素和第三子像素，所述第一子像素、所述第二子像素和所述第三子像素分别配置为发出三种基本色的光；所述显示基板还包括沿所述第二方向延伸的第一扫描线，所述第一扫描线与所述第一子像素、第二子像素及第三子像素中的第二晶体管的栅极电连接以提供所述第一控制信号。
在一些示例中，所述第一扫描线与所述第一子像素的发光元件的第一电极的第二电极部在垂直于所述衬底基板的方向上重叠。
在一些示例中，所述显示基板还包括彩膜层，所述彩膜层位于所述发光元件的第一电极靠近所述衬底基板的一侧；所述彩膜层包括分别对应于所述第一子像素、所述第二子像素和所述第三子像素的多个彩膜部，所述第一子像素、所述第二子像素和所述第三子像素发出的光分别经所对应的彩膜部射出显示基板形成显示光。
在一些示例中，在垂直于所述衬底基板的方向上，所述第一子像素对应的彩膜部、所述第二子像素对应的彩膜部和所述第二表面微结构在垂直于衬底基板的方向上均重叠。
在一些示例中，在垂直于所述衬底基板的方向上，所述多个彩膜部的每个与对应的子像素的发光元件的第一电极的第三电极部重叠，并与所述对应的子像素的发光元件的第一电极的第一电极部不重叠。
在一些示例中，所述第一扫描线位于所述彩膜层靠近所述衬底基板的一侧；在垂直于所述衬底基板的方向上，所述第一子像素的发光元件的第一电极的第二电极部与所述第一扫描线重叠的部分还与所述第一子像素所对应的彩膜部重叠。
在一些示例中，所述第一扫描线包括交替连接的第一部分和第二部分，所述第二部分为环状结构。
在一些示例中，在垂直于所述衬底基板的方向上，所述第一子像素的发光元件的第一电极与所述第一扫描线的第一部分重叠并与所述第一扫描线的第二部分不重叠。
在一些示例中，所述显示基板还包括沿所述第一方向延伸的多条第一信号线，在垂直于所述衬底基板的方向上，所述多条第一信号线与所述第一扫描线的第二部分重叠从而定义出沿所述第二方向布置的多个第一镂空区。
在一些示例中，每个像素单元中所对应的多个第一镂空区的几何中心不在一条直线上。
在一些示例中，在垂直于所述衬底基板的方向上，所述第一子像素对应的彩膜部与所述多个第一镂空区中的至少一个重叠，所述第二子像素对应的彩膜部与所述多个第一镂空区均不重叠。
在一些示例中，在垂直于所述衬底基板的方向上，所述第一子像素对应的彩膜部与所述多个第一镂空区中的一个重叠且具有第一重叠面积，所述第二子像素对应的彩膜部与所述多个第一镂空区中的另一个重叠且具有第二重叠面积；所述第一重叠面积与所述第二重叠面积不同。
在一些示例中，所述第一重叠面积与所述第二重叠面积差值的绝对值大于(n*λ)2，λ为所述第一子像素和第二子像素发出光的波长中的较大值。
在一些示例中，所述显示基板包括多个第一表面微结构和多个第二表面微结构，所述多个第一表面微结构和多个第二表面微结构中的一部分与所述第一扫描线的第一部分在垂直于衬底基板的方向上重叠，所述多个第一表面微结构和多个第二表面微结构的另一部分与所述第一扫描线的第二部分在垂直于所述衬底基板的方向上重叠；在垂直于衬底基板的方向上，与所述第一扫描线的第二部分重叠的第一表面微结构和第二表面微结构的分布密度大于与所述第一扫描线的第一部分的重叠的第一表面微结构和第二表面微结构的分布密度。
在一些示例中，所述第一重叠面积大于所述多个第一表面微结构或所述第二表面微结构中的每个在所述衬底基板的正投影的面积；所述第二重叠面积大于所述多个第一表面微结构或所述第二表面微结构中的每个在所述衬底基板的正投影的面积。
在一些示例中，所述像素单元还包括第四子像素，所述第四子像素配置为发白光，所述多个第一镂空区中靠近所述第四子像素的第一镂空区均与所述彩膜层在垂直于所述衬底基板的方向上不重叠。
在一些示例中，所述多条第一信号线包括多条数据线，所述多条数据线 与所述多个像素列一一对应连接；对于所述第一像素行，多条数据线被划分为与所述多个像素单元一一对应的多个数据线组，每个数据线组包括分别与所述第一子像素、第二子像素和第三子像素连接的第一数据线、第二数据线和第三数据线；对于每一个所述像素单元，与所述像素单元对应连接的所述第一数据线、所述第二数据线及所述第三数据线均位于所述第一子像素和所述第三子像素之间。
在一些示例中，所述显示基板还包括沿所述第一方向延伸的多条电源线，所述多条电源线配置为为所述多个子像素提供所述第一电源电压，所述多条电源线的每条与所述多条数据线中的任意一条之间间隔有至少一个像素列。
在一些示例中，所述显示基板包括多个第一表面微结构和多个第二表面微结构，所述多个第一表面微结构和多个第二表面微结构中的一部分分布在所述多条数据线上，所述多个第一表面微结构和多个第二表面微结构的另一部分分布在所述多条电源线上；所述多个第一表面微结构和所述多个第二表面微结构在所述多条数据线上的分布密度大于所述多个第一表面微结构和所述多个第二表面微结构在所述多条电源线上的分布密度。
在一些示例中，所述第二子像素与所述第三子像素直接相邻，所述第三子像素具有在所述第二方向上相对的第一侧与第二侧，所述第二数据线和所述第三数据线位于所述第三子像素的第一侧且位于所述第二子像素与所述第三子像素之间。
在一些示例中，所述第三子像素的发光元件的第一电极的第二电极部相对于其第一电极部和其第三电极部向远离所述第三子像素的第二侧的方向凹入。
在一些示例中，在垂直于所述衬底的方向上，所述第二数据线、所述第三数据线分别与所述彩膜层至少部分重叠。
在一些示例中，所述像素单元还包括第四子像素，所述第四子像素配置为发白光，所述每个数据线组还包括与所述第四子像素连接的第四数据线；
在垂直于衬底基板的方向上，所述第四数据线与所述彩膜层不重叠。
在一些示例中，所述多个像素行还包括第二像素行，所述第二像素行与所述第一像素行在所述第一方向上直接相邻，所述第二像素行包括沿所述第二方向依次排列的第五子像素、第六子像素和第七子像素，所述第五子像素 与所述第一子像素位于同一像素列，所述第六子像素与所述第二子像素位于同一像素列，所述第七子像素与所述第三子像素位于同一像素列。
在一些示例中，所述第一子像素对应的彩膜部具有靠近所述第五子像素的侧边，所述侧边与所述第二方向平行。
在一些示例中，所述显示基板还包括沿所述第二方向延伸的第二扫描线，所述第二扫描线与所述第五子像素、第六子像素及第七子像素中的第三晶体管的栅极电连接以提供所述第二控制信号。
在一些示例中，所述第二扫描线包括交替连接的第一部分和第二部分，所述第二部分为环状结构。
在一些示例中，在垂直于所述衬底基板的方向上，所述多条第一信号线与所述第二扫描线的第二部分重叠从而定义出沿所述第二方向依次布置的多个第二镂空区。
在一些示例中，所述第一导电结构为所述多条第一信号线之一，所述第一表面微结构和所述第二表面微结构位于所述第一信号线上，且所述第一表面微结构与所述第一信号线所对应的第二镂空区在垂直于所述衬底基板的方向上至少部分重叠。
在一些示例中，在垂直于所述衬底基板的方向上，所述第一子像素对应的彩膜部与所述多个第二镂空区中的一个第二镂空区重叠且具有第三重叠面积，所述第二子像素对应的彩膜部与所述多个第二镂空区中的另一个第二镂空区重叠且具有第四重叠面积，所述第三子像素对应的彩膜部与所述多个第二镂空区中的又一个第二镂空区重叠且具有第五重叠面积；所述第三重叠面积、所述第四重叠面积和所述第五重叠面积均不相同。
在一些示例中，所述第三晶体管的第二极通过第四过孔与沿所述第二方向延伸的检测部电连接，所述检测部与沿所述第一方向延伸的检测线电连接，从而所述第三晶体管的第二极通过所述检测部和所述所述检测线与所述检测电路连接。
在一些示例中，所述第一导电结构为所述第三晶体管的第二极，所述第一表面微结构和所述第二表面微结构位于所述第三晶体管的第二极上，且所述第一表面微结构与所述第四过孔在垂直于所述衬底基板的方向上至少部分重叠。
在一些示例中，所述第三晶体管的有源层包括第一极接触区、第二极接触区以及位于所述第一极接触区和所述第二极接触区之间的沟道区，所述第三晶体管的第一极通过第五过孔与所述第三晶体管的第一极接触区电连接。
在一些示例中，所述第一导电结构为所述第三晶体管的第一极，所述第一表面微结构和所述第二表面微结构位于所述第三晶体管的第一极上，且所述第一表面微结构与所述第五过孔在垂直于所述衬底基板的方向上至少部分重叠。
本公开至少一实施例还提供一种显示基板，包括衬底基板和位于所述衬底基板上的第一导电结构，所述第一导电结构包括背离所述衬底基板的第一表面和第二表面，所述第一表面和所述第二表面的材料相同；所述第一表面上设置有第一表面微结构，所述第二表面上设置有第二表面微结构；所述第一表面微结构具有与所述衬底基板垂直的第一截面，所述第二表面微结构具有与所述衬底基板垂直的第二截面；所述第一表面微结构在所述第一截面上具有第一端点和第二端点，所述第二表面微结构在所述第二截面上具有第三端点和第四端点；所述第一端点和所述第二端点的连线的中点与所述第三端点和所述第四端点的连线的中点相对于所述衬底基板的板面的距离不同。
在一些示例中，所述第一导电结构在所述第一表面微结构处的最小厚度小于所述第一导电结构的平均厚度且大于所述第一导电结构的平均厚度的3/5。
在一些示例中，所述第一导电结构还包括靠近所述衬底基板的第三表面和第四表面，在垂直于所述衬底基板的方向上，所述第一表面微结构与所述第三表面至少部分重叠，所述第二表面微结构与所述第四表面至少部分重叠。
在一些示例中，所述第三表面和所述第四表面的至少之一为平坦表面。
在一些示例中，所述第一表面微结构在所述第三表面上的正投影的面积小于所述第一表面微结构的表面积；所述第二表面微结构在所述第四表面上的正投影的面积小于所述第二表面微结构的表面积。
在一些示例中，所述第一表面微结构在所述第一截面上还具有位于所述第一端点和所述第二端点之间的第一中间点，所述第二表面微结构在所述第二截面上还具有位于所述第三端点和所述第四端点之间的第二中间点；所述第一中间点与所述第三表面的距离和所述第一端点及第二端点与所述第三表 面的距离均不相等，所述第二中间点与所述第四表面的距离和所述第三端点及所述第四端点与所述第四表面的距离均不相等。
在一些示例中，所述第一表面与所述衬底基板的板面具有第一夹角，所述第二表面与所述衬底基板的板面具有第二夹角，所述第一夹角与所述第二夹角不同。
在一些示例中，所述第一夹角大于0度，所述第二夹角等于0。
在一些示例中，所述显示基板还包括位于所述第一导电结构靠近所述衬底基板一侧的第一绝缘层，所述第一绝缘层包括分别与所述第一导电结构的第三表面和第四表面分别直接接触的第一部分和第二部分，所述第一部分的最小厚度小于所述第二部分的最小厚度。
在一些示例中，所述显示基板还包括位于所述第一绝缘层靠近所述衬底基板一侧的第二导电结构，所述第一绝缘层的第一部分包覆所述第二导电结构的至少部分。
在一些示例中，在垂直于衬底基板的方向上，所述第一表面微结构与所述第二导电结构不重叠。
在一些示例中，所述第一导电结构通过贯穿所述第一绝缘层的第一过孔与所述第二导电结构电连接；在垂直于所述衬底基板的方向上，所述第一表面微结构与所述第一过孔的至少部分重叠。
在一些示例中，所述第一绝缘层包括层叠设置的第一子层和第二子层，所述第二子层相较于所述第一子层远离所述衬底基板；所述第一子层包括被所述第一过孔暴露的第一侧面，所述第二子层包括被所述第一过孔暴露的第二侧面，所述第一侧面与所述第二侧面中的至少之一与所述第一导电结构的第三表面直接接触。
在一些示例中，所述第一侧面与所述衬底基板的夹角大于所述第二侧面与所述衬底基板的夹角。
在一些示例中，所述第二子层的致密度高于所述第一子层。
在一些示例中，所述第一表面的氧含量高于所述第三表面的氧含量。
本公开至少一实施例还提供一种显示装置，包括如上任一实施例提供的显示基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1A为本公开至少一实施例提供的显示基板的示意图之一；
图1B为本公开至少一实施例提供的显示基板的示意图之二；
图2A为本公开至少一实施例提供的显示基板的示意图之三；
图2B为本公开至少一实施例提供的显示基板中的像素电路图之一；
图2C为本公开至少一实施例提供的显示基板中的像素电路图之二；
图2D-图2F为本公开实施例提供的像素电路的驱动方法的信号时序图；
图3A为本公开至少一实施例提供的一种显示基板的示意图之四；
图3B为图3A沿剖面线I-I’的剖视图；
图3C-3E为本公开另一些实施例提供的显示基板的示意图；
图4A为本公开至少一实施例提供的显示基板中的第一导电层的平面示意图；
图4B为本公开至少一实施例提供的显示基板中的半导体层的平面示意图；
图4C为本公开至少一实施例提供的显示基板中的第二导电层的平面示意图；
图4D为本公开至少一实施例提供的显示基板中的第三导电层的平面示意图；
图5A为本公开至少一实施例提供的显示面板的示意图之一；
图5B为本公开至少一实施例提供的显示面板的示意图之二；以及
图6为本公开至少一实施例提供的显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造 性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示面板的朝向轻薄化发展，尤其是应用于大尺寸显示应用中，显示面板容易因外界应力而发生不良，例如在制作或使用过程中，显示面板中的信号线容易在外界应力作用下发生断裂，造成面板失效。
本公开至少一实施例提供一种显示基板，包括衬底基板及位于所述衬底基板上的第一导电结构，所述第一导电结构包括背离所述衬底基板的第一表面和第二表面，所述第一表面和所述第二表面的材料相同；所述第一表面与所述衬底基板的板面具有第一夹角，所述第二表面与所述衬底基板的板面具有第二夹角，所述第一夹角与所述第二夹角不同；所述第一表面上设置有第一表面微结构，所述第二表面上设置有第二表面微结构；所述第一导电结构还包括靠近所述衬底基板的第三表面和第四表面，所述第三表面与所述第一表面相对，所述第四表面与所述第二表面相对；所述第一表面微结构在第一投影面上具有第一截面，所述第一投影面垂直于所述衬底基板的板面；所述第一截面在所述第三表面具有第一正投影，所述第一正投影的长度小于所述第一截面的长度；所述第二表面微结构在所述第一投影面上具有第二截面，所述第二截面在所述第四表面上具有第二正投影，所述第二正投影的长度小于所述第二截面的长度。
本公开实施例提供的显示基板通过在第一导电结构的第一表面和第二表面分别设置第一表面微结构和第二表面微结构，从而可以使得该第一导电结 构在不同的角度或不同的方向上得到应力的释放，避免应力集中而导致面板失效。
本公开实施例中的第一表面微结构和第二表面微结构可以实现为多种具体结构，本公开对此不作限制。例如该第一应力结构和第二表面微结构为凹槽、凸起或者贯穿孔，这些结构可以有效增大该导电结构的表面积，从而有助于释放应力。
图1A示出了本公开至少一实施例提供的显示基板10的示意图，如图1A所示，该显示基板10包括位于衬底基板101上的第一导电结构110，该第一导电结构110包括背离衬底基板101的第一表面111和第二表面112，该第一表面111与衬底基板101的板面具有第一夹角α，该第二表面112与衬底基板101的板面具有第二夹角，该第一夹角与第二夹角不同。例如，该第一夹角α大于0，也即第一表面111为斜面；例如，该第二夹角为0，也即该第二表面112与衬底基板的板面平行。该第一表面111上设置有第一表面微结构11，该第二表面112上设置有第二表面微结构12。
例如，该第一表面微结构11在该第一表面111上的正投影的最大尺寸大于该第二表面微结构12在该第二表面112上的正投影的最大尺寸。例如，该第一表面微结构11在垂直于该第一表面111的方向上的最大尺寸大于该第二表面微结构12在垂直于第二表面112的方向上的最大尺寸。由于第一表面111较第二表面112相对于衬底基板更为倾斜，应力更为集中，因此将该第一表面微结构11的尺寸设置得较大有助于应力释放更加均匀。
例如，该第一表面微结构11在该第一表面111上的正投影的最大尺寸为0.15-0.35微米，例如为0.22-0.28微米；在垂直于该第一表面111的方向上，该第一表面微结构11的最大尺寸范围为0.03-0.1微米，例如为0.05-0.08微米。例如，该第一导电结构的线宽范围为5-30微米。例如，该第一表面微结构11在垂直于该第一表面111的方向上的最大尺寸为该第一导电结构的平均厚度的5％-20％。
例如，该第二表面微结构12在该第二表面112上的正投影的最大尺寸为0.1-0.2微米，例如为0.12-0.15微米；在垂直于第二表面112的方向上，该第二表面微结构12的最大尺寸范围为0.02-0.08微米，例如为0.03-0.07微米。该第一导电结构的线宽范围为5-30微米。例如，该第二表面微结构12在垂 直于该第二表面112的方向上的最大尺寸为该第一导电结构的平均厚度的5％-20％。
这种设置可以使得该表面微结构可以有效释放应力的同时防止该第一导电结构由于该表面微结构的设置而出现不良。如图1A所示，该第一导电结构110还包括靠近衬底基板101的第三表面113和第四表面114，第三表面113与第一表面111相对，第四表面114与第二表面112相对。
该第一表面微结构11具有垂直于衬底基板的第一截面11a，该第二表面微结构具有垂直于衬底基板的第二截面12a。例如，如图1A所示，该第一截面11a和第二截面12a均位于纸面内。该第一截面11a在第三表面113具有第一正投影(C1C2)，该第一正投影的长度小于该第一表面微结构11在该第一截面11a上的长度，也即曲线A1A2的长度。该第二表面微结构12在第一投影面上具有第二截面12a，第二截面12a在第四表面114上具有第二正投影(D1D2)，该第二正投影的长度小于该第二表面微结构12在该第二截面12a上的长度，也即曲线B1B2的长度。
该曲线A1A2或B1B2可以有效增大该第一表面微结构11或第二表面微结构12的表面积，从而提高该第一表面微结构11和第二表面微结构12的应力释放能力。例如，该曲线A1A2和/或曲线B1B2包括弧线，从而使得应力释放更加均匀。
第一截面11a和第二截面12a均投影为线形结构(一维结构)，该线形结构与第三表面和第四表面的形状有关。当该第三表面和第四表面为平坦表面时，该第一正投影和第二正投影分别为直线，如图1A所示；当该第三表面和第四表面为曲面时，该第一正投影和第二正投影分别为曲线。
例如，需要说明的是，当投影面为曲面时，某结构在该投影面上的正投影为该结构沿该投影面上的每一点的法线的方向形成在该投影面上的投影。
例如，该第三表面113和第四表面114的至少之一为平坦表面。如图1A所示，该第三表面113和第四表面114均为平坦表面。在垂直于衬底基板101的方向上，该第一表面微结构11与所述第三表面113至少部分重叠，该第二表面微结构12与该第四表面114至少部分重叠。
需要说明的是，该第三表面113和第四表面114的平坦性是相对于该第一表面微结构11或第二表面微结构12的尺度而言的，该第三表面113和第 四表面114的平坦性的判断尺度应该与该第一表面微结构11或第二表面微结构12的尺度在同一量级。例如，在与该第三表面113或第四表面114平行的方向上的判断尺度在0.1微米量级，在与该第三表面113或第四表面114垂直的方向上的判断尺度在0.01微米量级。例如，当该第三表面113/第四表面114中存在平行方向上尺寸达到0.1微米量级、垂直方向上尺寸达到0.01微米量级的凹陷或凸起结构，则判断该第三表面113/第四表面114为非平坦表面。
例如，该第一表面微结构11在第三表面113上的正投影的面积小于该第一表面微结构的表面积；该第二表面微结构12在该第四表面114上的正投影的面积小于该第二表面微结构的表面积。通过这种设置增大了该第一导电结构的表面积，从而有助于应力释放。
例如，沿第一导电结构的延伸方向，第一表面微结构具有第一端点、第一中间点和第二端点，第二表面微结构具有第三端点、第二中间点和第四中间点；所述第一中间点与所述第三表面的距离和所述第一端点及第二端点与所述第三表面的距离均不相等，所述第二中间点与所述第四表面的距离和所述第三端点及所述第四端点与所述第四表面的距离均不相等。
例如，如图1A所示，该第一表面微结构11和第二表面微结构12分别包括第一凹面结构和第二凹面结构，该第一凹面结构相对于该第一表面111所在的基准平面凹入，该第二凹面结构相对于该第二表面112所在的基准平面凹入。该凹面结构增大了该第一导电结构110的表面积，从而有助于应力的释放，降低该第一导电结构110受到应力断裂的风险。
如图1A所示，该第一凹面结构与第二凹面结构分别朝向不同的方向，例如该第一凹面结构的朝向可以定义为与该第一表面111垂直的方向，该第二凹面结构的朝向可以定义为与该第二表面112垂直的方向。这有助于分散该第一导电结构110上的应力，进一步降低不良风险。例如，该凹面结构的最大深度为该第一导电结构在该凹面结构所处的厚度的十分之一到五分之二。
例如，该第一导电结构在该第一表面微结构处的最小厚度小于该第一导电结构的平均厚度且大于该第一导电结构的平均厚度的3/5。
例如，如图1A所示，该第一表面微结构11在该第一截面11a上具有第 一端点A1和第二端点A2，该第二表面微结构12在该第二截面12a具有第三端点B1和第四端点B2。该第一端点A1与第二端点A2的线段的中点(未示出)与该第三端点B1和该第四端点B2的线段的中点(未示出)相对于衬底基板101的板面的距离不同。这种设置使得第一表面微结构11和第二表面微结构12相对于衬底基板具有不同的高度，有助于进一步分散第一导电结构110上的应力，降低不良风险。
例如，该第一端点A1与第二端点A2之间的距离L1大于该第三端点B1与该第四端点B2之间的距离L2。例如，该第一凹面结构在垂直于该第一表面111的方向上的最大尺寸大于该第二凹面结构在垂直于第二表面112的方向上的最大尺寸。
例如，该第一端点A1与第二端点A2之间的距离L1和该第三端点B1与该第四端点B2之间的距离L2分别大于0.1微米小于1微米。
例如，该第一端点A1与第二端点A2之间的距离L1大于该第三端点B1与该第四端点B2之间的距离L2；也即，位于斜面上的第一表面微结构长度更长。
例如，该第一端点A1与第二端点A2之间的距离L1为0.15-0.35微米，例如为0.22-0.28微米；例如，该第一凹面结构在垂直于该第一表面111的方向上的最大尺寸为0.03-0.1微米，例如为0.05-0.08微米。在该尺寸范围内，既保证了导电结构不至于断裂，又可以充分释放应力。
例如，该第三端点B1与该第四端点B2之间的距离L2为0.1-0.2微米，例如为0.12-0.15微米；例如，该第二凹面结构在垂直于第二表面112的方向上的最大尺寸范围为0.02-0.08微米，例如为0.03-0.07微米。
由于第一表面111较第二表面112相对于衬底基板更为倾斜，应力更为集中，因此将该第一凹陷结构的尺寸设置得较大有助于应力释放更加均匀。此外没通过将第一凹面结构和第二凹面结构进行上述尺寸的设置，既保证了导电结构不至于断裂，又可以充分释放应力。
在至少一实施例中，如图1A所示，该第一表面微结构11在该第一截面11a上具有第一端点A1和第二端点A2，该第二表面微结构12在该第二截面12a上具有第三端点B1和第四端点B2；该第一端点A1和第二端点A2的连线的中点与该第三端点B1和第四端点B2的连线的中点相对于该衬底基板 101的板面的距离不同。
这种设置使得第一表面微结构11和第二表面微结构12相对于衬底基板具有不同的高度，有助于进一步分散第一导电结构110上的应力，降低不良风险。例如，第一表面111的粗糙度高于第三表面113的粗糙度，第二表面112的粗糙度高于第四表面114的粗糙度。这种设置可以提高该第一导电结构110与位于其上的绝缘层直接的粘附性，避免绝缘层的脱落。例如，可以通过在制作过程中对第一导电结构110远离衬底基板一侧的表面进行轻微的氧化处理来提高该表面的粗糙度，从而提高该第一表面和第二表面的粗糙度。例如，第一表面111的含氧量高于第三表面113，第二表面112的含氧量高于第四表面114。
例如，如图1A所示，该显示基板10还包括位于该第一导电结构110靠近该衬底基板101一侧的第一绝缘层103，该第一绝缘层103包括分别与该第一导电结构110的第三表面113和第四表面114分别直接接触的第一部分103a和第二部分103b，该第一部分103a的最小厚度d1小于该第二部分103b的最小厚度d2。需要说明的是，如图1A所示，此处的厚度是指该第一绝缘层103在垂直于膜层表面方向上的的尺寸。由于第三表面113为斜面，这种设置将第一绝缘层103的第一部分103进行了减薄，有助于降低第一绝缘层103的第一部分103a的爬坡难度，从而降低第一导电结构110的断裂风险。
例如，所述第一表面微结构距离所述第三表面最近的点不是该第一端点或第二端点，且与所述第一端点和所述第二端点的距离不相等。
例如，如图1A所示，该第一凹面结构包括平滑的曲面，也即该曲面的切线与衬底基板101的夹角连续变化；在远离衬底基板101的方向上，该曲面的切线与衬底基板101的夹角变化率逐渐增大，也即该第一凹面结构是不对称的，在上游(远离衬底基板一侧)的坡度角小于下游(靠近衬底基板的一侧)的坡度角。
由于上游的凹面更容易反射上方来的光线，这种设置使得该第一导电结构可以更好地反射位于该第一导电结构远离衬底基板一侧的发光元件所发出的光线，从而提高光线的利用利用率。后文会结合显示基板的具体结构对此详细描述。
例如，如图1A所示，该第二凹面结构包括平滑的曲面，该曲面例如为 对称结构，也即该曲面的切线与衬底基板101的夹角连续变化且变化率保持不变。这种设置有助于平面上应力的均匀释放。
如图1A所示，该显示基板10还包括位于第一绝缘层103靠近衬底基板一侧的第二导电结构120，例如该第一绝缘层103将该第一导电结构110与第二导电结构120间隔。例如，该第一绝缘层103形成于该第二导电结构102上，该第一绝缘层103的第一表面111因该第二导电结构102的存在而形成为斜面。
例如，在垂直于衬底基板101的方向上，该第一表面微结构11与该第二导电结构120不重叠。由于第一表面微结构11处应力较为集中，尤其集中在该第一表面微结构11的最深处，将该第一表面微结构11设置为与该第二导电结构120不重叠，降低由该第一表面微结构11处发生断裂导致的该第一导电结构110与该第二导电结构120之间的短路风险。
例如，如图1A所示，该显示基板10还包括位于第二导电结构120靠近衬底基板一侧的缓冲层102，例如该缓冲层102与衬底基板101直接接触。该缓冲层102有助于提高衬底基板101的平坦度，以及提高第二导电结构120对衬底基板101的粘附性。在衬底基板101为有机柔性基板时，该缓冲层102还可以有效隔离外界的氧气或水分从而对基板上的电路结构形成保护。
图1B为本公开另一实施例提供的显示基板的示意图，图中仅示出了第一表面微结构11。如图1B所示，第一导电结构110通过绝缘层103中的过孔130与第二导电结构120电连接，该过孔130与第一表面微结构11在垂直于衬底基板101的方向上至少部分重叠。
由于过孔处的应力较为集中，将该表面微结构11对应于该过孔130设置，可以有助于缓解过孔处的应力，降低断线风险。
如图1B所示，该第一绝缘层103包括层叠设置的第一子层131和第二子层132，第二子层132相较于第一子层131远离衬底基板101。过孔130贯穿该第一子层131和第二子层132。该第一子层131包括被该过孔130暴露的第一侧面131a，该第二子层132包括被该过孔130暴露的第二侧面132a，该第一侧面131a与该第二侧面132a中的至少之一与该第一导电结构130的第三表面133直接接触。如图1B所示，该第一侧面131a与该第一导电结构130的第三表面133直接接触。
如图1B所示，该第一侧面131a与该衬底基板101的夹角(坡度角)为β1，该第二侧面132a与衬底基板101的夹角为β2，β1小于β2。
通过这种设置，一方面可以减缓第一绝缘层103在过孔130处的坡度，从而防止过孔过于陡直所带来的断线风险，另一方面可以防止过孔过于平缓而导致过孔占用的空间过大。
例如，在制作过程中，可以采用高温沉积工艺形成该第一子层131，并采用低温沉积工艺形成该第二子层132，如此该第二子层132的致密度高于第一子层131的致密度；然后采用干法刻蚀工艺刻蚀该第一绝缘层，从而使得第一子层131的坡度角小于第二子层132的坡度角。
图2A是本公开至少一实施例提供的显示基板的框图。如图2A所示，显示基板10包括呈阵列排布的多个子像素100，例如，每个子像素100包括发光元件以及驱动该发光元件发光的像素电路。例如，该显示基板是有机发光二极管(OLED)显示基板，该发光元件为OLED。该显示基板还可以包括多条扫描线、多条数据线以用于为该多个子像素提供扫描信号(控制信号)和数据信号，从而驱动该多个子像素。根据需要，该显示基板还可以进一步包括电源线、检测线等。
该像素电路包括用于驱动发光元件发光的驱动子电路和用于检测该子像素电特性以实现外部补偿的检测子电路。本公开实施例对于该像素电路的具体结构不作限制。
图2B示出了一种用于该显示基板的一种3T1C像素电路的示意图。根据需要，该像素电路还可以进一步包括补偿电路、复位电路等，本公开的实施例对此不作限制。
请一并参照图2A和图2B，该像素电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容Cst。第二晶体管T2的第一极与存储电容Cst的第一电容电极和第一晶体管T1的栅极电连接，第二晶体管T2的第二极配置为接收数据信号GT，第二晶体管T2配置为响应于第一控制信号G1将该数据信号DT写入第一晶体管T1的栅极和存储电容Cst；第一晶体管T1的第一极与存储电容Cst的第二电容电极电连接，并配置为与发光元件的第一电极电连接，第一晶体管T1的第二极配置为接收第一电源电压V1(例如为高电源电压VDD)，第一晶体管T1配置为在第一晶体管T1的栅极的电 压的控制下控制用于驱动发光元件的电流；第三晶体管T3的第一极与第一晶体管T1的第一极以及存储电容Cst的第二电容电极电连接，第三晶体管T3的第二极配置为与检测线230连接以连到外部检测电路21，第三晶体管T3配置为响应于第二控制信号G2检测所属的子像素的电特性以实现外部补偿；该电特性例如包括第一晶体管T1的阈值电压和/或载流子迁移率，或者发光元件的阈值电压、驱动电流等。该外部检测电路21例如为包括数模转换器(DAC)和模数转换器(ADC)等的常规电路，本公开的实施例对此不作赘述。
本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。需要说明的是，在下面的描述中均以图2B中的晶体管为N型晶体管为例进行说明，然而不作为对本公开的限制。
下面结合图2D-图2F所示的信号时序图对图2B所示的像素电路的工作原理进行说明，其中图2D示出了该像素电路在显示过程的信号时序图，图2E和图2F示出了该像素电路在检测过程的信号时序图。
例如，如图2D所示，每一帧图像的显示过程包括数据写入和复位阶段1以及发光阶段2。图2C示出了每个阶段中各个信号的时序波形。该3T1C像素电路的一种工作过程包括：在数据写入和复位阶段1，第一控制信号G1和第二控制信号G2均为开启信号，第二晶体管T2和第三晶体管T3导通，数据信号DT经第二晶体管T2传输至第一晶体管T1的栅极，第一开关K1关闭，模数转换器通过检测线230及第三晶体管T3向发光元件的第一电极(例如OLED的阳极)写入复位信号，第一晶体管T1导通并产生驱动电流 将发光元件的第一电极充电至工作电压；在发光阶段2，第一控制信号G1和第二控制信号G2均为关闭信号，由于存储电容Cst的自举效应，存储电容Cst两端的电压保持不变，第一晶体管T1工作在饱和状态且电流不变，并驱动发光元件发光。
例如，图2E示出了该像素电路在进行阈值电压的检测时的信号时序图。该3T1C像素电路的一种工作过程包括：第一控制信号G1和第二控制信号G2均为开启信号，第二晶体管T2和第三晶体管T3导通，数据信号DT经第二晶体管T2传输至第一晶体管T1的栅极；第一开关K1关闭，模数转换器通过检测线230及第三晶体管T3向发光元件的第一电极(节点S)写入复位信号，第一晶体管T1导通并对节点S进行充电直至第一晶体管截止，数模转换器对检测线230上的电压取样即可得到第一晶体管T1的阈值电压。该过程例如可以在显示装置关机时进行。
例如，图2F示出了该像素电路在进行载流子迁移率的检测时的信号时序图。该3T1C像素电路的一种工作过程包括：在第一阶段，第一控制信号G1和第二控制信号G2均为开启信号，第二晶体管T2和第三晶体管T3导通，数据信号DT经第二晶体管T2传输至第一晶体管T1的栅极；第一开关K1关闭，模数转换器通过检测线230及第三晶体管T3向发光元件的第一电极(节点S)写入复位信号；在第二阶段，第一控制信号G1为关闭信号，第二控制信号G1为开启信号，第二晶体管T2关断，第三晶体管T3导通，并将第一开关K1、第二开关K2断开以将检测线230浮置；由于存储电容Cst的自举效应，存储电容Cst两端的电压保持不变，第一晶体管T1工作在饱和状态且电流不变并驱动发光元件发光，然后数模转换器对检测线230上的电压取样，并结合发光电流的大小和持续时间可以计算出第一晶体管T1中的载流子迁移率。例如，该过程可以在显示阶段之间的消隐阶段进行。
通过上述检测可以得到第一晶体管T1的电特性并实现相应的补偿算法。
例如，如图2A所示，显示基板10还可以包括数据驱动电路23和扫描驱动电路24。数据驱动电路23配置为根据需要(例如输入显示装置的图像信号)可发出数据信号，例如上述数据信号DT；每个子像素的像素电路还配置为接收该数据信号并将该数据信号施加至该第一晶体管的栅极。扫描驱动电路24配置为输出各种扫描信号，例如包括上述第一控制信号G1和第二 控制信号G2，其例如为集成电路芯片(IC)或者为直接制备在显示基板上的栅驱动电路(GOA)。
例如，显示基板10还包括控制电路22。例如，控制电路22配置为控制数据驱动电路23施加数据信号，以及控制栅极驱动电路施加扫描信号。该控制电路22的一个示例为时序控制电路(T-con)。控制电路22可以为各种形式，例如包括处理器121和存储器127，存储器121包括可执行代码，处理器121运行该可执行代码以执行上述检测方法。
例如，处理器121可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
例如，存储器127可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器121可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据，例如在上述检测方法中获取的电特性参数等。
图3A为本公开至少一个实施例提供的显示基板10的子像素的示意图，如图3A所示，该显示基板10包括衬底基板101，多个子像素100位于该衬底基板101上。多个子像素100沿第一方向D1和第二方向D2分布为像素阵列，该像素阵列包括多个像素列和多个像素行，该像素阵列的列方向为第一方向D1，行方向为第二方向D2，第一方向D1与第二方向D2交叉，例如正交。
例如，每个像素行的子像素被划分为多个像素单元，每个像素单元配置为发出全彩光。图3A中示例性地示出了一个像素单元，本公开的实施不限于此布局；图3B示出了图3A沿剖面线I-I’的剖视图。如图3A所示，该像素单元包括沿第二方向D2依次布置的第一子像素P1、第二子像素P2和第三子像素P3，该第一子像素P1、第二子像素P2和第三子像素P3分别用于发出三种基本色(RGB)的光；例如，第一子像素P1为红色子像素，第二 子像素P2为蓝色子像素，第三子像素P3为绿色子像素。
例如，该像素单元还可以包括第四子像素P4，该第四子像素P4用于发白光。例如，该第四子像素P4位于该第一子像素P1和第二子像素P2之间，然而本公开实施例对于第四子像素P4的位置不作限制。
结合参考图3A和图3B，该显示基板10包括依次设置在衬底基板101上的第一导电层501、第一绝缘层201、半导体层104、第二绝缘层202、第二导电层502、第三绝缘层203和第三导电层503。
以下将对图3A所示的显示基板10中子像素的具体结构进行说明。为了方便说明，在以下的描述中用T1g、T1s、T1d、T1a分别表示第一晶体管T1的栅极、第一极、第二极和有源层，用T2g、T2s、T2d、T2a分别表示第二晶体管T2的栅极、第一极、第二极和有源层，用T3g、T3s、T3d、T3a分别表示第三晶体管T3的栅极、第一极、第二极和有源层，用Ca、Cb和Cc分别表示存储电容Cst的第一电容电极、第二电容电极和第三电容电极。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。本公开中的“一体的结构”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
例如，结合参考图3A和图3B，该第一导电层501包括屏蔽层170，该屏蔽层170在衬底基板101上的正投影覆盖第一晶体管T1的有源层T1a在衬底基板101上的正投影。第一晶体管T1作为像素电路的驱动晶体管，其电特性的稳定对于发光元件的发光特性非常重要。该屏蔽层170为不透光层，可以避免光线从衬底基板101的背面射入第一晶体管T1的有源层而引起第一晶体管T1的阈值电压的漂移，从而避免影响与之连接的对应的发光元件的发光特性。
例如，该屏蔽层170为不透光的导电材料，例如为金属或金属合金材料。这种设置可以缓解衬底基板101由于捕获电荷所导致的背沟道现象。
例如，该半导体层104包括第一晶体管T1的有源层T1a、第二晶体管T2的有源层T2a和第三晶体管T3的有源层T3a。
例如，该半导体层104还包括该存储电容Cst的第一电容电极Ca，该第 一电容电极Ca由该半导体层104经导体化处理得到；也即第一电容电极Ca与第一晶体管T1的有源层T1a、第二晶体管的有源层T2a及所述第三晶体管的有源层T3a同层设置。
例如，该第二导电层502包括第一晶体管T1的栅极T1g、第二晶体管T2的栅极T2g和第三晶体管T3的栅极T3g。
例如，该显示基板10采用自对准工艺，利用第二导电层502作为掩膜对该半导体层104进行导体化处理(例如掺杂处理)，使得该半导体层104未被该第二导电层502覆盖的部分被导体化，从而得到该第一电容电极Ca，并使得各晶体管的有源层位于沟道区两侧的部分被导体化而形成分别第一极接触区及第二极接触区，该第一极接触区和第二极接触区分别用于与该晶体管的第一极和第二极电连接。
例如，该第三导电层503包括第一晶体管T1的第一极T1s和第二极T1d、第二晶体管T2的第一极T2s和第二极T2d以及第三晶体管T3的第一极T3s和第二极T3d。
例如，该第三导电层503还包括存储电容Cst的第二电容电极Cb。例如，如图3B所示，该第二电容电极Cb与第一晶体管T1的第二极T1d同层设置且彼此连接为一体的结构。如图3B所示，该第一电容电极Ca和第二电容电极Cb在垂直于衬底基板101的方向上彼此重叠形成存储电容Cst。
图2C示出了本公开另一实施例提供的显示基板中的像素电路图。例如，该存储电容Cst还包括第三电容电极Cc，该第三电容电极位于第一电容电极Ca远离第二电容电极Cb的一侧且与第二电容电极Cb通过图3A所示的7号过孔彼此电连接从而形成并联电容的结构，增大存储电容Cst的电容值。例如，在垂直于衬底基板101的方向上，该第三电容电极Cc、第二电容电极Cb、第一电容电极Ca三者均彼此重叠。
例如，如图3B所示，该第三电容电极Cc位于第一导电层501。例如，该屏蔽层170与该存储电容Cst的第二电容电极Cb同层设置且材料相同。例如，该屏蔽层170与该存储电容Cst的第二电容电极Cb为同一电极块。在这种情形，该屏蔽层170连接到第三晶体管T3的第一极T3s从而避免该屏蔽层因浮置而在显示操作中发生电位变化而影响晶体管的阈值电压。
例如，结合参考图3A-3B，对于每个子像素，第一晶体管T1与第二晶 体管T2沿第二方向D2排列，在该第二方向D2上并列设置。例如，在第一方向D1上，第一晶体管T1与第二晶体管T2位于第二电容电极Cb的同一侧，并与第三晶管T3位于第二电容电极Cb的相对两侧。
例如，该显示基板10还包括从第一晶体管T1的栅极T1g突出的延伸部180，该延伸部180从该第一晶体管T1的栅极T1g沿第二方向D2延伸并与该第二晶体管T2的第一极T2s在垂直于衬底基板101的方向上至少部分重叠且电连接。
如图3B所示，第二晶体管T2的第一极T2s通过过孔800(本公开第二过孔的一个示例)与其第一极接触区Ta1、该延伸部180(也即该第一晶体管T1的栅极T1g)以及该第一电容电极Ca电连接。该第二晶体管T2的第一极T2s通过一个过孔与该三部分电连接，比起通过多个过孔与该三部分分别进行电连接，可以减小占用的版图空间，提高布线密度，从而提高像素密度。如图3B所示，该过孔800形成于该第三绝缘层203中，该延伸部180与第二绝缘层202位于该延伸部180下方的部分位于该过孔800中将该过孔800间隔为两个凹槽部分，即第一凹槽V1和第二凹槽V2，该第二凹槽V2相对于第一凹槽V1更靠近第三晶体管T3。该第二晶体管T2的第一极T2s填充在该过孔800中并覆盖该第一凹槽V1和第二凹槽V2且具有相对于衬底基板平行或倾斜的表面。
结合参照图3A-3B，该第二晶体管T2的第一极T2s沿第一方向D1延伸，跨越该延伸部180(与该延伸部180交叉)并通过该过孔800(也即图3A中的2号过孔)与第一电容电极Ca电连接。例如，该延伸部180具有在第一方向上相对的第一侧面和第二侧面；例如，该过孔800沿第一方向D1延伸，并暴露出该延伸部180的表面以及该第一侧面和第二侧面的至少部分。该第二晶体管T2的第一极T2s包括第一部分S1、第二部分S2和第三部分S3，该第一部分S1、第二部分S2和第三部分S3在第一方向D1上依次连接。该第二部分S2与该延伸部180重叠，该第一部分S1和第三部分S3在第一方向D1上分别位于该第二部分S2的两侧，该第三部分S3位于该第二部分S2靠近该第三晶体管T3的一侧；该第一部分S1填充该第一凹槽V1，该第三部分S3填充该第二凹槽V2。例如，通过该过孔800，该第一部分S1与第二晶体管T2的有源层T2a的第一极接触区T2a1电连接，该第二部分S2与该 延伸部180直接接触电连接，这有助于增大接触面积降低电阻；该第三部分S3与第一电容电极Ca电连接。
例如，第二晶体管T2的第一极T2s沿第一方向延伸，并通过该过孔800包覆该延伸部180的两个侧面，例如，该第一部分S1覆盖第一侧面，该第三部分S3覆盖该第二侧面。这样使得第二晶体管T2的第一极T2s与该延伸部180具有较大的接触面积，从而降低二者的接触电阻。
例如，如图3B所示，该显示基板10还可以包括连接部720，该连接部720与该延伸部180在垂直于衬底基板101的方向重叠且与该第一电容电极Ca同层的连接部720，该连接部720将该第一电容电极Ca与第二晶体管T2的第一极接触区T2a1连接为一体的结构。该连接部720由于被该延伸部180遮挡而为未被导体化的部分。当该第二晶体管T2导通，将数据信号从该第二晶体管T2的第二极T2d传输至其第一极T2s及第一晶体管T1的栅极T1g时，该连接部720在其上方的延伸部180及该第二晶体管T2的第一极T2s中的数据信号的作用下导通，从而可以将该第二晶体管T2的第一极T2s与该第一电容电极Ca电连接。这样就在该第二晶体管T2的第一极T2s与该第一电容电极Ca之间形成了双通道结构，有助于降低通道电阻。
此外，如图3B所示，该连接部720将该第一电容电极Ca与该第二晶体管T2的第一极接触区T2a1连接为一体的结构，从而将该第二晶体管T2的第一极接触区T2a1也纳入该第一电容电极Ca范围内。这样可以使得该第一电容电极Ca具有较大的面积，并且与该第三电容电极Cc具有较大的重叠面积，从而增大该存储电容Cst的容值。
例如，如3B所示，该第三电容电极Cc可以与该第二晶体管T2的第一极接触区T2a1在垂直于衬底基板的方向至少部分重叠，以与该第一电容电极具有更大的重叠面积从而提高存储电容Cst的容值。例如，该第三电容电极Cc与该第二晶体管T2的沟道区T2a0在垂直于衬底基板101的方向上不重叠。这是为了避免该第三电容电极Cc上的电位对于该第二晶体管T2的工作造成不利影响，例如防止该第三电容电极Cc上的电位对该第二晶体管T2的沟道区T2a0进行作用而导致该第二晶体管T2不能正常关闭、漏电流较大等问题。
例如，如图3A所示，该显示基板10还可以包括与每个像素行对应连接 的第一扫描线150和第二扫描线160。例如，该第一扫描线150和第二扫描线160位于第二导电层502中且沿第二方向D2延伸。
例如，该第一扫描线150与对应的一行子像素的第二晶体管T2的栅极T2g为一体的结构，该第二扫描线160分别与对应的一行子像素的第三晶体管T3的栅极T3g为一体的结构。
例如，如图3A所示，对于每行子像素，沿第一方向D1，所对应的第一扫描线150与第二扫描线160分别位于该行子像素中的第一晶体管T1的两侧。
例如，每条第一扫描线150包括交替连接的第一部分151和第二部分152，第二部分152为环状结构，且在第一方向上D1，该第二部分152的尺寸大于第一部分151。类似地，每条第二扫描线160包括交替连接的第一部分161和第二部分162，第二部分162为环状结构，且在第一方向上D1，该第二部分162的尺寸大于第一部分161。
例如，所述显示基板包括多个第一表面微结构和多个第二表面微结构，所述多个第一表面微结构和多个第二表面微结构中的一部分与所述第一扫描线的第一部分在垂直于衬底基板的方向上重叠，所述多个第一表面微结构和多个第二表面微结构的另一部分与所述第一扫描线的第二部分在垂直于所述衬底基板的方向上重叠；在垂直于衬底基板的方向上，与所述第一扫描线的第二部分重叠的第一表面微结构和第二表面微结构的分布密度大于与所述第一扫描线的第一部分的重叠的第一表面微结构和第二表面微结构的分布密度。
由于具有环状结构的第二部分的应力较具有条状结构的第一部分的应力更集中，通过上述设置可以提高应力释放效果。
例如，所述第一重叠面积大于所述多个第一表面微结构或所述第二表面微结构中的每个在所述衬底基板的正投影的面积；所述第二重叠面积大于所述多个第一表面微结构或所述第二表面微结构中的每个在所述衬底基板的正投影的面积。
释放结构面积太大，容易出现应力的过释放，导致面板不良，当表面微结构的面积小于该重叠面积的时候，可以使得在该区域内的应力得到充分释放，保证该区域面板的稳定性。
需要说明的是，本公开中表面微结构的分布密度是指基板的单位面积内所分布的表面微结构的个数。
例如，该显示基板10还包括沿第一方向D1延伸的多条信号线，例如，该信号线可以是数据线、电源线或辅助电极线等。如图3A所示，每个第二部分152均与至少一条数据线在垂直于衬底基板101的方向上交叉，从而定义出沿第二方向D2布置的多个第一镂空区H1；每个第二部分162均与至少一条数据线在垂直于衬底基板101的方向上交叉，从而定义出沿第二方向D2布置的多个第二镂空区H2。
通过将扫描线与信号线交叉的部分设置为环状结构，也即双通道结构，可以有效提高器件的良率。例如，信号线交叉的位置容易因寄生电容发生静电击穿而导致短路不良，在检测过程中当检测到该环状结构的一个通道发生短路不良，可以将该通道切除(例如通过激光切割)，电路结构仍可以通过另一个通道进行正常工作。
例如，如图3A所示，该多条信号线包括多条数据线DL，该多条数据线DL与该子像素阵列中的每一列子像素一一对应连接以为子像素提供数据信号。对于一个像素行，该多条数据线被划分为与该像素行中的多个像素单元一一对应的多个数据线组，如图3A所示，每个数据线组包括与第一子像素P1连接的第一数据线DL1、与第二子像素P2连接的第二数据线DL2、与第三子像素P3连接的第三数据线DL3以及与第四子像素P4连接的第四数据线DL4。对于每个像素单元，与该像素单元对应连接的数据线DL1-DL4均位于第一子像素P1与第三子像素P3之间。这种设置可以为检测线和电源线的设置提供空间。
例如，如图2A所示，显示基板10还包括沿第一方向D1延伸的多条检测线230，该检测线230用于与子像素100中检测子电路(如第三晶体管T3)连接，并将该检测子电路连接到外部检测电路。例如，每条检测线230与多条数据线DL中的任意一条之间间隔有至少一列所述子像素；也即，该检测线230不与任一数据线DL直接相邻。例如，如图2A所示，对于每个像素单元，第一数据线DL1与第四数据线DL4位于第一子像素P1与第四子像素P4之间，第二数据线DL2与第三数据线DL3位于第二子像素P2与第三子像素P3之间，检测线230位于第四子像素P4与第二子像素P2之间。
通过这种设置，避免数据线因与该检测线直接相邻而引起阻容负载造成数据线上的信号延迟，进一步避免了该延迟导致的显示不均等不良问题。此外，由于数据线DL上传输的信号通常为高频信号，将检测线230与数据线DL设置为不直接相邻可以避免检测线230在外部补偿充电采样过程中收到高频信号串扰从而影响采样精度。
例如，如图3A所示，该像素单元中的四个子像素共用一条检测线230，该检测线230通过沿第二方向D2延伸的检测部231分别与四个子像素中的第三晶体管T3的第二极T3d电连接。该检测线230通过过孔与检测部231电连接，该检测部231通过10号过孔与第三晶体管T3的第二极T3d电连接。该第三晶体管T3的第一极T3s通过6号过孔与第三晶体管T3的第一极接触区T3a1电连接，第三晶体管T3的第二极T3d通过5号过孔与第三晶体管T3的第二极接触区T3a2电连接。
例如，该第三晶体管T3与第二电容电极Cb同层设置且连接为一体的结构。
例如，如图3A所示，该显示基板10还包括沿第一方向D1延伸的多条电源线240，该多条电源线240配置为为多个子像素提供第一电源电压，该电源电压例如为高电源电压VDD。该电源线240例如位于第三导电层503中。如图3A所示，该多条电源线240的每条与多条数据线中的任意一条之间间隔有至少一个像素列；也即，电源线240不与任一数据线DL直接相邻。通过这种设置，避免数据线因与电源线直接相邻而引起阻容负载造成数据线上的信号延迟，进一步避免了该延迟导致的色偏、显示不均等不良问题。
例如，任一电源线240与检测部231在垂直于衬底基板101的方向上不交叠，也即该电源线240对应于相邻的检测部231的间隔处设置。这种设置方式降低了信号线的交叠从而有效降低信号线之间的寄生电容以及由此引起的信号延迟。
例如，如图3B所示，该电源线240通过3号过孔与直接相邻的子像素(例如第一子像素P1)的第一晶体管T1的第二极T1d电连接，例如该电源线与该第一晶体管T1的第二极T1d为一体的结构。例如，该电源线240通过连接电极241与和该电源线240不直接相邻的子像素的第一晶体管T1的第二极T1d电连接。例如，该连接电极241通过11号过孔与第二子像素或 第四子像素的第一晶体管T1的第二极T1d电连接。
例如，所述显示基板包括多个第一表面微结构11和多个第二表面微结构12，所述多个第一表面微结构和多个第二表面微结构中的一部分分布在所述多条数据线DL上，所述多个第一表面微结构和多个第二表面微结构的另一部分分布在所述多条电源线上；所述多个第一表面微结构和所述多个第二表面微结构在所述多条数据线上的分布密度大于所述多个第一表面微结构和所述多个第二表面微结构在所述多条电源线上的分布密度。
由于数据线上加载的动态电压，对应力的敏感性更高，因此将数据线上的表面微结构的分布密度设置得更高，有助于提高面板的稳定性。
例如，该连接电极241与检测部231均位于第一导电层501中。
例如，在垂直于衬底基板的方向上，连接电极241与检测线230不重叠。如图3B所示，该连接电极241在对应检测线230的位置断开从而不与检测线230重叠，这样可以降低寄生电容。
例如，本公开中的第一表面微结构和第二表面微结构可以设置在上述本公开提供的显示基板中的任意信号线或任意导电结构中，例如，设置在该信号线或导电结构对应过孔处的部分，以帮助释放该信号线或导电结构在该过孔处的应力，从而降低断线风险。
例如，该第一表面微结构和第二表面微结构之间的距离小于一个子像素的尺寸的1/10。这种设置可以有效释放像素尺寸范围内的应力。
例如，所述第一表面微结构在所述衬底基板上的正投影与所述第二表面微结构在所述衬底基板上的正投影之间的中心距离在所述第一方向和所述第二方向的分量分别小于所述多个子像素的每个在所述第一方向和所述第二方向的平均尺寸。
例如，一个子像素的大小由与其直接相邻且分别位于两侧的信号线所限定。例如，如图3B所示，每个子像素在第一方向上的平均尺寸(长度)为与其对应的第一扫描线150和第二扫描线160的平均间距，每个子像素在第二方向上的平均尺寸(宽度)为其对应的数据线DL和检测线230/电源线240的平均间距。
例如，一个子像素的长度和宽度分别为100-500微米，该第一表面微结构11和第二表面微结构12在所述衬底基板上的正投影之间的中心距离为 5-20微米。
例如，该第一表面微结构11与第二表面微结构12沿第一方向D1排列，例如位于沿第一方向D1延伸的信号线(如数据线、电源线、检测线等)上。例如，如图3A所示，第一表面微结构11和第二表面微结构12位于同一电源线240上，第一表面微结构11包括第一凹面结构，第二表面微结构12包括第二凹面结构，该第一凹面结构与第二凹面结构朝向颜色相同的子像素，例如，该第一凹面结构和该第二凹面结构的法线在衬底基板上的正投影与第一方向D1的夹角均为锐角，也即指向同一列子像素。
例如，每个像素列的子像素(也即位于同一列的子像素)发相同颜色的光。当发光元件发光的光斜射入该凹面结构上时，该凹面结构可以将该光线发生回发光元件(例如发光元件的阴极)，上述设置可以使得凹面结构将光线发射回与该光线颜色相同的子像素，从而避免不同延伸的子像素的光线的串色。
以下以该第二晶体管T2的第一极T2s作为本公开的第一导电结构为例对本公开提供的显示基板进行示例性说明，然而本公开实施例并不限于此。
例如，第一表面微结构11位于该第二晶体管T2的第二极T2的与衬底基板倾斜的表面上，例如位于该第二晶体管T2的第二极T2的第一部分、第二部分、第三部分的至少一个上，该第二表面微结构12位于该第二晶体管T2的第二极T2s的与衬底基板平行的表面上，例如位于该第二晶体管T2的第二极T2的第一部分、第二部分、第三部分的至少一个上。
例如，如图3A-3B，该第一表面微结构11位于该第二晶体管T2的第二极T2的第三部分S3，该第三部分S3由于填充到过孔800(或者第一第二凹槽V2中)中而具有相对于成基板的两个斜面(本公开第一导电结构的第一表面的一个示例)，该第一表面结构11位于两个斜面的至少之一上。例如，如图3B所示，该第一表面微结构11位于靠近第三晶体管T3的斜面上。
例如，在另一些示例中，第一表面微结构11可以位于该第二晶体管T2的第二极T2的第一部分S1，该第一部分S1由于填充到过孔800中而具有相对于衬底基板的斜面(本公开第一导电结构的第一表面的一个示例)，该第一表面微结构11位于该斜面上。
例如，如图3B所示，该第二表面微结构位于该第三部分S3填充入该第 二凹槽且形成与该衬底基板的板面平行的表面的部分上。由于导电结构在凹槽中所受的应力较大，在该第三部分S3填充入凹槽的部分设置表面微结构可有助于应力释放。
在另一些示例中，该第二晶体管T2的第二极T2的第一部分S1、第二部分S2和第三部分S3的与衬底基板的板面平行的表面(本公开第一导电结构的第二表面的若干示例)上分别设置有该第二表面微结构12。例如，该第二晶体管T2的第二极T2的第一部分S1包括位于该过孔800中与该半导体层104直接接触的部分，该部分的上表面可以设置该第二表面微结构12以缓解应力。
需要说明的是，为了方便示意，图3B中用空白示出了该第一表面微结构11和第二表面微结构12的凹陷结构，在实际结构中，该凹陷结构可能至少被周围的绝缘层填充，例如全部被该第四绝缘层204填充。
由于过孔800的尺寸相对较大，在该第二晶体管T2的第二极T2s上设置该第一表面微结构11和第二表面微结构12可以有效缓解该第二晶体管T2的第二极T2s上的应力，从而降低不良风险。
例如，该第一表面微结构在第一方向上的尺寸小于该第三部分S3沿该第一方向的最大尺寸的十分之一。
例如，该第一表面微结构11或第二表面微结构12在第一方向D1上的尺寸(也即图3B中沿剖面线I-I’方向的尺寸)小于该过孔800在衬底基板101上的正投影在第一方向D1上的最大尺寸的十分之一，例如为2％-5％。
例如，参考图3A-3B，每个子像素还包括发光元件125，例如，该发光元件为有机发光二极管，包括依次层叠设置的第一电极123、发光层124和第二电极122。例如，该发光元件125为顶发射结构，第一电极具有反射性而第二电极122具有透射性或半透射性。例如，第一电极为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极122为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，该显示基板10还包括位于第三导电层503与发光元件的第一电极123之间的第四绝缘层204和第五绝缘层205。例如，该第四绝缘层204为钝化层，例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、 硅的氮化物或硅的氮氧化物；该第五绝缘层205为有机绝缘材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。例如，第五绝缘层205为平坦化层。
例如，显示基板10还包括位于发光元件125的第一电极123上的像素界定层206，该像素界定层206为有机绝缘材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。该发光元件125的第一电极123通过过孔700(也即图3A中的8号过孔)与第一晶体管T1的第一极T1s以及第二电容电极Cb电连接，该过孔700例如贯穿第四绝缘层204和第五绝缘层205。
例如，如图3A-3B所示，发光元件的第一电极123包括在第一方向D1上依次连接的第一电极部123a、第二电极部123b和第三电极部123c，该第一电极部123a用于与对应的第一晶体管T1的第一极T1s电连接且在垂直于衬底基板101的方向上与对应的第一晶体管T1的第一极T1s重叠。该第三电极部123c用于与发光层124直接接触，与发光元件的开口区(未示出)在垂直于衬底基板的方向上重叠，也即该第三电极部123c对应于该发光元件的有效发光区域；与过孔700在垂直于衬底基板的方向上不重叠，从而避免过孔700处界面对发光材料的发光效率造成不良影响。该第二电极部123b将该第一电极部123a与第三电极部123c连接。例如，发光元件的开口区为像素界定层206中与该发光元件对应设置的开口区，该开口区暴露出该发光元件的第一电极123，并容纳该发光元件的发光层的至少部分。
如图3A所示，发光元件的第一电极123的第二电极部123b在第二方向D2的平均尺寸小于第一电极部123a在第二方向D2的平均尺寸，也小于第三电极部123c在第二方向D2的平均尺寸。
例如，所述第一电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺寸之和小于所述第三电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺寸之和；所述第二电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺寸之和小于所述第三电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺寸之和。
例如，显示基板包括多个第一表面微结构11和多个第二表面微结构12，所述多个第一表面微结构和多个第二表面微结构中的一部分与所述第一电极 部在垂直于衬底基板的方向上重叠，所述多个第一表面微结构和多个第二表面微结构的另一部分与所述第三电极部在垂直于所述衬底基板的方向上重叠；与所述第一电极部重叠的第一表面微结构和第二表面微结构的分布密度大于与所述第三电极部的重叠的第一表面微结构和第二表面微结构的分布密度。
由于第一电极部靠近像素驱动区，例如与第一晶体管T1在垂直于衬底基板的方向上至少部分重叠，而像素驱动区应力更为集中，通过上述设置可以对驱动区的应力进行有效释放，提高显示基板的性能。
如图3A所示，在第一方向D1上，第一扫描线150位于第一电极部123a与第三电极部123c之间，该第二电极部123b与第一扫描线150在垂直于衬底基板的方向上重叠，降低该第二电极部123b在第二方向D2上的尺寸有助于减小该第二电极部123b与第一扫描线150的交叠面积从而降低寄生电容。
例如，该第二电极部123b与第一扫描线150的第一部分151在垂直于衬底基板101的方向上重叠，并与第一扫描线150的第二部分152在垂直于衬底基板101的方向上不重叠。
由于第一扫描线150的第二部分152与沿第一方向D1的信号线(如电源线、检测线、数据线等)重叠，因此该第二部分152容易出现短路等不良，需要在修复过程中进行修复。将该发光元件的第一电极设置为与该第一扫描线150的第二部分152不重叠，可以降低第二部分152处的修复难度。
如图3A所示，该第一子像素P1具有在第二方向D2上相对的第一侧和第二侧，该第一侧设置有电源线240，该第二侧设置有数据线DL(第一数据线DL1和第四数据线DL4)，该第二电极部123b相对于该第一电极部123a和第三电极部123c向第一侧凹入，也即向远离第二侧的方向凹入；也即该第二电极部123b距离电源线比距离数据线近。
由于电源线240上传输的是恒定电压，数据线DL上传输的是高频信号，将该第二电极部123b设置得更靠近电源线可以防止数据线DL上的高频信号对发光元件的第一电极上的电位造成影响，从而影响显示灰阶。
对于第二子像素、第三子像素和第四子像素也有类似的设置。例如，如图3A所示，该第二子像素P2与第三子像素P3直接相邻，该第三子像素P3具有在第二方向上相对的第一侧与第二侧，第二数据线DL2和第三数据线 DL3位于该第三子像素P3的第一侧且位于第二子像素P2与第三子像素P3之间，检测线230位于该第三子像素P3的第二侧。第三子像素的发光元件的第一电极的第二电极部相对于其第一电极部和其第三电极部向远离第三子像素的第二侧的方向凹入，也即该第二电极部距离检测线230比距离数据线近。
由于检测线230上传输的是低频检测信号，数据线DL上传输的是高频信号，将该第二电极部设置得更靠近检测线可以防止数据线DL上的高频信号对发光元件的第一电极上的电位造成影响，从而影响显示灰阶。
例如，每个子像素中的发光元件OLED均配置为发白光，该显示基板10还包括彩膜层，白光透过彩膜层射出实现全彩显示。例如，该发光层124可以通过Open Mask结合蒸镀工艺整面形成，这样例如避免使用精细金属掩模(Fine Metal Mask，FMM)对发光层进行构图工艺，从而避免了FMM精度有限而限制了显示基板的分辨率。
例如，本公开的一些实施例提供的显示基板10的发光元件可以采用底发射结构。例如，如图3A-3B所示，彩膜层位于发光元件的第一电极靠近衬底基板101的一侧，例如位于第四绝缘层204和第五绝缘层205之间。彩膜层包括分别对应于除白色子像素之外多个子像素的多个彩膜部190，也即该第一子像素P1、第二子像素P2和第三子像素P3分别对应一个彩膜部190，该第一子像素P1、第二子像素P2和第三子像素P3的发光元件发出的光经过该彩膜部90射出形成显示光。白色子像素的光线不需要经过彩膜层，因此第四子像素P4并不对应设置彩膜部。
例如，相邻彩膜部在垂直于衬底基板的方向上有交叠，对应交叠处设置有第一表面微结构或第二表面微结构。由于彩膜交叠导致应力不均匀，表面微结构可以对该区域应力进行有效释放。
例如，在垂直于所述衬底基板的方向上，所述第一子像素对应的彩膜部、所述第二子像素对应的彩膜部和所述第二表面微结构在垂直于衬底基板的方向上重叠。
结合参考图3A-3B，每个彩膜部190与对应的子像素的发光元件的第一电极的第一电极部123a重叠，并与该发光元件的第一电极的第三电极部123c不重叠，这是由于彩膜层仅需要对应于发光元件的发光层设置。如图3B所 示，在垂直于衬底基板的方向上，发光元件的第一电极的第三电极部123c、发光层124以及彩膜部190彼此重叠。
例如，如图3A-3B所示，在垂直于衬底基板101的方向上，第一子像素P1的发光元件的第一电极的第二电极部123b与第一扫描线150重叠的部分还与该第一子像素P1对应的彩膜部190重叠。由于在垂直于衬底基板的方向上，彩膜部190位于第一扫描线150与发光元件的第一电极123之间，由于彩膜部190上的第五绝缘层205为平坦化层，因此彩膜部190的形成并不影响该第五绝缘层205在该彩膜部处相对于该衬底基板的高度，也即并不改变发光元件的第一电极与第一扫描线150的间距，然而彩膜部190的介电常数相较于该第五绝缘层205的介电常数更低，因此将该彩膜部190形成在第二电极部123b与第一扫描线150之间并与二者重叠有助于进一步降低该发光元件的第一电极与第一扫描线之间的寄生电容。
发明人发现，多个第一镂空区H1或第二镂空区H2沿第二方向D2规律排列时，出现一定的有规律的连续性时，会产生周期性的衍射现象，造成该镂空区与非镂空区的金属线处对于环境光的反光差异明显，从而导致显示不均。
一方面，如图3A所示，在一个像素单元中，多个第一镂空区H1的几何中心不在一条直线上，从而有助于降低该第一镂空区沿同一方向排列的规律性，降低周期性衍射带来的显示不均。
另一方面，本公开实施例提供的显示基板利用彩膜层对位于同一行且对应于一个像素单元的多个镂空区进行选择性的遮挡，从而打破镂空区在像素单元中的排列规律，削弱衍射效应，提高显示均一性。
如图3A所示，在第一方向D1上，一个像素行(第一像素行)所对应的彩膜部位于该像素行所对应的第一扫描线150与直接相邻的下一个像素行(第二像素行)所对应的第二扫描线160之间。
例如，该第二像素行包括沿第二方向D2依次排列的第五子像素P5、第六子像素P6和第七子像素P7，该第五子像素P5与第一子像素P1位于同一列，该第六子像素P6与第二子像素P2位于同一列，该第七子像素P7与第三子像素P3位于同一列。例如，位于同一列的子像素发相同颜色的光。
例如，如图3B所示，每个子像素的发光元件的第一电极还在第一方向 D1上延伸以与相邻的下一个像素行中的子像素的第二电容电极Cb在垂直于衬底基板的方向上重叠。在正常状态下，该发光元件的第一电极与下一行子像素的第二电容电极Cb之间间隔有第四绝缘层204和第五绝缘层205，当该子像素的像素电路发生不良，可以在该发光元件的第一电极与下一行子像素的第二电容电极Cb之间形成修复孔，例如用激光将该第四绝缘层204去除并使得该发光元件的第一电极填充入该修复孔中与下一行子像素的第二电容电极Cb电连接，而该第二电容电极Cb是与其所属的子像素的发光元件的第一电极电连接的，因此发生不良的子像素的发光元件的第一电极与下一行子像素的发光元件的第一电极形成了电连接，从而使得该不良子像素得到修复。图3A中用9号过孔示意出了该修复孔的位置。
例如，该第一像素行对应的彩膜部190分别具有靠近第二像素行的侧边，例如，该侧边为直线型并与第二方向D2平行。
例如，在垂直于衬底基板的方向上，第一子像素P1对应的彩膜部190与多个第一镂空区H1中的至少一个重叠，第二子像素P2对应的彩膜部190与多个第一镂空区H1均不重叠。
例如，在垂直于衬底基板的方向上，第一子像素P1对应的彩膜部与多个第一镂空区H1中的一个重叠且具有第一重叠面积，第二子像素P2对应的彩膜部与多个第一镂空区H1中的另一个重叠且具有第二重叠面积；该第一重叠面积与第二重叠面积不同。
例如，该第一重叠面积与第二重叠面积差值的绝对值大于(n*λ)2(即整数倍波长的平方)，λ为该第一子像素P1和第二子像素P2发出光的波长中的较大值。该第一重叠面积与第二重叠面积差值的绝对值越大，光衍射对显示效果的影响越小。
如图3A所示，在垂直于衬底基板的方向上，第一子像素P1对应的彩膜部190与多个第一镂空区H1中的一个重叠，第二子像素P2对应的彩膜部190与第三子像素P3对应的彩膜部190与多个第一镂空区H1均不重叠。
如图3A所示，第二像素行对应的第二扫描线160的第二部分162与电源线240、数据线DL以及检测线230在垂直于衬底基板的方向重叠定义出沿第二方向D2依次布置的多个第二镂空区H2。
如图3A所示，在垂直于衬底基板的方向上，第一子像素P1对应的彩膜 部与多个第二镂空区H2中的一个第二镂空区重叠且具有第三重叠面积A3，第二子像素P2对应的彩膜部与多个第二镂空区H2中的另一个第二镂空区重叠且具有第四重叠面积A4，第三子像素P3与多个第二镂空区H2中的又一个第二镂空区重叠且具有第五重叠面积A5；该第三重叠面积A3、第四重叠面积A4和第五重叠面积A5均不相同。例如，如图3B所示，A3＞A4＞A5。
如图3A所示，多个第一镂空区H1中靠近第四子像素P4的第一镂空区H1’均与彩膜层在垂直于衬底基板的方向上不重叠；多个第二镂空区H2中靠近第四子像素P4的第二镂空区H2’均与彩膜层在垂直于衬底基板的方向上不重叠。
如图3A所示，在第二方向D2与该第一镂空区H1’直接相邻的第一镂空区H1”与彩膜层在垂直于衬底基板的方向上不重叠；在第二方向D2与该第二镂空区H2’直接相邻的第二镂空区H2”与彩膜层在垂直于衬底基板的方向上不重叠。
由于第四子像素P4发白光，白光的衍射对显示的均一性较小，因此靠近该第四子像素P4的镂空区可以不进行遮挡。
例如，如图3B所示，在垂直于衬底基板的方向上，第一数据线DL1、第二数据线DL2以及第三数据线DL3均与彩膜层重叠。这种设置可以避免数据线对光线的反射从而发生显示不均。
例如，第四数据线DL4与彩膜层不重叠。
如图3B所示，在垂直于衬底基板的方向上，检测线230与彩膜层重叠，且重叠面积小于第一数据线DL1、第二数据线DL2以及第三数据线DL3中任一条数据线与彩膜层的重叠面积。
由于第四数据线DL4与检测线230相较于第一数据线DL1、第二数据线DL2以及第三数据线DL3距离第四子像素P4最近，而该第四子像素P4发白光，白光的衍射对显示的均一性较小，因此第四数据线DL4和该检测线230对于第一子像素P4发出的光的反射的影响较小，可以不对该第四数据线和检测线进行遮挡。
在另一些示例中，如图3C所示，该第一表面微结构11和第二表面微结构12位于同一条电源线240上，也即该电源线240充当该第一导电结构；且该第一表面微结构11与该电源线240所对应的第二镂空区H2在垂直于衬底 基板的方向上至少部分重叠。
由于该电源线240在该第二镂空区H2处存在坡度，应力较大，将该第一表面微结构12设置在该电源线240对应于第二镂空区H2处有助于释放应力，提高良率。
在又一些示例中，如图3D所示，该第一表面微结构11和第二表面微结构12位于第三晶体管T3的第二极T3d上，也即第三晶体管T3的第二极T3d充当该第一导电结构；且该第一表面微结构与10号过孔(本公开第四过孔的一个示例)在垂直于衬底基板的方向上至少部分重叠。
在再一些示例中，如图3E所示，该第一表面微结构11和第二表面微结构12位于第三晶体管T3的第一极T3s上，也即第三晶体管T3的第一极T3s充当该第一导电结构；且该第一表面微结构与6号过孔在垂直于衬底基板的方向上至少部分重叠。
为了清楚起见，图3D和3E中均用黑点示出了该第一表面微结构11和第二表面微结构12。由于过孔第一处导电结构的坡度较大，应力较大，在该第一导电结构对应过孔处设置该第一表面微结构可以有助于应力的释放。
本公开的至少一实施例还提供上述显示基板的制作方法。以下将结合图3A-3B和图4A-图4D、并以一个子像素为例对本公开实施例提供的显示基板的制作方法进行实例性说明，然而本公开实施例并不限于此。图4A-图4D分别示出了一个子像素(例如第一子像素P1)中第一导电层、半导体层、第二导电层、第三导电层的图案。
该制作方法包括如下步骤S61-S65。
步骤S61：形成第一导电材料层，并对该第一导电材料层进行构图工艺从而形成如图4A所示的第一导电层501，也即遮光层170以及存储电容Cst的第三电容电极Cc。该构图工艺还形成彼此绝缘的检测部231和连接电极241。
步骤S62：在该第一导电层501上形成第一绝缘层201并在该第一绝缘层上形成半导体材料层，并对该半导体材料层进行构图工艺从而形成如图4B所示的半导体层104，也即形成彼此间隔的第一晶体管T1的有源层T1a、第二晶体管T2的有源层T2a和第三晶体管T3的有源层T3a。
步骤S63：在该半导体层104上形成第二绝缘层202并在该第二绝缘层 上形成第二导电材料层，对该第二导电材料层进行构图工艺形成如图4C所示的第二导电层502，也即形成彼此绝缘的第一晶体管T1的栅极T1g、第二晶体管T2的栅极T2g和第三晶体管T3的栅极T3g。图4C还示出了延伸部180。
例如，如图4C所示，该第二导电层502还包括彼此绝缘的第一扫描线150和第二扫描线160。
例如，该第一扫描线150和第二扫描线160的线宽范围为5-15微米。
例如，该第一扫描线150与对应的一行子像素的第二晶体管T2的栅极T2g为一体的结构，该第二扫描线160分别与对应的一行子像素的第三晶体管T3的栅极T3g为一体的结构。
步骤S64：采用自对准工艺，利用该第二导电层502作为掩膜对该半导体层204进行导体化处理(例如掺杂处理)，从而使得该半导体层204未被该第二导电层502覆盖的部分被导体化，从而得到该第一电容电极Ca，并使得各晶体管的有源层位于沟道区两侧的部分被导体化而形成分别第一极接触区及第二极接触区，该第一极接触区和第二极接触区分别用于与该晶体管的第一极和第二极电连接。图4B中示出了第一晶体管T1的有源层T1a的第一极接触区T1a1和第二极接触区T1a2、第二晶体管T2的有源层T2a的第一极接触区T2a1和第二极接触区T2a2、以及第三晶体管T3的有源层T3a的第一极接触区T3a1和第二极接触区T3a2。图4B中还示出了连接部720。
例如，在对该半导体层104进行导体化处理之前对第二绝缘层202进行刻蚀工艺，使得该第二绝缘层202未被该第二导电层502覆盖的区域全部被刻蚀，也即第二绝缘层103与第二导电层502在垂直于衬底基板101的方向上重合。这样，在采用离子注入对半导体层204未被第二导电层202覆盖的区域进行导体化处理时，注入的离子可以不被第二绝缘层202阻挡。
步骤S65：在该第二导电层502上形成第三绝缘层203，并在该第三绝缘层203上形成第三导电材料层，对该第三导电材料层进行构图工艺形成如图4D所示的第三导电层503，也即形成第一晶体管T1的第一极T1s和第二极T1d、第二晶体管T2的第一极T2s和第二极T2d以及第三晶体管T3的第一极T3s和第二极T3d。
例如，该第三导电层503还包括彼此绝缘的数据线DL、检测线230和 电源线240。
例如，数据线DL的线宽范围为5-15微米，检测线230的线宽范围为5-30微米，电源线240的线宽范围为5-30微米。
例如，如图4D所示，该电源线240和与之直接相邻的(最近的)子像素中的第一晶体管T1的第二极T1d为一体的结构。例如，每条数据线110和与之连接的子像素中的第二晶体管T2的第二极T2d为一体的结构。
例如，该半导体材料层的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，上述第一导电材料层为遮光导电材料，例如包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料。例如，该第一导电材料层可以是钼钛合金，例如厚度为50-100纳米。
例如，第二导电材料层和第三导电材料层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，第二导电材料层为钼钛合金与铜的叠层结构，例如钼钛合金的厚度为30-50纳米，铜的厚度为300-400纳米。
例如，第三导电材料层为钼钛合金与铜的叠层结构，例如钼钛合金的厚度为30-50纳米，铜的厚度为400-700纳米。
例如，该半导体材料层的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，该半导体材料层的材料为氧化铟镓锌，厚度为30-50纳米。
例如，第一绝缘层201、第二绝缘层202、第三绝缘层203例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。例如，这些绝缘层也可以是有机材料，例如聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等，本公开实施例对此不作限制。
例如，第一绝缘层201的材料为氧化硅，厚度为300-500纳米。例如，第二绝缘层202的材料为氧化硅，厚度为100-160纳米。例如，第三绝缘层的材料为氧化硅，厚度为400-600纳米。
例如，参考图3B，还可以在该第三导电层503上依次形成第四绝缘层204、彩膜层以及第五绝缘层205，并在该第五绝缘层205上形成发光元件的第一电极123，然后在该第一电极123上形成像素界定层206，并依次形成发光层124和第二电极122，这样就形成了如图3A所示的显示基板10。
例如，形成该彩膜层可以包括先形成红色彩膜层并对该红色彩膜层进行构图工艺形成对应红色子像素的彩膜部，再形成绿色彩膜层并对该绿色彩膜层进行构图工艺形成对应绿色子像素的彩膜部，然后形成蓝色彩膜层并对该蓝色彩膜层进行构图工艺形成对应蓝色子像素的彩膜部。
例如，该红色彩膜层、绿色彩膜层和蓝色彩膜层的厚度分别为2000-3000纳米，也即每个彩膜部的厚度为2000-3000纳米。
例如，相邻的子像素之间可以通过彩膜部的重叠形成遮光部避免串色。
例如，可以通过对该显示基板中的导电结构或信号线进行刻蚀形成凹面结构，或者对该导电结构或信号线的表面进行等离子体处理以形成上述第一表面微结构和第二表面微结构。
本公开至少一实施例还提供一种显示面板，包括以上任一显示基板10。需要说明的是，本公开至少一实施例提供的上述显示基板10可以包括发光元件125，也可以不包括发光元件125，也即该发光元件125可以在显示基板10完成后在面板厂形成。在该显示基板10本身不包括发光元件125的情形下，本公开实施例提供的显示面板除了包括显示基板10之外，还进一步包括发光元件125。
例如，该显示面板为OLED显示面板，相应地其包括的显示基板10为OLED显示基板。如图5A所示，例如，该显示面板20还包括设置于显示基板10上的封装层801和盖板802，该封装层801配置为对显示基板10上的发光元件进行密封以防止外界的湿气和氧向该发光元件及驱动电路的渗透而造成对器件的损坏。例如，封装层801包括有机薄膜或者包括有机薄膜及无机薄膜交替层叠的结构。例如，该封装层801与显示基板10之间还可以设置吸水层(未示出)，配置为吸收发光元件在前期制作工艺中残余的水汽或者 溶胶。盖板802例如为玻璃盖板。例如，盖板802和封装层801可以为一体的结构。
在另一些示例中，如图5B所示，该显示面板包括设置于显示基板10上的黏胶层901和金属封装层902。该金属封装层902除了起到封装作用外，还可以对该显示基板10起到支撑和固定作用，例如在大尺寸应用中对该显示基板10进行支撑从而降低该显示基板10所受的应力冲击。例如，该显示基板10为底发射结构，该金属封装层902不会对显示光进行遮挡。
本公开的至少一实施例还提供一种显示装置30，如图6所示，该显示装置30包括上述任一显示基板10或显示面板20，本实施例中的显示装置可以为：显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
例如，上述构图工艺可以采用常规的光刻工艺，例如包括光刻胶的涂布、曝光、显影、烘干、刻蚀等步骤。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (87)

  1. 一种显示基板，包括衬底基板及位于所述衬底基板上的第一导电结构，
    其中，所述第一导电结构包括背离所述衬底基板的第一表面和第二表面，所述第一表面和所述第二表面的材料相同；所述第一表面与所述衬底基板的板面具有第一夹角，所述第二表面与所述衬底基板的板面具有第二夹角，所述第一夹角与所述第二夹角不同；所述第一表面上设置有第一表面微结构，所述第二表面上设置有第二表面微结构；所述第一导电结构还包括靠近所述衬底基板的第三表面和第四表面，所述第三表面与所述第一表面相对，所述第四表面与所述第二表面相对；
    所述第一表面微结构具有与所述衬底基板垂直的第一截面，所述第一截面在所述第三表面具有第一正投影；所述第一正投影的长度小于所述第一表面微结构在所述第一截面上的长度；
    所述第二表面微结构具有与所述衬底基板垂直的第二截面，所述第二截面在所述第四表面上具有第二正投影，所述第二正投影的长度小于所述第二表面微结构在所述第二截面上的长度。
  2. 如权利要求1所述的显示基板，其中，所述第一截面的两端之间的距离和所述第二截面的两端的距离分别大于0.1微米小于1微米。
  3. 如权利要求1或2所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述第一表面微结构与所述第三表面至少部分重叠，所述第二表面微结构与所述第四表面至少部分重叠。
  4. 如权利要求1-3任一所述的显示基板，其中，所述第三表面和所述第四表面的至少之一为平坦表面。
  5. 如权利要求1-4任一所述的显示基板，其中，所述第一表面微结构在所述第三表面上的正投影的面积小于所述第一表面微结构的表面积；所述第二表面微结构在所述第四表面上的正投影的面积小于所述第二表面微结构的表面积。
  6. 如权利要求1-5任一所述的显示基板，其中，所述第一导电结构在所述第一表面微结构处的最小厚度小于所述第一导电结构的平均厚度且大于所述第一导电结构的平均厚度的3/5。
  7. 如权利要求1-6任一所述的显示基板，其中，所述第一表面微结构在所述第一截面上具有第一端点、第一中间点和第二端点，所述第二表面微结构在所述第二截面上具有第三端点、第二中间点和第四端点；
    所述第一中间点与所述第三表面的距离和所述第一端点及第二端点与所述第三表面的距离均不相等，
    所述第二中间点与所述第四表面的距离和所述第三端点及所述第四端点与所述第四表面的距离均不相等。
  8. 如权利要求1-7任一所述的显示基板，其中，所述第一夹角大于0度，所述第二夹角等于0度。
  9. 如权利要求8所述的显示基板，其中，所述第一表面微结构在所述第一截面上具有第一端点和第二端点，所述第二表面微结构在所述第二截面上具有第三端点和第四端点；
    所述第一端点和所述第二端点的构成的线段的中点与所述第三端点和所述第四端点的构成的线段的中点相对于所述衬底基板的板面的距离不同。
  10. 如权利要求9所述的显示基板，其中，所述第一端点与所述第二端点之间的距离大于所述第三端点与所述第四端点之间的距离。
  11. 如权利要求8或9所述的显示基板，还包括位于所述第一导电结构靠近所述衬底基板一侧的第一绝缘层，
    其中，所述第一绝缘层包括分别与所述第一导电结构的第三表面和第四表面分别直接接触的第一部分和第二部分，所述第一部分的最小厚度小于所述第二部分的最小厚度。
  12. 如权利要求11所述的显示基板，还包括位于所述第一绝缘层靠近所述衬底基板一侧的第二导电结构，
    其中，所述第一绝缘层的第一部分包覆所述第二导电结构的至少部分。
  13. 如权利要求12所述的显示基板，其中，在垂直于衬底基板的方向上，所述第一表面微结构与所述第二导电结构不重叠。
  14. 如权利要求12或13所述的显示基板，其中，所述第一导电结构通过贯穿所述第一绝缘层的第一过孔与所述第二导电结构电连接；
    在垂直于所述衬底基板的方向上，所述第一表面微结构与所述第一过孔 的至少部分重叠。
  15. 如权利要求14所述的显示基板，其中，所述第一绝缘层包括层叠设置的第一子层和第二子层，所述第二子层相较于所述第一子层远离所述衬底基板；
    所述第一子层包括被所述第一过孔暴露的第一侧面，所述第二子层包括被所述第一过孔暴露的第二侧面，所述第一侧面与所述第二侧面中的至少之一与所述第一导电结构的第三表面直接接触。
  16. 如权利要求15所述的显示基板，其中，所述第一侧面与所述衬底基板的夹角大于所述第二侧面与所述衬底基板的夹角。
  17. 如权利要求15或16所述的显示基板，其中，所述第二子层的致密度高于所述第一子层。
  18. 如权利要求1-17任一所述的显示基板，其中，所述第一表面的氧含量高于所述第三表面的氧含量。
  19. 如权利要求1-18任一所述的显示基板，其中，所述第一表面微结构在所述第一截面上具有第一端点和第二端点，所述第一截面距离所述第三表面最近的点与所述第一端点和所述第二端点的距离不相等。
  20. 如权利要求1-19任一所述的显示基板，其中，所述第一表面微结构包括第一凹面结构，所述第二表面微结构包括第二凹面结构。
  21. 如权利要求1-20任一所述的显示基板，还包括位于所述衬底基板上的多个子像素，
    其中，所述多个子像素沿第一方向和第二方向布置为多个像素列和多个像素行，所述第一方向与所述第二方向交叉；
    所述多个子像素中的每个包括在所述衬底基板上的第一晶体管、第二晶体管、第三晶体管和存储电容，
    所述第二晶体管的第一极与所述存储电容的第一电容电极和所述第一晶体管的栅极电连接，所述第二晶体管的第二极配置为接收数据信号，所述第二晶体管的栅极配置为接收第一控制信号，所述第二晶体管配置为响应于所述第一控制信号将所述数据信号写入所述第一晶体管的栅极和所述存储电容，
    所述第一晶体管的第一极与所述存储电容的第二电容电极电连接，并配置为与发光元件的第一电极电连接，所述第一晶体管的第二极配置为接收第一电源电压，所述第一晶体管配置为在所述第一晶体管的栅极的电压的控制下控制用于驱动所述发光元件的电流，
    所述第三晶体管的第一极与所述第一晶体管的第一极以及所述存储电容的第二电容电极电连接，所述第三晶体管的第二极配置为与检测电路连接。
  22. 如权利要求21所述的显示基板，其中，所述第一表面微结构在所述衬底基板上的正投影与所述第二表面微结构在所述衬底基板上的正投影之间的中心距离在所述第一方向和所述第二方向的分量分别小于所述多个子像素的每个在所述第一方向和所述第二方向的平均尺寸。
  23. 如权利要求21或22所述的显示基板，其中，每个像素列的子像素发相同颜色的光。
  24. 如权利要求23所述的显示基板，其中，所述第一表面微结构包括第一凹面结构，所述第二表面微结构包括第二凹面结构；
    所述第一凹面结构和所述第二凹面结构沿所述第一导电结构的延伸方向排列，且朝向颜色相同的子像素。
  25. 如权利要求21-24任一所述的显示基板，其中，
    所述显示基板还包括从所述第一晶体管的栅极突出的延伸部，所述延伸部从所述第一晶体管的栅极沿所述第二方向延伸并与所述第二晶体管的第一极在垂直于所述衬底基板的方向上至少部分重叠且电连接。
  26. 如权利要求25所述的显示基板，其中，所述第二晶体管的有源层包括第一极接触区、第二极接触区以及位于所述第一极接触区和所述第二极接触区之间的沟道区，所述第二晶体管的第一极通过第二过孔分别与所述第一极接触区、所述延伸部以及所述第一电容电极电连接。
  27. 如权利要求26所述的显示基板，其中，
    所述第二过孔沿所述第一方向延伸并暴露出所述延伸部的表面以及在所述第一方向上相对的两个侧面的至少部分。
  28. 如权利要求27所述的显示基板，其中，所述延伸部将所述第二过孔间隔为第一凹槽和第二凹槽，所述第二晶体管的第一极填充所述第一凹槽和 所述第二凹槽并包覆所述延伸部的所述两个侧面；
    所述第二晶体管的第一极包括第一部分、第二部分以及第三部分，
    所述第二部分覆盖所述延伸部的所述表面，所述第一部分覆盖所述第一凹槽，所述第三部分覆盖所述第二凹槽；所述第一部分和所述第三部分还分别覆盖所述延伸部的所述两个侧面。
  29. 如权利要求28所述的显示基板，其中，所述第一导电结构为所述第二晶体管的第一极，所述第一表面微结构和所述第二表面微结构均位于所述第二晶体管的第一极的第三部分。
  30. 如权利要求29所述的显示基板，其中，所述第一表面微结构在所述第一方向上的尺寸小于所述第三部分沿所述第一方向的最大尺寸的十分之一。
  31. 如权利要求29或30所述的显示基板，其中，所述第一表面微结构在所述第一方向上的尺寸小于所述第二过孔在所述衬底基板上的正投影在所述第一方向上的最大尺寸的十分之一。
  32. 如权利要求21-31任一所述的显示基板，其中，所述多个子像素的每个还包括所述发光元件，所述发光元件包括依次层叠设置的第一电极、发光层和第二电极，所述第一电极相较于所述第二电极更靠近所述衬底基板，所述发光元件的第一电极通过第三过孔与所述发光元件所属的子像素的第一晶体管的第一极电连接。
  33. 如权利要求32所述的显示基板，其中，所述发光元件的第一电极包括在所述第一方向上依次连接的第一电极部、第二电极部和第三电极部，所述第一电极部用于与对应的第一晶体管的第一极电连接且在垂直于所述衬底基板的方向上与所述对应的第一晶体管的第一极重叠；
    所述发光元件的第三电极部与所述发光元件的开口区在垂直于所述衬底基板的方向上至少部分重叠。
  34. 如权利要求33所述的显示基板，其中，所述第一电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺寸之和小于所述第三电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺寸之和；
    所述第二电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺 寸之和小于所述第三电极部沿所述第一方向的最大尺寸和沿所述第二方向的最大尺寸之和。
  35. 如权利要求33或34所述的显示基板，其中，所述显示基板包括多个第一表面微结构和多个第二表面微结构，所述多个第一表面微结构和多个第二表面微结构中的一部分与所述第一电极部在垂直于衬底基板的方向上重叠，所述多个第一表面微结构和多个第二表面微结构的另一部分与所述第三电极部在垂直于所述衬底基板的方向上重叠；
    与所述第一电极部重叠的第一表面微结构和第二表面微结构的分布密度大于与所述第三电极部的重叠的第一表面微结构和第二表面微结构的分布密度。
  36. 如权利要求33-35任一所述的显示基板，其中，所述发光元件的第一电极的第二电极部在所述第二方向的平均尺寸小于所述第一电极部在所述第二方向的平均尺寸，也小于所述第三电极部在所述第二方向的平均尺寸。
  37. 如权利要求33-36任一所述的显示基板，其中，所述多个像素行包括第一像素行，所述第一像素行划分为多个像素单元，每个像素单元包括沿所述第二方向依次布置的第一子像素、第二子像素和第三子像素，所述第一子像素、所述第二子像素和所述第三子像素分别配置为发出三种基本色的光；
    所述显示基板还包括沿所述第二方向延伸的第一扫描线，所述第一扫描线与所述第一子像素、第二子像素及第三子像素中的第二晶体管的栅极电连接以提供所述第一控制信号。
  38. 如权利要求37所述的显示基板，其中，所述第一扫描线与所述第一子像素的发光元件的第一电极的第二电极部在垂直于所述衬底基板的方向上重叠。
  39. 如权利要求38所述的显示基板，还包括彩膜层，其中，所述彩膜层位于所述发光元件的第一电极靠近所述衬底基板的一侧；
    所述彩膜层包括分别对应于所述第一子像素、所述第二子像素和所述第三子像素的多个彩膜部，所述第一子像素、所述第二子像素和所述第三子像素发出的光分别经所对应的彩膜部射出显示基板形成显示光。
  40. 如权利要求39所述的显示基板，其中，在垂直于所述衬底基板的方 向上，所述第一子像素对应的彩膜部、所述第二子像素对应的彩膜部和所述第二表面微结构在垂直于衬底基板的方向上均重叠。
  41. 如权利要求39或40所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述多个彩膜部的每个与对应的子像素的发光元件的第一电极的第三电极部重叠，并与所述对应的子像素的发光元件的第一电极的第一电极部不重叠。
  42. 如权利要求41所述的显示基板，其中，所述第一扫描线位于所述彩膜层靠近所述衬底基板的一侧；
    在垂直于所述衬底基板的方向上，所述第一子像素的发光元件的第一电极的第二电极部与所述第一扫描线重叠的部分还与所述第一子像素所对应的彩膜部重叠。
  43. 如权利要求42所述的显示基板，其中，所述第一扫描线包括交替连接的第一部分和第二部分，所述第二部分为环状结构。
  44. 如权利要求43所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述第一子像素的发光元件的第一电极与所述第一扫描线的第一部分重叠并与所述第一扫描线的第二部分不重叠。
  45. 如权利要求43或44所述的显示基板，还包括沿所述第一方向延伸的多条第一信号线，
    其中，在垂直于所述衬底基板的方向上，所述多条第一信号线与所述第一扫描线的第二部分重叠从而定义出沿所述第二方向布置的多个第一镂空区。
  46. 如权利要求45所述的显示基板，其中，每个像素单元中所对应的多个第一镂空区的几何中心不在一条直线上。
  47. 如权利要求45或46所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述第一子像素对应的彩膜部与所述多个第一镂空区中的至少一个重叠，所述第二子像素对应的彩膜部与所述多个第一镂空区均不重叠。
  48. 如权利要求45-47任一所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述第一子像素对应的彩膜部与所述多个第一镂空区中的一个重叠且具有第一重叠面积，所述第二子像素对应的彩膜部与所述多个第一镂 空区中的另一个重叠且具有第二重叠面积；
    所述第一重叠面积与所述第二重叠面积不同。
  49. 如权利要求48所述的显示基板，其中，所述第一重叠面积与所述第二重叠面积差值的绝对值大于(n*λ)2，λ为所述第一子像素和第二子像素发出光的波长中的较大值。
  50. 如权利要求48或49所述的显示基板，其中，所述显示基板包括多个第一表面微结构和多个第二表面微结构，所述多个第一表面微结构和多个第二表面微结构中的一部分与所述第一扫描线的第一部分在垂直于衬底基板的方向上重叠，所述多个第一表面微结构和多个第二表面微结构的另一部分与所述第一扫描线的第二部分在垂直于所述衬底基板的方向上重叠；
    在垂直于衬底基板的方向上，与所述第一扫描线的第二部分重叠的第一表面微结构和第二表面微结构的分布密度大于与所述第一扫描线的第一部分的重叠的第一表面微结构和第二表面微结构的分布密度。
  51. 如权利要求50所述的显示基板，其中，所述第一重叠面积大于所述多个第一表面微结构或所述第二表面微结构中的每个在所述衬底基板的正投影的面积；
    所述第二重叠面积大于所述多个第一表面微结构或所述第二表面微结构中的每个在所述衬底基板的正投影的面积。
  52. 如权利要求45-51任一所述的显示基板，其中，所述像素单元还包括第四子像素，所述第四子像素配置为发白光，
    所述多个第一镂空区中靠近所述第四子像素的第一镂空区均与所述彩膜层在垂直于所述衬底基板的方向上不重叠。
  53. 如权利要求45-52任一所述的显示基板，其中，所述多条第一信号线包括多条数据线，所述多条数据线与所述多个像素列一一对应连接；
    对于所述第一像素行，多条数据线被划分为与所述多个像素单元一一对应的多个数据线组，每个数据线组包括分别与所述第一子像素、第二子像素和第三子像素连接的第一数据线、第二数据线和第三数据线；
    对于每一个所述像素单元，与所述像素单元对应连接的所述第一数据线、所述第二数据线及所述第三数据线均位于所述第一子像素和所述第三子像素 之间。
  54. 如权利要求53所述的显示基板，还包括沿所述第一方向延伸的多条电源线，
    其中，所述多条电源线配置为为所述多个子像素提供所述第一电源电压，所述多条电源线的每条与所述多条数据线中的任意一条之间间隔有至少一个像素列。
  55. 如权利要求54所述的显示基板，其中，所述显示基板包括多个第一表面微结构和多个第二表面微结构，所述多个第一表面微结构和多个第二表面微结构中的一部分分布在所述多条数据线上，所述多个第一表面微结构和多个第二表面微结构的另一部分分布在所述多条电源线上；
    所述多个第一表面微结构和所述多个第二表面微结构在所述多条数据线上的分布密度大于所述多个第一表面微结构和所述多个第二表面微结构在所述多条电源线上的分布密度。
  56. 如权利要求53-55任一所述的显示基板，其中，所述第二子像素与所述第三子像素直接相邻，所述第三子像素具有在所述第二方向上相对的第一侧与第二侧，
    所述第二数据线和所述第三数据线位于所述第三子像素的第一侧且位于所述第二子像素与所述第三子像素之间。
  57. 如权利要求56所述的显示基板，其中，所述第三子像素的发光元件的第一电极的第二电极部相对于其第一电极部和其第三电极部向远离所述第三子像素的第二侧的方向凹入。
  58. 如权利要求53-57任一所述的显示基板，其中，在垂直于所述衬底的方向上，所述第二数据线、所述第三数据线分别与所述彩膜层至少部分重叠。
  59. 如权利要求53-58任一所述的显示基板，其中，所述像素单元还包括第四子像素，所述第四子像素配置为发白光，
    所述每个数据线组还包括与所述第四子像素连接的第四数据线；
    在垂直于衬底基板的方向上，所述第四数据线与所述彩膜层不重叠。
  60. 如权利要求45-59任一所述的显示基板，其中，所述多个像素行还包括第二像素行，所述第二像素行与所述第一像素行在所述第一方向上直接相 邻，
    所述第二像素行包括沿所述第二方向依次排列的第五子像素、第六子像素和第七子像素，所述第五子像素与所述第一子像素位于同一像素列，所述第六子像素与所述第二子像素位于同一像素列，所述第七子像素与所述第三子像素位于同一像素列。
  61. 如权利要求60所述的显示基板，其中，所述第一子像素对应的彩膜部具有靠近所述第五子像素的侧边，所述侧边与所述第二方向平行。
  62. 如权利要求60或61所述的显示基板，其中，所述显示基板还包括沿所述第二方向延伸的第二扫描线，所述第二扫描线与所述第五子像素、第六子像素及第七子像素中的第三晶体管的栅极电连接以提供第二控制信号。
  63. 如权利要求62所述的显示基板，其中，所述第二扫描线包括交替连接的第一部分和第二部分，所述第二部分为环状结构。
  64. 如权利要求63所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述多条第一信号线与所述第二扫描线的第二部分重叠从而定义出沿所述第二方向依次布置的多个第二镂空区。
  65. 如权利要求64所述的显示基板，其中，所述第一导电结构为所述多条第一信号线之一，所述第一表面微结构和所述第二表面微结构位于所述第一信号线上，且所述第一表面微结构与所述第一信号线所对应的第二镂空区在垂直于所述衬底基板的方向上至少部分重叠。
  66. 如权利要求64或65所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述第一子像素对应的彩膜部与所述多个第二镂空区中的一个第二镂空区重叠且具有第三重叠面积，所述第二子像素对应的彩膜部与所述多个第二镂空区中的另一个第二镂空区重叠且具有第四重叠面积，所述第三子像素对应的彩膜部与所述多个第二镂空区中的又一个第二镂空区重叠且具有第五重叠面积；
    所述第三重叠面积、所述第四重叠面积和所述第五重叠面积均不相同。
  67. 如权利要求21-66任一所述的显示基板，其中，所述第三晶体管的第二极通过第四过孔与沿所述第二方向延伸的检测部电连接，所述检测部与沿所述第一方向延伸的检测线电连接，从而所述第三晶体管的第二极通过所述 检测部和所述检测线与所述检测电路连接。
  68. 如权利要求67所述的显示基板，其中，所述第一导电结构为所述第三晶体管的第二极，所述第一表面微结构和所述第二表面微结构位于所述第三晶体管的第二极上，且所述第一表面微结构与所述第四过孔在垂直于所述衬底基板的方向上至少部分重叠。
  69. 如权利要求21-68任一所述的显示基板，其中，所述第三晶体管的有源层包括第一极接触区、第二极接触区以及位于所述第一极接触区和所述第二极接触区之间的沟道区，
    所述第三晶体管的第一极通过第五过孔与所述第三晶体管的第一极接触区电连接。
  70. 如权利要求69所述的显示基板，其中，所述第一导电结构为所述第三晶体管的第一极，所述第一表面微结构和所述第二表面微结构位于所述第三晶体管的第一极上，且所述第一表面微结构与所述第五过孔在垂直于所述衬底基板的方向上至少部分重叠。
  71. 一种显示基板，包括衬底基板和位于所述衬底基板上的第一导电结构，
    其中，所述第一导电结构包括背离所述衬底基板的第一表面和第二表面，所述第一表面和所述第二表面的材料相同；所述第一表面上设置有第一表面微结构，所述第二表面上设置有第二表面微结构；
    所述第一表面微结构具有与所述衬底基板垂直的第一截面，所述第二表面微结构具有与所述衬底基板垂直的第二截面；
    所述第一表面微结构在所述第一截面具有第一端点和第二端点，所述第二表面微结构在所述第二截面上具有第三端点和第四端点；
    所述第一端点和所述第二端点的连线的中点与所述第三端点和所述第四端点的连线的中点相对于所述衬底基板的板面的距离不同。
  72. 如权利要求71所述的显示基板，其中，所述第一导电结构在所述第一表面微结构处的最小厚度小于所述第一导电结构的平均厚度且大于所述第一导电结构的平均厚度的3/5。
  73. 如权利要求71或72所述的显示基板，其中，所述第一导电结构还 包括靠近所述衬底基板的第三表面和第四表面，在垂直于所述衬底基板的方向上，所述第一表面微结构与所述第三表面至少部分重叠，所述第二表面微结构与所述第四表面至少部分重叠。
  74. 如权利要求73所述的显示基板，其中，所述第三表面和所述第四表面的至少之一为平坦表面。
  75. 如权利要求73或74所述的显示基板，其中，所述第一表面微结构在所述第三表面上的正投影的面积小于所述第一表面微结构的表面积；
    所述第二表面微结构在所述第四表面上的正投影的面积小于所述第二表面微结构的表面积。
  76. 如权利要求73-75任一所述的显示基板，其中，所述第一表面微结构在所述第一截面上还具有位于所述第一端点和所述第二端点之间的第一中间点，所述第二表面微结构在所述第二截面上还具有位于所述第三端点和所述第四端点之间的第二中间点；
    所述第一中间点与所述第三表面的距离和所述第一端点及第二端点与所述第三表面的距离均不相等，
    所述第二中间点与所述第四表面的距离和所述第三端点及所述第四端点与所述第四表面的距离均不相等。
  77. 如权利要求71-76任一所述的显示基板，其中，所述第一表面与所述衬底基板的板面具有第一夹角，所述第二表面与所述衬底基板的板面具有第二夹角，所述第一夹角与所述第二夹角不同。
  78. 如权利要求77所述的显示基板，其中，所述第一夹角大于0度，所述第二夹角等于0。
  79. 如权利要求78所述的显示基板，还包括位于所述第一导电结构靠近所述衬底基板一侧的第一绝缘层，
    其中，所述第一绝缘层包括分别与所述第一导电结构的第三表面和第四表面分别直接接触的第一部分和第二部分，所述第一部分的最小厚度小于所述第二部分的最小厚度。
  80. 如权利要求79所述的显示基板，还包括位于所述第一绝缘层靠近所述衬底基板一侧的第二导电结构，
    其中，所述第一绝缘层的第一部分包覆所述第二导电结构的至少部分。
  81. 如权利要求80所述的显示基板，其中，在垂直于衬底基板的方向上，所述第一表面微结构与所述第二导电结构不重叠。
  82. 如权利要求80或81所述的显示基板，其中，所述第一导电结构通过贯穿所述第一绝缘层的第一过孔与所述第二导电结构电连接；
    在垂直于所述衬底基板的方向上，所述第一表面微结构与所述第一过孔的至少部分重叠。
  83. 如权利要求82所述的显示基板，其中，所述第一绝缘层包括层叠设置的第一子层和第二子层，所述第二子层相较于所述第一子层远离所述衬底基板；
    所述第一子层包括被所述第一过孔暴露的第一侧面，所述第二子层包括被所述第一过孔暴露的第二侧面，所述第一侧面与所述第二侧面中的至少之一与所述第一导电结构的第三表面直接接触。
  84. 如权利要求83所述的显示基板，其中，所述第一侧面与所述衬底基板的夹角大于所述第二侧面与所述衬底基板的夹角。
  85. 如权利要求83或84所述的显示基板，其中，所述第二子层的致密度高于所述第一子层。
  86. 如权利要求73-85任一所述的显示基板，其中，所述第一表面的氧含量高于所述第三表面的氧含量。
  87. 一种显示装置，包括如权利要求1-86任一所述的显示基板。
PCT/CN2021/098923 2021-01-04 2021-06-08 显示基板及显示装置 WO2022142141A1 (zh)

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