WO2022140972A1 - 芯片堆叠结构及其制作方法、芯片封装结构、电子设备 - Google Patents

芯片堆叠结构及其制作方法、芯片封装结构、电子设备 Download PDF

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WO2022140972A1
WO2022140972A1 PCT/CN2020/140360 CN2020140360W WO2022140972A1 WO 2022140972 A1 WO2022140972 A1 WO 2022140972A1 CN 2020140360 W CN2020140360 W CN 2020140360W WO 2022140972 A1 WO2022140972 A1 WO 2022140972A1
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chip
layer
redistribution layer
passive surface
stack structure
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PCT/CN2020/140360
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English (en)
French (fr)
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高山
朱继锋
雷电
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华为技术有限公司
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Priority to PCT/CN2020/140360 priority Critical patent/WO2022140972A1/zh
Priority to CN202080107430.7A priority patent/CN116635996A/zh
Publication of WO2022140972A1 publication Critical patent/WO2022140972A1/zh
Priority to US18/341,880 priority patent/US20230361082A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/32146—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the layer connector connecting to a via connection in the semiconductor or solid-state body
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L2924/30—Technical effects
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    • H01L2924/37001—Yield

Definitions

  • the present application relates to the field of chip technology, and in particular, to a chip stack structure and a manufacturing method thereof, a chip packaging structure, and an electronic device.
  • 3D chip also known as 3D IC (integrated circuit, integrated circuit)
  • 3D chip stacking technology can integrate multiple chips together, thereby improving chip performance, reducing power consumption, reducing production costs, reducing package size, and shortening processing cycles. And significantly improve the integration of the chip.
  • 3D chip stacking technology has been successfully applied by many semiconductor manufacturers to produce CMOS (complementary metal oxide semiconductor) image sensors, NAND flash (flash memory), high bandwidth memory (high bandwidth memory, HBM) and other products, and Greatly improved product performance.
  • CMOS complementary metal oxide semiconductor
  • NAND flash flash memory
  • HBM high bandwidth memory
  • 3D chip stacking technologies include die-to-die bonding (D2D bonding), die-to-wafer bonding (D2W bonding), and wafer-to-wafer bonding.
  • D2D bonding die-to-die bonding
  • D2W bonding die-to-wafer bonding
  • W2W bonding wafer-to-wafer bonding
  • D2D bonding, D2W bonding, or W2W bonding is used to make a chip stack structure, before stacking the next chip (for example, the chip can be a die or wafer), it is necessary to form a via hole on the previous chip, and the latter chip needs to be formed.
  • Embodiments of the present application provide a chip stack structure and a manufacturing method thereof, a chip packaging structure, and an electronic device, which can reduce the production cost of manufacturing the chip stack structure and improve the production efficiency.
  • a chip stack structure comprises a plurality of chips stacked in sequence and a first rewiring layer disposed on the active surface of each chip; the first rewiring layer is in contact with and electrically connected to the corresponding chip; The outermost first chip and the second chip; both the passive surface of the first chip and the passive surface of the second chip face the outside of the chip stacking structure, and the chip stacking structure further includes: a passive surface disposed on the first chip.
  • the structure also includes: a first dielectric layer and a second redistribution layer disposed on the active surface of the first chip, the first dielectric layer is located between the first redistribution layer and the second redistribution layer; wherein, the second redistribution layer The layer is electrically connected to at least one first redistribution layer through first vias. Due to the prior art, before stacking the next chip, a via hole needs to be formed on the previous chip, and the latter chip is electrically connected to the previous chip through the via hole.
  • the second redistribution layer is electrically connected to at least one layer of the first redistribution layer through the first via holes, and each layer of the first redistribution layer is electrically connected to the corresponding chip, at least one chip can directly pass through the first redistribution layer.
  • a first via is electrically connected to the second rewiring layer, and the second rewiring layer is used for electrical connection with the external circuit, so as to realize the electrical connection between the chip and the external circuit, and each first via can be punched at one time Therefore, it is beneficial to simplify the manufacturing process of the chip stack structure, save the production cost, and improve the production efficiency.
  • a plurality of wafers may be stacked together in sequence, and then the plurality of wafers may be cut to form a chip stack structure.
  • the wafer is cut first, and then the die is stacked. Since the cutting process of the wafer will produce impurity pollution, it is The dies need to be cleaned before stacking them.
  • the chip stack structure when the chip stack structure is fabricated, a plurality of wafers can be stacked in sequence, and then the plurality of wafers can be cut.
  • the cleaning process is much less complicated than the cleaning process before die stacking.
  • each die compared with the die-to-die bonding technology and the die-to-wafer bonding technology in the prior art, each die needs to undergo die-to-die alignment or die-to-wafer bonding. Alignment, since in the embodiment of the present application, in the stacking process of wafer and wafer, only one wafer-to-wafer alignment operation can be performed to achieve the alignment of multiple dies with multiple dies. It can improve production efficiency and reduce production cost.
  • the chip stack structure is fabricated in the embodiment of the present application, a plurality of wafers can be directly stacked together in sequence. Therefore, compared with the die-to-die bonding technology and the die-to-wafer technology in the prior art
  • the present application does not need to inspect the crystal grains one by one, so the production efficiency can also be improved and the production cost can be reduced.
  • multiple wafers are firstly stacked together when manufacturing the above-mentioned chip stacking structure, which is beneficial to simplify the process and save the production cost.
  • the second rewiring layer is located on the side of the passive surface of the first chip or the side of the passive surface of the second chip; the above-mentioned multiple chips further include a layer disposed on the first chip and the second chip.
  • the third chip between them; wherein, the active surface of the first chip is opposite to the active surface of the third chip, and the active surface of the second chip faces the passive surface of the third chip; A second dielectric layer between the active side of one chip and the active side of a third chip.
  • the passive surface of the second chip faces the outside of the chip stack structure.
  • the passive surfaces of the first chip and the second chip are both facing the outside of the chip stacking structure, so the passive surfaces of the first chip or the passive surface of the second chip can be located on the side of the passive surface of the first chip or the passive surface of the second chip. side to form a second redistribution layer.
  • the second rewiring layer is located on the active surface of the first chip; the active surface of the second chip faces the passive surface of the first chip.
  • the active surface of the second chip faces the passive surface of the first chip, the two outermost chips, the first chip and the second chip, have the first chip and the second chip.
  • the active surface faces the outside of the chip stack structure, and the passive surface of the second chip faces the outside of the chip stack structure, so a second redistribution layer can be formed on the active surface side of the first chip.
  • the chip stack structure further includes a third dielectric layer disposed between the first redistribution layer and the passive surface of the chip adjacent to the first redistribution layer. Since a third dielectric layer is disposed between the first rewiring layer and the passive surface of the chip adjacent to the first rewiring layer, the third dielectric layer can be formed on the passive surface side of the chip first, and then the third dielectric layer can be formed on the passive surface of the chip. The fusion bonding method bonds two adjacent chips together.
  • the chip stack structure further includes a third redistribution layer disposed on the side of the first redistribution layer away from the chip electrically connected to the first redistribution layer; the third redistribution layer is connected to the first redistribution layer.
  • the redistribution layer is electrically connected, and the second redistribution layer is electrically connected to the third redistribution layer through the first via hole; wherein the thickness of the metal wire layer in the third redistribution layer is greater than that of the metal wire in the first redistribution layer layer thickness.
  • the second redistribution layer is electrically connected to the third redistribution layer through the first via hole, which can ensure The reliability of the electrical connection between the second redistribution layer and the third redistribution layer further improves the reliability of the electrical connection between the second redistribution layer and the chip.
  • the chip stack structure further includes micro-bumps disposed on the side of the second redistribution layer away from the chip and electrically connected to the second redistribution layer. Since the first redistribution layer is electrically connected to the chip, the second redistribution layer is electrically connected to at least one of the first redistribution layers, and the second redistribution layer is electrically connected to the microbumps, so that the microbumps can be electrically connected to at least one chip. connection, and the micro-bumps are used for electrical connection with the package substrate, so as to realize the electrical connection between the chip and the package substrate. In addition, when any two chips in the chip stack structure need to be electrically connected, the connection between any two chips can be realized through the connection between the micro-bumps, so as to realize the communication between any two chips.
  • the chip stack structure further includes a second via hole; any two layers of the first redistribution layers are electrically connected through the second via hole. Since any two layers of the first rewiring layers are electrically connected through the second via hole, any two chips can be electrically connected through the second via hole, so as to realize the communication between any two chips.
  • the electrical connection between two non-adjacent chips needs to be realized through a plurality of via holes, which leads to a complicated process for fabricating the chip stack structure.
  • two non-adjacent chips can be electrically connected through the second via hole, and one second via hole can be fabricated through a single punching process, thus simplifying the fabrication process of the chip stack structure.
  • the chip stack structure further includes a package substrate; and the second redistribution layer is electrically connected to the package substrate. Since the second redistribution layer is electrically connected to the first redistribution layer through the at least one first via hole, and the first redistribution layer is in contact with and electrically connected to the corresponding chip, the at least one chip can be electrically connected to the package substrate.
  • a chip packaging structure in a second aspect, includes a packaging substrate and the above-mentioned chip stacking structure; the second rewiring layer in the chip stacking structure is electrically connected to the packaging substrate. Since the chip package structure has the same technical effect as the foregoing embodiment, it will not be repeated here.
  • an electronic device in a third aspect, includes a printed circuit board and the aforementioned chip stacking structure; the chip stacking structure is electrically connected to the printed circuit board. Since the electronic device has the same technical effect as the foregoing embodiment, it will not be repeated here.
  • a method for fabricating a chip stack structure includes: first, stacking a plurality of chips together in sequence; wherein, a first rewiring layer is formed on one side of the active surface of each chip, and the first rewiring layer is in contact with the corresponding chip and is electrically connected;
  • Each chip includes a first chip and a second chip that are located at the outermost side of a plurality of chips stacked in sequence; next, a plurality of first via holes are formed, and conductive materials are filled in the first via holes;
  • a second rewiring layer is formed on the side of the passive surface of the second chip or the passive surface of the second chip; wherein, the passive surface of the first chip and the passive surface of the second chip are both facing the outside of the stacked multiple chips Or, a second rewiring layer is formed on the active surface side of the first chip; wherein, the passive surface of the second chip faces the outer side of the sequentially stacked multiple chips, and the active surface of the first chip faces the
  • the outer side of the plurality of chips, and the active surface of the first chip is further formed with a first dielectric layer, and the second redistribution layer is located on the side of the first dielectric layer away from the first redistribution layer; the second redistribution layer passes through the first redistribution layer.
  • the via hole is electrically connected to the at least one first redistribution layer.
  • the chip is electrically connected to the first rewiring layer and the second rewiring layer through the first via hole, that is, at least one chip is electrically connected to the second rewiring layer through the first via hole.
  • the second rewiring layer is electrically connected to the external circuit, so as to realize the electrical connection between the chip and the external circuit. Therefore, the embodiment of the present application is beneficial to simplify the fabrication process of the chip stack structure, save the production cost, and improve the production efficiency.
  • the wafer is first diced, and then the dies are stacked. Impurity contamination occurs, requiring die cleaning before stacking.
  • the chip stack structure when the chip stack structure is fabricated, a plurality of wafers can be stacked in sequence, and then the plurality of wafers can be cut, and the chip stack structure obtained after cutting (in this case, the chip is a die) Compared with the cleaning process before the die stacking, the complexity of the cleaning process is greatly reduced.
  • each die needs to undergo die-to-die alignment or die-to-wafer bonding.
  • Alignment since in the embodiment of the present application, in the stacking process of wafer and wafer, only one wafer-to-wafer alignment operation can be performed to achieve the alignment of multiple dies with multiple dies. It can improve production efficiency and reduce production cost.
  • the chip stack structure is fabricated in the embodiment of the present application, a plurality of wafers are directly stacked together in sequence.
  • the present application does not need to inspect the dies one by one, so the production efficiency can also be improved and the production cost can be reduced. Based on this, compared with the prior art, the method for fabricating the chip stack structure in the embodiment of the present application adopts the method of stacking multiple wafers together, which is beneficial to simplify the process and save the production cost.
  • stacking a plurality of chips in sequence includes: stacking a third chip on the first chip; wherein the active surface of the third chip faces the active surface of the first chip; A second dielectric layer is formed between the first rewiring layer of one chip and the first rewiring layer of the third chip; the passive surface of the third chip is thinned, and the second chip is stacked on the third chip.
  • the passive surface of the first chip or the passive surface of the second chip is thinned; wherein, the active surface of the second chip faces the passive surface of the third chip.
  • performing thinning processing on the passive surface of the first chip, and forming a second redistribution layer on the passive surface side of the first chip or the passive surface side of the second chip includes: A second redistribution layer is formed on the passive surface side of the first chip; or, the passive surface of the second chip is thinned, and the passive surface side of the first chip or the passive surface of the second chip is thinned
  • Forming the second redistribution layer on one side includes: forming the second redistribution layer on the passive surface side of the second chip. Since both the passive surface of the first chip and the passive surface of the second chip face the outside of the wafer stack structure, the second chip can be formed on the passive surface side of the first chip or the passive surface side of the second chip. Rewiring layers.
  • the above-mentioned manufacturing method further includes: thinning the passive surface of the second chip; After the second rewiring layer is formed on one side of the passive surface of the two chips, the above manufacturing method further includes: thinning the passive surface of the first chip. This can reduce the thickness of the chip stack structure.
  • the above manufacturing method further includes: forming a second rewiring layer on the side of the second rewiring layer away from the chip.
  • the layers are electrically connected to the microbumps.
  • the second redistribution layer is electrically connected to at least one layer of the first redistribution layer, and the second redistribution layer is electrically connected to the microbumps, so that the microbumps and at least one chip can be realized. electrical connection.
  • the micro-bumps are used for electrical connection with the package substrate, so as to realize the electrical connection between the chip and the package substrate. On this basis, when any two chips in the chip stack structure need to be electrically connected, the connection between any two chips can be realized through the connection between the micro-bumps, so as to realize the communication between any two chips.
  • the above manufacturing method further includes: A third dielectric layer is formed on the source side. In this way, the third chip and the second chip can be electrically connected together by means of fusion bonding.
  • stacking a plurality of chips in sequence includes: stacking the first chip on a carrier; wherein a first dielectric layer is formed between the carrier and the first redistribution layer of the first chip ; carry out thinning processing on the passive surface of the first chip, and stack the second chip on the passive surface of the first chip; wherein, the active surface of the second chip faces the passive surface of the first chip; remove the vector.
  • the carrier is a carrier wafer or a carrier substrate.
  • a second redistribution layer is formed on a side of the first dielectric layer remote from the first chip. Since the active surface of the first chip faces the outside of the chip stack structure, the second redistribution layer can be formed on the active surface side of the first chip.
  • the above-mentioned manufacturing method further includes: thinning the passive surface of the second chip. This can reduce the thickness of the chip stack structure.
  • the above manufacturing method further includes: A side of the second redistribution layer remote from the first dielectric layer forms microbumps electrically connected to the second redistribution layer. Since the formed micro-bumps have the same technical effects as those of the foregoing embodiments, details are not repeated here.
  • the above-mentioned manufacturing method further includes: on the first chip A third dielectric layer is formed on one side of the passive surface. Since the third dielectric layer is formed on the passive surface side of the first chip before stacking the second chip on the passive surface of the first chip, when the second chip is stacked on the passive surface of the first chip , the second chip and the first chip can be stacked together by means of fusion bonding.
  • two adjacent chips are connected together by fusion bonding.
  • fusion bonding to connect two adjacent chips together can avoid organic pollution.
  • problems such as wafer warpage can also be avoided, ensuring the reliability of the process.
  • the active surface of each chip is further formed with a third rewiring layer located on the side of the first rewiring layer away from the chip electrically connected to the first rewiring layer; the third rewiring layer The layer is electrically connected to the first redistribution layer, and the second redistribution layer is electrically connected to the third redistribution layer through the first via hole; wherein, the thickness of the metal wire layer in the third redistribution layer is greater than that in the first redistribution layer the thickness of the metal wire layer. Since the formed third redistribution layer has the same technical effect as that of the previous embodiment, it will not be repeated here.
  • At least one of the plurality of chips is a wafer; a second redistribution layer is formed on the passive surface side of the first chip or the passive surface side of the second chip; After the second rewiring layer is formed on the side of the active surface of the first chip, the above manufacturing method further includes: cutting the wafer to obtain a plurality of chip stacking structures with identical structures and functions.
  • stacking the plurality of chips in sequence includes: stacking the mth chip on the nth chip, and thinning the passive surface of the mth chip; wherein m and n are both A positive integer; a second via hole is formed, and a conductive material is filled in the second via hole; the first redistribution layer of the mth chip and the first redistribution layer of the nth chip are electrically connected through the second via hole.
  • the first rewiring layer of the mth chip and the first rewiring layer of the nth chip are electrically connected through a second via hole, and one second via hole can be fabricated through a single punching process, so it can be The fabrication process of the chip stack structure is simplified.
  • FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • 2a is a schematic structural diagram of a chip stacking structure provided by an embodiment of the present application.
  • FIG. 2b is a schematic structural diagram of a chip stacking structure provided by another embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a chip and a first rewiring layer provided by an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a chip stacking structure provided by the prior art
  • FIG. 5a is a schematic structural diagram of a chip stacking structure according to another embodiment of the present application.
  • FIG. 5b is a schematic structural diagram of a chip stacking structure according to still another embodiment of the present application.
  • FIG. 5c is a schematic structural diagram of a chip stacking structure provided by another embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a method for fabricating a chip stack structure provided by an embodiment of the present application
  • FIG. 7 is a first structural schematic diagram in the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 8 is a second structural schematic diagram in the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 9 is a third structural schematic diagram in the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 10 is a fourth schematic structural diagram in the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram 5 during the process of a method for fabricating a chip stack structure provided by an embodiment of the present application;
  • FIG. 12 is a schematic structural diagram 6 in the process of a method for fabricating a chip stack structure provided by an embodiment of the application;
  • FIG. 13 is a seventh schematic structural diagram in the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram eight in the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram 9 in the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram ten in the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram eleven in the process of a manufacturing method of a chip stack structure provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram 12 during the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram thirteen during the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 20 is a schematic structural diagram fourteen in the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 21 is a fifteenth schematic structural diagram in the process of a method for fabricating a chip stack structure provided by an embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of a chip stacking structure provided by another embodiment of the present application.
  • connection should be understood in a broad sense.
  • connection may be a fixed connection, a detachable connection, or an integrated; It can also be indirectly connected through an intermediary.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or illustrations. Any embodiments or designs described in the embodiments of the present application as “exemplary” or “such as” should not be construed as preferred or advantageous over other embodiments or designs. Rather, use of words such as “exemplary” or “such as” is intended to present the related concepts in a specific manner.
  • Embodiments of the present application provide an electronic device.
  • the electronic device may include CMOS image sensor, NAND flash memory, high bandwidth memory, mobile phone, tablet computer (pad), TV, smart wearable products (eg, smart watch, smart bracelet), virtual reality (virtual reality, etc.) VR) terminal equipment, augmented reality (AR) terminal equipment and other electronic products.
  • the embodiments of the present application do not specifically limit the specific form of the above electronic device.
  • the above-mentioned electronic device 01 may include a chip package structure 02 and a printed circuit board (printed circuit board, PCB).
  • a printed circuit board is not shown in FIG. 1 .
  • the chip package structure 02 includes a chip stack structure 10 and a package substrate 20 , and the chip stack structure 10 is electrically connected to the package substrate 20 .
  • the above-mentioned chip stacking structure 10 includes a plurality of chips 100 stacked in sequence (in FIG. 1 , two chips 100 are used as an example for illustration).
  • the chip stack structure 10 may further include micro bumps (micro bumps, ubumps) 11 , and the package substrate 20 may be electrically connected to the chips 100 through a plurality of micro bumps 11 .
  • the electronic device 01 may further include a connector 30 ; the package substrate 20 in the chip package structure 02 is electrically connected to the printed circuit board through the connector 30 . In this way, the communication between the chip stack structure 10 and the electronic system can be realized.
  • the connectors 30 may be solder balls or micro bumps.
  • the chip stack structure 10 includes: a plurality of chips 100 stacked in sequence and a first redistribution layer 101 (redistribution layer, RDL) disposed on the active surface F of each chip 100; a first redistribution layer 101 (RDL); The rewiring layer 101 is in contact with and electrically connected to the corresponding chip 100 .
  • RDL redistribution layer
  • RDL redistribution layer
  • the chip 100 in the embodiment of the present application may be a die (also referred to as a particle or a bare chip) (die), or may be a wafer (wafer). It can be understood that what is obtained by dicing the wafer is the die. Based on this, in some embodiments, the plurality of chips 100 are all die. In other embodiments, the plurality of chips 100 are wafers. In still other embodiments, the first chip 100a of the plurality of chips 100 is a wafer, and the other chips are die.
  • the plurality of chips 100 in the chip stack structure 10 are stacked in sequence, there are two chips 100 located at the outermost side of the chip stack structure 10 along the stacking direction, that is, the plurality of chips 100 include the chips 100 located in the chip stack structure 10 The outermost first chip 100a and the second chip 100b.
  • the passive surface B of the first chip 100a and the passive surface B of the second chip 100b both face the outside of the chip stack structure 10.
  • the chip stack structure 10 further includes: a passive surface disposed on the first chip 100a The second redistribution layer 102 on the surface B side or the passive surface B side of the second chip 100b.
  • the passive surface B of the second chip 100b faces the outside of the chip stack structure 10
  • the active surface F of the first chip 100a faces the outside of the chip stack structure 10.
  • the chip stack structure 10 further includes: setting The first dielectric layer 103 and the second redistribution layer 102 on the active surface F of the first chip 100 a, the first dielectric layer 103 is located between the first redistribution layer 101 and the second redistribution layer 102 .
  • the second redistribution layer 102 is electrically connected to at least one layer of the first redistribution layer 101 through the first via hole 104 .
  • the number of stacked chips 100 in the chip stack structure 10 is not limited, and the number of stacked chips 100 can be set according to application requirements.
  • the above-mentioned chip 100 may be a memory chip, a logic chip or a chip with any other function.
  • the plurality of chips in the above-mentioned chip stacking structure 10 may be of the same type of chips (for example, the plurality of chips are memory chips); they may also be of different types of chips (for example, the plurality of chips include memory chips and logic chips), that is, the present application
  • the chip stacking structure 10 provided by the embodiment can realize the integration between the same or different types of chips.
  • any chip in this embodiment of the present application may include a substrate and a circuit structure disposed on the substrate, and the circuit structure may enable the chip to perform its own functions, such as logic operations or data storage, during operation.
  • the material constituting the substrate of the chip may include silicon wafer, glass, amorphous silicon (a-Si) or silicon carbide (SiC).
  • the surface of the chip on the side of the circuit structure away from the substrate may be referred to as the active surface F (or front side F) of the chip, and the surface of the substrate away from the circuit structure side may be referred to as the passive surface B (or backside B) of the chip.
  • the first via hole 104 may be formed using a through silicon via (TSV) technology.
  • TSV through silicon via
  • the first redistribution layer 101 may include one or more metal wire layers 105 and one or more insulating layers 106 .
  • the first redistribution layer 101 includes multiple metal wire layers 105
  • two adjacent metal wire layers 105 in the first redistribution layer 101 are separated by an insulating layer 106.
  • the metal wire layers 105 are electrically connected together, so the first redistribution layer 101 further includes via holes disposed on the insulating layer 106 , and two adjacent metal wire layers 105 are electrically connected together through the via holes.
  • the material of the metal wire layer 105 includes, but is not limited to, one material or a combination of two or more materials selected from copper, aluminum, nickel, gold, silver, and titanium.
  • the material of the above-mentioned insulating layer 106 includes, but is not limited to, one material or a combination of two or more materials selected from silicon oxide, silicon nitride, silicon oxynitride, silica gel, and polyimide.
  • the electrical connection between the first redistribution layer 101 and the chip 100 refers to the electrical connection between the metal wire layer 105 in the first redistribution layer 101 and the circuit structure of the active surface F of the chip 100 .
  • the second redistribution layer 102 may also include one or more metal wire layers 105 and one or more insulating layers 106 .
  • the second redistribution layer 102 includes a metal wire layer 105 and an insulating layer 106 .
  • the second redistribution layer 102 is electrically connected to at least one layer of the first redistribution layer 101 through the first via A metal wire layer 105 in a first redistribution layer 101 is electrically connected.
  • each of the first vias 104 is only electrically connected to one layer of the first redistribution layer 101 , that is, each of the first vias 104 is electrically connected to only one chip 100 .
  • the first via hole 104 is filled with conductive material, so that the electrical connection between the second redistribution layer 102 and the first redistribution layer 101 can be realized.
  • the conductive material here can be, for example, copper, aluminum, nickel and other conductive materials with good conductive effect. Since copper has better electrical conductivity, in some embodiments of the present application, the conductive material filled in the first via hole 104 is copper.
  • a plurality of chips 100 stacked in sequence can be regarded as a whole, if the passive surface B of the outermost chip 100 (eg, the first chip 100a or the second chip 100b ) is far away from the active surface F
  • the center of the whole is considered to be the passive surface B of the outermost chip 100 facing the outside of the chip stack structure 10; if the active surface F of the outermost chip 100 is farther from the center of the whole than the passive surface B, Then, it is considered that the active surface F of the chip 100 located on the outermost side faces the outside of the chip stack structure 10 .
  • the two adjacent chips 100 can be connected together by adhesive; the two adjacent chips 100 can also be connected by bonding or the like. connected.
  • the bump 13 is connected to the package substrate 20
  • the chip 100-1 and the chip 100-2 are connected through the second metal layer 14 and the micro-bumps 15, and the chip 100-2 is connected through the silicon vias 16,
  • the collapse-controlled chip connection bumps 13 are connected to the package substrate 20 .
  • the package substrate 20 communicates with the electronic system through the solder balls 17 .
  • the through silicon vias 16 and the micro-bumps 15 need to be formed on the chip 100-1, and then the chip 100-2 is stacked, and the chip 100-2 passes through the second metal
  • the layer 14 , the micro-bumps 15 , the through silicon vias 16 , and the controlled collapse chip connection bumps 13 are electrically connected to the package substrate 20 .
  • through silicon vias 16 and micro-bumps 15 need to be formed on the chip 100-2, and the chip 100-3 passes through the through-silicon vias 16 and the micro-bumps 15,
  • the through-silicon vias 16 and the micro-bumps 15 formed on the chip 100-1 and the control-collapse chip connection bumps 13 are electrically connected to the package substrate 20. It can be seen from this that a plurality of through-silicon vias 16 need to be formed to realize the chip 100- 3.
  • the electrical connection with the package substrate 20 leads to complicated manufacturing process of the chip stack structure 10 .
  • An embodiment of the present application provides a chip stack structure 10, the chip stack structure 10 includes a plurality of chips 100 stacked in sequence and a first rewiring layer 101 disposed on the active surface F of each chip 100; the first rewiring layer 101 is in contact with and electrically connected to the corresponding chip 100 .
  • the plurality of chips includes a first chip 100 a and a second chip 100 b located at the outermost side of the chip stack structure 10 .
  • the chip stack structure 10 further includes: disposed on the side of the passive surface B of the first chip 100a Or the second redistribution layer 102 on the passive surface B side of the second chip 100b.
  • the chip stacking structure 10 further includes: disposed on the first chip The first dielectric layer 103 and the second redistribution layer 102 of the active face F of 100a, the first dielectric layer 103 is located between the first redistribution layer 101 and the second redistribution layer 102.
  • the second redistribution layer 102 is electrically connected to at least one layer of the first redistribution layer 101 through the first via hole 104 .
  • a via hole needs to be formed on the previous chip 100 , and the latter chip 100 is electrically connected to the previous chip 100 through the via hole.
  • the electrical connection between the chip 100 and an external circuit eg, a package substrate is realized, so that the fabrication process of the chip stack structure is complicated.
  • the second redistribution layer 102 is electrically connected to at least one layer of the first redistribution layer 101 through the first vias 104, and each layer of the first redistribution layer 101 is electrically connected to the corresponding chip 100, at least A chip 100 can be directly electrically connected to the second rewiring layer 102 through a first via 104, and the second rewiring layer 102 is used for electrical connection with an external circuit, so as to realize the electrical connection between the chip 100 and the external circuit, and each The first via hole 104 can be formed by a one-time drilling process, which is beneficial to simplify the fabrication process of the chip stack structure 10 , save the production cost, and improve the production efficiency.
  • the chip stack structure 10 shown in FIG. 4 is fabricated by the die-to-die bonding technology, since the chip 100-1 and the chip 100-2 need to undergo wafer dicing first, the dicing process will generate impurity contamination Therefore, before stacking the chip 100-1 and the chip 100-2, the chip 100-1 and the chip 100-2 need to be cleaned, and the cleaning process is complicated. In addition, in the process of stacking the chip 100 - 1 and the chip 100 - 2 , alignment needs to be performed.
  • the chips need to be tested one by one, which will also lead to lower production efficiency and increased production costs. Since the die-to-wafer bonding technology is used to fabricate the chip stack structure 10, it is also necessary to cut the wafer, align the chip with the wafer, and check whether the chip is qualified, etc., which will also lead to lower production efficiency. , increase the production cost and other issues, which will not be described in detail here.
  • the wafer is cut first, and then the die is stacked. Since the cutting process of the wafer will produce impurity pollution, it is The dies need to be cleaned before stacking them.
  • the cleaning process is much less complicated than the cleaning process before die stacking.
  • each die needs to undergo die-to-die alignment or die-to-wafer bonding. Alignment, since in the embodiment of the present application, in the stacking process of wafer and wafer, only one wafer-to-wafer alignment operation can be performed to achieve the alignment of multiple dies with multiple dies.
  • the chip stack structure 10 is fabricated in the embodiment of the present application, a plurality of wafers are directly stacked together in sequence. Therefore, compared with the die-to-die bonding technology and the die-to-wafer technology in the prior art The present application does not need to inspect the crystal grains one by one, so the production efficiency can also be improved and the production cost can be reduced. Based on this, compared with the prior art, in the embodiment of the present application, when manufacturing the above-mentioned chip stacking structure 10, a plurality of wafers are firstly stacked together, which is beneficial to simplify the process and save the production cost.
  • the chip stack structure 10 further includes a micro-bump 11 disposed on the side of the second redistribution layer 102 away from the chip 100 and electrically connected to the second redistribution layer 102 .
  • the first redistribution layer 101 is electrically connected to the chip 100
  • the second redistribution layer 102 is electrically connected to at least one first redistribution layer 101
  • the second redistribution layer 102 is electrically connected to the micro-bumps 11
  • the micro-bumps 11 are electrically connected to at least one chip 100
  • the micro-bumps 11 are used for electrical connection with the aforementioned packaging substrate 20 , so that the chip 100 and the packaging substrate 20 can be electrically connected.
  • connection between any two chips 100 can be realized through the connection between the micro-bumps 11 to realize the connection between any two chips 100 Communication.
  • the chip stack structure 10 further includes a second via hole 112; any two layers of the first rewiring layer 101 are electrically connected through the second via hole 112, that is, any two chips are electrically connected through the second via hole 112.
  • the 100 is electrically connected through the second via hole 112 to realize communication between any two chips 100 .
  • the two chips 100 that are electrically connected to any two of the above-mentioned first redistribution layers 101 may or may not be adjacent.
  • the first redistribution layer 101 electrically connected to the third chip 100 c and the first redistribution layer 101 electrically connected to the fifth chip 100 e are electrically connected through the second via holes 112 .
  • two non-adjacent chips 100 can be electrically connected through the second via hole 112 , and one second via hole 112 can be fabricated through a single punching process, thus simplifying the fabrication process of the chip stack structure 10 .
  • the The second via hole 112 passes through the third chip 100c, the fourth chip 100d and the fifth chip 100e, so as to realize the electrical connection between the third chip 100c and the fifth chip 100e.
  • the chip 100 further includes a third chip 100c disposed between the first chip 100a and the second chip 100c; wherein, the active surface F of the first chip 100a and the active surface F of the third chip 100c are opposite, and the second chip 100b The active surface F faces the passive surface B of the third chip 100c; the chip stack structure 10 further includes a second dielectric layer disposed between the active surface F of the first chip 100a and the active surface F of the third chip 100c 107.
  • the chip stack structure 10 further includes a fourth chip 100d
  • the fourth chip 100d is stacked on the third chip 100c
  • the active surface F of the fourth chip 100d faces the third chip 100d.
  • the chip stack structure 10 further includes the fifth chip 100e
  • the fifth chip 100e is stacked on the fourth chip 100d
  • the active surface F of the fifth chip 100e faces the passive surface B of the fourth chip 100d; and so on. , and will not be repeated here.
  • the second redistribution layer 102 is located on the passive surface B side of the first chip 100a or the passive surface B side of the second chip 100b, in the stacking direction (The stacking direction is indicated by thick arrows in FIG. 5a), except for the first chip 100a and the third chip 100c, the active surface F of the latter chip faces the passive surface B of the previous chip 100; the first chip 100a has a The source surface F is opposite to the active surface F of the third chip 100c; the chip stack structure 10 further includes a second dielectric layer 107 disposed between the active surface F of the first chip 100a and the active surface F of the third chip 100c .
  • FIG. 5a illustrates by taking an example that the second redistribution layer 102 is located on the passive surface B side of the second chip 100b.
  • the second dielectric layer 107 disposed between the active surface F of the first chip 100a and the active surface F of the third chip 100c can connect the active surface F of the first chip 100a to the active surface F of the third chip 100c
  • the source faces F are spaced apart.
  • the second dielectric layer 107 can be formed on the active surface F of the first chip 100a, and then the first chip 100a and the third chip 100c can be bonded together by fusion bonding;
  • the second dielectric layer 107 is formed on the active surface F of the third chip 100c, and the first chip 100a and the third chip 100c are bonded together by fusion bonding.
  • the passive surface B of the first chip 100a faces the outside of the chip stack structure 10 .
  • the passive surface B of the last chip ie, the second chip 100 b .
  • the passive surfaces of the first chip 100a and the passive surface of the second chip 100b of the two outermost chips are both facing the outside of the chip stack structure 10 .
  • the first via hole 104 can be fabricated from the last chip, that is, the passive surface B of the second chip 100b. Except for the first chip 100a, for other chips 100, the fabrication When the first via hole 104 is used, the first via hole 104 penetrates from the passive surface B of the chip 100 to the active surface F of the chip 100 , so this punching method can also be called a back punching method, that is, using A plurality of first vias 104 are formed by back drilling.
  • the second redistribution layer 102 is located on the passive surface B of the second chip 100b.
  • the first vias 104 can also be fabricated from the passive surface B of the first chip 100a.
  • the first vias 104 are all formed by the chips 100.
  • the active surface F penetrates to the passive surface B of the chip 100, so this punching method can also be called a front-side punching method, that is, a plurality of first vias 104 are formed by using the front-side punching method.
  • the second redistribution layer 102 is located on the passive surface B of the first chip 100a.
  • the active surface F of the second chip 100b faces the passive surface of the first chip 100a face B.
  • the chip stack structure 10 when the chip stack structure 10 further includes the third chip 100c, the third chip 100c is stacked on the first chip 100a, and the active surface F of the third chip 100c faces the third chip 100c.
  • the chip stack structure 10 further includes the fourth chip 100d, the fourth chip 100d is stacked on the third chip 100c, and the active surface F of the fourth chip 100d faces the passive surface B of the third chip 100c.
  • the chip stack structure 10 further includes the fifth chip 100e
  • the fifth chip 100e is stacked on the fourth chip 100d, and the active surface F of the fifth chip 100e faces the passive surface B of the fourth chip 100d; and so on. , and details are not repeated here; finally, the second chip 100b is stacked.
  • the active surface F of the subsequent chip 100 faces the passive surface B of the previous chip 100
  • the two outermost chips namely the first chip 100a and the second chip 100b
  • the active surface F of the first chip 100 a faces the outside of the chip stack structure 10
  • the passive surface B of the second chip 100 b faces the outside of the chip stack structure 10 .
  • the first vias 104 can be formed from the active surface F of the first chip 100a.
  • the first vias 104 are fabricated, the first via The holes 104 are all penetrated from the active surface F of the chip 100 to the passive surface B of the chip 100. Therefore, this punching method can also be called a front-side punching method, that is, a front-side punching method is used to form a plurality of first holes. hole 104 .
  • the chip stack structure 10 further includes a first redistribution layer 101 disposed between the first redistribution layer 101 and the passive surface B of the chip 100 adjacent to the first redistribution layer 101 . the third dielectric layer 108 .
  • the third dielectric layer 108 is disposed between the first redistribution layer 101 and the passive surface F of the chip 100 adjacent to the first redistribution layer 101 , the third dielectric layer 108 can be formed on the passive surface B side of the chip 100 first.
  • the third dielectric layer 108 is used to bond two adjacent chips 100 together by fusion bonding.
  • the materials of the first dielectric layer 103 , the second dielectric layer 107 and the third dielectric layer 108 may be the same or different.
  • the materials of the first dielectric layer 103, the second dielectric layer 107 and the third dielectric layer 108 may be one or more of silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (SiOxNy) .
  • the chip stack structure 10 further includes a chip 100 disposed on the first redistribution layer 101 away from the first redistribution layer 101 electrically connected to the first redistribution layer 101 .
  • the third redistribution layer 109 on the side; the third redistribution layer 109 is electrically connected to the first redistribution layer 101, and the second redistribution layer 102 is electrically connected to the third redistribution layer 109 through the first via 104; wherein, The thickness of the metal wire layer 105 in the third redistribution layer 109 is greater than the thickness of the metal wire layer 105 in the first redistribution layer 101 .
  • the third redistribution layer 109 includes one or more metal wire layers 105 and one or more insulating layers 106 .
  • the third redistribution layer 109 includes a metal wire layer 105 and an insulating layer 106 .
  • the second redistribution layer 102 is electrically connected to the third redistribution layer 109 through the first via hole 104" refers to that the metal wire layer 105 in the second redistribution layer 102 is connected to the third redistribution layer 109 through the first via hole 104.
  • the metal wire layer 105 in the third redistribution layer 109 is electrically connected.
  • the second redistribution layer 102 since the thickness of the metal wire layer 105 in the third redistribution layer 109 is greater than the thickness of the metal wire layer 105 in the first redistribution layer 101 , the second redistribution layer 102 passes through the first via hole 104 The electrical connection between the second redistribution layer 102 and the third redistribution layer 109 can ensure the reliability of the electrical connection between the second redistribution layer 102 and the third redistribution layer 109 , thereby improving the reliability of the electrical connection between the second redistribution layer 102 and the chip 100 .
  • Embodiments of the present application further provide a method for fabricating a chip stack structure, which can be used to fabricate the above-mentioned chip stack structure 10 .
  • the fabrication method of the chip stack structure includes:
  • the plurality of chips 100 include a first chip 100a and a second chip 100b located at the outermost side of the plurality of chips stacked in sequence.
  • the chip 100 in the embodiment of the present application may be a die; it may also be a wafer. Based on this, in some embodiments, the plurality of chips 100 are all die. In other embodiments, the plurality of chips 100 are wafers. In still other embodiments, the first chip 100a of the plurality of chips 100 is a wafer, and the other chips are die.
  • the surfaces of the chips 100 need to be cleaned before stacking the plurality of chips 100 together.
  • the electrical connection between the first redistribution layer 101 and the corresponding chip 100 means that the metal wire layer 105 in the first redistribution layer 101 is electrically connected to the circuit structure of the active surface F of the chip 100 .
  • the two adjacent chips 100 may be connected together by an adhesive; the two adjacent chips 100 may also be connected together by means of bonding or the like.
  • the number of sequentially stacked chips 100 can be set according to application requirements. For example, four or six chips 100 may be stacked together in sequence.
  • the first via holes 104 may be formed in the plurality of chips 100 stacked in sequence formed in S10 by means of dry etching or wet etching. Specifically, a plurality of first via holes 104 may be formed by using a through silicon via technology.
  • the conductive material can be filled in the first via hole 104 by chemical vapor deposition, sputter deposition, ion beam deposition, physical vapor deposition, atomic layer deposition, molecular beam epitaxy, and other methods.
  • the conductive material can be, for example, copper, aluminum, nickel and other conductive materials with good conductive effect. Since copper has better electrical conductivity, in some embodiments of the present application, the conductive material filled in the first via hole 104 is copper.
  • the plurality of first via holes 104 with different depths may be fabricated simultaneously or separately.
  • step S12 can be implemented in the following two manners.
  • S12 when both the passive surface B of the first chip 100a and the passive surface B of the second chip 100b face the outside of the multiple chips 100 stacked in sequence, S12 includes:
  • a second redistribution layer 102 is formed on the passive surface B side of the first chip 100a or the passive surface B side of the second chip 100b; wherein the second redistribution layer 102 is connected to at least one layer through the first via 104
  • the first redistribution layer 101 is electrically connected; the second redistribution layer 102 is used to electrically connect the first redistribution layer 101 with the package substrate 20 .
  • S12 includes:
  • a second redistribution layer 102 is formed on the active surface F side of the first chip 100a; the second redistribution layer 102 is located on the side of the first dielectric layer 103 away from the first redistribution layer 101; wherein the second redistribution layer 102 is electrically connected to at least one layer of the first redistribution layer 101 through the first via hole 104 ; the second redistribution layer 102 is used to electrically connect the first redistribution layer 101 to the package substrate 20 .
  • the structure of the second redistribution layer 102 can be referred to the above, and details are not repeated here.
  • the above-mentioned manufacturing method further includes:
  • step S13 is an optional step, and this step may be omitted when multiple chips are all die.
  • An embodiment of the present application provides a method for fabricating a chip stack structure.
  • the fabrication method for the chip stack structure includes first stacking a plurality of chips 100 together in sequence; A redistribution layer 101, the first redistribution layer 101 is in contact with and electrically connected to the corresponding chip 100; the plurality of chips 100 includes a first chip 100a and a second chip 100b located at the outermost side of the plurality of chips 100 stacked in sequence; next, A plurality of first vias 104 are formed, and conductive materials are filled in the first vias 104; next, the passive surface B of the first chip 100a and the passive surface B of the second chip 100b are both facing the stacked multiple In the case of the outside of the first chip 100, the second redistribution layer 102 is formed on the passive surface B side of the first chip 100a or the passive surface B side of the second chip 100b; wherein the second redistribution layer 102 passes through The first via hole 104 is electrically connected to at least one layer of the first redistribution
  • a second rewiring is formed on the side of the active surface F of the first chip 100a layer 102; the second redistribution layer 102 is located on the side of the first dielectric layer 103 away from the first redistribution layer 101; wherein the second redistribution layer 102 communicates with at least one layer of the first redistribution layer 101 through the first via 104 electrical connection.
  • a via hole 104 is fabricated by one-time drilling, and the first via hole 104 is used to electrically connect the chip 100 to the first rewiring layer 101 and the second rewiring layer 102, that is, at least one chip 100 passes through the first rewiring layer 101.
  • the via hole 104 is electrically connected to the second redistribution layer 102 , and the second redistribution layer 102 is electrically connected to the external circuit, so as to realize the electrical connection between the chip 100 and the external circuit. Therefore, the embodiment of the present application is conducive to simplifying the chip stacking structure 10 .
  • the production process saves production costs and improves production efficiency.
  • the wafer is first diced, and then the dies are stacked. Impurity contamination occurs, requiring die cleaning before stacking.
  • the chip stack structure 10 when the chip stack structure 10 is fabricated, a plurality of wafers can be stacked in sequence, and then the wafers can be cut, and the chip stack structure 10 obtained after cutting (in this case, the chips are Compared with the cleaning process before the grains are stacked, the cleaning process of the grains is much less complicated.
  • each die needs to undergo die-to-die alignment or die-to-wafer bonding.
  • Alignment since in the embodiment of the present application, in the stacking process of wafer and wafer, only one wafer-to-wafer alignment operation can be performed to achieve the alignment of multiple dies with multiple dies. It can improve production efficiency and reduce production cost.
  • the chip stack structure 10 is fabricated in the embodiment of the present application, a plurality of wafers are directly stacked together in sequence.
  • the present application does not need to inspect the crystal grains one by one, so the production efficiency can also be improved and the production cost can be reduced. Based on this, compared with the prior art, the method for fabricating the chip stack structure 10 according to the embodiment of the present application adopts stacking a plurality of wafers together, which is beneficial to simplify the process and save the production cost.
  • the embodiment of the present application makes The chip stack structure 10 can improve the yield of the chip stack structure 10 in other ways. For example, in the process of manufacturing the chip stack structure 10, increasing the number of stacked wafers, that is, increasing the number of die in the chip stack structure 10, can A corresponding function is realized by a qualified die; or, using a redundant method, a function corresponding to one die in the prior art is realized by a plurality of die.
  • the active surface F of each chip 100 is further formed with a third redistribution layer 109 located on the side of the first redistribution layer 101 away from the chip 100 electrically connected to the first redistribution layer 101 ;
  • the third redistribution layer 109 is electrically connected to the first redistribution layer 101, and the second redistribution layer 102 is electrically connected to the third redistribution layer 109 through the first via 104; wherein, the metal wire layer in the third redistribution layer 109
  • the thickness of 105 is greater than the thickness of the metal wire layer 105 in the first redistribution layer 101 .
  • the second redistribution layer 102 since the thickness of the metal wire layer 105 in the third redistribution layer 109 is greater than the thickness of the metal wire layer 105 in the first redistribution layer 101 , the second redistribution layer 102 passes through the first via hole 104 The electrical connection between the second redistribution layer 102 and the third redistribution layer 109 can ensure the reliability of the electrical connection between the second redistribution layer 102 and the third redistribution layer 109 , thereby improving the reliability of the electrical connection between the second redistribution layer 102 and the chip 100 .
  • manufacturing the chip stack structure 10 shown in FIG. 5a specifically includes the following steps:
  • the second dielectric layer 107 can be formed on the side of the first redistribution layer 101 of the first chip 100a away from the first chip 100a; the first redistribution layer 101 of the third chip 100c can also be formed away from the third chip 100c A second dielectric layer 107 is formed on one side.
  • FIG. 7 illustrates the formation of the second dielectric layer 107 on the side of the first redistribution layer 101 of the first chip 100a away from the first chip 100a as an example.
  • first chip 100a and the third chip 100c can be connected together by adhesive; they can also be connected together by fusion bonding.
  • organic contamination the adhesive is usually an organic substance
  • the warping of the wafer can also be avoided. Qu and other problems, to ensure the reliability of the process.
  • the chip stack structure 10 further includes the fourth chip 100d
  • the fourth chip 100d after thinning the passive surface B of the third chip 100c, the fourth chip 100d is stacked on the passive surface of the third chip 100c.
  • Surface B the active surface F of the fourth chip 100d faces the passive surface B of the third chip 100c, and the passive surface B of the fourth chip 100d is thinned
  • the chip stack structure 10 further includes a fifth chip 100e
  • thinning processing is performed on the passive surface B of the fourth chip 100d
  • the fifth chip 100e is stacked on the passive surface B of the fourth chip 100d
  • the active surface F of the fifth chip 100e faces the fourth chip 100d
  • the passive surface B of the fifth chip 100e is thinned, and so on, and will not be repeated here
  • the second chip 100b is stacked, and the passive surface B of the second chip 100b is thinned. Perform thinning processing.
  • the passive surface B of the chip 100 may be thinned to a desired thickness by means of physical grinding and/or chemical mechanical polishing.
  • the range of the final thickness h of the chip 100 is 0 ⁇ h ⁇ 100 ⁇ m.
  • two adjacent chips 100 may be connected together by adhesive; they may also be connected by fusion bonding.
  • a method for fabricating the chip stack structure 10 It also includes: forming a third dielectric layer 108 on the passive surface B side of the third chip 100c.
  • the second chip 100b Since the third dielectric layer 108 is formed on the passive surface B side of the third chip 100c before stacking the second chip 100b on the passive surface B of the third chip 100c, the second chip 100b is stacked on the first When there are three passive surfaces B of the chips 100c, the second chip 100b and the third chip 100c may be stacked together by means of fusion bonding. Compared with connecting by adhesive, organic contamination can be avoided by adopting fusion bonding (the adhesive is usually organic), and when the second chip 100b and/or the third chip 100c are wafers, it can also be avoided. Wafer warpage and other issues ensure the reliability of the process.
  • Step S21 will be described in detail below.
  • the passive surface B of the third chip 100c is thinned; then, as shown in FIG. A third dielectric layer 108 is formed on the side of the source surface B; next, as shown in FIG. 10 , the fourth chip 100d is stacked on the passive surface B of the third chip 100c, and the active surface F of the fourth chip 100d faces the third chip 100d.
  • the passive surface B of the chip 100c is thinned, and the passive surface B of the fourth chip 100d is thinned; and so on, as shown in FIG.
  • the passive surface B is thinned.
  • a plurality of first vias 104 are formed from one side of the second chip 100b, and conductive material is filled in the first vias 104.
  • the wiring layer 101 is electrically connected.
  • first vias 104 are formed from one side of the second chip 100b. Except for the first chip 100a in the stacking direction, for other chips, when making the first vias 104, the first vias 104 is penetrated from the passive surface B of the chip 100 to the active surface F of the chip 100, so this punching method can also be called a back punching method, that is, a plurality of first vias are formed by using the backside punching method. 104.
  • each A via hole 104 is electrically connected to a third redistribution layer 109 .
  • a second redistribution layer 102 is formed on the last chip 100, that is, on the passive surface B side of the second chip 100b .
  • this step is an optional step, and may be omitted, for example, in some embodiments.
  • the passive surface B of the first chip 100a may be thinned to a desired thickness by means of physical grinding and/or chemical mechanical polishing.
  • the above-mentioned manufacturing method further includes:
  • step S25 and step S26 may be interchanged. For example, step S25 is performed first, and then step S26 is performed. For another example, step S26 is performed first, and then step S25 is performed.
  • step S26 is an optional step, and this step can be omitted in the case that the plurality of chips are all die.
  • steps S21 , S22 , S23 , S24 and S25 can also be created by referring to the following steps.
  • the chip stack structure 10 further includes the fourth chip 100d
  • the fourth chip 100d after thinning the passive surface B of the third chip 100c, the fourth chip 100d is stacked on the passive surface of the third chip 100c.
  • Surface B the active surface F of the fourth chip 100d faces the passive surface B of the third chip 100c, and the passive surface B of the fourth chip 100d is thinned
  • the chip stack structure 10 further includes a fifth chip 100e
  • thinning processing is performed on the passive surface B of the fourth chip 100d
  • the fifth chip 100e is stacked on the passive surface B of the fourth chip 100d
  • the active surface F of the fifth chip 100e faces the fourth chip 100d
  • the passive surface B of the fifth chip 100e is thinned and processed; and so on, which will not be repeated here; finally, the second chip 100b is stacked.
  • first vias 104 are formed from one side of the first chip 100a. Except for the first chip 100a in the stacking direction, for other chips 100, when making the first vias 104, the The holes 104 are all penetrated from the active surface F of the chip 100 to the passive surface B of the chip 100. Therefore, this punching method can also be called a front-side punching method, that is, a front-side punching method is used to form a plurality of first holes. hole 104 .
  • a second redistribution layer 102 is formed on the passive surface B side of the first chip 100a.
  • micro-bumps 11 electrically connected to the second redistribution layer 102 on the side of the second redistribution layer 102 away from the first chip 100a.
  • this step is an optional step, and may be omitted, for example, in some embodiments.
  • manufacturing the chip stack structure 10 as shown in FIG. 5b specifically includes the following steps:
  • the first dielectric layer 103 can be formed on the side of the first redistribution layer 101 of the first chip 100a away from the first chip 100a; the first dielectric layer 103 can also be formed on the side of the carrier 40 facing the first chip 100a .
  • FIG. 15 illustrates the formation of the first dielectric layer 103 on the side of the carrier 40 facing the first chip 100 a as an example.
  • the above-mentioned carrier 40 is a carrier chip. In other embodiments, the above-mentioned carrier 40 is a carrier substrate. Wherein, the material of the carrier substrate may be one or more of glass, silicon oxide, silicon nitride, and silicon oxynitride.
  • the carrier 40 is a carrier chip and the first dielectric layer 103 is formed on the side of the carrier 40 facing the first chip 100 a
  • the first dielectric layer 103 may be formed on the active surface F side of the carrier chip 100 .
  • the first chip 100a and the carrier 40 can be connected together by using adhesive; they can also be connected together by means of fusion bonding.
  • the first chip 100a and the carrier 40 are connected together by fusion bonding, organic contamination can be avoided, and in the case where the first chip 100a is a wafer, problems such as wafer warpage can also be avoided, and the process is ensured reliability.
  • first chip 100a and the second chip 100b may be connected together by adhesive; they may also be connected by fusion bonding.
  • the chip stack structure 10 further includes a third chip 100c
  • the third chip 100c is stacked on the first chip 100c.
  • the active surface F of the third chip 100c faces the passive surface B of the first chip 100a, and the passive surface B of the third chip 100c is thinned;
  • the chip stack structure 10 further includes a fourth In the case of the chip 100d, the fourth chip 100d is stacked on the passive surface B of the third chip 100c, the active surface F of the fourth chip 100d faces the passive surface B of the third chip 100c, and the The passive surface B is thinned;
  • the chip stack structure 10 further includes the fifth chip 100e
  • the fifth chip 100e is stacked on the passive surface B of the fourth chip 100d, and the active surface F of the fifth chip 100e Facing the passive surface B of the fourth chip 100d
  • thinning processing is performed on the passive surface B of the fifth chip 100e; and so on
  • a method for fabricating the chip stack structure 10 It also includes: forming a third dielectric layer 108 on the passive surface B side of the first chip 100a.
  • the third dielectric layer 108 is formed on the passive surface side of the first chip 100a before the second chip 100b is stacked on the passive surface B of the first chip 100a,
  • the first chip 100a and the second chip 100b may be stacked together by means of fusion bonding.
  • organic contamination can be avoided by adopting fusion bonding (the adhesive is usually an organic substance), and in the case where the first chip 100a and the second chip 100b are wafers, the warping of the wafer can also be avoided. Qu and other problems, to ensure the reliability of the process.
  • the carrier 40 may be removed by cutting; the carrier 40 may also be removed by physical grinding and chemical mechanical polishing.
  • S43 form a plurality of first vias 104 from one side of the first dielectric layer 103 , and fill the first vias 104 with conductive material, each of the first vias 104 and a layer of first The wiring layer 101 is electrically connected.
  • first vias 104 are all formed by the active source of the chip 100 .
  • the surface F penetrates the passive surface of the chip 100 , so the punching method can also be called a front-side punching method, that is, a plurality of first vias 104 are formed by using the front-side punching method.
  • each A via hole 104 is electrically connected to a third redistribution layer 109 .
  • a second redistribution layer 102 is formed on the side of the first dielectric layer 103 away from the first chip 100a.
  • micro-bumps 11 electrically connected to the second redistribution layer 102 on the side of the second redistribution layer 102 away from the first dielectric layer 103 .
  • this step is an optional step, and may be omitted, for example, in some embodiments.
  • the passive surface B of the second chip 100b may be thinned to a desired thickness by means of physical grinding and/or chemical mechanical polishing.
  • the above-mentioned manufacturing method further includes:
  • step S45 is performed first, and then step S46 is performed.
  • step S46 is performed first, and then step S45 is performed.
  • step S46 is an optional step, and this step can be omitted when the plurality of chips are all die.
  • carrier 40 is a carrier wafer
  • one carrier wafer will be consumed when the chip stack structure 10 is fabricated according to S40-S46.
  • stacking the plurality of chips 100 in sequence includes: stacking the mth chip 100m on the nth chip 100n, and thinning the passive surface B of the mth chip 100m; wherein, m, n are both positive integers; the active surface F of the mth chip faces the nth chip; the second via hole 112 is formed, and the conductive material is filled in the second via hole 112; the first rewiring layer of the mth chip 100m 101 and the first rewiring layer 101 of the nth chip 100n are electrically connected through the second via hole 112 .
  • the m-th chip 100m and the n-th chip 100n may or may not be adjacent.
  • the manufacturing process of the second via hole 112 is described below by taking the mth chip 100m as the fifth chip 100e and the nth chip 100n as the third chip 100c as an example.
  • the third chip 100c is stacked on the first chip 100a, the active surface F of the third chip 100c faces the passive surface B of the first chip 100a, and the passive surface B of the third chip 100c faces the passive surface B of the third chip 100c.
  • Thinning processing is performed; the fourth chip 100d is stacked on the third chip 100c, the active surface F of the fourth chip 100d faces the passive surface B of the third chip 100c, and the passive surface B of the fourth chip 100d is Thinning process: stack the fifth chip 100e on the fourth chip 100d, the active surface F of the fifth chip 100e faces the passive surface B of the fourth chip 100d, and reduce the passive surface B of the fifth chip 100e Thin processing; next, a second via hole 112 is formed and filled with conductive material, the second via hole 112 is connected to the first rewiring layer 101 of the third chip 100c and the first redistribution layer 101 of the fifth chip 100e The redistribution layers 101 are all in contact, so that the first redistribution layer 101 of the fifth chip 100e and the first redistribution layer 101 of the third chip 100c can be electrically connected together through the second via hole 112, and finally the third chip 100c and Electrical connection of the fifth chip 100e.
  • the m-th chip 100m and the n-th chip 100n are not adjacent to each other, in order to realize the electrical connection between the m-th chip 100m and the n-th chip 100n, it is necessary to form a plurality of via holes, which leads to the fabrication of a chip stack.
  • the process of the structure 10 is complicated.
  • the first rewiring layer 101 of the mth chip 100m and the first rewiring layer 101 of the nth chip 100n are electrically connected through the second via holes 112 , and one second via hole 112 can be drilled at one time.
  • the hole process is used for fabrication, so the fabrication process of the chip stack structure 10 can be simplified.
  • a specific embodiment is provided below to exemplarily introduce the above-mentioned chip stack structure 10 and a manufacturing method thereof.
  • the chip stack structure 10 includes one or more memory chips 110 and one or more logic chips 111 stacked in sequence
  • FIG. 22 takes the case of including four memory chips 110 and one logic chip 111 stacked in sequence as an example
  • the active surface F of each logic chip 111 and memory chip 110 is formed with a first rewiring layer 101 and a third rewiring layer 109
  • the first rewiring layer 101 is in contact with and electrically connected to the logic chip 111 and the memory chip 110
  • the first redistribution layer 101 and the third redistribution layer 109 are electrically connected.
  • the chip stack structure 10 further includes a third dielectric layer 108 disposed between the first redistribution layer 101 and the passive surface B of the chip 100 adjacent to the first redistribution layer 101, and a third redistribution layer for each layer. 109 A plurality of first vias 104 electrically connected, the first dielectric layer 103 disposed on the active surface F of the logic chip 111, the second redistribution layer 102 disposed on the side of the first dielectric layer 103 away from the logic chip 111 and the micro-bumps 11 disposed on the side of the second redistribution layer 102 away from the first dielectric layer 103 .
  • the chip stack structure 10 can be applied to realize high bandwidth memory. As needed, more memory chips 110 can be stacked to achieve higher bandwidth.
  • the chip stack structure 10 shown in FIG. 22 adopts a front-side drilling process to form a plurality of first vias 104 .
  • the first vias 104 penetrate from the active surface F to the passive surface B during drilling.
  • the carrier 40 is a carrier wafer, one carrier wafer will be consumed.
  • each first via hole 104 is formed by a one-time drilling process, and each logic chip 111 and memory chip 110 can be electrically connected to the second rewiring layer 102 through the first via hole 104 , thus simplifying the fabrication process of the chip stack structure 10 .
  • a plurality of first vias 104 can also be formed by using the backside punching process, and the backside punching process does not need to consume a carrier wafer.
  • a non-transitory computer-readable storage medium for use with a computer, the computer having software for creating and fabricating the above-mentioned chip stack structure 10, the computer-readable storage medium having stored thereon
  • One or more computer readable data structures having control data, such as photomask data, for fabricating the chip stack structure 10 provided by any of the illustrations provided above.

Abstract

本申请实施例提供一种芯片堆叠结构及其制作方法、芯片封装结构、电子设备，涉及芯片技术领域，可以降低制作芯片堆叠结构的生产成本，提高生产效率。芯片堆叠结构包括依次堆叠的多个芯片以及设置于每个芯片有源面的第一重新布线层；多个芯片包括位于最外侧的第一芯片和第二芯片；第一芯片和第二芯片的无源面均朝向外侧，芯片堆叠结构还包括设置于第一芯片或第二芯片的无源面的第二重新布线层；或者，第二芯片无源面朝向外侧，第一芯片有源面朝向外侧，芯片堆叠结构还包括设置于第一芯片的有源面的第一电介质层和第二重新布线层，第一电介质层位于第一重新布线层和第二重新布线层之间；第二重新布线层通过第一过孔与至少一层第一重新布线层电连接。

Description

芯片堆叠结构及其制作方法、芯片封装结构、电子设备 技术领域
本申请涉及芯片技术领域，尤其涉及一种芯片堆叠结构及其制作方法、芯片封装结构、电子设备。
背景技术
随着半导体技术的快速发展，传统的通过缩减二维(2D，2dimensions)晶体管沟道尺寸来获得芯片性能提升的方法已出现一些问题，例如迁移率降低，短沟道效应等。目前，将芯片制造从二维转到三维(3D)为提升芯片性能提供新的方向。
3D芯片(也可以称为3D IC(integrated circuit，集成电路))堆叠技术可以将多颗芯片集成在一起，从而提升芯片性能、减小功耗、降低生产成本、缩减封装尺寸、缩短加工周期，并显著提升芯片的集成度。3D芯片堆叠技术已被许多半导体制造商成功应用于生产CMOS(complementary metal oxide semiconductor，互补金属氧化物半导体)图像传感器、NAND flash(闪存)、高带宽存储器(high bandwidth memory，HBM)等产品，并大幅提升了产品性能。
目前，3D芯片堆叠技术包括晶粒与晶粒键合(die-to-die bonding，D2D bonding)、晶粒与晶圆键合(die-to-wafer bonding，D2W bonding)以及晶圆与晶圆键合(wafer-to-wafer bonding，W2W bonding)三种。然而，无论采用D2D bonding、D2W bonding，还是W2W bonding制作芯片堆叠结构，在堆叠后一芯片(芯片例如可以为晶粒或晶圆)之前，都需要在前一芯片上形成过孔，后一芯片通过过孔与前一芯片电连接，这样就需要形成多次过孔，才能实现芯片与外部电路(例如封装基板)的电连接，从而导致芯片堆叠结构的制作工序复杂，提高了制作芯片堆叠结构的生产成本，降低了生产效率。
发明内容
本申请实施例提供一种芯片堆叠结构及其制作方法、芯片封装结构、电子设备，可以降低制作芯片堆叠结构的生产成本，提高生产效率。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种芯片堆叠结构。该芯片堆叠结构包括依次堆叠的多个芯片以及设置于每个芯片的有源面的第一重新布线层；第一重新布线层与对应的芯片接触且电连接；多个芯片包括位于芯片堆叠结构最外侧的第一芯片和第二芯片；第一芯片的无源面和第二芯片的无源面均朝向芯片堆叠结构的外侧，芯片堆叠结构还包括：设置于第一芯片的无源面一侧或第二芯片的无源面一侧的第二重新布线层；或者，第二芯片的无源面朝向芯片堆叠结构的外侧，第一芯片的有源面朝向芯片堆叠结构的外侧，芯片堆叠结构还包括：设置于第一芯片的有源面的第一电介质层和第二重新布线层，第一电介质层位于第一重新布线层和第二重新布线层之间；其中，第二重新布线层通过第一过孔与至少一层第一重新布线层电连接。由于现有技术，在堆叠后一芯片之前，都需要在前一芯片上形成过孔，后一芯片通过过孔与前一芯片电连接，这样就需要形成 多次过孔，才能实现芯片与外部电路(例如封装基板)的电连接，从而导致芯片堆叠结构的制作工序复杂。而本申请实施例，由于第二重新布线层通过第一过孔与至少一层第一重新布线层电连接，每层第一重新布线层和对应的芯片电连接，因而至少一个芯片可以直接通过一个第一过孔与第二重新布线层电连接，第二重新布线层用于与外部电路电连接，从而实现芯片与外部电路的电连接，而每个第一过孔可以通过一次性打孔工艺形成，因而有利于简化芯片堆叠结构的制作工艺，节约生产成本，提高生产效率。
基于上述，本申请实施例，在制作上述的芯片堆叠结构，芯片堆叠结构中的芯片为晶粒时，可以先将多个晶圆依次堆叠在一起，再对多个晶圆进行切割形成芯片堆叠结构。相对于现有技术中晶粒与晶粒键合技术以及晶粒与晶圆键合技术中先对晶圆进行切割，再堆叠晶粒，由于对晶圆的切割过程会产生杂质污染，因而在堆叠晶粒前需要对晶粒进行清理。而本申请实施例由于在制作芯片堆叠结构时，可以先将多个晶圆依次堆叠在一起，再对多个晶圆进行切割，而切割后的芯片堆叠结构(此时芯片为晶粒)的清理过程相对晶粒堆叠前的清理过程，复杂程度大大降低。此外，相对于现有技术中的晶粒与晶粒键合技术以及晶粒与晶圆的键合技术，每个晶粒都要进行晶粒与晶粒的对准或晶粒与晶圆的对准，由于本申请实施例中，在晶圆与晶圆的堆叠过程，只需要进行一次晶圆与晶圆的对准操作就可以实现多个晶粒与多个晶粒的对准，因而可以提高生产效率，降低生产成本。在此基础上，本申请实施例在制作芯片堆叠结构时，可以直接将多个晶圆依次堆叠在一起，因而相对于现有技术中的晶粒与晶粒键合技术以及晶粒与晶圆的键合技术，本申请无需对晶粒进行逐个检验，因而也可以提高生产效率，降低生产成本。基于此，相对于现有技术，本申请实施例在制作上述的芯片堆叠结构时采用先将多个晶圆堆叠在一起，有利于简化工艺，节约生产成本。
在一种可能的实施方式中，第二重新布线层位于第一芯片的无源面一侧或第二芯片的无源面一侧；上述多个芯片还包括设置于第一芯片和第二芯片之间的第三芯片；其中，第一芯片的有源面和第三芯片的有源面相对，第二芯片的有源面朝向第三芯片的无源面；芯片堆叠结构还包括设置于第一芯片的有源面和第三芯片的有源面之间的第二电介质层。按照该堆叠方式对多个芯片进行堆叠时，由于第一芯片的有源面和第三芯片的有源面相对，因而第一芯片的无源面朝向芯片堆叠结构的外侧。此外，由于第二芯片的有源面朝向第三芯片的无源面，因而第二芯片的无源面朝向芯片堆叠结构的外侧。这样一来，在该堆叠结构中，第一芯片和第二芯片的无源面均朝向芯片堆叠结构的外侧，因此可以在第一芯片的无源面一侧或第二芯片的无源面一侧形成第二重新布线层。
在一种可能的实施方式中，第二重新布线层位于第一芯片的有源面；第二芯片的有源面朝向第一芯片的无源面。按照该堆叠方式对多个芯片进行堆叠时，由于第二芯片的有源面朝向第一芯片的无源面，因而位于最外侧的两个芯片第一芯片和第二芯片，第一个芯片的有源面朝向芯片堆叠结构的外侧，第二芯片的无源面朝向芯片堆叠结构的外侧，因此可以在第一芯片的有源面一侧形成第二重新布线层。
在一种可能的实施方式中，芯片堆叠结构还包括设置在第一重新布线层和与该第一重新布线层相邻的芯片的无源面之间的第三电介质层。由于第一重新布线层和与该第一重新布线层相邻的芯片的无源面之间设置有第三电介质层，因而可以先在芯片的 无源面一侧形成第三电介质层，再采用熔融键合的方法将相邻两个芯片键合在一起。
在一种可能的实施方式中，芯片堆叠结构还包括设置在第一重新布线层远离与该第一重新布线层电连接的芯片一侧的第三重新布线层；第三重新布线层与第一重新布线层电连接，且第二重新布线层通过第一过孔与第三重新布线层电连接；其中，第三重新布线层中的金属线层的厚度大于第一重新布线层中的金属线层的厚度。由于第三重新布线层中的金属线层的厚度大于第一重新布线层中的金属线层的厚度，因而第二重新布线层通过第一过孔与第三重新布线层电连接，这样可以确保第二重新布线层与第三重新布线层电连接的可靠性，进而提高了第二重新布线层与芯片电连接的可靠性。
在一种可能的实施方式中，芯片堆叠结构还包括设置在第二重新布线层远离芯片一侧，且与第二重新布线层电连接的微凸块。由于第一重新布线层与芯片电连接，第二重新布线层与至少一个第一重新布线层电连接，第二重新布线层与微凸块电连接，因而可以实现微凸块与至少一个芯片电连接，而微凸块用于与封装基板电连接，进而可以实现芯片与封装基板的电连接。此外，当芯片堆叠结构中的任意两个芯片需要电连接，可以通过微凸块之间的连接实现任意两个芯片的连接，以实现任意两个芯片之间的通信。
在一种可能的实施方式中，芯片堆叠结构还包括第二过孔；任意两层第一重新布线层之间通过第二过孔电连接。由于任意两层第一重新布线层之间通过第二过孔电连接，因而任意两个芯片之间可以通过第二过孔电连接，以实现任意两个芯片之间的通信。相对于现有技术需要通过多个过孔实现不相邻的两个芯片之间的电连接，从而导致制作芯片堆叠结构的工序复杂。而本申请实施例中，不相邻的两个芯片可以通过第二过孔电连接，而一个第二过孔可以通过一次打孔工艺制作，因而可以简化芯片堆叠结构的制作工序。
在一种可能的实施方式中，芯片堆叠结构还包括封装基板；第二重新布线层与封装基板电连接。由于第二重新布线层通过至少一个第一过孔与第一重新布线层电连接，而第一重新布线层与对应的芯片接触且电连接，从而可以将至少一个芯片与封装基板电连接。
第二方面，提供一种芯片封装结构。该芯片封装结构包括封装基板和上述的芯片堆叠结构；芯片堆叠结构中的第二重新布线层与封装基板电连接。由于芯片封装结构具有与前述实施例相同的技术效果，因而此处不再赘述。
第三方面，提供一种电子设备。该电子设备包括印刷电路板以及前述的芯片堆叠结构；芯片堆叠结构与印刷电路板电连接。由于该电子设备具有与前述实施例相同的技术效果，因而此处不再赘述。
第四方面，提供一种芯片堆叠结构的制作方法。该制作方法包括：首先，将多个芯片依次堆叠在一起；其中，每个芯片的有源面一侧形成有第一重新布线层，第一重新布线层与对应的芯片接触且电连接；多个芯片包括位于依次堆叠的多个芯片最外侧的第一芯片和第二芯片；接下来，形成多个第一过孔，并在第一过孔内填充导电材料；接下来，在第一芯片的无源面一侧或第二芯片的无源面一侧形成第二重新布线层；其中，第一芯片的无源面和第二芯片的无源面均朝向依次堆叠的多个芯片的外侧；或者，在第一芯片的有源面一侧形成第二重新布线层；其中，第二芯片的无源面朝向依次堆 叠的多个芯片的外侧，第一芯片的有源面朝向依次堆叠的多个芯片的外侧，且第一芯片的有源面还形成有第一电介质层，第二重新布线层位于第一电介质层远离第一重新布线层的一侧；第二重新布线层通过第一过孔与至少一层第一重新布线层电连接。相对于现有技术，需要制作多个过孔才能实现芯片与外部的电连接，本申请实施例在制作芯片堆叠结构的过程中，由于将多个芯片堆叠在一起后，每个第一过孔通过一次性打孔制作，且通过第一过孔将与该芯片电连接在第一重新布线层与第二重新布线层电连接，即至少一个芯片通过第一过孔与第二重新布线层电连接，而第二重新布线层与外部电路电连接，从而实现芯片与外部电路的电连接，因而本申请实施例有利于简化芯片堆叠结构的制作工艺，节约生产成本，提高生产效率。
在此基础上，相对于现有技术中的晶粒与晶粒键合技术以及晶粒与晶圆的键合技术先对晶圆进行切割，再堆叠晶粒，由于对晶圆的切割过程会产生杂质污染，因而在堆叠晶粒前需要对晶粒进行清理。而本申请实施例由于在制作芯片堆叠结构时，可以先将多个晶圆依次堆叠在一起，再对多个晶圆进行切割，而切割后得到的芯片堆叠结构(此时芯片为晶粒)的清理过程相对晶粒堆叠前的清理过程，复杂程度大大降低。此外，相对于现有技术中的晶粒与晶粒键合技术以及晶粒与晶圆的键合技术，每个晶粒都要进行晶粒与晶粒的对准或晶粒与晶圆的对准，由于本申请实施例中，在晶圆与晶圆的堆叠过程，只需要进行一次晶圆与晶圆的对准操作就可以实现多个晶粒与多个晶粒的对准，因而可以提高生产效率，降低生产成本。在此基础上，本申请实施例在制作芯片堆叠结构时，直接将多个晶圆依次堆叠在一起，因而相对于现有技术中的晶粒与晶粒键合技术以及晶粒与晶圆的键合技术，本申请无需对晶粒进行逐个检验，因而也可以提高生产效率，降低生产成本。基于此，相对于现有技术，本申请实施例制作芯片堆叠结构的方法采用先将多个晶圆堆叠在一起，有利于简化工艺，节约生产成本。
在一种可能的实施方式中，将多个芯片依次堆叠在一起，包括：将第三芯片堆叠在第一芯片上；其中，第三芯片的有源面朝向第一芯片的有源面；第一芯片的第一重新布线层和第三芯片的第一重新布线层之间形成有第二电介质层；对第三芯片的无源面进行减薄加工，将第二芯片堆叠在第三芯片的无源面，并对第一芯片的无源面或第二芯片的无源面进行减薄加工；其中，第二芯片的有源面朝向第三芯片的无源面。按照该堆叠方式对多个芯片进行堆叠时，第一芯片的无源面和第二芯片的无源面均朝向晶圆堆叠结构的外侧。
在一种可能的实施方式中，对第一芯片的无源面进行减薄加工，在第一芯片的无源面一侧或第二芯片的无源面一侧形成第二重新布线层包括：在第一芯片的无源面一侧形成第二重新布线层；或者，对第二芯片的无源面进行减薄加工，在第一芯片的无源面一侧或第二芯片的无源面一侧形成第二重新布线层包括：在第二芯片的无源面一侧形成第二重新布线层。由于第一芯片的无源面和第二芯片的无源面均朝向晶圆堆叠结构的外侧，因而可以在第一芯片的无源面一侧或第二芯片的无源面一侧形成第二重新布线层。
在一种可能的实施方式中，在第一芯片的无源面一侧形成第二重新布线层之后，上述制作方法还包括：对第二芯片的无源面进行减薄加工；或者，在第二芯片的无源 面一侧形成第二重新布线层之后，上述制作方法还包括：对第一芯片的无源面进行减薄加工。这样可以减小芯片堆叠结构的厚度。
在一种可能的实施方式中，在第一芯片的无源面一侧形成第二重新布线层之后，在对第二芯片的无源面进行减薄加工之前；或者，在第二芯片的无源面一侧形成第二重新布线层之后，在对第一芯片的无源面进行减薄加工之前，上述制作方法还包括：在第二重新布线层远离芯片的一侧形成与第二重新布线层电连接的微凸块。由于第一重新布线层与芯片电连接，第二重新布线层与至少一层第一重新布线层电连接，第二重新布线层与微凸块电连接，因而可以实现微凸块与至少一个芯片电连接。此外，微凸块用于与封装基板电连接，进而可以实现芯片与封装基板的电连接。在此基础上，当芯片堆叠结构中的任意两个芯片需要电连接，可以通过微凸块之间的连接实现任意两个芯片的连接，以实现任意两个芯片之间的通信。
在一种可能的实施方式中，对第三芯片的无源面进行减薄加工之后，将第二芯片堆叠在第三芯片的无源面之前，上述制作方法还包括：在第三芯片的无源面一侧形成第三电介质层。这样便可以采用熔融键合的方法将第三芯片和第二芯片电连接在一起。
在一种可能的实施方式中，将多个芯片依次堆叠在一起，包括：将第一芯片堆叠在载体上；其中，载体和第一芯片的第一重新布线层之间形成有第一电介质层；对第一芯片的无源面进行减薄加工，并将第二芯片堆叠在第一芯片的无源面；其中，第二芯片的有源面朝向第一芯片的无源面；去除所述载体。按照该堆叠方式对多个芯片进行堆叠时，由于第二芯片的有源面朝向第一芯片的无源面，因而去除载体后，位于最外侧的两个芯片，第一芯片和第二芯片，第一芯片的有源面朝向芯片堆叠结构的外侧，第二芯片的无源面朝向芯片堆叠结构的外侧。
在一种可能的实施方式中，载体为载体晶圆或载体基板。
在一种可能的实施方式中，在第一电介质层远离第一芯片的一侧形成第二重新布线层。由于第一芯片的有源面朝向芯片堆叠结构的外侧，因而可以在第一芯片的有源面一侧形成第二重新布线层。
在一种可能的实施方式中，在第一电介质层远离第一芯片的一侧形成第二重新布线层之后，上述制作方法还包括：对第二芯片的无源面进行减薄加工。这样可以减小芯片堆叠结构的厚度。
在一种可能的实施方式中，在第一电介质层远离第一芯片的一侧形成第二重新布线层之后，对第二芯片的无源面进行减薄加工之前，上述制作方法还包括：在第二重新布线层远离第一电介质层的一侧形成与第二重新布线层电连接的微凸块。由于形成的微凸块具有与前述实施例相同的技术效果，因而此处不再赘述。
在一种可能的实施方式中，在对第一芯片的无源面进行减薄加工之后，在将第二芯片堆叠在第一芯片的无源面之前，上述制作方法还包括：在第一芯片的无源面一侧形成第三电介质层。由于在将第二芯片堆叠在第一芯片的无源面之前，在第一芯片的无源面一侧形成了第三电介质层，因而在将第二芯片堆叠在第一芯片的无源面时，可以采用熔融键合的方式将第二芯片和第一芯片堆叠在一起。
在一种可能的实施方式中，通过熔融键合的方式，将相邻的两个芯片连接在一起。采用熔融键合的方式将相邻的两个芯片连接在一起，可以避免有机污染，在芯片为晶 圆的情况下，还可以避免晶圆翘曲等问题，保证了工艺的可靠性。
在一种可能的实施方式中，每个芯片的有源面还形成有位于第一重新布线层远离与该第一重新布线层电连接的芯片一侧的第三重新布线层；第三重新布线层与第一重新布线层电连接，第二重新布线层通过第一过孔与第三重新布线层电连接；其中，第三重新布线层中的金属线层的厚度大于第一重新布线层中的金属线层的厚度。由于形成的第三重新布线层具有与前述实施例相同的技术效果，因而此处不再赘述。
在一种可能的实施方式中，多个芯片中至少一个芯片为晶圆；在第一芯片的无源面一侧或第二芯片的无源面一侧形成第二重新布线层；或者，在第一芯片的有源面一侧形成第二重新布线层之后，上述制作方法还包括：对晶圆进行切割，从而得到多个结构完全相同，且功能完全相同的芯片堆叠结构。
在一种可能的实施方式中，将多个芯片依次堆叠在一起包括：将第m芯片堆叠在第n芯片上，对第m芯片的无源面进行减薄加工；其中，m，n均为正整数；形成第二过孔，并在第二过孔内填充导电材料；第m芯片的第一重新布线层和第n芯片的第一重新布线层通过第二过孔电连接。现有技术中在第m芯片和第n芯片不相邻的情况下，若要实现第m芯片和第n芯片的电连接，则需要形成多个过孔，从而导致制作芯片堆叠结构的工序复杂。而本申请实施例中，第m芯片的第一重新布线层和第n芯片的第一重新布线层通过第二过孔电连接，而一个第二过孔可以通过一次打孔工艺制作，因而可以简化芯片堆叠结构的制作工序。
附图说明
图1为本申请的实施例提供的一种电子设备的结构示意图；
图2a为本申请的实施例提供的一种芯片堆叠结构的结构示意图；
图2b为本申请的另一实施例提供的一种芯片堆叠结构的结构示意图；
图3为本申请的实施例提供的一种芯片与第一重新布线层的结构示意图；
图4为现有技术提供的一种芯片堆叠结构的结构示意图；
图5a为本申请的又一实施例提供的一种芯片堆叠结构的结构示意图；
图5b为本申请的再一实施例提供的一种芯片堆叠结构的结构示意图；
图5c为本申请的另一实施例提供的一种芯片堆叠结构的结构示意图；
图6为本申请的实施例提供的一种芯片堆叠结构的制作方法的流程示意图；
图7为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图一；
图8为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图二；
图9为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图三；
图10为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图四；
图11为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图五；
图12为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意 图六；
图13为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图七；
图14为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图八；
图15为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图九；
图16为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图十；
图17为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图十一；
图18为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图十二；
图19为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图十三；
图20为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图十四；
图21为本申请的实施例提供的一种芯片堆叠结构的制作方法过程中的结构示意图十五；
图22为本申请的又一实施例提供的一种芯片堆叠结构的结构示意图。
附图标记：
01-电子设备；02-芯片封装结构；10-芯片堆叠结构；11-微凸块；12-第一金属层；13-控制塌陷芯片连接凸块；14-第二金属层；15-微凸块；16-硅通孔；17-焊球；20-封装基板；30-连接件；40-载体；100-芯片；101-第一重新布线层；102-第二重新布线层；103-第一电介质层；104-第一过孔；105-金属线层；106-绝缘层；107-第二电介质层；108-第三电介质层；109-第三重新布线层；110-存储芯片；111-逻辑芯片；112-第二过孔。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元。
本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“电连接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。
本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或“例如”等词旨在以具体方式呈现相关概念。
本申请实施例提供一种电子设备。该电子设备可以包括CMOS图像传感器、NAND闪存、高带宽存储器、手机(mobile phone)、平板电脑(pad)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备等电子产品。本申请实施例对上述电子设备的具体形式不做特殊限制。
如图1所示，上述电子设备01可以包括芯片封装结构02和印刷电路板(printed circuit board，PCB)。附图1中未示意出印刷电路板。芯片封装结构02包括芯片堆叠结构10以及封装基板20，芯片堆叠结构10与封装基板20电连接。
上述芯片堆叠结构10包括依次堆叠的多个芯片100(图1中以包括两个芯片100为例进行示意)。在一些实施例中，芯片堆叠结构10还可以包括微凸块(micro bump，ubump)11，封装基板20可以通过多个微凸块11与芯片100电连接。另外，在一些实施例中，如图1所示，电子设备01还可以包括连接件30；芯片封装结构02中的封装基板20通过连接件30与印刷电路板电连接。这样一来，便可以实现芯片堆叠结构10与电子系统的通信。此处，连接件30可以是焊球或微凸块。
以下对上述芯片堆叠结构10的结构进行详细的说明。
如图2a和图2b所示，芯片堆叠结构10包括：依次堆叠的多个芯片100以及设置于每个芯片100的有源面F的第一重新布线层101(redistribution layer，RDL)；第一重新布线层101与对应的芯片100接触且电连接。
需要说明的是，本申请实施例中的芯片100可以是晶粒(也可以称为颗粒或裸芯片)(die)；也可以是晶圆(wafer)。可以理解的是，对晶圆进行切割得到的是晶粒。基于此，在一些实施例中，多个芯片100均为晶粒。在另一些实施例中，多个芯片100均为晶圆。在又一些实施例中，多个芯片100中的第一芯片100a为晶圆，其它芯片为晶粒。
本申请实施例中，由于芯片堆叠结构10中的多个芯片100依次堆叠，因而沿堆叠方向上，位于芯片堆叠结构10最外侧的芯片100有两个，即多个芯片100包括位于芯片堆叠结构10最外侧的第一芯片100a和第二芯片100b。
如图2a所示，第一芯片100a的无源面B和第二芯片100b的无源面B均朝向芯片堆叠结构10的外侧，芯片堆叠结构10还包括：设置于第一芯片100a的无源面B一侧或第二芯片100b的无源面B一侧的第二重新布线层102。或者，如图2b所示，第二芯片100b的无源面B朝向芯片堆叠结构10的外侧，第一芯片100a的有源面F朝向芯片堆叠结构10的外侧，芯片堆叠结构10还包括：设置于第一芯片100a的有源面F的第一电介质层103和第二重新布线层102，第一电介质层103位于第一重新布线层101和第二重新布线层102之间。其中，第二重新布线层102通过第一过孔104与至少一层第一重新布线层101电连接。
此处，对于芯片堆叠结构10中堆叠的芯片100的数量不进行限定，可以根据应用 需要设置堆叠的芯片100的数量。在此基础上，上述的芯片100可以是存储芯片、逻辑芯片或其它任何功能的芯片。此外，上述芯片堆叠结构10中的多个芯片可以是同一类芯片(例如多个芯片都是存储芯片)；也可以是不同类芯片(例如多个芯片包括存储芯片和逻辑芯片)，即本申请实施例提供的芯片堆叠结构10可以实现同类或不同类芯片间的集成。
需要说明的是，本申请实施例中任意一个芯片可以包括基底以及设置于基底上的电路结构，该电路结构在工作的过程中可以使得芯片实现其自身的功能，例如逻辑运算或者存储数据等。其中，构成上述芯片的基底的材料可以包括硅片、玻璃、非晶硅(amorphous silicon，a-Si)或者碳化硅(SiC)等。该芯片中上述电路结构远离基底一侧的表面可以称为芯片的有源面F(或正面F)，基底远离电路结构一侧的表面可以称为芯片的无源面B(或背面B)。
此处，可以采用硅通孔(through silicon via，TSV)技术形成第一过孔104。
可以理解的是，如图3所示，第一重新布线层101可以包括一层或多层金属线层105和一层或多层绝缘层106。在第一重新布线层101包括多层金属线层105的情况下，第一重新布线层101中相邻两层金属线层105之间通过绝缘层106间隔开，此外，为了将相邻两层金属线层105电连接在一起，因而第一重新布线层101还包括设置于绝缘层106上的过孔，相邻两层金属线层105通过过孔电连接在一起。
示例的，上述金属线层105的材料包括但不限于铜、铝、镍、金、银、钛中的一种材料或两种及两种以上的组合材料。
示例的，上述绝缘层106的材料包括但不限于氧化硅、氮化硅、氮氧化硅、硅胶、聚酰亚胺中的一种材料或两种及两种以上的组合材料。
基于上述可知，上述第一重新布线层101与芯片100电连接指的是第一重新布线层101中的金属线层105与芯片100的有源面F的电路结构电连接。
此外，第二重新布线层102也可以包括一层或多层金属线层105和一层或多层绝缘层106。具体可以参考上述对第一重新布线层101的解释说明，此处不再赘述。在一些实施例中，第二重新布线层102包括一层金属线层105和一层绝缘层106。
上述“第二重新布线层102通过第一过孔104与至少一层第一重新布线层101电连接”指的是第二重新布线层102中的金属线层105通过第一过孔104与至少一层第一重新布线层101中的金属线层105电连接。此外，应当理解到，每个第一过孔104仅与一层第一重新布线层101电连接，即每个第一过孔104仅与一个芯片100电连接。
可以理解的是，第一过孔104内填充有导电材料，这样才能实现第二重新布线层102与第一重新布线层101的电连接。此处的导电材料例如可以为铜、铝、镍等具有良好导电效果的导电材料。由于铜的导电性能较好，因而在本申请的一些实施例中，第一过孔104内填充的导电材料为铜。
应当理解到，可以将依次堆叠的多个芯片100看作是一个整体，若位于最外侧的芯片100(例如第一芯片100a或第二芯片100b)的无源面B相对于有源面F远离该整体的中心，则认为位于最外侧的芯片100的无源面B朝向芯片堆叠结构10的外侧；若位于最外侧的芯片100的有源面F相对于无源面B远离该整体的中心，则认为位于最外侧的芯片100的有源面F朝向芯片堆叠结构10的外侧。
在此基础上，对于芯片堆叠结构10中任意相邻的两个芯片100，可以利用粘结剂将相邻两个芯片100连接在一起；也可以利用键合等方式将相邻两个芯片100连接在一起。
现有技术中，以采用晶粒与晶粒键合技术制作芯片堆叠结构10为例，如图4所示，芯片堆叠结构10中芯片100-1通过第一金属层12、控制塌陷芯片连接(controlled collapse chip connection，C4)凸块13与封装基板20连接，芯片100-1和芯片100-2之间通过第二金属层14、微凸块15连接，芯片100-2通过硅通孔16、控制塌陷芯片连接凸块13与封装基板20连接。封装基板20通过焊球17实现与电子系统的通信。在制作芯片堆叠结构10时，堆叠完芯片100-1后，需要在芯片100-1上形成硅通孔16和微凸块15后，再堆叠芯片100-2，芯片100-2通过第二金属层14、微凸块15、硅通孔16以及控制塌陷芯片连接凸块13与封装基板20电连接。若还要堆叠芯片100-3，则需要在芯片100-2上形成硅通孔16和微凸块15，芯片100-3通过芯片100-2上形成的硅通孔16和微凸块15、芯片100-1上形成的硅通孔16和微凸块15、以及控制塌陷芯片连接凸块13与封装基板20电连接，由此可知，需要形成多个硅通孔16，才能实现芯片100-3与封装基板20的电连接，从而导致芯片堆叠结构10的制作工序复杂。
本申请实施例提供一种芯片堆叠结构10，该芯片堆叠结构10包括依次堆叠的多个芯片100以及设置于每个芯片100的有源面F的第一重新布线层101；第一重新布线层101与对应的芯片100接触且电连接。多个芯片包括位于芯片堆叠结构10最外侧的第一芯片100a和第二芯片100b。在第一芯片100a的无源面B和第二芯片100b的无源面B均朝向芯片堆叠结构10的外侧时，芯片堆叠结构10还包括：设置于第一芯片100a的无源面B一侧或第二芯片100b的无源面B一侧的第二重新布线层102。或者，在第二芯片100b的无源面B朝向芯片堆叠结构10的外侧，第一芯片100a的有源面F朝向芯片堆叠结构10的外侧时，芯片堆叠结构10还包括：设置于第一芯片100a的有源面F的第一电介质层103和第二重新布线层102，第一电介质层103位于第一重新布线层101和第二重新布线层102之间。其中，第二重新布线层102通过第一过孔104与至少一层第一重新布线层101电连接。由于现有技术，在堆叠后一芯片100之前，都需要在前一芯片100上形成过孔，后一芯片100通过过孔与前一芯片100电连接，这样就需要形成多次过孔，才能实现芯片100与外部电路(例如封装基板)的电连接，从而导致芯片堆叠结构的制作工序复杂。而本申请实施例，由于第二重新布线层102通过第一过孔104与至少一层第一重新布线层101电连接，每层第一重新布线层101和对应的芯片100电连接，因而至少一个芯片100可以直接通过一个第一过孔104与第二重新布线层102电连接，第二重新布线层102用于与外部电路电连接，从而实现芯片100与外部电路的电连接，而每个第一过孔104可以通过一次性打孔工艺形成，因而有利于简化芯片堆叠结构10的制作工艺，节约生产成本，提高生产效率。
此外，在采用晶粒与晶粒键合技术制作如图4所示的芯片堆叠结构10时，由于芯片100-1和芯片100-2需要先经过晶圆切割处理，而切割过程会产生杂质污染，因而在将芯片100-1和芯片100-2堆叠之前，需要对芯片100-1和芯片100-2进行清理，清理过程比较复杂。此外，在芯片100-1和芯片100-2堆叠的过程中，需要做对准，对准精度越高，对准步骤所化时间越长，且随着芯片堆叠结构10中芯片100尺寸的减小， 对对准精度的要求会越来越高，对准步骤耗时会进一步增加，进而导致生产效率(through put)的降低。在此基础上，芯片100在堆叠前，为了利用已知合格的芯片，需要对芯片逐个进行测试，这样一来，也会导致生产效率降低，增加生产成本。由于采用晶粒与晶圆键合技术制作芯片堆叠结构10时，也需要对晶圆进行切割，将芯片与晶圆进行对准以及对芯片是否合格进行检验等步骤，因而也会导致生产效率降低，增加生产成本等问题，此处不再详细说明。
而本申请实施例，在制作上述的芯片堆叠结构10，芯片堆叠结构10中的芯片100为晶粒时，可以先将多个晶圆依次堆叠在一起，再对多个晶圆进行切割形成芯片堆叠结构10。相对于现有技术中晶粒与晶粒键合技术以及晶粒与晶圆键合技术中先对晶圆进行切割，再堆叠晶粒，由于对晶圆的切割过程会产生杂质污染，因而在堆叠晶粒前需要对晶粒进行清理。而本申请实施例由于在制作芯片堆叠结构10时，可以先将多个晶圆依次堆叠在一起，再对多个晶圆进行切割，而切割后的芯片堆叠结构10(此时芯片为晶粒)的清理过程相对晶粒堆叠前的清理过程，复杂程度大大降低。此外，相对于现有技术中的晶粒与晶粒键合技术以及晶粒与晶圆的键合技术，每个晶粒都要进行晶粒与晶粒的对准或晶粒与晶圆的对准，由于本申请实施例中，在晶圆与晶圆的堆叠过程，只需要进行一次晶圆与晶圆的对准操作就可以实现多个晶粒与多个晶粒的对准，因而可以提高生产效率，降低生产成本。在此基础上，本申请实施例在制作芯片堆叠结构10时，直接将多个晶圆依次堆叠在一起，因而相对于现有技术中的晶粒与晶粒键合技术以及晶粒与晶圆的键合技术，本申请无需对晶粒进行逐个检验，因而也可以提高生产效率，降低生产成本。基于此，相对于现有技术，本申请实施例在制作上述的芯片堆叠结构10时采用先将多个晶圆堆叠在一起，有利于简化工艺，节约生产成本。
在一些实施例中，如图5a和图5b所示，芯片堆叠结构10还包括设置在第二重新布线层102远离芯片100一侧，且与第二重新布线层102电连接的微凸块11。
此处，由于第一重新布线层101与芯片100电连接，第二重新布线层102与至少一个第一重新布线层101电连接，第二重新布线层102与微凸块11电连接，因而可以实现微凸块11与至少一个芯片100电连接，而微凸块11用于与上述的封装基板20电连接，进而可以实现芯片100与封装基板20电连接。
当芯片堆叠结构10中的任意两个芯片100需要电连接，在一些实施例中，可以通过微凸块11之间的连接实现任意两个芯片100的连接，以实现任意两个芯片100之间的通信。
在另一些实施例中，如图5c所示，芯片堆叠结构10还包括第二过孔112；任意两层第一重新布线层101之间通过第二过孔112电连接，即任意两个芯片100之间通过第二过孔112电连接，以实现任意两个芯片100之间的通信。
此处，与上述任意两层第一重新布线层101分别电连接的两个芯片100可以相邻，也可以不相邻。例如，如图5c所示，与第三芯片100c电连接的第一重新布线层101和与第五芯片100e电连接的第一重新布线层101通过第二过孔112电连接。
现有技术中，若要实现不相邻的两个芯片100之间的电连接，例如若要实现第三芯片100c和第五芯片100e的电连接，则在堆叠完第三芯片100c之后，需要在第三芯片100c上形成过孔；再堆叠第四芯片100d，接下来，在第四芯片100d上形成过孔； 之后，堆叠第五芯片100e，第五芯片100e通过第三芯片100c上形成的过孔和第四芯片100d上形成的过孔与第三芯片100c电连接，即现有技术需要通过多个过孔实现不相邻的两个芯片100之间的电连接，从而导致制作芯片堆叠结构10的工序复杂。而本申请实施例中，不相邻的两个芯片100可以通过第二过孔112电连接，而一个第二过孔112可以通过一次打孔工艺制作，因而可以简化芯片堆叠结构10的制作工序。例如，如图5c所示，若要实现第三芯片100c和第五芯片100e的电连接，则在堆叠完第一芯片100a、第三芯片100c、第四芯片100d和第五芯片100e后，形成第二过孔112，第二过孔112穿过第三芯片100c、第四芯片100d和第五芯片100e，以实现第三芯片100c和第五芯片100e的电连接。
对于芯片堆叠结构10中的多个芯片100如何进行堆叠，以下示例性地提供两种具体的实施方式。
第一种实施方式，如图5a所示，在第二重新布线层102位于第一芯片100a的无源面B一侧或第二芯片100b的无源面B一侧的情况下，上述多个芯片100还包括设置于第一芯片100a和第二芯片100c之间的第三芯片100c；其中，第一芯片100a的有源面F和第三芯片100c的有源面F相对，第二芯片100b的有源面F朝向第三芯片100c的无源面B；芯片堆叠结构10还包括设置于第一芯片100a的有源面F和第三芯片100c的有源面F之间的第二电介质层107。
需要说明的是，如图5a所示，在芯片堆叠结构10还包括第四芯片100d的情况下，第四芯片100d堆叠在第三芯片100c上，且第四芯片100d的有源面F朝向第三芯片100c的无源面B。在芯片堆叠结构10还包括第五芯片100e的情况下，第五芯片100e堆叠在第四芯片100d上，且第五芯片100e的有源面F朝向第四芯片100d的无源面B；依次类推，此处不再赘述。
基于上述，也就是说如图5a所示，在第二重新布线层102位于第一芯片100a的无源面B一侧或第二芯片100b的无源面B一侧的情况下，在堆叠方向(图5a中用粗箭头表示堆叠方向)上，除第一芯片100a和第三芯片100c外，后一芯片的有源面F朝向前一芯片100的无源面B；第一芯片100a的有源面F和第三芯片100c的有源面F相对；芯片堆叠结构10还包括设置于第一芯片100a的有源面F和第三芯片100c的有源面F之间的第二电介质层107。
附图5a以第二重新布线层102位于第二芯片100b的无源面B一侧为例进行示意。
此处，设置于第一芯片100a的有源面F和第三芯片100c的有源面F之间的第二电介质层107可以将第一芯片100a的有源面F和第三芯片100c的有源面F间隔开。此外，可以将第二电介质层107形成在第一芯片100a的有源面F上，再采用熔融键合(fusion bonding)的方法将第一芯片100a和第三芯片100c键合在一起；也可以将第二电介质层107形成在第三芯片100c的有源面F，再采用熔融键合的方法将第一芯片100a和第三芯片100c键合在一起。
应当理解到，在芯片堆叠结构10中，由于第一芯片100a的有源面F和第三芯片100c的有源面F相对，因而第一芯片100a的无源面B朝向芯片堆叠结构10的外侧。此外，由于后一芯片100的有源面F朝向前一芯片100的无源面B，因而最后一个芯片，即第二芯片100b的无源面B朝向芯片堆叠结构10的外侧。这样一来，在该堆叠 结构中，位于最外侧的两个芯片第一芯片100a的无源面和第二芯片100b的无源面均朝向芯片堆叠结构10的外侧。
若按照第一种实施方式依次堆叠多个芯片100，可以从最后一个芯片即第二芯片100b的无源面B开始制作第一过孔104，除了第一芯片100a外，对于其它芯片100，制作第一过孔104时，第一过孔104都是由芯片100的无源面B向芯片100的有源面F穿透，因而将该打孔方式也可以称为背面打孔方式，即利用背面打孔方式形成多个第一过孔104，在此情况下，第二重新布线层102位于第二芯片100b的无源面B。也可以从第一芯片100a的无源面B开始制作第一过孔104，除了第一芯片100a外，对于其它芯片100，制作第一过孔104时，第一过孔104都是由芯片100的有源面F向芯片100的无源面B穿透，因而将该打孔方式也可以称为正面打孔方式，即利用正面打孔方式形成多个第一过孔104，在此情况下，第二重新布线层102位于第一芯片100a的无源面B。
第二种实施方式，如图5b所示，在第二重新布线层102位于第一芯片100a的有源面F的情况下，第二芯片100b的有源面F朝向第一芯片100a的无源面B。
需要说明的是，如图5b所示，在芯片堆叠结构10还包括第三芯片100c的情况下，第三芯片100c堆叠在第一芯片100a上，且第三芯片100c的有源面F朝向第一芯片100a的无源面B。在芯片堆叠结构10还包括第四芯片100d的情况下，第四芯片100d堆叠在第三芯片100c上，且第四芯片100d的有源面F朝向第三芯片100c的无源面B。在芯片堆叠结构10还包括第五芯片100e的情况下，第五芯片100e堆叠在第四芯片100d上，且第五芯片100e的有源面F朝向第四芯片100d的无源面B；依次类推，此处不再赘述；最后堆叠第二芯片100b。
基于上述，也就是说如图5b所示，在第二重新布线层102位于第一芯片100a的有源面F的情况下，在堆叠方向(图5b中用粗箭头表示堆叠方向)上，后一芯片100的有源面F朝向前一芯片100的无源面B。
应当理解到，在芯片堆叠结构10中，由于后一芯片100的有源面F朝向前一芯片100的无源面B，因而位于最外侧的两个芯片即第一芯片100a和第二芯片100b，第一芯片100a的有源面F朝向芯片堆叠结构10的外侧，第二芯片100b的无源面B朝向芯片堆叠结构10的外侧。
若按照第二种实施方式依次堆叠多个芯片100，可以从第一芯片100a的有源面F开始制作第一过孔104，对于任意一个芯片100，制作第一过孔104时，第一过孔104都是由芯片100的有源面F向芯片100的无源面B穿透，因而将该打孔方式也可以称为正面打孔方式，即利用正面打孔方式形成多个第一过孔104。
在一些实施例中，如图5a和图5b所示，芯片堆叠结构10还包括设置在第一重新布线层101和与该第一重新布线层101相邻的芯片100的无源面B之间的第三电介质层108。
由于第一重新布线层101和与该第一重新布线层101相邻的芯片100的无源面F之间设置有第三电介质层108，因而可以先在芯片100的无源面B一侧形成第三电介质层108，再采用熔融键合的方法将相邻两个芯片100键合在一起。
需要说明的是，上述第一电介质层103、第二电介质层107以及第三电介质层108 的材料可以相同，也可以不相同。示例的，第一电介质层103、第二电介质层107以及第三电介质层108的材料可以为氮化硅(SiNx)、氧化硅(SiOx)或氮氧化硅(SiOxNy)中的一种或多种。
在一些实施例中，如图2a、图2b、图5a以及图5b所示，芯片堆叠结构10还包括设置在第一重新布线层101远离与该第一重新布线层101电连接的芯片100一侧的第三重新布线层109；第三重新布线层109与第一重新布线层101电连接，且第二重新布线层102通过第一过孔104与第三重新布线层109电连接；其中，第三重新布线层109中的金属线层105的厚度大于第一重新布线层101中的金属线层105的厚度。
此处，第三重新布线层109包括一层或多层金属线层105和一层或多层绝缘层106。具体可以参考上述对第一重新布线层101的解释说明，此处不再赘述。在一些实施例中，第三重新布线层109包括一层金属线层105和一层绝缘层106。
应当理解到，上述“第二重新布线层102通过第一过孔104与第三重新布线层109电连接”指的是第二重新布线层102中的金属线层105通过第一过孔104与第三重新布线层109中的金属线层105电连接。
本申请实施例中，由于第三重新布线层109中的金属线层105的厚度大于第一重新布线层101中的金属线层105的厚度，因而第二重新布线层102通过第一过孔104与第三重新布线层109电连接，这样可以确保第二重新布线层102与第三重新布线层109电连接的可靠性，进而提高了第二重新布线层102与芯片100电连接的可靠性。
本申请的实施例还提供一种芯片堆叠结构的制作方法，可以用于制备上述的芯片堆叠结构10。如图6所示，该芯片堆叠结构的制作方法包括：
S10、将多个芯片100依次堆叠在一起；其中，每个芯片10的有源面F一侧形成有第一重新布线层101，第一重新布线层101与对应的芯片100接触且电连接；多个芯片100包括位于依次堆叠的多个芯片最外侧的第一芯片100a和第二芯片100b。
需要说明的是，本申请实施例中的芯片100可以是晶粒；也可以是晶圆。基于此，在一些实施例中，多个芯片100均为晶粒。在另一些实施例中，多个芯片100均为晶圆。在又一些实施例中，多个芯片100中的第一芯片100a为晶圆，其它芯片为晶粒。
在一些实施例中，在将多个芯片100堆叠在一起之前，需要对芯片100的表面进行清洗。
此处，第一重新布线层101的结构可以参考上述实施例，此处不再赘述。在此基础上，第一重新布线层101与对应的芯片100电连接指的是第一重新布线层101中的金属线层105与芯片100的有源面F的电路结构电连接。
此外，对于任意相邻的两个芯片100，可以利用粘结剂将相邻两个芯片100连接在一起；也可以利用键合等方式将相邻两个芯片100连接在一起。
另外，对于依次堆叠的芯片100的数量可以根据应用需要进行设置。例如，可以将四个或六个芯片100依次堆叠在一起。
S11、形成多个第一过孔104，并在第一过孔104内填充导电材料。
此处，可以采用干法刻蚀或湿法刻蚀的方式在S10形成的依次堆叠的多个芯片100中制作第一过孔104。具体可以采用硅通孔技术形成多个第一过孔104。形成第一过孔104之后，可以采用化学气相沉积、溅镀沉积、离子束沉积、物理气相沉积、原子层 沉积、分子束外延蒸镀等方法在第一过孔104内填充导电材料。导电材料例如可以为铜、铝、镍等具有良好导电效果的导电材料。由于铜的导电性能较好，因而在本申请的一些实施例中，第一过孔104内填充的导电材料为铜。
需要说明的是，根据形成第一过孔104采用的工艺，不同深度的多个第一过孔104可以同步制作，也可以分别制作。
在步骤S11之后，接下来，根据S10中多个芯片100的堆叠方式的不同，步骤S12可以采用以下两种方式实现。
第一种：在第一芯片100a的无源面B和第二芯片100b的无源面B均朝向依次堆叠的多个芯片100的外侧的情况下，S12包括：
在第一芯片100a的无源面B一侧或第二芯片100b的无源面B一侧形成第二重新布线层102；其中，第二重新布线层102通过第一过孔104与至少一层第一重新布线层101电连接；第二重新布线层102用于将第一重新布线层101与封装基板20电连接。
第二种：在第二芯片100b的无源面B朝向依次堆叠的多个芯片100的外侧，第一芯片100a的有源面F朝向依次堆叠的多个芯片100的外侧，且第一芯片100a的有源面F还形成有第一电介质层103的情况下，S12包括：
在第一芯片100a的有源面F一侧形成第二重新布线层102；第二重新布线层102位于第一电介质层103远离第一重新布线层101的一侧；其中，第二重新布线层102通过第一过孔104与至少一层第一重新布线层101电连接；第二重新布线层102用于将第一重新布线层101与封装基板20电连接。
此处，第二重新布线层102的结构可以参考上述，此处不再赘述。
在上述多个芯片中至少一个芯片为晶圆的情况下，上述制作方法还包括：
S13、对晶圆进行切割，以形成芯片堆叠结构10。
需要说明的是，步骤S13是可选步骤，在多个芯片均为晶粒的情况下，该步骤可以省略。
应当理解到，对晶圆进行切割后，可以得到结构完全相同，且功能完全相同的多个芯片堆叠结构10。
本申请实施例提供一种芯片堆叠结构的制作方法，该芯片堆叠结构的制作方法包括首先将多个芯片100依次堆叠在一起；其中，每个芯片100的有源面F一侧形成有第一重新布线层101，第一重新布线层101与对应的芯片100接触且电连接；多个芯片100包括位于依次堆叠的多个芯片100最外侧的第一芯片100a和第二芯片100b；接下来，形成多个第一过孔104，并在第一过孔内104填充导电材料；接下来，在第一芯片100a的无源面B和第二芯片100b的无源面B均朝向依次堆叠的多个芯片100的外侧的情况下，在第一芯片100a的无源面B一侧或第二芯片100b的无源面B一侧形成第二重新布线层102；其中，第二重新布线层102通过第一过孔104与至少一层第一重新布线层101电连接；或者，在第二芯片100b的无源面B朝向依次堆叠的多个芯片100的外侧，第一芯片100a的有源面F朝向依次堆叠的多个芯片100的外侧，且第一芯片100a的有源面F还形成有第一电介质层103的情况下，在第一芯片100a的有源面F一侧形成第二重新布线层102；第二重新布线层102位于第一电介质层103远离第一重新布线层101的一侧；其中，第二重新布线层102通过第一过孔104与至 少一层第一重新布线层101电连接。相对于现有技术，需要制作多个过孔才能实现芯片100与外部的电连接，本申请实施例在制作芯片堆叠结构10的过程中，由于将多个芯片100堆叠在一起后，每个第一过孔104通过一次性打孔制作，且通过第一过孔104将与该芯片100电连接在第一重新布线层101与第二重新布线层102电连接，即至少一个芯片100通过第一过孔104与第二重新布线层102电连接，而第二重新布线层102与外部电路电连接，从而实现芯片100与外部电路的电连接，因而本申请实施例有利于简化芯片堆叠结构10的制作工艺，节约生产成本，提高生产效率。
在此基础上，相对于现有技术中的晶粒与晶粒键合技术以及晶粒与晶圆的键合技术先对晶圆进行切割，再堆叠晶粒，由于对晶圆的切割过程会产生杂质污染，因而在堆叠晶粒前需要对晶粒进行清理。而本申请实施例由于在制作芯片堆叠结构10时，可以先将多个晶圆依次堆叠在一起，再对多个晶圆进行切割，而切割后得到的芯片堆叠结构10(此时芯片为晶粒)的清理过程相对晶粒堆叠前的清理过程，复杂程度大大降低。此外，相对于现有技术中的晶粒与晶粒键合技术以及晶粒与晶圆的键合技术，每个晶粒都要进行晶粒与晶粒的对准或晶粒与晶圆的对准，由于本申请实施例中，在晶圆与晶圆的堆叠过程，只需要进行一次晶圆与晶圆的对准操作就可以实现多个晶粒与多个晶粒的对准，因而可以提高生产效率，降低生产成本。在此基础上，本申请实施例在制作芯片堆叠结构10时，直接将多个晶圆依次堆叠在一起，因而相对于现有技术中的晶粒与晶粒键合技术以及晶粒与晶圆的键合技术，本申请无需对晶粒进行逐个检验，因而也可以提高生产效率，降低生产成本。基于此，相对于现有技术，本申请实施例制作芯片堆叠结构10的方法采用先将多个晶圆堆叠在一起，有利于简化工艺，节约生产成本。
虽然，本申请实施例在晶圆堆叠前，为了提升生产效率，对晶圆中晶粒是否合格不进行检验，但是在芯片堆叠结构10中的芯片为晶粒的情况下，本申请实施例制作的芯片堆叠结构10可以通过其它方式提高芯片堆叠结构10的良率，例如在制作芯片堆叠结构10的过程中，增加堆叠的晶圆的数量，即增加芯片堆叠结构10中晶粒的数量，可以通过合格的晶粒实现对应的功能；或者，利用冗余的方法，通过多个晶粒实现现有技术中一个晶粒对应的功能。
在一些实施例中，每个芯片100的有源面F还形成有位于第一重新布线层101远离与该第一重新布线层101电连接的芯片100一侧的第三重新布线层109；第三重新布线层109与第一重新布线层101电连接，第二重新布线层102通过第一过孔104与第三重新布线层109电连接；其中，第三重新布线层109中的金属线层105的厚度大于第一重新布线层101中的金属线层105的厚度。
此处，第三重新布线层109的结构可以参考上述实施例，此处不再赘述。
本申请实施例中，由于第三重新布线层109中的金属线层105的厚度大于第一重新布线层101中的金属线层105的厚度，因而第二重新布线层102通过第一过孔104与第三重新布线层109电连接，这样可以确保第二重新布线层102与第三重新布线层109电连接的可靠性，进而提高了第二重新布线层102与芯片100电连接的可靠性。
以下对多个芯片100采用不同堆叠方式时，芯片堆叠结构10的制作方法的具体实现方式进行举例说明。
在一个可选的实施例中，例如制作如图5a所示的芯片堆叠结构10，具体包括如下步骤：
S20、如图7所示，将第三芯片100c堆叠在第一芯片100a上；其中，第三芯片100c的有源面F朝向第一芯片100a的有源面F；第一芯片100a的第一重新布线层101和第三芯片100c的第一重新布线层101之间形成有第二电介质层107。
此处，可以在第一芯片100a的第一重新布线层101远离第一芯片100a的一侧形成第二电介质层107；也可以在第三芯片100c的第一重新布线层101远离第三芯片100c的一侧形成第二电介质层107。附图7以在第一芯片100a的第一重新布线层101远离第一芯片100a的一侧形成第二电介质层107为例进行示意。
此外，第一芯片100a和第三芯片100c可以利用粘结剂连接在一起；也可以利用熔融键合的方式连接在一起。采用熔融键合的方式将第一芯片100a和第三芯片100c连接在一起时，可以避免有机污染(粘结剂通常为有机物)，在芯片100为晶圆的情况下，还可以避免晶圆翘曲等问题，保证了工艺的可靠性。
S21、对第三芯片100c的无源面B进行减薄加工，将第二芯片100b堆叠在第三芯片100c的无源面B，并对第二芯片100b的无源面B进行减薄加工；其中，第二芯片100b的有源面F朝向第三芯片100c的无源面B。
需要说明的是，在芯片堆叠结构10还包括第四芯片100d的情况下，对第三芯片100c的无源面B进行减薄加工之后，将第四芯片100d堆叠在第三芯片100c的无源面B，第四芯片100d的有源面F朝向第三芯片100c的无源面B，并对第四芯片100d的无源面B进行减薄加工；在芯片堆叠结构10还包括第五芯片100e的情况下，对第四芯片100d的无源面B进行减薄加工，将第五芯片100e堆叠在第四芯片100d的无源面B，第五芯片100e的有源面F朝向第四芯片100d的无源面B，并对第五芯片100e的无源面B进行减薄加工；依次类推，此处不再赘述；最后，堆叠第二芯片100b，并对第二芯片100b的无源面B进行减薄加工。
需要说明的是，可以利用物理研磨和/或化学机械抛光的方法对芯片100的无源面B减薄至所需的厚度。
在本申请的一些实施例中，芯片100减薄后，芯片100的最终厚度h的范围为0＜h≤100μm。
此处，相邻两个芯片100可以利用粘结剂连接在一起；也可以利用熔融键合的方式连接在一起。
在一些实施例中，在对第三芯片100c的无源面B进行减薄加工之后，在将第二芯片100b堆叠在第三芯片100c的无源面B之前，该芯片堆叠结构10的制作方法还包括：在第三芯片100c的无源面B一侧形成第三电介质层108。
由于在将第二芯片100b堆叠在第三芯片100c的无源面B之前，在第三芯片100c的无源面B一侧形成了第三电介质层108，因而在将第二芯片100b堆叠在第三芯片100c的无源面B时，可以采用熔融键合的方式将第二芯片100b和第三芯片100c堆叠在一起。相对于通过粘结剂连接，采用熔融键合的方式可以避免有机污染(粘结剂通常为有机物)，且在第二芯片100b和/或第三芯片100c为晶圆的情况下，还可以避免晶圆翘曲等问题，保证了工艺的可靠性。
以下对步骤S21进行详细说明，具体的，如图8所示，首先，对第三芯片100c的无源面B进行减薄加工；接下来，如图9所示，在第三芯片100c的无源面B一侧形成第三电介质层108；接下来，如图10所示，将第四芯片100d堆叠在第三芯片100c的无源面B，第四芯片100d的有源面F朝向第三芯片100c的无源面B，并对第四芯片100d的无源面B进行减薄加工；依次类推，如图11所示，依次堆叠多个芯片，并对最后一个芯片即第二芯片100b的无源面B进行减薄加工。
S22、如图12所示，从第二芯片100b的一侧形成多个第一过孔104，并在第一过孔104内填充导电材料，每个第一过孔104与一层第一重新布线层101电连接。
需要说明的是，从第二芯片100b的一侧形成多个第一过孔104，除了在堆叠方向上的第一芯片100a外，对于其它芯片，制作第一过孔104时，第一过孔104都是由芯片100的无源面B向芯片100的有源面F穿透，因而将该打孔方式也可以称为背面打孔方式，即利用背面打孔方式形成多个第一过孔104。
此处，该步骤的具体实现方式可以参考上述步骤S11。
在每个芯片100的有源面F还形成有位于第一重新布线层101远离与该第一重新布线层101电连接的芯片100一侧的第三重新布线层109的情况下，每个第一过孔104与一层第三重新布线层109电连接。
S23、如图13所示，在堆叠方向上(附图13中用粗箭头表示堆叠方向)，在最后一个芯片100，即第二芯片100b的无源面B一侧形成第二重新布线层102。
此处，第二重新布线层102的结构可以参考上述实施例，此处不再赘述。
S24、如图14所示，在第二重新布线层102远离第二芯片100b的一侧形成与第二重新布线层102电连接的微凸块11。
需要说明的是，该步骤为可选的步骤，例如在一些实施例中也可以省略。
S25、如图5a所示，对第一芯片100a的无源面B进行减薄加工。
此处，可以利用物理研磨和/或化学机械抛光的方法将第一芯片100a的无源面B减薄至所需的厚度。
在上述多个芯片中至少一个芯片为晶圆的情况下，上述制作方法还包括：
S26、对晶圆进行切割，以形成如图5a所示的芯片堆叠结构10。
需要说明的是，步骤S25和步骤S26的顺序可以互换。例如先执行步骤S25，再执行步骤S26，又例如，先执行步骤S26，再执行步骤S25。
此处，步骤S26是可选步骤，在多个芯片均为晶粒的情况下，该步骤可以省略。
基于上述，步骤S21、S22、S23、S24以及S25也可以参照以下步骤制作。
S27、对第三芯片100c的无源面B进行减薄加工，将第二芯片100b堆叠在第三芯片100c的无源面B。
需要说明的是，在芯片堆叠结构10还包括第四芯片100d的情况下，对第三芯片100c的无源面B进行减薄加工之后，将第四芯片100d堆叠在第三芯片100c的无源面B，第四芯片100d的有源面F朝向第三芯片100c的无源面B，并对第四芯片100d的无源面B进行减薄加工；在芯片堆叠结构10还包括第五芯片100e的情况下，对第四芯片100d的无源面B进行减薄加工，将第五芯片100e堆叠在第四芯片100d的无源面B，第五芯片100e的有源面F朝向第四芯片100d的无源面B，并对第五芯片100e的 无源面B进行减薄加工；依次类推，此处不再赘述；最后，堆叠第二芯片100b。
S28、对第一芯片100a的无源面B进行减薄加工。
S29、从第一芯片100a的一侧形成多个第一过孔104，并在第一过孔104内填充导电材料，每个第一过孔104与一层第一重新布线层101电连接。
需要说明的是，从第一芯片100a的一侧形成多个第一过孔104，除了在堆叠方向上的第一芯片100a外，对于其它芯片100，制作第一过孔104时，第一过孔104都是由芯片100的有源面F向芯片100的无源面B穿透，因而将该打孔方式也可以称为正面打孔方式，即利用正面打孔方式形成多个第一过孔104。
S30、在堆叠方向上，在第一芯片100a的无源面B一侧形成第二重新布线层102。
S31、在第二重新布线层102远离第一芯片100a的一侧形成与第二重新布线层102电连接的微凸块11。
需要说明的是，该步骤为可选的步骤，例如在一些实施例中也可以省略。
S32、对第二芯片100b的无源面B进行减薄加工。
上述步骤S27中对第三芯片100c的无源面B进行减薄加工以及步骤S32中对第二芯片100b的无源面B进行减薄加工的方法可以参考上述实施例，此处不再赘述。在另一个可选的实施例中，例如制作如图5b所示的芯片堆叠结构10，具体包括如下步骤：
S40、如图15所示，将第一芯片100a堆叠在载体40上；其中，载体40和第一芯片100a的第一重新布线层101之间形成有第一电介质层103。
此处，可以在第一芯片100a的第一重新布线层101远离第一芯片100a的一侧形成第一电介质层103；也可以在载体40朝向第一芯片100a的一侧形成第一电介质层103。附图15以在载体40朝向第一芯片100a的一侧形成第一电介质层103为例进行示意。
在一些实施例中，上述载体40为载体芯片。在另一些实施例中，上述载体40为载体基板。其中，载体基板的材料可以为玻璃、氧化硅、氮化硅、氮氧化硅中的一种或多种。
在载体40为载体芯片，且在载体40朝向第一芯片100a的一侧形成第一电介质层103的情况下，可以在载体芯片100的有源面F一侧形成第一电介质层103。
在此基础上，第一芯片100a和载体40可以利用粘结剂连接在一起；也可以利用熔融键合的方式连接在一起。采用熔融键合的方式将第一芯片100a和载体40连接在一起时，可以避免有机污染，在第一芯片100a为晶圆的情况下，还可以避免晶圆翘曲等问题，保证了工艺的可靠性。
S41、对第一芯片100a的无源面B进行减薄加工，并将第二芯片100b堆叠在第一芯片100a的无源面B；其中，第二芯片100b的有源面F朝向第一芯片100a的无源面B。
此处，第一芯片100a和第二芯片100b可以利用粘结剂连接在一起；也可以利用熔融键合的方式连接在一起。
需要说明的是，对第一芯片100a的无源面B进行减薄加工之后，如图16所示，在芯片堆叠结构10还包括第三芯片100c的情况下，将第三芯片100c堆叠在第一芯片 100a上，第三芯片100c的有源面F朝向第一芯片100a的无源面B，并对第三芯片100c的无源面B进行减薄加工；在芯片堆叠结构10还包括第四芯片100d的情况下，将第四芯片100d堆叠在第三芯片100c的无源面B，第四芯片100d的有源面F朝向第三芯片100c的无源面B，并对第四芯片100d的无源面B进行减薄加工；在芯片堆叠结构10还包括第五芯片100e的情况下，将第五芯片100e堆叠在第四芯片100d的无源面B，第五芯片100e的有源面F朝向第四芯片100d的无源面B，并对第五芯片100e的无源面B进行减薄加工；依次类推，此处不再赘述；最后，堆叠第二芯片100b。
在一些实施例中，在对第一芯片100a的无源面B进行减薄加工之后，在将第二芯片100b堆叠在第一芯片100a的无源面B之前，该芯片堆叠结构10的制作方法还包括：在第一芯片100a的无源面B一侧形成第三电介质层108。
由于在将第二芯片100b堆叠在第一芯片100a的无源面B之前，在第一芯片100a的无源面一侧形成了第三电介质层108，因而在将第二芯片100b堆叠在第一芯片100a的无源面B时，可以采用熔融键合的方式将第一芯片100a和第二芯片100b堆叠在一起。相对于通过粘结剂连接，采用熔融键合的方式可以避免有机污染(粘结剂通常为有机物)，在第一芯片100a和第二芯片100b为晶圆的情况下，还可以避免晶圆翘曲等问题，保证了工艺的可靠性。
S42、如图17所示，去除载体40。
此处，可以利用切割的方法去除载体40；也可以利用物理研磨和化学机械抛光的方法去除载体40。
S43、如图18所示，从第一电介质层103一侧形成多个第一过孔104，并在第一过孔104内填充导电材料，每个第一过孔104与一层第一重新布线层101电连接。
需要说明的是，从第一电介质层103一侧形成多个第一过孔104时，对于任意一个芯片100，制作第一过孔104时，第一过孔104都是由芯片100的有源面F向芯片100的无源面穿透，因而将该打孔方式也可以称为正面打孔方式，即利用正面打孔方式形成多个第一过孔104。
此处，该步骤的具体实现方式可以参考上述步骤S11。
在每个芯片100的有源面F还形成有位于第一重新布线层101远离与该第一重新布线层101电连接的芯片100一侧的第三重新布线层109的情况下，每个第一过孔104与一层第三重新布线层109电连接。
S43、如图19所示，在第一电介质层103远离第一芯片100a的一侧形成第二重新布线层102。
此处，第二重新布线层102的结构可以参考上述实施例，此处不再赘述。
S44、如图20所示，在第二重新布线层102远离第一电介质层103的一侧形成与第二重新布线层102电连接的微凸块11。
需要说明的是，该步骤为可选的步骤，例如在一些实施例中也可以省略。
S45、如图5b所示，对第二芯片100b的无源面B进行减薄加工。
此处，可以利用物理研磨和/或化学机械抛光的方法将第二芯片100b的无源面B减薄至所需的厚度。
在上述多个芯片中至少一个芯片为晶圆的情况下，上述制作方法还包括：
S46、对晶圆进行切割，以形成如图5b所示的芯片堆叠结构10。
需要说明的是，步骤S45和步骤S46的顺序可以互换。例如先执行步骤S45，再执行步骤S46，又例如，先执行步骤S46，再执行步骤S45。
此处，步骤S46是可选步骤，在多个芯片均为晶粒的情况下，该步骤可以省略。在上述载体40为载体晶圆的情况下，按照S40-S46制作芯片堆叠结构10时会消耗一片载体晶圆。
基于上述，在一些实施例中，将多个芯片100依次堆叠在一起包括：将第m芯片100m堆叠在第n芯片100n上，对第m芯片100m的无源面B进行减薄加工；其中，m，n均为正整数；第m芯片的有源面F朝向第n芯片；形成第二过孔112，并在第二过孔112内填充导电材料；第m芯片100m的第一重新布线层101和第n芯片100n的第一重新布线层101通过第二过孔112电连接。
此处，第m芯片100m和第n芯片100n可以相邻，也可以不相邻。
需要说明的是，各个芯片100的堆叠过程可以参考上述，此处不再赘述。
以下以第m芯片100m为第五芯片100e，第n芯片100n为第三芯片100c为例，说明上述第二过孔112的制作过程。
如图21所示，将第三芯片100c堆叠在第一芯片100a上，第三芯片100c的有源面F朝向第一芯片100a的无源面B，并对第三芯片100c的无源面B进行减薄加工；将第四芯片100d堆叠在第三芯片100c上，第四芯片100d的有源面F朝向第三芯片100c的无源面B，并对第四芯片100d的无源面B进行减薄加工；将第五芯片100e堆叠在第四芯片100d上，第五芯片100e的有源面F朝向第四芯片100d的无源面B，并对第五芯片100e的无源面B进行减薄加工；接下来，形成第二过孔112，并在第二过孔112内填充导电材料，第二过孔112与第三芯片100c的第一重新布线层101和第五芯片100e的第一重新布线层101均接触，从而第五芯片100e的第一重新布线层101和第三芯片100c的第一重新布线层101可以通过第二过孔112电连接在一起，最终实现第三芯片100c和第五芯片100e的电连接。现有技术中在第m芯片100m和第n芯片100n不相邻的情况下，若要实现第m芯片100m和第n芯片100n的电连接，则需要形成多个过孔，从而导致制作芯片堆叠结构10的工序复杂。而本申请实施例中，第m芯片100m的第一重新布线层101和第n芯片100n的第一重新布线层101通过第二过孔112电连接，而一个第二过孔112可以通过一次打孔工艺制作，因而可以简化芯片堆叠结构10的制作工序。
以下提供一个具体的实施例，对上述芯片堆叠结构10及其制作方法进行示例性介绍。
如图22所示，芯片堆叠结构10包括依次堆叠的一个或多个存储芯片110以及一个或多个逻辑芯片111，附图22以包括依次堆叠的四个存储芯片110和一个逻辑芯片111为例，每个逻辑芯片111和存储芯片110的有源面F均形成有第一重新布线层101和第三重新布线层109，第一重新布线层101与逻辑芯片111、存储芯片110接触且电连接，第一重新布线层101和第三重新布线层109电连接。芯片堆叠结构10还包括设置在第一重新布线层101和与该第一重新布线层101相邻的芯片100的无源面B之间的第三电介质层108、与每层第三重新布线层109电连接的多个第一过孔104、设置于 在逻辑芯片111的有源面F的第一电介质层103、设置于第一电介质层103远离逻辑芯片111一侧的第二重新布线层102以及设置于第二重新布线层102远离第一电介质层103一侧的微凸块11。该芯片堆叠结构10可以应用于实现高带宽存储器。根据需要，可以堆叠更多的存储芯片110，以实现更高带宽。
图22所示的芯片堆叠结构10采用正面打孔工艺形成多个第一过孔104，对于任意一个芯片，打孔时第一过孔104由有源面F向无源面B穿透。利用正面打孔工艺形成多个第一过孔104时，在载体40为载体晶圆的情况下，会消耗一片载体晶圆。本申请实施例，由于每个第一过孔104都是采用一次性打孔工艺形成，且通过第一过孔104可以将每个逻辑芯片111和存储芯片110与第二重新布线层102电连接，因而简化了芯片堆叠结构10的制作工艺。当然，也可以将逻辑芯片111和存储芯片110堆叠完成后，采用背面打孔工艺形成多个第一过孔104，采用背面打孔工艺不需要消耗载体晶圆。
在本申请的另一方面，还提供一种与计算机一起使用的非瞬时性计算机可读存储介质，该计算机具有用于创建制作上述芯片堆叠结构10的软件，该计算机可读存储介质上存储有一个或多个计算机可读数据结构，一个或多个计算机可读数据结构具有用于制造上文所提供的任意一个图示所提供的芯片堆叠结构10的控制数据，例如光掩膜数据。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种芯片堆叠结构，其特征在于，包括：依次堆叠的多个芯片以及设置于每个所述芯片的有源面一侧的第一重新布线层；所述第一重新布线层与对应的芯片接触且电连接；
    所述多个芯片包括位于所述芯片堆叠结构最外侧的第一芯片和第二芯片；
    所述第一芯片的无源面和所述第二芯片的无源面均朝向所述芯片堆叠结构的外侧，所述芯片堆叠结构还包括：设置于所述第一芯片的无源面一侧或所述第二芯片的无源面一侧的第二重新布线层；
    或者，所述第二芯片的无源面朝向所述芯片堆叠结构的外侧，所述第一芯片的有源面朝向所述芯片堆叠结构的外侧，所述芯片堆叠结构还包括：设置于所述第一芯片的有源面的第一电介质层和第二重新布线层，所述第一电介质层位于所述第一重新布线层和所述第二重新布线层之间；
    其中，所述第二重新布线层通过第一过孔与至少一层所述第一重新布线层电连接。
  2. 根据权利要求1所述的芯片堆叠结构，其特征在于，所述第二重新布线层位于所述第一芯片的无源面一侧或所述第二芯片的无源面一侧；
    所述多个芯片还包括设置于所述第一芯片和所述第二芯片之间的第三芯片；其中，所述第一芯片的有源面和所述第三芯片的有源面相对，所述第二芯片的有源面朝向所述第三芯片的无源面；
    所述芯片堆叠结构还包括设置于所述第一芯片的有源面和所述第三芯片的有源面之间的第二电介质层。
  3. 根据权利要求1所述的芯片堆叠结构，其特征在于，所述第二重新布线层位于所述第一芯片的有源面；
    所述第二芯片的有源面朝向所述第一芯片的无源面。
  4. 根据权利要求1-3任一项所述的芯片堆叠结构，其特征在于，所述芯片堆叠结构还包括设置在所述第一重新布线层和与所述第一重新布线层相邻的所述芯片的无源面之间的第三电介质层。
  5. 根据权利要求1-4任一项所述的芯片堆叠结构，其特征在于，所述芯片堆叠结构还包括设置在所述第一重新布线层远离与所述第一重新布线层电连接的芯片一侧的第三重新布线层；
    所述第三重新布线层与所述第一重新布线层电连接，且所述第二重新布线层通过所述第一过孔与所述第三重新布线层电连接；
    其中，所述第三重新布线层中的金属线层的厚度大于所述第一重新布线层中的金属线层的厚度。
  6. 根据权利要求1-5任一项所述的芯片堆叠结构，其特征在于，所述芯片堆叠结构还包括设置在所述第二重新布线层远离所述芯片一侧，且与所述第二重新布线层电连接的微凸块。
  7. 根据权利要求1-6任一项所述的芯片堆叠结构，其特征在于，所述芯片堆叠结构还包括第二过孔；
    任意两层所述第一重新布线层之间通过所述第二过孔电连接。
  8. 一种芯片封装结构，其特征在于，包括封装基板和如权利要求1-7任一项所述的芯片堆叠结构；
    所述芯片堆叠结构中的第二重新布线层与所述封装基板电连接。
  9. 一种电子设备，其特征在于，包括印刷电路板以及如权利要求8所述的芯片封装结构；
    所述芯片封装结构中的封装基板与所述印刷电路板电连接。
  10. 一种芯片堆叠结构的制作方法，其特征在于，所述制作方法包括：
    将多个芯片依次堆叠在一起；其中，每个所述芯片的有源面一侧形成有第一重新布线层，所述第一重新布线层与对应的芯片接触且电连接；所述多个芯片包括位于依次堆叠的多个芯片最外侧的第一芯片和第二芯片；
    形成多个第一过孔，并在所述第一过孔内填充导电材料；
    在所述第一芯片的无源面一侧或所述第二芯片的无源面一侧形成第二重新布线层；其中，所述第一芯片的无源面和所述第二芯片的无源面均朝向依次堆叠的多个芯片的外侧；或者，在所述第一芯片的有源面一侧形成第二重新布线层；其中，所述第二芯片的无源面朝向依次堆叠的多个芯片的外侧，所述第一芯片的有源面朝向依次堆叠的多个所述芯片的外侧，且所述第一芯片的有源面还形成有第一电介质层，所述第二重新布线层位于所述第一电介质层远离所述第一重新布线层的一侧；所述第二重新布线层通过所述第一过孔与至少一层所述第一重新布线层电连接。
  11. 根据权利要求10所述的芯片堆叠结构的制作方法，其特征在于，所述将多个芯片依次堆叠在一起，包括：
    将第三芯片堆叠在所述第一芯片上；其中，所述第三芯片的有源面朝向所述第一芯片的有源面；所述第一芯片的所述第一重新布线层和所述第三芯片的所述第一重新布线层之间形成有第二电介质层；
    对所述第三芯片的无源面进行减薄加工，将所述第二芯片堆叠在所述第三芯片的无源面，并对所述第一芯片的无源面或所述第二芯片的无源面进行减薄加工；其中，所述第二芯片的有源面朝向所述第三芯片的无源面。
  12. 根据权利要求11所述的芯片堆叠结构的制作方法，其特征在于，对所述第一芯片的无源面进行减薄加工，所述在所述第一芯片的无源面一侧或所述第二芯片的无源面一侧形成第二重新布线层包括：
    在所述第一芯片的无源面一侧形成第二重新布线层；
    或者，对所述第二芯片的无源面进行减薄加工，所述在所述第一芯片的无源面一侧或所述第二芯片的无源面一侧形成第二重新布线层包括：
    在所述第二芯片的无源面一侧形成第二重新布线层。
  13. 根据权利要求12所述的芯片堆叠结构的制作方法，其特征在于，所述在所述第一芯片的无源面一侧形成第二重新布线层之后，所述制作方法还包括：对所述第二芯片的无源面进行减薄加工；
    或者，所述在所述第二芯片的无源面一侧形成第二重新布线层之后，所述制作方法还包括：对所述第一芯片的无源面进行减薄加工。
  14. 根据权利要求13所述的芯片堆叠结构的制作方法，其特征在于，所述在所述 第一芯片的无源面一侧形成第二重新布线层之后，在所述对所述第二芯片的无源面进行减薄加工之前；或者，所述在所述第二芯片的无源面一侧形成第二重新布线层之后，在所述对所述第一芯片的无源面进行减薄加工之前，所述制作方法还包括：
    在所述第二重新布线层远离所述芯片的一侧形成与所述第二重新布线层电连接的微凸块。
  15. 根据权利要求11所述的芯片堆叠结构的制作方法，其特征在于，所述对所述第三芯片的无源面进行减薄加工之后，所述将所述第二芯片堆叠在所述第三芯片的无源面之前，所述制作方法还包括：
    在所述第三芯片的无源面一侧形成第三电介质层。
  16. 根据权利要求10所述的芯片堆叠结构的制作方法，其特征在于，所述将多个芯片依次堆叠在一起，包括：
    将所述第一芯片堆叠在载体上；其中，所述载体和所述第一芯片的所述第一重新布线层之间形成有第一电介质层；
    对所述第一芯片的无源面进行减薄加工，并将所述第二芯片堆叠在所述第一芯片的无源面；其中，所述第二芯片的有源面朝向所述第一芯片的无源面；
    去除所述载体。
  17. 根据权利要求16所述的芯片堆叠结构的制作方法，其特征在于，所述载体为载体晶圆或载体基板。
  18. 根据权利要求16或17所述的芯片堆叠结构的制作方法，其特征在于，在所述第一电介质层远离所述第一芯片的一侧形成所述第二重新布线层。
  19. 根据权利要求18所述的芯片堆叠结构的制作方法，其特征在于，所述在所述第一电介质层远离所述第一芯片的一侧形成所述第二重新布线层之后，所述制作方法还包括：
    对所述第二芯片的无源面进行减薄加工。
  20. 根据权利要求19所述的芯片堆叠结构的制作方法，其特征在于，所述在所述第一电介质层远离所述第一芯片的一侧形成所述第二重新布线层之后，所述对所述第二芯片的无源面进行减薄加工之前，所述制作方法还包括：
    在所述第二重新布线层远离所述第一电介质层的一侧形成与所述第二重新布线层电连接的微凸块。
  21. 根据权利要求16所述的芯片堆叠结构的制作方法，其特征在于，
    在所述对所述第一芯片的无源面进行减薄加工之后，在所述将所述第二芯片堆叠在所述第一芯片的无源面之前，所述制作方法还包括：
    在所述第一芯片的无源面一侧形成第三电介质层。
  22. 根据权利要求15或21所述的芯片堆叠结构的制作方法，其特征在于，通过熔融键合的方式，将相邻的两个所述芯片连接在一起。
  23. 根据权利要求10-22任一项所述的芯片堆叠结构的制作方法，其特征在于，每个所述芯片的有源面还形成有位于所述第一重新布线层远离与所述第一重新布线层电连接的芯片一侧的第三重新布线层；
    所述第三重新布线层与所述第一重新布线层电连接，所述第二重新布线层通过第 一过孔与所述第三重新布线层电连接；
    其中，所述第三重新布线层中的金属线层的厚度大于所述第一重新布线层中的金属线层的厚度。
  24. 根据权利要求10-23任一项所述的芯片堆叠结构的制作方法，其特征在于，所述多个芯片中至少一个芯片为晶圆；
    所述在所述第一芯片的无源面一侧或所述第二芯片的无源面一侧形成第二重新布线层；或者，在所述第一芯片的有源面一侧形成第二重新布线层之后，所述制作方法还包括：
    对所述晶圆进行切割。
  25. 根据权利要求10所述的芯片堆叠结构的制作方法，其特征在于，所述将多个芯片依次堆叠在一起包括：
    将第m芯片堆叠在第n芯片上，对所述第m芯片的无源面进行减薄加工；其中，m，n均为正整数；所述第m芯片的有源面朝向所述第n芯片；
    形成第二过孔，并在所述第二过孔内填充导电材料；所述第m芯片的所述第一重新布线层和所述第n芯片的所述第一重新布线层通过所述第二过孔电连接。
PCT/CN2020/140360 2020-12-28 2020-12-28 芯片堆叠结构及其制作方法、芯片封装结构、电子设备 WO2022140972A1 (zh)

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