TWI706526B - 藉由混合接合之半導體晶片與另一晶片的組合 - Google Patents

藉由混合接合之半導體晶片與另一晶片的組合 Download PDF

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TWI706526B
TWI706526B TW105125782A TW105125782A TWI706526B TW I706526 B TWI706526 B TW I706526B TW 105125782 A TW105125782 A TW 105125782A TW 105125782 A TW105125782 A TW 105125782A TW I706526 B TWI706526 B TW I706526B
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chips
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wafer
master
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TW105125782A
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TW201721819A (zh
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全箕玟
布倫南 穆勒
保羅 費雪
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美商英特爾股份有限公司
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Abstract

本文說明混合接合，其用於組合一半導體晶片與另一半導體晶片。一些實施例包括將一晶圓上的小晶片附著至一暫時載體；使用該暫時載體將該等晶片對準一主晶圓上之複數個更大主晶片上方；使用該暫時載體將該等小晶片對著該等主晶片施加，使得一子集的該等小晶片接合到各別主晶片；分開該暫時載體，使得該子集的接合小晶片附著至一各別主晶片，且該等剩餘的小晶片與該暫時載體分開；將該等主晶片切單；以及將該等主晶片封裝。

Description

藉由混合接合之半導體晶片與另一晶片的組合
本揭露關於組裝半導體晶片以用於封裝，且尤其關於具有連接在一起之不同尺寸晶片的組件。
為了增加速度與功率效率，且為了減少電子設備的尺寸，積體電路晶片做得越來越小。這些晶片更緊密地安裝在一起，使得這些晶片之間的連接也做得更短。最短的連接係為在積體電路封裝內進行的連接。在一些情形中，晶片並列地安裝在封裝基材上，且透過封裝基材連接在一起，或直接與佈線連接。在其他情形中，晶片一個接著另一個地安裝於其上，以直接連接，而沒有任何中間佈線或封裝基材。這有時稱為堆疊晶片封裝。使用取放(pick and place)機或許多其他類型的設備，可將一個晶片放置於另一個上。可將該組合封裝，就像是具有兩倍高度的單一個晶片。
將多數個晶片組合成單一個封裝，以允許兩個或更多個不同類型的晶片放入單一個封裝內。這可稱為晶片對晶 片連接的非均勻整合。舉一個實例，晶片可使用不同材料來製作，諸如Si、Ge、Ⅲ-V族、SiC等等。舉另一個實例，晶片可使用不同技術節點(諸如22nm、14nm、10nm等等)來製作。可將這些不同點組合，且與其他類型的不同點組合，使得可將來自不同製程與不同製造商的不同類型晶片放在單一個小型封裝內。
2‧‧‧板
4‧‧‧處理器
6‧‧‧通訊晶片
8‧‧‧揮發性記憶體
9‧‧‧非揮發性記憶體
10‧‧‧大量儲存裝置
11‧‧‧計算裝置
12‧‧‧圖形處理器
14‧‧‧晶片組
16‧‧‧天線
18‧‧‧顯示器
20‧‧‧觸控螢幕控制器
22‧‧‧電池
24‧‧‧功率放大器
26‧‧‧全球定位系統裝置
28‧‧‧羅盤
30‧‧‧揚聲器
32‧‧‧照相機
102‧‧‧裝置晶圓
104‧‧‧小晶片
105‧‧‧小晶片
106‧‧‧劃線溝
108‧‧‧暫時黏著劑
110‧‧‧暫時載體
110‧‧‧載體晶圓
112‧‧‧通孔
114‧‧‧傳導柱
114‧‧‧著陸墊
120‧‧‧主晶圓
122‧‧‧主晶片
124‧‧‧傳導線或線跡
126‧‧‧介電質層
130‧‧‧傳導柱或通孔
132‧‧‧傳導性接觸墊或線
134‧‧‧介電質
202‧‧‧裝置晶圓
204‧‧‧晶片
205‧‧‧晶片
206‧‧‧劃線溝或鋸縫
208‧‧‧黏著劑
210‧‧‧暫時載體
212‧‧‧晶片穿孔
304‧‧‧島形晶片
305‧‧‧島形晶片
310‧‧‧載體
314‧‧‧著陸墊
320‧‧‧主晶圓
322‧‧‧晶片
324‧‧‧金屬層
326‧‧‧內層介電質
404‧‧‧小晶片
405‧‧‧小晶片
410‧‧‧暫時載體
412‧‧‧晶片穿孔
414:著陸墊
420:主晶圓
422:主晶片
426:內層介電質
427:內層介電質
502:主晶圓
505:小晶片
514:著陸墊
515:連接墊
520:主晶圓
522:主晶片
530:垂直通孔
532:金屬路由層
534:內層介電質
605:小晶片
614:著陸墊
620:主晶圓
622:主晶片
624:連接墊
642:微C4凸塊
646:接觸墊
648:封裝基材
本發明的實施例係藉由示例的方式而非藉由限制的方式來繪示，在附加圖式的圖中，相同的參考數字意指相似的元件。
圖1係一部分裝置晶圓的側截面圖圖式，根據一實施例，該裝置晶圓承載多個小晶片、於各晶片之間具有劃線溝。
圖2係根據一實施例、使用暫時黏著劑將暫時載體附著到小晶片前側之裝置晶圓的側截面圖圖式。
圖3係根據一實施例、使裝置晶圓變薄到劃線溝水平之後、裝置晶圓與暫時載體的側截面圖圖式。
圖4係根據一實施例、將晶片穿孔添加到小晶片的後側上之後、裝置晶圓與暫時載體的側截面圖圖式。
圖5係根據一實施例、以用於其中一小晶片的著陸墊、在承載主晶片之主晶圓的一部分上方、將裝置晶圓與暫時載體對準的側截面圖圖式。
圖6係根據一實施例、將其中一小晶片的晶片穿孔接 合到主晶片之著陸墊的側截面圖圖式。
圖7係根據一實施例、將暫時載體與沒有接合的其他小晶片自主晶圓移除的側截面圖圖式。
圖8係根據一實施例、將介電質與金屬路由層添加在小晶片上方以完成封裝的側截面圖圖式。
圖9係根據一實施例、承載多個小晶片之裝置晶圓(具有介於各晶片之間的劃線溝以及具有從晶片電路至裝置晶圓內的晶片穿孔)的側截面圖圖式。
圖10係根據一實施例、具有晶片穿孔之裝置晶圓(使用暫時黏著劑將暫時載體附著到小晶片前側)的側截面圖圖式。
圖11係根據一實施例、具有晶片穿孔之裝置晶圓與暫時載體(在使裝置晶圓變薄到劃線溝與晶片穿孔之水平以後)的側截面圖圖式。
圖12係根據一實施例、以用於其中一小晶片的著陸墊、在承載主晶片之主晶圓的一部分上方、將裝置晶圓與暫時載體對準的側截面圖圖式，其中介電質形成於著陸墊周圍，但卻凹陷以暴露著陸墊。
圖13係根據一實施例、以用於其中一小晶片的著陸墊、在承載主晶片之主晶圓的一部分上方、將裝置晶圓與暫時載體對準的側截面圖圖式，其中介電質層在著陸墊周圍凹陷，且亦在第二小晶片的位置處凹陷，使得第二小晶片沒有實體接觸介電質。
圖14係根據一實施例、將小晶片的前側面對面接合 至主晶片前側、使得變薄的基材是在與著陸墊對置之小晶片側上的側截面圖圖式。
圖15係根據一實施例、將面對面接合的小晶片覆蓋在介電質與金屬層、以連接主晶片到外部組件且完成封裝之後的側截面圖圖式。
圖16係根據一實施例、使用小焊球將小晶片的前側面對面接合至主晶片前側的側截面圖圖式。
圖17係根據一實施例、經面對面焊球接合的小晶片主晶片組合(附著習知的C4焊球)的側截面圖圖式。
圖18係根據一實施例、經面對面焊球接合之小晶片主晶片組合的側截面圖圖式，其顯示使用C4焊球附著到封裝基材，以完成封裝。
圖19係根據一實施例、將計算裝置結合混合接合混合半導體晶片封裝的方塊圖。
【發明內容及實施方式】
如本文中所說明，可將功能性小晶片或島形物整合到建構在主晶圓上之晶片上的現存位置內。藉由使用晶圓級處理，可整批地處理非常小且薄的晶片。整個晶圓可一次處理，而非在小位置內操縱單一個小晶片，但晶片卻只傳輸到主晶圓上之更大晶片的選定區域。
在一些情形中，可使用混合接合，以減少將島形物附著到晶片所施加的熱量。這允許使用較低的製程溫度。相較於其他類型的永久接合，如所說明的，混合接合在相對 低溫產生強接合。可使用混合接合，以提供更低的總熱預算或更寬的製程窗，以使島形物自載體晶圓脫離。
在一些說明的實例中，含有小晶片的載體晶圓係接合到主晶圓。在主晶圓上的小晶片或島形物與所形成的晶片兩者均具有金屬著陸墊、晶片穿孔或一些其他的金屬連接器。藉由放置載體晶圓於主晶圓上方，使得能對準著陸墊，且隨後施加輕度的熱與壓力，金屬墊與穿孔則形成強接合。不具有金屬著陸墊的區域則僅僅非常微弱地附著在一起。
在施加輕度熱與壓力之後，載體與主晶圓會分開，以選擇性地將島形物傳輸到大晶片的接合區域。假如有島形物留在載體晶圓上，那麼則可將載體晶圓放置在另一主晶圓上方，以將其中一些島形物傳輸到另一組大晶片。這可重複，直到放置好全部島形物為止。
如所說明的，在晶圓上，將小晶片成組地處理。當固持在載體晶圓上時，可將非常小且薄的晶片傳輸。該等晶片比由晶片取放組件可輕易操縱者還更小且更薄很多。藉由形成互連件在島形物的頂部與底部兩者上，可獲得更多的路由資源。使用暫時載體，對著主晶片，施加小晶片，使得在載體晶圓上的一些小晶片或一子集的全部晶片能接合到在主晶圓上的各別主晶片。該施加可能沒有實質壓力，或者可能施加壓力，以將該等晶片的金屬壓在一起。亦可能使用熱，而不是用壓力。
圖1至圖8顯示一實例製程，其用於將小島形晶片放 在一位置中，使得該小島形晶片可能完全嵌入在主晶片內。圖1係為一組小晶片104、105形成在裝置晶圓102上的側截面圖。裝置晶圓係為上面形成晶片的基材，其係並且牢固地承載晶片。可藉由鋸、劃線、或蝕刻將晶片部分地切塊，使得介於晶片之間有劃線溝106或鋸縫，該劃線溝106或鋸縫並且到晶圓102內。
在此實例中，將晶片視為是小的，這僅僅意味著該等晶片比起所將附著的主晶片更小。小晶片可以是主晶片尺寸的一半，該尺寸或任何其他相關尺寸的十分之一。裝置晶圓含有將傳輸到已經形成在主晶圓上之晶片的許多小晶片。該等晶片可以是對與主晶圓整合有益的功能性材料。此等功能性材料的實例可包括矽、鍺、碳化矽、Ⅲ-V族以及Ⅲ族氮化物化合物半導體。因為小晶片獨立地形成在分開的晶圓上，所以其等可使用與主晶片不同的技術、不同的材料、或不同的製程節點來形成。小晶片可以是功率、射頻、光學、記憶體、或其他類型的裝置，其係最佳與主晶圓分開形成。
圖2係為圖1之裝置晶圓102反向且使用暫時黏著劑108附著到暫時載體110的截面側圖圖式。晶片104、105的前側係由載體覆蓋，且晶圓102的後側暴露。此裝置晶圓接合到暫時載體晶圓，使得晶圓可藉由載體來處理。選擇暫時黏著劑，以承受在研磨晶圓期間可能導致的任何機械力以及在使晶圓變薄期間的任何熱或機械性過載。這些力可包括剪力、壓縮力、拉力等等。亦選擇暫時黏著劑， 使得當必要時可輕易地將晶片自載體脫黏。一種此種類的黏著劑係為聚合物黏著劑。聚合物黏著劑可包括聚甲基丙烯酸鹽、聚丙烯酸酯、聚苯乙烯、聚矽倍半氧烷、聚矽氧烷、聚降冰片烯、聚醯亞胺、聚苯並噁唑、環氧樹脂、酚醛清漆、苯環丁烯、以及聚碳酸酯。無機黏著劑可包括植入H的矽(或植以其他揮發性物種的矽)或非晶Si：H。
圖3係圖2的裝置晶圓與晶片在裝置變薄之後的截面側圖圖式。這可藉由研磨或以任何其他方式來進行。在其他方式中，可使用體型微加工技術，諸如研磨、溼式蝕刻、乾式蝕刻及化學機械拋光。變薄的數量或變薄的目標在整合度上改變。假如將晶片嵌入到互連堆疊內，如圖8所示，那麼晶片則不需要結構穩定性，且晶圓可做得非常薄，例如，小於1μm厚。舉另一個實例，假如將小晶片嵌入，以作為C4或封裝的一部分，如在圖18中，那麼晶片則需要一些機械性補強與穩定性，但仍可僅僅是數十微米厚。
在此實例中，劃線溝延伸到裝置晶圓內。劃線溝做得夠深，使得裝置晶圓變薄達到劃線溝。由於圖3，在變薄之後，晶片藉由劃線溝來切單。以此方式，當晶片附著到暫時載體時，晶片藉由裝置晶圓而維持在它們最初的位置中。在附著與變薄之後，藉由暫時載體來維持對準。可使用此精確的對準，將小晶片準確地放置在主晶圓上，如圖6所示。
圖4係為圖3之晶片104、105添加通孔112的側截 面圖。在變薄之後，可製造「晶片穿孔」。這與矽穿孔(TSV)類似，但卻鑽、蝕刻、或鑽孔穿過後側基材或晶圓，以與晶片的前端電路進行接觸。所鑽的孔隨後填以金屬(諸如Cu、Ti、Ta)，以進行連接。將該等孔過量充填，使得在通孔頂部上的金屬表面暴露。
圖5係為晶片與暫時載體再度反向使得晶片的後側面向下之圖式。圖5亦顯示形成在主晶圓120上的對應更大主晶片122。主晶圓亦具有下方堆疊。有形成著陸墊至小晶片105之晶片穿孔的垂直傳導柱114。大晶片具有傳導再分配層或其他金屬或傳導層(在晶片上方具有傳導線或線跡124)。著陸墊114提供用於通道到這些金屬層的連接。如圖示，將兩晶圓(主裝置晶圓120與載體晶圓110)對準。
圖6係為接合兩晶圓的圖式。在對準之後，例如藉由將載體晶圓與兩晶片105、122移動在一起，可使兩晶圓在一起。在繪示的圖中，兩晶片接台。將通孔的金屬頂表面施加到著陸墊，使得它們實體上彼此接觸。可施加熱或壓力或兩者，以形成充分的金屬接合。就壓力而言，將通孔壓抵著陸墊。就熱而言，將主晶圓與暫時載體放在加熱室中，或施加熱，以協助兩晶片接合在一起。可調整情況，以形成強的金屬接合。在此實例中，主要由ILD(層間介電質)做的主晶圓的剩下區域僅具有非常弱的接合，使得這些區域稍後將能分開。
可使用多種不同的接合機構，以將小晶片連接到主晶 片。在一些實施例中，使用金屬內部擴散，穿過具有晶粒生長的接合邊界。在此情形中，因為金屬之間的擴散率與溫度相依，所以更高的溫度可導致更快且更強的接合。不過，更高的溫度亦影響晶片之其他材料的特徵，以及甚至靠近內部金屬擴散接合的那些，譬如在混合接合介面處的ILD。如本文所說明，使用較低溫度減少或消除對材料的任何負面影響，除了接合金屬以外。
在一些實施例中，不施加熱，且在室溫將金屬接合。在其他實施例中，溫度提高到100℃或甚至到200℃或到介於之間的某溫度。這促進金屬之間的擴散而沒有傷害其他材料。在使用本文中所說明之混合接合來接合金屬之後，可將具有沒有接合之晶片的暫時載體移除。在一些實施例中，可允許接合金屬在分開之前冷卻。這將提供用於甚至更強的金屬對金屬接合。當將暫時載體移除時，如圖7所示，金屬對金屬接合比暫時的接合黏著劑更強。黏著劑接合的強度可使用於具體判定如何控制用於任何特定實施方案的金屬對金屬接合。
圖7係使載體晶圓與主晶圓分開的圖式。這導致兩晶片分開。在暫時黏著劑上的接合比金屬或混合接合更弱。在一些實施例中，可施加一些外部刺激，譬如熱，以減弱在島形晶片與暫時載體晶圓之間的接合。在分開之後，可使用載體晶圓，以施加晶片到另一主晶圓。
如圖示，主晶圓在對應該等小晶片中只有一個的位置中具有著陸墊114。圖5顯示兩個小晶片在一個大主晶片 122的表面上方。在晶片穿孔形成於兩個小晶片的同時，只有其中一個晶片的通孔接觸主晶圓上的著陸墊。其他晶片的通孔則接觸主晶片的介電質層126。因此，金屬接合僅僅發生於接觸著陸墊的小晶片105。其他晶片104沒有接合但卻仍然連接到暫時載體。
在圖7分開時，金屬熱或壓縮接合是比暫時黏著劑更強的接合。結果，當暫時載體移除時，在著陸墊上方的晶片與主晶片留著。在晶片穿孔與介電質之間沒有明顯接合。因為暫時黏著劑比此接合更強，所以第二晶片藉由暫時載體自主晶片抬開。如上文所提及，藉由劃線溝106，晶片已經與一部分晶圓分開，如圖示。於是，在圖3，使晶圓變薄之後，只有載體使晶片固持在一起。這些晶片已經予以切塊或切單。
圖8係為暫時載體與其他小晶片經移除的圖式。附著小晶片者仍然金屬接合至主晶片。進一步將主晶圓處理，以將經傳輸的小晶片完全嵌入到互連堆疊內。在所示的實例中，進一步處理包括額外介電質134、額外傳導柱或通孔130、以及用以連接至其他組件的傳導性接觸墊或線132。如圖示，較小的晶片105完全嵌入於主晶片的ILD內。這允許特殊的功能並允許特定的晶片結合到更大的晶片組件內，而沒有在主晶片的封裝與其他處理態樣上有任何變化。
在本實例中，只有兩個小晶片104、105顯示於裝置晶圓102上。一般而言，將會有更多。這些晶片一起形成 在裝置晶圓上。隨後它們會受到測試。這些功能性晶片可承載於晶圓上，並且成組地受到操縱。類似地，主晶圓120僅僅顯示具有部分的單個晶片122，不過，將會有更多。傳輸操作可使用晶圓處置器來施行，使得在一次操作中，將許多小晶片傳輸到許多主晶片。隨後可移動暫時載體，以將更多的小晶片傳輸到在主晶片上之不同位置處的相同主晶圓，或者可將它移動，以將小晶片傳輸到不同主晶圓的晶片。
與其他TSV(矽穿孔)製程類似的，圖4的晶片穿孔可用先通孔或後通孔的方式來製造。圖4顯示後通孔的方式，其中，在完全形成晶片(圖1)且已經使晶圓變薄(圖3)之後，通孔形成在晶片的後側或晶圓側上。圖9至圖11顯示替換的先通孔製程。
圖9係為圖1裝置晶圓之替換物的截面側圖圖式。在此情形中，兩晶片204、205形成在晶圓202上，如在圖1，除了在施加晶片的上層之前形成晶片穿孔212以外。因此這些通孔在晶片變薄之前就已形成。將用於通孔的孔洞鑽或鑽孔到晶圓內的深度，使得在變薄之後暴露。該等晶片已經分開，且劃線溝或鋸縫206顯示介於晶片之間。
圖10係在暫時載體210以黏著劑208附著之後、相同晶片204、205的圖式。圖11係在晶圓已經變薄之後、相同裝置晶圓202的圖式。如圖示，使變薄的晶圓向下到現在暴露之晶片穿孔212的水平以下。該結構非常類似圖4的結構，且可使用於與圖5至圖8所示的相同製程中， 或使用於其他製程中。
如另一選項，為了改善接合與鬆開，金屬性的著陸墊可突出到相鄰的ILD以上。圖12係主晶圓的截面側圖圖式，其中ILD已經移到著陸墊的水平以下。主晶圓320具有許多晶片，其中顯示一晶片322的一部分。在形成晶圓之後，有許多金屬層，且ILD 326與著陸墊314形成，以與金屬層324進行連接，以與晶片的電路連接。在形成著陸墊之後，ILD已經移除。著陸墊現在突出到ILD上方。
島形晶片304、305係以上文說明的任何方式形成，且附著到載體310。該等晶片是分開的，且具有準備與著陸墊314進行金屬連接的晶片穿孔。當以相關於圖6與圖7來說明的方式使兩者靠在一起時。晶片穿孔將因為ILD已經移除而與暴露的著陸墊314進行更明顯的接觸且將不會干擾。這可導致更強且更牢固的金屬壓縮接合。不在著陸墊上方的晶片304甚至不會與ILD進行接觸。這將防止任何與主晶片的接合，使得當分開時，在與暫時載體的接合上，甚至有更少的應力。
圖13顯示另一替換物。在圖13中，形成與將接合之小晶片尺寸匹配的台面，而不是如在圖12中金屬著陸墊突出、全部ILD凹入。換句話說，ILD僅僅在沒有晶片接合之處凹入。
圖13係類似的小晶片404、405彼此分開且附著到暫時載體410的截面側圖圖式。在其中一晶片中的晶片穿孔412的位置，係直接在其本身主晶圓420上之大或主晶片 422的著陸墊414上方。著陸墊係在多層ILD 426的頂部。ILD 427已經凹入於沒附著的晶片405下方。在將附著的晶片下方，ILD 426不會改變。結果，當使小晶片與大晶片在一起時，如在圖6中，在沒有著陸墊、ILD凹入處的小晶片將不會與主晶片進行任何實體接觸。假如有任何接觸，將是以比著陸接點上方之小晶片更小的壓力。
在著陸接點414上方的小晶片405將以與相關於圖6來說明的相同方式而接合到主晶片422。當暫時載體抬起晶片時，如圖7，在著陸接點上方的小晶片將接合到主晶片。在凹入的ILD上方的小晶片將與主晶片有很少實體接觸或無實體接觸，且與主晶片有很少至無的接合。此晶片將與暫時載體留在一起，且自其抬起。
圖14係進一步替換物的截面側圖圖式，其中小晶片與主晶片面對面地附著。在以上實例中，使用晶片穿孔，以將小晶片的後側附著到主晶片的前側或面。假如小晶片的前側附著到主晶片，則可在沒有晶片穿孔之下得到混合接合。
在圖14中，主晶片522形成在具有多層金屬線與ILD的主晶圓520上。著陸柱514形成在適當位置，以與小晶片進行電性連接。小晶片505係放置在主晶片上方，其前側向下或面對主晶圓。小晶片已經形成在與主晶片相反的晶圓502上。小晶片亦具有金屬層與ILD，且最頂部的金屬層具有連接墊515，以與著陸柱進行接觸。在本實例中，最頂層係為最接近主晶片者。
當將小晶片載體110(未圖示)施加到主晶片時，如在圖6，著陸墊514進行金屬連接到小晶片並且接合。可使用混合接合製程，如上文所說明，使用壓力或熱或兩者。使用金屬接觸層，而非使用晶片穿孔，會在小島形晶片與主晶片之間提供更多數的可用連接。這至少部分因為比起晶片穿孔，前側連接可能做得更緊密、更牢固，以用於更高的節距。依據特定的實施方案，小晶片晶圓可能或不可能變薄。
圖15顯示藉由添加額外路由到主晶片以完成圖14之結構的實例。將晶片嵌入ILD 534中，且添加額外的垂直通孔530與金屬路由層532，以提供從主晶片至外部組件的連接。在此實例與圖8的實例中，小晶片僅連接到主晶片，不過，可能會有額外的通孔與路由層，以在小晶片與外部組件之間提供直接或不直接的連接。
本文中所說明的技術與結構不僅使用於後段級整合上，而且使用於C4(控制塌陷高度晶片連接)或遠後段級整合上。圖16係使用微C4凸塊之小晶片整合之實例的截面側圖圖式。主晶片622已經形成在主晶圓620上。主晶片具有連接墊624於頂部金屬層處，以及具有著陸墊614形成於連接墊上方。小晶片605以金屬連接網格形成於基材662上方。在此情形中，小晶片前端面對主晶片前端地放置，不過，小晶片605可反向，如在圖6中。小或微C4凸塊642已經放在著陸墊各個上，而不是直接金屬壓縮或熱接合。當使小晶片與主晶片接觸時，接觸層沒有 直接接觸主晶片，但卻經由微C4凸塊接觸主晶片。將該組件回焊，使得C4凸塊提供連接於兩晶片之間。這導致如圖示之組件的完成。
結果產生的結構可如圖8所示地完成。或者，可使用標準C4或焊料凸塊附接到封裝基材來完成該組件。在圖17中，規則的C4凸塊係施加到開啟區域且在主晶片622上接觸。在圖18中，主晶片附著至封裝基材648。焊料凸塊係施加到該封裝的接觸墊646。該組件隨後放置在回焊爐中，使得焊料凸塊接合到該封裝與晶片。
雖然只有顯示一小晶片與一個C4凸塊，但是可能會有更多的晶片且將會有更多的C4凸塊。如圖示，具有變薄晶圓的小晶片能夠附著在C4或焊料凸塊的陣列內。結果，額外的小晶片不會影響整個封裝的尺寸。藉由在分開製程中形成小晶片，小晶片可含有可能形成在主晶片上之非常不同的組件。非均勻的積體裝置是可實現的，諸如具有Ⅲ-V族電壓調整器、光學波導、多種被動裝置、或射頻調變器的矽處理晶片。
圖19繪示根據本發明一項實施方案的計算裝置11。計算裝置11將板2罩住。板2可包括一些組件，包括但不限於處理器4與至少一通訊晶片6。處理器4實體且電性耦合至板2。在一些實施方案中，至少一通訊晶片6亦實體且電性耦合至板2。在進一步實施方案中，通訊晶片6係為處理器4的一部分。
依據其應用，計算裝置11可能包括可能或可能不會 實體且電性耦合至板2的其他組件。這些其他組件包括但不限於揮發性記憶體(例如，DRAM)8、非揮發性記憶體(例如，ROM)9、快閃記憶體(未圖示)、圖形處理器12、數位訊號處理器(未圖示)、密碼處理器(未圖示)、晶片組14、天線16、顯示器18(諸如觸控螢幕顯示器)、觸控螢幕控制器20、電池22、音訊編解碼器(未圖示)、視訊編解碼器(未圖示)、功率放大器24、全球定位系統(GPS)裝置26、羅盤28、加速度計(未圖示)、陀螺儀(未圖示)、揚聲器30、照相機32、以及大量儲存裝置(諸如硬式磁碟機)10、光碟片(CD)(未圖示)、數位多功能光碟(DVD)(未圖示)、等等。這些組件可連接至系統板2、安裝至系統板、或與任何其他組件組合。
通訊晶片6實現無線及/或有線通訊，以傳輸資料往返計算裝置11。術語「無線」及其衍生物可使用來說明電路、裝置、系統、方法、技術、通訊通道等等，其可透過使用經過非固態媒介的調變電磁輻射來通訊資料。該術語沒有意指相關裝置不含有任何佈線，雖然在一些實施例中該等相關裝置可能不含。通訊晶片6可實施一些無線或有線標準或協定的任一者，包括但不限於Wi-Fi(IEEE 802.11家族)、全球互通微波存取(WiMAX)(IEEE 802.16家族)、IEEE 802.20、長期演進(LTE)、演進資料最佳化(Ev-DO)、增強版高速封包存取(HSPA+)、增強版高速下行封包存取(HSDPA+)、增強版高速上行 封包存取(HSUPA+)、GSM增強數據率演進(EDGE)、全球行動通訊系統(GSM)、通用封包無線服務技術(GPRS)、分碼多重進接(CDMA)、分時多工(TDMA)、數位增強無線通訊(DECT)、藍芽、其衍生物、以及被指定為3G、4G、5G、以及以上的任何其他無線與有線協定。計算裝置11可包括複數個通訊晶片6。例如，第一通訊晶片6可專用於較短範圍的無線通訊，譬如WiFi與藍芽，且第二通訊晶片6可專用於較長範圍的無線通訊，譬如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、以及其他。
計算裝置11的處理器4包括封裝在處理器4內的積體電路晶片。在本發明的一些實施方案中，處理器、記憶體裝置、通訊裝置、或其他組件的積體電路晶片包括或封裝在一起且接合在主晶片上，如本文中所說明的。術語「處理器」可意指處理來自暫存器及/或記憶體的電子資料以將那電子資料轉換成可儲存在暫存器及/或記憶體中之其他電子資料的任何裝置或一裝置的任何部分。
在多種實施方案中，計算裝置11可以是膝上型電腦、小筆電、筆記型電腦、超輕薄筆電、智慧型手機、平板、個人數位助理(PDA)、超級行動個人電腦、行動電話、桌上型電腦、伺服器、印表機、掃瞄器、監視器、機上盒、娛樂控制單元、數位照相機、可攜式音樂播放器、或數位視訊記錄器。在進一步實施方案中，計算裝置11可能是處理資料的任何其他電子裝置，包括可穿戴裝置。 以一或多個記憶體晶片、控制器、CPU(中央處理單元)、使用主機板互連的微晶片或積體電路、特殊應用積體電路(ASIC)、及/或場可程式化閘陣列(FPGA)的一部分，可將實施例實施。
提及「一項實施例」、「一實施例」、「實例實施例」、「多項實施例」等等，指示如此說明的本發明實施例可包括特定特徵、結構、或特色，但不是各實施例一定包括特定特徵、結構、或特色。再者，一些實施例可具有一些、全部、或不具有針對其他實施例來說明的特徵。
在接下來的說明與申請專利範圍中，可使用術語「耦合」連同其衍生物。「耦合」係使用來指示兩或多個元件彼此合作或互動，但是在其等之間可能或可能不具有中介的實體或電性組件。
如在申請專利範圍中所使用的(除非另有指定)，用以說明常用元件之序數形容詞(「第一」、「第二」、「第三」等等)的使用，僅僅指示相同元件的不同情形正令人提及，其係並且不打算意指如此說明的元件必須呈特定順序(時間性、空間性、順序、或任何其他方式)。
圖式與先前說明產生實施例的實例。所屬技術領域中具有通常知識者將理解，所說明元件中的一個或多個可能充分組合成單一個功能性元件。或者，特定元件可分成多個功能性元件。來自一項實施例的元件可添加到另一實施例。例如，本文中所說明之製程的順序可能會改變，而且不限於本文中所說明的方式。更者，任何流程圖的動作不 需要按所示的順序實施；不一定需要施行全部的動作。同樣地，沒有依據其他動作的那些動作可與其他動作平行施行。實施例的範圍絕不受到這些具體實例限制。許多變化均是可能的(諸如結構、尺寸、及材料使用中的差異)，不論是否在說明書中明確產生。實施例的範圍至少與接下來申請專利範圍所產生的一樣寬。
以下實例與進一步的實施例有關。不同實施例的許多特徵可多方面地結合所包括的一些特徵及不包括的其他特徵，以適合許多不同的應用。一些實施例與一種方法有關，該方法包括將一晶圓上的小晶片附著至一暫時載體；使用該暫時載體將該等晶片對準一主晶圓上之複數個更大主晶片上方；使用該暫時載體對著該等主晶片施加該等小晶片，使得一子集的該等小晶片接合到各別主晶片；分開該暫時載體，使得該子集的接合小晶片附著至一各別主晶片，且該等剩餘的小晶片與該暫時載體分開；將該等主晶片切單；以及將該等主晶片封裝。
在進一步實施例中，施加進一步包含將該等小晶片壓抵該等主晶片。
在進一步實施例中，施加進一步包含加熱該等小晶片同時壓著該等小晶片，該加熱係在小於一迴焊溫度的一溫度。
進一步實施例包括劃線通過該等小晶片，使得該等小晶片具有劃線溝，以透過一部分的該小晶片晶圓來分開該等晶片，且在將該等晶片附著至該暫時載體之後使該小晶 片變薄，使得該等晶片藉由該等劃線溝來分開。
在進一步實施例中，將該暫時載體附著至該等晶片的前側，該方法進一步包含形成通過該等晶片之後側的通孔，以連接至一各別主晶片。
在進一步實施例中，將該暫時載體附著至該等晶片的後側，該方法進一步包含形成矽穿孔於該等晶片的前側上，以連接至一各別主晶片。
進一步實施例包括將著陸墊形成於接合至一小晶片之位置處的該等主晶片上，且其中該等小晶片在該等著陸墊處接合至該等主晶片。
在進一步實施例中，將該等著陸墊形成在一介電層上方，該方法進一步包含將圍繞該等著陸墊的一部分該介電層移除，以將該等著陸墊暴露至一各別小晶片。
在進一步實施例中，將該等著陸墊形成於一介電層上方，該方法進一步包含將該等著陸墊旁之該介電層的一部分移除，以防止將被接合至該主晶片之該小晶片旁的一小晶片接觸該主晶片。
進一步實施例包括將一焊料球附著至該等著陸墊各者，其中該等小晶片透過該焊料球在該著陸墊處接合至該等主晶片。
在進一步實施例中，該接合係為一金屬壓縮接合。
在進一步實施例中，封裝包含將該小晶片覆蓋於一介電質中，且形成金屬路由層於該介電質中，以將該主晶片連接至外部組件。
在進一步實施例中，封裝包含將一焊料球陣列附著至該小晶片周圍的該主晶片，且將該焊料球陣列附著至一封裝基材。
一些實施例與一種多重晶片封裝有關，其包括：一主晶片；複數個小晶片，其小於形成在一晶圓上的該主晶片、附著至一暫時載體、使用該暫時載體對準同時在主晶圓上的該主晶片上方、且使用該暫時載體對著該主晶片施加，該等小晶片具有至該主晶片的一混合接合；以及一封裝，其用以將該主晶片與該等小晶片一起覆蓋。
進一步實施例包括在將接合至一小晶片的位置處之該主晶片上的著陸墊，該等著陸墊係形成在一介電層上方，以及用以接合至該等著陸墊之該小晶片上的金屬接點。
進一步實施例包括將該小晶片與該主晶片覆蓋的一介電質，以及用以將該主晶片連接至外部組件之該介電質中的金屬路由層。
一些實施例與一種方法有關，其包括：形成複數個小晶片於一晶圓上，該等小晶片具有用以附著至主晶片的金屬接點；將該等小晶片附著至一暫時載體；形成複數個較大主晶片於一主晶圓上；形成一介電層於該等主晶片各者的至少一部分上；形成著陸墊於將接合至一小晶片之位置處的該等主晶片上；將圍繞該等著陸墊的一部分該介電層移除，以將該等著陸墊暴露至一各別小晶片；使用該暫時載體將該等晶片對準該主體上方；加熱該等小晶片；使用該暫時載體將該等小晶片的該等金屬接點，壓抵該等主晶 片的該等著陸墊上，使得一子集的該等小晶片接合到各別主晶片；將該暫時載體分開，使得該子集的接合小晶片附著至一各別主晶片，且該等剩餘的小晶片與該暫時載體分開；將該等主晶片切單；以及將該等主晶片封裝。
在進一步實施例中，形成複數個小晶片包含使用一第一製造技術來形成該等小晶片，且其中形成複數個主晶片包含使用與該第一製造技術不同的一第二製造技術來形成該等主晶片。
在進一步實施例中，將該等小晶片附著至該暫時載體，包含將該等晶片的前側附著至該暫時載體、使該等晶片的後側變薄、形成通孔穿過該等晶片的該等後側以連接至一各別主晶片、以及將該等小晶片彼此分開同時附著至該暫時載體。
在進一步實施例中，封裝包含在分開該暫時載體之後將該小晶片覆蓋在一介電質中，以及形成金屬路由層在該介電質中，以將該小晶片連接至外部組件。
102‧‧‧裝置晶圓
104‧‧‧小晶片
105‧‧‧小晶片
106‧‧‧劃線溝

Claims (18)

  1. 一種組合晶片的方法，其包含：將一晶圓上的小晶片附著至一暫時載體；使用該暫時載體將該等晶片對準一主晶圓上之複數個更大主晶片上方；使用該暫時載體對著該等主晶片施加該等小晶片，使得一子集的該等小晶片接合到各別主晶片；分開該暫時載體，使得該子集的接合小晶片附著至一各別主晶片，且該等剩餘的小晶片與該暫時載體分開；將該等主晶片切單；以及將該等主晶片封裝；其中，該方法進一步包含劃線通過該等小晶片，使得該等小晶片具有劃線溝，以透過一部分的該小晶片晶圓來分開該等晶片，且在將該等晶片附著至該暫時載體之後使該小晶片變薄，使得該等晶片藉由該等劃線溝而分開。
  2. 如申請專利範圍第1項之方法，其中施加進一步包含將該等小晶片壓抵該等主晶片。
  3. 如申請專利範圍第2項之方法，其中施加進一步包含加熱該等小晶片同時壓著該等小晶片，該加熱係在小於一迴焊溫度的一溫度。
  4. 如申請專利範圍第1項之方法，其中將該暫時載體附著至該等晶片的前側，該方法進一步包含形成通過該等晶片之後側的通孔，以連接至一各別主晶片。
  5. 如申請專利範圍第1項之方法，其中將該暫時載體 附著至該等晶片的後側，該方法進一步包含形成矽穿孔於該等晶片的前側上，以連接至一各別主晶片。
  6. 如申請專利範圍第1項之方法，其進一步包含將著陸墊形成於將接合至一小晶片之位置處的該等主晶片上，且其中該等小晶片在該等著陸墊處接合至該等主晶片。
  7. 如申請專利範圍第6項之方法，其中該等著陸墊形成在一介電層上方，該方法進一步包含將圍繞該等著陸墊的一部分該介電層移除，以將該等著陸墊暴露至一各別小晶片。
  8. 如申請專利範圍第6項之方法，其中將該等著陸墊形成於一介電層上方，該方法進一步包含將該等著陸墊旁之該介電層的一部分移除，以防止將被接合至該主晶片之該小晶片旁的一小晶片接觸該主晶片。
  9. 如申請專利範圍第6項之方法，其進一步包含將一焊料球附著至該等著陸墊各者，其中該等小晶片透過該焊料球在該著陸墊處接合至該等主晶片。
  10. 如申請專利範圍第1項之方法，其中該接合係為一金屬壓縮接合。
  11. 如申請專利範圍第1項之方法，其中封裝包含將該小晶片覆蓋於一介電質中，且形成金屬路由層於該介電質中，以將該主晶片連接至外部組件。
  12. 如申請專利範圍第1項之方法，其中封裝包含將一焊料球陣列附著至該小晶片周圍的該主晶片，且將該焊料球陣列附著至一封裝基材。
  13. 一種多重晶片封裝，其包含：一主晶片；複數個小晶片，其小於形成在一晶圓上的該主晶片、附著至一暫時載體、使用該暫時載體對準同時在主晶圓上的該主晶片上方、且使用該暫時載體對著該主晶片上施加，該等小晶片具有至該主晶片的一混合接合；以及一封裝，其用以將該主晶片與該等小晶片一起覆蓋；其中，該封裝前進一步包含劃線通過該等小晶片，使得該等小晶片具有劃線溝，以透過一部分的該小晶片晶圓來分開該等晶片，且在將該等晶片附著至該暫時載體之後使該小晶片變薄，使得該等晶片藉由該等劃線溝而分開。
  14. 如申請專利範圍第13項之封裝，其進一步包含在將接合至一小晶片的位置處之該主晶片上的著陸墊，該等著陸墊係形成在一介電層上方，以及用以接合至該等著陸墊之該小晶片上的金屬接點。
  15. 如申請專利範圍第13項之封裝，其進一步包含將該小晶片與該主晶片覆蓋的一介電質，以及用以將該主晶片連接至外部組件之該介電質中的金屬路由層。
  16. 一種組合晶片的方法，其包含：形成複數個小晶片於一晶圓上，該等小晶片具有用以附著至主晶片的金屬接點；將該等小晶片附著至一暫時載體；形成複數個較大主晶片於一主晶圓上；形成一介電層於該等主晶片各者的至少一部分上； 形成著陸墊於將接合至一小晶片之位置處的該等主晶片上；將圍繞該等著陸墊的一部分該介電層移除，以將該等著陸墊暴露至一各別小晶片；使用該暫時載體將該等晶片對準該等主體晶片上方；加熱該等小晶片；使用該暫時載體將該等小晶片的該等金屬接點，壓在該等主晶片的該等著陸墊上，使得一子集的該等小晶片接合到各別主晶片；將該暫時載體分開，使得該子集的接合小晶片接合至一各別主晶片，且該等剩餘的小晶片與該暫時載體分開；將該等主晶片切單；以及將該等主晶片封裝；其中形成複數個小晶片包含使用一第一製造技術來形成該等小晶片，且其中形成複數個主晶片包含使用與該第一製造技術不同的一第二製造技術來形成該等主晶片。
  17. 如申請專利範圍第16項之方法，其中將該等小晶片附著至該暫時載體，包含將該等晶片的前側附著至該暫時載體、使該等晶片的後側變薄、形成通孔穿過該等晶片的該等後側以連接至一各別主晶片、以及將該等小晶片彼此分開同時附著至該暫時載體。
  18. 如申請專利範圍第16項之方法，其中封裝包含在分開該暫時載體之後將該小晶片覆蓋在一介電質中，以及形成金屬路由層在該介電質中，以將該小晶片連接至外部 組件。
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