WO2022133655A1 - 一种雪崩光电二极管 - Google Patents

一种雪崩光电二极管 Download PDF

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WO2022133655A1
WO2022133655A1 PCT/CN2020/138048 CN2020138048W WO2022133655A1 WO 2022133655 A1 WO2022133655 A1 WO 2022133655A1 CN 2020138048 W CN2020138048 W CN 2020138048W WO 2022133655 A1 WO2022133655 A1 WO 2022133655A1
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layer
width
contact layer
substrate
epitaxial layers
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PCT/CN2020/138048
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English (en)
French (fr)
Inventor
陈冠宇
向伟
王恺
张盛祥
魏巍
张石勇
曹均凯
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华为技术有限公司
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Priority to CN202080100027.1A priority Critical patent/CN115443546A/zh
Priority to PCT/CN2020/138048 priority patent/WO2022133655A1/zh
Publication of WO2022133655A1 publication Critical patent/WO2022133655A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes

Definitions

  • the present application relates to the field of photoelectric conversion, and in particular, to an avalanche photodiode.
  • Avalanche photodiode is a photoelectric conversion device that converts optical signals into electrical signals. Because it has a certain gain while realizing photoelectric conversion, it can realize the detection of weak optical signals compared with ordinary photodetectors. Therefore, it is widely used in optical signal receivers such as optical communication, optical sensing, defense industry and quantum communication. Intensity modulation and direct detection schemes are generally used in short-distance optical communication systems (such as access networks). With the continuous improvement of transmission distance and transmission rate, higher and higher conversion rates and receiving sensitivity of photoelectric conversion devices are proposed. Require. Therefore, realizing a high-speed, high-sensitivity photoelectric conversion device has great application prospect and commercial value.
  • an avalanche photodiode (APD) based on indium phosphide (InP) or indium aluminum arsenide (InAlAs) as a multiplication layer is generally used for photoelectric conversion on the receiver side of the optical signal.
  • APD avalanche photodiode
  • InP indium phosphide
  • InAlAs indium aluminum arsenide
  • the k value is large, the k value is the ratio of the electron-hole ionization rate in the material
  • the sensitivity and rate of APD based on this material have reached the limit, and it is difficult to further promote.
  • the present application provides an avalanche photodiode, which can improve the sensitivity and speed of the avalanche photodiode.
  • an avalanche photodiode in a first aspect, includes: a substrate and a plurality of epitaxial layers disposed on the substrate, the plurality of epitaxial layers including a first contact layer, a multiplication layer, an electric field regulation layer, an absorption layer and a second contact layer that are stacked in sequence; Among them, the multiplication layer adopts a digital alloy containing antimony element Sb.
  • the absorption layer when external light irradiates the avalanche photodiode, the absorption layer can absorb photons to generate electron-hole pairs. , the two carriers (electrons and holes) accelerate their drift in opposite directions.
  • the drift speed When the drift speed is large enough, they will collide with the lattice atoms of the multiplication layer and ionize new electron-hole pairs.
  • the electrons generated in the multiplication layer The hole pair further collides with the lattice atoms to ionize new electron-hole pairs again, resulting in a collision ionization effect. If both electrons and holes participate in collision ionization, it will cause the device to generate excessive noise and reduce the avalanche photodiode.
  • the k value of the multiplication layer can be lower, for example, the k value can be 0.001 to 0.02, so that either the electron ionization rate or the hole ionization rate is higher, so that most of the carrier ionization effect in the multiplication layer is caused by one type of carrier (hole or electron) collisions are generated, thereby reducing the noise generated by the device and increasing the sensitivity and speed of the avalanche photodiode.
  • the k value of the multiplication layer is less than a predetermined value, wherein the k value is the ratio of hole ionization rate to electron ionization rate, or the ratio of electron ionization rate to hole ionization rate.
  • the multiplication layer is in the form of a digital alloy of AlGaAsSb or AlInAsSb.
  • a specific structure of an avalanche photodiode is provided, and the plurality of epitaxial layers further include one or more layers of the following: a first buffer layer disposed between the substrate and the first contact layer, a first buffer layer disposed between the substrate and the first contact layer, a a second buffer layer between the absorption layer and the second contact layer.
  • the plurality of epitaxial layers further include a stop layer disposed between the absorber layer and the second buffer layer.
  • the first buffer layer is mainly used for lattice matching between the epitaxial layer and the substrate.
  • the second buffer layer is mainly used for electric field adaptation of avalanche photodiodes, and the cut-off layer is mainly used for surface control of the epitaxially formed absorber layer.
  • the doped regions of the cut-off layer, the second buffer layer and the second contact layer are doped with impurity element ions.
  • the minimum distance between the doped region and the edge of the cut-off layer is greater than or equal to a first threshold; and/or, the The minimum distance between the doped region and the edge of the second buffer layer is greater than or equal to a first threshold; and/or, the minimum distance between the doped region and the edge of the second contact layer is greater than or equal to the first threshold.
  • the cut-off layer, the second buffer layer and the second contact layer are not doped in the whole layer, but only in the doped region, which can effectively control the electric field of the device and significantly reduce the dark current of the device.
  • the doping region is located in the central region of the stack structure formed by the cut-off layer, the second buffer layer and the second contact layer.
  • a first step is formed on the absorption layer, wherein a width of a first surface of the first step close to the second contact layer is smaller than a width of a second surface close to the electric field regulation layer and the width of the second contact layer is equal to the width of the first surface; the width of the first contact layer, the width of the multiplication layer and the width of the electric field regulation layer are all equal to the width of the second surface width, wherein the direction of the width is perpendicular to the stacking direction of the epitaxial layers.
  • the avalanche photodiode is provided with steps, the area facing each other between the layers can be reduced as much as possible, thereby reducing the size of the parasitic capacitance between the epitaxial layers and improving the characteristics of the device.
  • the width of the cutoff layer and the width of the second buffer layer are equal to the width of the first surface.
  • the width of the first buffer layer is equal to the width of the second surface.
  • the step thickness of the first step is greater than one-tenth of the thickness of the absorption layer and less than one-half of the thickness of the absorption layer, and the thickness direction is parallel to the thickness of the absorption layer.
  • a second step is formed on the substrate, and the width of the second step close to the first surface of the first contact layer is smaller than the width of the second surface away from the first contact layer width; the width of the first contact layer, the width of the multiplication layer and the width of the electric field regulation layer are all equal to the width of the first surface, wherein the direction of the width is perpendicular to the stacking direction of the epitaxial layers . Since the avalanche photodiode is provided with steps, the area facing each other between the layers can be reduced as much as possible, thereby reducing the size of the parasitic capacitance between the epitaxial layers and improving the characteristics of the device. When the plurality of epitaxial layers includes the first buffer layer, the width of the first buffer layer is equal to the width of the first surface.
  • the step thickness of the second step is greater than 100 nm, wherein the direction of the thickness is parallel to the stacking direction of the epitaxial layers.
  • it further includes a first electrode layer and a second electrode layer; the first electrode layer is formed on a side of the second contact layer away from the substrate, and the second electrode layer It is formed on a side of the substrate away from the first contact layer.
  • the material of the substrate is a semiconductor, and the substrate is doped with impurities that provide carriers.
  • the substrate when a second electrode layer is provided on the side of the substrate away from the first contact layer as a back electrode, the substrate needs to be made of conductive material, so a semiconductor doped with impurities that provide carriers can be used .
  • the first contact layer is formed with a third step; the width of the first surface of the third step close to the multiplication layer is smaller than that of the second surface close to the substrate; so the substrate The width is equal to the width of the second surface; the width of the multiplication layer, the width of the electric field regulation layer, the width of the absorption layer, and the width of the second contact layer are all equal to the width of the first surface, wherein the width The direction is perpendicular to the stacking direction of the epitaxial layers. Since the avalanche photodiode is provided with steps, the area facing each other between the layers can be reduced as much as possible, thereby reducing the size of the parasitic capacitance between the epitaxial layers and improving the characteristics of the device.
  • the width of the first buffer layer is equal to the width of the second surface.
  • the plurality of epitaxial layers include a cutoff layer and a second buffer layer, the width of the cutoff layer and the width of the second buffer layer are equal to the width of the first surface.
  • it further includes a first electrode layer and a second electrode layer, the first electrode layer is formed on a side of the second contact layer away from the substrate, and the second electrode layer is formed on the side of the first contact layer away from the substrate.
  • the material of the substrate is a semi-insulator.
  • the substrate does not need to be made of conductive material, so a semi-insulator can be used.
  • a method for fabricating an avalanche photodiode including fabricating a substrate; fabricating a plurality of epitaxial layers on the substrate, the plurality of epitaxial layers including a first contact layer, a multiplication layer, an electric field regulation layer, an absorption layer layer and a second contact layer; wherein, the multiplication layer adopts a digital alloy containing antimony element Sb.
  • the method further includes: doping impurity element ions in the doped region of the second contact layer.
  • the plurality of epitaxial layers further includes a second buffer layer disposed between the absorption layer and the second contact layer; the method further includes: in the second buffer layer The doped region is doped with impurity element ions.
  • a cutoff layer is provided between the absorption layer and the second buffer layer; the method further includes: doping impurity element ions in a doped region of the cutoff layer.
  • a mesa is formed on the plurality of epitaxial layers by an etching process, and a first step is formed on the absorption layer, wherein the first step is close to the first step of the second contact layer.
  • the width of one surface is smaller than the width of the second surface close to the electric field regulation layer; the width of the second contact layer is equal to the width of the first surface; the width of the first contact layer, the width of the multiplication layer and The width of the electric field regulating layer is equal to the width of the second surface, wherein the direction of the width is perpendicular to the stacking direction of the epitaxial layers.
  • a mesa is formed on the plurality of epitaxial layers through an etching process, and a second step is formed on the substrate, and the second step is close to the first surface of the first contact layer
  • the width of the first contact layer is smaller than the width of the second surface away from the first contact layer; the width of the first contact layer, the width of the multiplication layer and the width of the electric field regulation layer are all equal to the width of the first surface,
  • the direction of the width is perpendicular to the stacking direction of the epitaxial layers.
  • a mesa is formed on the plurality of epitaxial layers by an etching process, and a third step is formed on the first contact layer; the third step is close to the first surface of the multiplication layer.
  • the width is smaller than the second surface close to the substrate; so the width of the substrate is equal to the width of the second surface; the width of the multiplication layer, the width of the electric field regulation layer, the width of the absorber layer, and the width of the second contact layer
  • the widths are all equal to the width of the first surface, wherein the direction of the width is perpendicular to the stacking direction of the epitaxial layers.
  • doping impurity element ions in the doping region of the second contact layer includes: forming a passivation layer covering the plurality of epitaxial layers; The passivation layer of the doped region is removed; the doped region of the second contact layer is doped with impurity element ions.
  • impurity element ions are also doped in the cut-off layer and the doped regions of the second buffer layer in the above-mentioned manner.
  • FIG. 1 is a schematic structural diagram of an optical module according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an avalanche photodiode according to an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of an avalanche photodiode according to another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an avalanche photodiode according to another embodiment of the present application.
  • FIG. 5 is a structural diagram 1 of a method for fabricating an avalanche photodiode provided by an embodiment of the present application
  • FIG. 6 is a second structural diagram of a method for fabricating an avalanche photodiode provided by an embodiment of the present application.
  • FIG. 7 is a structural diagram 3 in a method for manufacturing an avalanche photodiode provided by an embodiment of the present application.
  • FIG. 8 is a fourth structural diagram in a method for fabricating an avalanche photodiode provided by an embodiment of the present application.
  • FIG. 9 is a structural diagram 5 in a method for fabricating an avalanche photodiode provided by an embodiment of the present application.
  • FIG. 10 is a structural diagram 6 of a method for fabricating an avalanche photodiode provided by an embodiment of the application;
  • FIG. 11 is a seventh structural diagram of a method for fabricating an avalanche photodiode provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a simulation curve of gain and bandwidth of an avalanche photodiode according to an embodiment of the application;
  • FIG. 13 is a schematic diagram of simulation curves of photocurrent and dark current of an avalanche photodiode provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of simulation curves of photocurrent and dark current of an avalanche photodiode according to another embodiment of the present application.
  • a semiconductor is a material whose electrical conductivity is between conductors and insulators at room temperature; semiconductors include intrinsic semiconductors and impurity semiconductors.
  • Semiconductors doped with a certain amount of impurities are called impurity semiconductors or extrinsic semiconductors. Among them, the impurities doped in the impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons, and the impurity semiconductors doped with impurities that provide electrons (such as 5-valent phosphorus element) are also called electron-type semiconductors or N-type semiconductors.
  • impurity semiconductors that are doped with impurities that provide holes are also called hole type semiconductors or P (positive, positive) type semiconductors), can improve the intrinsic semiconductor Generally speaking, the higher the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity.
  • this type of impurity semiconductor is also called conductive type semiconductor, for example, conductive type liner At the bottom, the impurities doped with InP are nitrogen N, boron B, aluminum Al, and the like.
  • the impurities doped in the impurity semiconductor can compensate the impurity semiconductor, the donor electrons are just enough to fill the acceptor energy level, but cannot provide electrons and holes in the conduction band and valence band, so that the semiconductor material with a wider band gap has Resistivity similar to that of an insulator.
  • the impurity compensation for InP is realized by doping InP, thereby increasing the resistivity of InP.
  • This type of impurity semiconductor is also called semi-insulating semiconductor or semi-insulator, or has semi-insulator characteristics.
  • Digital alloy A superlattice composed of alternating layers of stacked alloys or elements.
  • the k value the ratio of electron-hole ionization rate
  • the k value is the ratio of hole ionization rate to electron ionization rate, or the ratio of electron ionization rate to hole ionization rate. It should be noted that the k value usually takes the larger of the hole ionization rate and the electron ionization rate as the denominator, and the smaller one as the numerator, so the k value usually takes a decimal value.
  • At least one (a) of a, b or c may represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be It can be single or multiple.
  • words such as “first” and “second” do not limit the quantity and order.
  • the embodiments of the present application are applied to an optical signal receiver.
  • the optical signal receiver includes a photoelectric conversion device and a signal receiving circuit.
  • the function of the photoelectric conversion device is to convert the optical signal received from the optical fiber into an electrical signal
  • the signal receiving circuit converts the electrical signal from the electrical signal. Unpack the carried data.
  • the embodiments of the present application can also be applied to an optical module, and the function of the optical module is photoelectric conversion.
  • the optical module is also called an optical transmission module. Referring to FIG. 1 , the optical module includes an optical signal transmitter 11 and an optical signal receiver 12 .
  • the function of the optical signal transmitter 11 is to convert the electrical signal into an optical signal, and input the optical fiber 13 for transmission.
  • the function of the optical signal receiver 12 is to receive the optical signal transmitted from the optical fiber 13 and convert it into an electrical signal.
  • the optical signal transmitter 11 and the optical signal receiver 12 in FIG. 1 can multiplex the optical fiber 13 .
  • the optical signals of the optical signal transmitter 11 and the optical signal receiver 12 can also be transmitted in two optical fibers respectively.
  • the optical module at the transmitting end converts the electrical signal into an optical signal, and after transmission through the optical fiber, the optical module at the receiving end converts the optical signal into an electrical signal.
  • optical signal receivers or optical modules are mainly used in Ethernet, fiber to the home (FTTH), optical transport network (OTN), network storage, data centers and other fields.
  • optical signal receivers or optical modules are mainly used in the above fields, such as: optical line terminal (OLT), optical network unit (ONU), switch, optical fiber router, video Optical transceivers, optical transceivers, optical fiber network cards and other equipment.
  • OLT optical line terminal
  • ONU optical network unit
  • switch optical fiber router
  • video Optical transceivers optical transceivers
  • optical fiber network cards and other equipment.
  • OLT optical line terminal
  • switch optical fiber router
  • video Optical transceivers optical transceivers
  • optical transceivers optical fiber network cards and other equipment.
  • optical signal receivers and optical modules support different rate classifications, such as: 1G ⁇ 10G low rate, 25G, 40G, 50G, 100G, 200G/400G, etc.
  • the photoelectric conversion device may be an avalanche photodiode.
  • the avalanche photodiode includes: a substrate and a plurality of epitaxial layers disposed on the substrate, the plurality of epitaxial layers including a first contact layer, a multiplication layer, an electric field regulation layer, an absorption layer and a second contact layer arranged in sequence; Among them, the multiplication layer adopts a digital alloy containing antimony element Sb.
  • the k value of the multiplication layer is smaller than a predetermined value, wherein the k value is the ratio of hole ionization rate to electron ionization rate, or the ratio of electron ionization rate to hole ionization rate.
  • the specific value of k can be between 0.0001 and 0.02. It should be noted that the k value usually takes the larger of the hole ionization rate and the electron ionization rate as the denominator, and the smaller one as the numerator, so the k value usually takes a decimal value.
  • the multiplication layer is in the form of a digital alloy of AlGaAsSb or AlInAsSb.
  • the substrate is usually made of materials such as indium phosphide (InP).
  • the multiplication layer may also use a compound containing antimony element Sb, a digital alloy of InAlAs with a smaller k value.
  • the compound of antimony element Sb can be the above-mentioned digital alloy containing antimony element Sb, or an intrinsic alloy crystal material containing antimony element Sb, for example: intrinsic Al x Ga 1-x As y Sb 1-y crystal material, whose intrinsic The concentration of charge carriers is less than 10 16 cm -3 .
  • the thickness of the multiplication layer is between 10 nm and 2 ⁇ m. In one example, the width of the multiplication layer in the direction perpendicular to the stacking direction is 10 nm to 2000 nm.
  • the absorption layer when external light is irradiated on the avalanche photodiode, the absorption layer can absorb photons to generate electron-hole pairs.
  • the two carriers (electrons and holes) accelerate and drift in opposite directions. When the drift speed is large enough, they will collide with the lattice atoms of the multiplication layer and ionize new electron-hole pairs.
  • the electron-hole pair generated by the multiplication layer further collides with the lattice atoms to ionize new electron-hole pairs again, resulting in a collision ionization effect. If both electrons and holes participate in collision ionization, it will lead to excessive noise in the device.
  • the k value of the multiplication layer can be lower, such as k The value can be made between 0.001 and 0.02, so that either the electron ionization rate or the hole ionization rate is high, so that most of the carrier ionization effect in the multiplication layer is caused by a carrier (hole or electron) collisions are generated, thereby reducing the noise generated by the device and improving the sensitivity and speed of the avalanche photodiode.
  • the plurality of epitaxial layers include a first buffer layer 22 , a first contact layer 23 , a multiplication layer 24 , an electric field regulation layer 25 , and an absorption layer 26 , which are stacked and arranged on the substrate 21 in sequence. , a cutoff layer 27 , a second buffer layer 28 and a second contact layer 29 .
  • the cut-off layer 27 , the second buffer layer 28 and the doped regions 30 of the second contact layer 29 are doped with impurity element ions.
  • the first buffer layer 22 and the first contact layer 23 may be doped with N-type impurity ions, such as phosphorus (P) and other doped ions that generate electrons.
  • the electric field regulating layer 25 can be doped with P-type impurity ions, such as Be, C, Mg, Zn, etc., which generate holes.
  • the doping concentration of the electric field regulating layer 25 ranges from 1e16cm -3 to 1e18cm -3 between.
  • the materials of the first buffer layer 22, the first contact layer 23, the electric field regulation layer 25, the cut-off layer 27, the second buffer layer 28 and the second contact layer 29 may be Al 1-xy Ga x In y As, In 1-x Ga x As y P 1-y , Al x Ga 1-x AsySb 1-y (wherein x, y are greater than or equal to 0 and less than or equal to 1) and the like.
  • the material of the absorption layer 26 may be InGaAs or the like.
  • the minimum distance between the doped region 30 and the edge of the cut-off layer 27 is greater than or equal to the first threshold; and or, the minimum distance between the doped region 30 and the edge of the second buffer layer 28 greater than or equal to the first threshold; and or, the minimum distance between the doped region 30 and the edge of the second contact layer 29 is greater than or equal to the first threshold.
  • the range of the first threshold is 1-10 ⁇ m.
  • the cut-off layer 27 , the second buffer layer 28 and the second contact layer 29 are not doped on the whole layer, but only on the doped region 30 , which can effectively control the electric field of the device and significantly reduce the power of the device. the dark current.
  • the doped region 30 is located in the central region of the stack structure formed by the cut-off layer 27 , the second buffer layer 28 and the second contact layer 29 .
  • the plurality of epitaxial layers further include a first buffer layer 22 disposed between the substrate 21 and the first contact layer 23 , a buffer layer 22 disposed between the absorption layer 26 and the second contact layer 29 The second buffer layer 28 and the cutoff layer 27 disposed between the absorption layer 26 and the second buffer layer 28 .
  • the first buffer layer 22 is mainly used to adapt the epitaxial layer to the lattice of the substrate 21 to overcome the lattice defects of the substrate.
  • the second buffer layer 28 is mainly used for the electric field adaptation of the avalanche photodiode
  • the cut-off layer 27 is mainly used for the surface control of the epitaxially formed absorption layer.
  • the first contact layer 23 , the cut-off layer 27 and the second buffer layer 28 are all optional layer structures. With these layer structures, avalanche photodiodes can achieve better results. That is, in some embodiments, these three layers may not be included or only any one or more of these three layers may be included. Of course, in some embodiments, the multiple epitaxial layers may also include more other layer structures as required.
  • a first step S1 is formed on the absorption layer 26, and the width of the first step S1 close to the first surface of the second contact layer 29 is smaller than the width of the second surface close to the electric field regulation layer 25; the width of the second contact layer 29 is equal to The width of the first surface; the width of the first contact layer 23 , the width of the multiplication layer 24 and the width of the electric field regulation layer 25 are all equal to the width of the second surface.
  • the step thickness H1 of the first step S1 is greater than one tenth of the thickness of the absorption layer 26 and less than one half of the thickness of the absorption layer 26 .
  • the direction of the width of each epitaxial layer is perpendicular to the stacking direction of the epitaxial layers.
  • the width of the cut-off layer 27 and the width of the second buffer layer 28 are equal to the width of the first surface.
  • the width of the first buffer layer 22 is equal to the width of the second surface.
  • a second step S2 is formed on the substrate 21, and the width of the first surface of the second step S2 close to the first contact layer 23 is smaller than the width of the second surface away from the first contact layer 23; the width of the first contact layer 23, the multiplication
  • the width of the layer 24 and the width of the electric field regulating layer 25 are both equal to the width of the first surface.
  • the step thickness of the second step H2 is greater than 100 nm.
  • a first electrode layer 31 and a second electrode layer 32 are also included.
  • the first electrode layer 31 is formed on the side of the second contact layer 29 away from the substrate 21
  • the second electrode layer 32 is formed on the side of the substrate 21 away from the first contact layer 23 .
  • the first electrode layer 31 and the second electrode layer 32 can be made of metal materials.
  • the material of the substrate 21 is a semiconductor, and the substrate 21 is doped with impurities that provide carriers, that is, in this embodiment, the epitaxial layers are all arranged on the conductive substrate.
  • the outer side of the epitaxial layers (21-30) is covered with a passivation layer 33, and the material of the passivation layer 33 may be SiO 2 or SiN x or the like.
  • the passivation layer 33 is formed with a window W on the second contact layer 29, wherein the first electrode layer 31 is formed in the window W, and a top-entry avalanche photodiode provided in FIG. medium incidence. As shown in Figure 2, the direction of incidence of the light rays is provided.
  • the area facing each other between the layers can be reduced as much as possible, thereby reducing the size of the parasitic capacitance between the epitaxial layers and improving the characteristics of the device.
  • the plurality of epitaxial layers include a first buffer layer 22 , a first contact layer 23 , a multiplication layer 24 , an electric field regulation layer 25 , an absorption layer 26 , The cutoff layer 27 , the second buffer layer 28 and the second contact layer 29 .
  • the cut-off layer 27 , the second buffer layer 28 and the doped regions 30 of the second contact layer 29 are doped with impurity element ions.
  • the specific materials and structural parameters of the epitaxial layer can be referred to as shown in FIG. 2 , which will not be repeated here.
  • the avalanche photodiode provided in FIG. 3 further includes that the first contact layer 23 is formed with a third step S3;
  • the width of one surface is smaller than that of the second surface close to the substrate 21; the width of the substrate 21 is equal to the width of the second surface;
  • the widths of the surfaces are all equal to the width of the first surface of the third step S3.
  • a first step S1 is formed on the absorption layer 26 , and a second step S2 is formed on the substrate.
  • the description of the first step and the second step can refer to the description in the embodiment corresponding to FIG. 2 , which will not be repeated here.
  • the first electrode layer 31 is formed on the side of the second contact layer away from the substrate 21, and the second electrode layer 32 is formed on the first contact layer
  • the layer 23 is on the side away from the substrate 21 .
  • the first electrode layer 31 and the second electrode layer 32 can be made of metal materials.
  • the material of the substrate 21 is a semi-insulator.
  • the outer side of the epitaxial layers (21-30) is covered with a passivation layer 33, and the material of the passivation layer 33 may be SiO 2 or SiN x or the like.
  • the passivation layer 22 is formed with a window W on the second contact layer, wherein the first electrode layer 31 is formed in the window W, and a top-entry avalanche photodiode provided in FIG. Incident. As shown in Figure 3, the incident direction of the light is provided.
  • the epitaxial layers in the avalanche photodiode provided in FIG. 3 are all arranged on a substrate formed of a semi-insulator, and the first electrode layer and the second electrode layer are located on the same surface of the avalanche photodiode. , that is, a coplanar electrode, which can be formed on the same material layer by a single communication process in the manufacturing process.
  • the avalanche photodiode is provided with three steps, the area facing each other can be reduced as much as possible, thereby reducing the parasitic capacitance between the epitaxial layers and improving the characteristics of the device.
  • the plurality of epitaxial layers include a first buffer layer 22 , a first contact layer 23 , a multiplication layer 24 , an electric field regulation layer 25 , an absorption layer 26 , The cutoff layer 27 , the second buffer layer 28 and the second contact layer 29 .
  • the cut-off layer 27 , the second buffer layer 28 and the doped regions 30 of the second contact layer 29 are doped with impurity element ions.
  • the specific materials and structural parameters of the epitaxial layer can be referred to as shown in FIG. 2 , which will not be repeated here.
  • the avalanche photodiode provided in FIG. 4 includes a third step S3 formed by the first contact layer 23 and a second step S2 formed on the substrate.
  • the first contact layer 23 is formed with a third step S3; the width of the first surface of the third step S3 close to the multiplication layer 24 is smaller than that of the second surface close to the substrate 21; the width of the first buffer layer 22 is equal to the width of the second surface; The width of the multiplication layer 24 , the width of the electric field regulation layer 25 , the width of the absorption layer 26 , the width of the cutoff layer 27 , the second buffer layer 28 and the second contact layer 29 are all equal to the width of the first surface.
  • the step thickness of the second step is greater than 100 nm.
  • the avalanche photodiode further includes a first electrode layer 31 and a second electrode layer 32, the first electrode layer 31 is formed on the side of the second contact layer away from the substrate 21, and the second electrode layer 32 is formed on the side of the second contact layer away from the substrate 21.
  • the first contact layer 23 is on the side away from the substrate 21 .
  • the first electrode layer 31 and the second electrode layer 32 can be made of metal materials.
  • the material of the substrate 21 is a semi-insulator.
  • the outer side of the epitaxial layers (21-30) is covered with a passivation layer 33, and the material of the passivation layer 33 may be SiO 2 or SiN x or the like.
  • the passivation layer 22 is formed with a window W on the second contact layer, wherein the first electrode layer 31 is formed in the window W, and a top-entry avalanche photodiode is provided in FIG. Incident. As shown in Figure 4, the incident direction of the light is provided.
  • Embodiments of the present application provide a method for fabricating an avalanche photodiode, comprising the following steps:
  • the substrate can be made of InP material, and according to the above-mentioned different requirements for the substrate material, the substrate can be formed by a direct deposition process or a growth process.
  • a direct deposition process or a growth process For example, when the substrate is made of a semi-insulator, due to the high requirements on the manufacturing process of the substrate, a high temperature chemical vapor deposition (chemical vapor deposition, CVD) method can be used to form the substrate.
  • CVD chemical vapor deposition
  • the substrate adopts a conductive substrate with lower requirements on the process technology, the crystal can usually be grown by a physical vapor transport process (PVT) method, and the crystal is then cut by wire, ground and polished.
  • PVT physical vapor transport process
  • the substrate is obtained by the process. Since the substrate can be a conductive substrate (for example, the substrate is doped with impurities that provide carriers), the requirements for the purity of the substrate and the process complexity of PVT are relatively low.
  • the plurality of epitaxial layers include a first contact layer, a multiplication layer, an electric field regulation layer, an absorption layer and a second contact layer; wherein the multiplication layer adopts a digital alloy containing antimony element Sb.
  • MBE molecular-beam epitaxy
  • an embodiment of the present application provides a method for fabricating an avalanche photodiode as shown in FIG. 2 , which specifically includes the following steps:
  • a plurality of epitaxial layers are fabricated on the substrate 21, and the plurality of epitaxial layers include a first contact layer, a multiplication layer, an electric field regulation layer, an absorption layer and a second contact layer that are stacked in sequence; wherein, The multiplication layer adopts a digital alloy containing antimony element Sb.
  • the plurality of epitaxial layers include a first buffer layer 22 , a first contact layer 23 , a multiplication layer 24 , an electric field regulation layer 25 , an absorption layer 26 , a cut-off layer 26 , a first buffer layer 22 , a first contact layer 23 , a multiplication layer 24 , an electric field regulation layer 25 , an absorption layer 26 , which are stacked and arranged in sequence on the substrate 21 .
  • layer 27 , second buffer layer 28 and second contact layer 29 are all optional layer structures as described above. In some embodiments, these three layers may not be fabricated or only any one of the three layers may be fabricated. one or more layers. Of course, in some embodiments, more other layer structures are fabricated in multiple epitaxial layers as desired.
  • a mesa is formed on a plurality of epitaxial layers by an etching process, and a first step S1 is formed on the absorption layer.
  • the etching process may be dry etching or wet etching.
  • the width of the first step S1 close to the first surface of the second contact layer 29 is smaller than the width of the second surface close to the electric field regulation layer 25 ;
  • the width of the cut-off layer 27 , the width of the second buffer layer 28 and the width of the second contact layer 29 are all equal to the width of the first surface;
  • the width of the first buffer layer 22 , the width of the first contact layer 23 , the width of the multiplication layer 24 and the width of the electric field regulation layer 25 are all equal to the width of the second surface. As shown in FIG.
  • the first step S1 is etched to a position greater than one-tenth of the thickness of the absorption layer 26 and less than one-half of the thickness of the absorption layer 26 .
  • the direction of the width of each epitaxial layer is perpendicular to the stacking direction of the epitaxial layers.
  • a mesa is formed on the plurality of epitaxial layers by an etching process, and a second step S2 is formed on the substrate.
  • the etching process may be dry etching or wet etching.
  • the width of the first surface of the second step S2 close to the first contact layer 23 is smaller than the width of the second surface away from the first contact layer 23; the width of the first buffer layer 22, the width of the first contact layer 23, the width of the multiplication layer 24
  • the width and the width of the electric field regulating layer 25 are both equal to the width of the first surface.
  • the etching of the second step H2 is greater than 100 nm.
  • the direction of the width is perpendicular to the stacking direction of the epitaxial layers.
  • step 203 and step 204 is not limited in the embodiments of the present application, that is, the first step S1 can be etched first and then the second step S2 can be etched, or the second step S2 can be etched first and then etched out The first step S1.
  • a passivation layer 33 is formed on the plurality of epitaxial layers.
  • a passivation layer is grown on the surface of the epitaxial layer by a thin film growth process (eg, plasma enhanced chemical vapor deposition).
  • a thin film growth process eg, plasma enhanced chemical vapor deposition
  • a window W is formed on the passivation layer 33 on the second contact layer 29 .
  • the passivation layer on the second buffer layer 28 where the doped region 30 needs to be formed is removed to form the window W through an exposure process (eg, photolithography and etching process).
  • the doping region 30 of the cutoff layer 27 , the second buffer layer 28 and the doping region 30 of the second contact layer 29 may be doped with impurity element ions to form the doped region 30 by ion implantation or diffusion.
  • the depth of the doped region 30 is less than or equal to the thickness of the cut-off layer, the second buffer layer and the second contact layer, and the width is as described above.
  • a first electrode layer 31 is formed on the side of the second contact layer 29 away from the substrate 21, and a second electrode layer 32 is formed on the side of the substrate 21 away from the first contact layer 23.
  • the first electrode layer 31 is processed through a photolithography process, metal deposition and lift-off process.
  • the avalanche photodiode is thinned and polished (mainly on the backside of the substrate (the surface away from the first buffer layer)), and a second electrode layer is formed by sputtering a layer of metal material on the backside of the substrate.
  • an embodiment of the present application provides a method for fabricating an avalanche photodiode as shown in FIG. 4 , which specifically includes the following steps:
  • a plurality of epitaxial layers are fabricated on the substrate 21, and the plurality of epitaxial layers include a first contact layer, a multiplication layer, an electric field regulation layer, an absorption layer and a second contact layer; Digital alloy of antimony element Sb.
  • the plurality of epitaxial layers include a first buffer layer 22 , a first contact layer 23 , a multiplication layer 24 , an electric field regulation layer 25 , an absorption layer 26 , a cut-off layer 27 , The second buffer layer 28 and the second contact layer 29 .
  • the first contact layer 23 , the cut-off layer 27 and the second buffer layer 28 are all optional layer structures as described above. In some embodiments, these three layers may not be fabricated or only any one of the three layers may be fabricated. one or more layers. Of course, in some embodiments, more other layer structures are fabricated in multiple epitaxial layers as desired.
  • a mesa is formed on a plurality of epitaxial layers by an etching process, and a first step S1 is formed on the absorption layer 26 .
  • the width of the first surface of the first step S1 close to the second contact layer 29 is smaller than the width of the second surface close to the electric field regulation layer 25 ; the width of the cut-off layer 27 , the width of the second buffer layer 28 and the width of the second contact layer 29
  • the width of the first contact layer 23 near the multiplication layer 24, the multiplication layer 24 and the electric field regulation layer 25 are all equal to the width of the second surface.
  • the direction of the width is perpendicular to the stacking direction of the epitaxial layers.
  • a mesa is formed on a plurality of epitaxial layers by an etching process, and a third step S3 is formed on the first contact layer 23.
  • the width of the first surface of the third step S3 close to the multiplication layer 24 is smaller than that of the second surface close to the substrate 21 ; the width of the first buffer layer 22 is equal to the width of the second surface; the width of the multiplication layer 24 and the width of the electric field regulation layer 25 .
  • the width of the second surface of the first step S1 of the absorption layer 26 is equal to the width of the first surface of the third step, wherein the direction of the width is perpendicular to the stacking direction of the epitaxial layers.
  • a mesa is formed on the plurality of epitaxial layers through an etching process, and a second step S2 is formed on the substrate 21 .
  • the width of the first surface of the second step S2 close to the first contact layer 23 is smaller than the width of the second surface away from the first contact layer 23 ; the width of the first buffer layer 22 , the width of the third step S3 of the first contact layer 23
  • the widths of the two surfaces are equal to the widths of the first surfaces of the second step S2 , wherein the direction of the widths is perpendicular to the stacking direction of the epitaxial layers.
  • the etching may be performed in the order of steps S1-S3-S2, or in the order of S2-S3-S1.
  • a passivation layer 33 is formed on the plurality of epitaxial layers.
  • a window W is formed on the passivation layer 33 on the second contact layer 29 .
  • a first electrode layer 31 is formed on the side of the second contact layer 29 away from the substrate 21
  • a second electrode layer 32 is formed on the side of the first contact layer 23 away from the substrate 21 .
  • the fabrication process of the first electrode layer and the second electrode layer may refer to the fabrication process of the first electrode layer in step 208, and will not be repeated here.
  • the manufacturing method of the avalanche photodiode as shown in FIG. 4 is provided in the manufacturing embodiments of the present application, and step 303 in the above-mentioned steps 301-308 can be directly eliminated.
  • the width of the multiplication layer, the width of the electric field regulation layer, the width of the absorption layer, the width of the cut-off layer, the width of the second buffer layer and the width of the second contact layer are all equal to the third step S1 the width of the first surface.
  • the gain and bandwidth of the avalanche photodiode provided in FIG. 2 and the conventional avalanche photodiode using InAlAs as the multiplication layer are simulated in the embodiments of the present application.
  • the gain and bandwidth curve provided in FIG. 12 it can be seen that after the gain is greater than 10 dB, the product of the gain and bandwidth of the avalanche photodiode provided by the embodiment of the present application is significantly larger than that of the conventional avalanche photodiode. Therefore, The avalanche photodiode provided by the embodiments of the present application can significantly improve the product of gain and bandwidth.
  • the photocurrent and dark current of the avalanche photodiode provided in FIG. 2 and the conventional avalanche photodiode using InAlAs as the multiplication layer are described.
  • the dark current of the avalanche photodiode provided by the embodiments of the present application is higher than that of the conventional avalanche photodiode. can be an order of magnitude lower.

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Abstract

一种雪崩光电二极管，涉及光电转换领域，能够提高雪崩光电二极管灵敏度和速率。雪崩光电二极管包括：衬底（21）以及设置于衬底（21）上的多个外延层，多个外延层包括依次层叠设置的第一接触层（23）、倍增层（24）、电场调控层（25）、吸收层（26）以及第二接触层（29）；其中，倍增层（24）采用含锑元素Sb的数字合金。

Description

一种雪崩光电二极管 技术领域
本申请涉及光电转换领域，尤其涉及一种雪崩光电二极管。
背景技术
雪崩光电二极管(avalanche photodiode，APD)是将光信号转换为电信号的光电转换器件，由于其在实现光电转换的同时具有一定的增益，因此相比于普通的光电探测器可以实现对微弱光信号的探测，因此广泛应用于光通信、光传感、国防工业以及量子通信等的光信号接收机。在短距光通信系统(如接入网)中一般采用强度调制和直接探测方案，随着传输距离和传输速率的不断提高，对光电转换器件的转换速率和接收灵敏度提出了越来越高的要求。因此实现一种高速、高灵敏度的光电转换器件，有较大的应用前景和商业价值。
目前，一般采用基于磷化铟(InP)或铟铝砷(InAlAs)做倍增层的雪崩光电二极管(APD)进行光信号接收机侧的光电转换。受限于InP和InAlAs体材料本身较高的噪声特性(k值较大，k值为材料中电子空穴离化率比值)，基于这种材料的APD灵敏度和速率已经达到极限，很难进一步提升。
发明内容
本申请提供一种雪崩光电二极管，能够提高雪崩光电二极管的灵敏度和速率。
第一方面，提供一种雪崩光电二极管。该雪崩光电二极管，包括：衬底以及设置于所述上的多个外延层，多个外延层包括依次层叠设置的第一接触层、倍增层、电场调控层、吸收层以及第二接触层；其中，倍增层采用含锑元素Sb的数字合金。在上述方案中，当外部光线照射到雪崩光电二极管上时，吸收层能够吸收光子产生电子空穴对，在第一接触层和第二接触层上施加电压后，在电场调控层产生的电场下，两种载流子(电子和空穴)向相反的方向加速漂移，当漂移速度足够大时会与倍增层的晶格原子发生碰撞电离出新的电子空穴对，在倍增层产生的电子空穴对进一步与晶格原子发生碰撞再次电离出新的电子空穴对，从而产生碰撞离化效应，如果电子和空穴都参与碰撞离化，则会导致器件产生过量噪声，降低雪崩光电二极管的灵敏性和速率，本申请的实施例中，由于雪崩光电二极管的倍增层采用了含锑元素Sb的数字合金，因此倍增层的k值可以做到较低，例如k值可以做到0.001至0.02之间，这样，电子离化率或空穴离化率中的一者较高，从而使得倍增层中大部分的载流子离化效应是由一种载流子(空穴或电子)碰撞产生，从而降低器件产生的噪声，提高雪崩光电二极管的灵敏性和速率。
在一种可能实现方式中，倍增层的k值小于预定值，其中k值为空穴离化率与电子离化率的比值，或者电子离化率与空穴离化率的比值。
在一种可能实现方式中，倍增层采用AlGaAsSb或AlInAsSb的数字合金形式。
在一种可能实现方式中，提供了雪崩光电二极管的具体结构，多个外延层还包括以下一层或多层：设置于所述衬底和第一接触层之间的第一缓冲层、设置于所述吸收层与所述第二接触层之间的第二缓冲层。所述多个外延层还包括设置于所述吸收层和所述第二缓冲层之间的截止层。其中，第一缓冲层主要用于外延层与衬底的晶格适配。 第二缓冲层主要用于雪崩光电二极管的电场适配，截止层主要用于外延形成的吸收层的表面控制。
在一种可能实现方式中，所述截止层、第二缓冲层以及第二接触层的掺杂区域掺杂有杂质元素离子。
在一种可能实现方式中，在垂直于所述多个外延层堆叠方向的平面上，所述掺杂区域与所述截止层的边缘的最小距离大于等于第一阈值；和/或，所述掺杂区域与所述第二缓冲层的边缘的最小距离大于等于第一阈值；和/或，所述掺杂区域与所述第二接触层的边缘的最小距离大于等于第一阈值。这样，对于截止层、第二缓冲层以及第二接触层并不是整层进行掺杂，而是仅对于掺杂区域进行掺杂，可以有效实现对器件电场的控制，显著降低器件的暗电流。其中，掺杂区域位于截止层、第二缓冲层以及第二接触层形成的堆叠结构的中心区域。
在一种可能实现方式中，所述吸收层上形成有第一台阶，其中，所述第一台阶靠近第二接触层的第一表面的宽度小于靠近所述电场调控层的第二表面的宽度；以及所述第二接触层的宽度等于所述第一表面的宽度；所述第一接触层的宽度、所述倍增层的宽度以及所述电场调控层的宽度均等于所述第二表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。由于雪崩光电二极管设置了台阶，这样可以尽量降低各层之间正对的面积，从而减少外延层之间寄生电容的大小，提高器件的特性。当然，当多个外延层包含截止层以及第二缓冲层时，截止层的宽度、所述第二缓冲层的宽度等于所述第一表面的宽度。当多个外延层包含第一缓冲层时，第一缓冲层的宽度等于第二表面的宽度。
在一种可能实现方式中，所述第一台阶的台阶厚度大于所述吸收层厚度的十分之一，并且小于所述吸收层厚度的二分之一，所述厚度的方向平行于所述外延层的堆叠方向。
在一种可能实现方式中，所述衬底上形成有第二台阶，所述第二台阶靠近所述第一接触层的第一表面的宽度小于远离所述第一接触层的第二表面的宽度；所述第一接触层的宽度、所述倍增层的宽度以及所述电场调控层的宽度均等于所述第一表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。由于雪崩光电二极管设置了台阶，这样可以尽量降低各层之间正对的面积，从而减少外延层之间寄生电容的大小，提高器件的特性。当多个外延层包含第一缓冲层时，第一缓冲层的宽度等于所述第一表面的宽度。
在一种可能实现方式中，所述第二台阶的台阶厚度大于100nm，其中所述厚度的方向平行于所述外延层的堆叠方向。
在一种可能实现方式中，还包括第一电极层和第二电极层；所述第一电极层形成于所述第二接触层上远离所述衬底的一侧，所述第二电极层形成于所述衬底上远离所述第一接触层的一侧。
在一种可能实现方式中，所述衬底的材料采用半导体，所述衬底掺杂有提供载流子的杂质。其中，当在衬底上远离所述第一接触层的一侧设置第二电极层作为背面电极时，衬底需要采用能够导电的材质，因此可以使用掺杂有提供载流子的杂质的半导体。
在一种可能实现方式中，所述第一接触层形成有第三台阶；所述第三台阶靠近所述倍增层的第一表面的宽度小于靠近所述衬底的第二表面；所以衬底的宽度等于所述第二表面的宽度；所述倍增层的宽度、电场调控层的宽度、吸收层的宽度、以及第二接触层的宽度均等于所述第一表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。由于雪崩光电二极管设置了台阶，这样可以尽量降低各层之间正对的面积，从而减少外延层之间寄生电容的大小，提高器件的特性。当多个外延层包含第一缓冲层时，所以第一缓冲层的宽度等于所述第二表面的宽度。当多个外延层包含截止层以及第二缓冲层时，截止层的宽度、所述第二缓冲层的宽度等于所述第一表面的宽度。
在一种可能实现方式中，还包括第一电极层和第二电极层，所述第一电极层形成于所述第二接触层上远离所述衬底的一侧，所述第二电极层形成于所述第一接触层上远离所述衬底的一侧。
在一种可能实现方式中，所述衬底的材料采用半绝缘体。其中，第一电极和第二电极不再设置于衬底上时，衬底不需要采用能够导电的材质，因此可以使用半绝缘体。
第二方面，提供一种雪崩光电二极管的制作方法，制作衬底；在所述衬底上制作多个外延层，所述多个外延层包括第一接触层、倍增层、电场调控层、吸收层以及第二接触层；其中，所述倍增层采用含锑元素Sb的数字合金。
在一种可能实现方式中，所述方法还包括：在所述第二接触层的掺杂区域掺杂杂质元素离子。
在一种可能实现方式中，所述多个外延层还包括设置于所述吸收层与所述第二接触层之间的第二缓冲层；所述方法还包括：在所述第二缓冲层的掺杂区域掺杂杂质元素离子。
在一种可能实现方式中，设置于所述吸收层和所述第二缓冲层之间的截止层；所述方法还包括：在所述截止层的掺杂区域掺杂杂质元素离子。
在一种可能实现方式中，通过刻蚀工艺在所述多个外延层上制作台面，在所述吸收层上形成第一台阶，其中，所述第一台阶靠近所述第二接触层的第一表面的宽度小于靠近所述电场调控层的第二表面的宽度；第二接触层的宽度均等于所述第一表面的宽度；所述第一接触层的宽度、所述倍增层的宽度以及所述电场调控层的宽度均等于所述第二表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。
在一种可能实现方式中，通过刻蚀工艺在所述多个外延层上制作台面，在所述衬底上形成第二台阶，所述第二台阶靠近所述第一接触层的第一表面的宽度小于远离所述第一接触层的第二表面的宽度；所述第一接触层的宽度、所述倍增层的宽度以及所述电场调控层的宽度均等于所述第一表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。
在一种可能实现方式中，通过刻蚀工艺在所述多个外延层上制作台面，在所述第一接触层形成第三台阶；所述第三台阶靠近所述倍增层的第一表面的宽度小于靠近所述衬底的第二表面；所以衬底的宽度等于所述第二表面的宽度；所述倍增层的宽度、电场调控层的宽度、吸收层的宽度、以及第二接触层的宽度均等于所述第一表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。
在一种可能实现方式中，在所述第二接触层的掺杂区域掺杂杂质元素离子包括： 制作覆盖所述多个外延层的钝化层；将所述第二接触层上对应所述掺杂区域的钝化层去除；在所述第二接触层的掺杂区域掺杂杂质元素离子。当多个外延层包含截止层以及第二缓冲层时，还采用上述方式在截止层以及第二缓冲层的掺杂区域掺杂杂质元素离子。
其中，第二方面中任一种可能实现方式中所带来的技术效果可参见上述第一方面不同的实现方式所带来的技术效果，此处不再赘述。
附图说明
图1为本申请的实施例提供的一种光模块的结构示意图；
图2为本申请的实施例提供的一种雪崩光电二极管的结构示意图；
图3为本申请的另一实施例提供的一种雪崩光电二极管的结构示意图；
图4为本申请的又一实施例提供的一种雪崩光电二极管的结构示意图；
图5为本申请的实施例提供的一种雪崩光电二极管的的制作方法中的结构图一；
图6为本申请的实施例提供的一种雪崩光电二极管的的制作方法中的结构图二；
图7为本申请的实施例提供的一种雪崩光电二极管的的制作方法中的结构图三；
图8为本申请的实施例提供的一种雪崩光电二极管的的制作方法中的结构图四；
图9为本申请的实施例提供的一种雪崩光电二极管的的制作方法中的结构图五；
图10为本申请的实施例提供的一种雪崩光电二极管的的制作方法中的结构图六；
图11为本申请的实施例提供的一种雪崩光电二极管的的制作方法中的结构图七；
图12为本申请的实施例提供的一种雪崩光电二极管的增益与带宽的仿真曲线示意图；
图13为本申请的实施例提供的一种雪崩光电二极管的光电流和暗电流的仿真曲线示意图；
图14为本申请的另一实施例提供的一种雪崩光电二极管的光电流和暗电流的仿真曲线示意图。
具体实施方式
下文将详细论述各实施例的制作和使用。但应了解，本申请提供的许多适用发明概念可实施在多种具体环境中。所论述的具体实施例仅仅说明用以实施和使用本说明和本技术的具体方式，而不限制本申请的范围。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。
半导体：半导体是一种常温下导电性能介于导体与绝缘体之间的材料；其中半导体包括本征半导体和杂质半导体。不含杂质和缺陷的纯净半导体，其内部电子和空穴浓度相等，称为本征半导体。掺入一定量杂质的半导体称为杂质半导体或非本征半导体。其中，杂质半导体中掺入的杂质能够提供一定浓度的载流子(如空穴或电子，其中掺杂提供电子的杂质(如5价的磷元素)的杂质半导体也称作电子型半导体或N(negative，负)型半导体，掺杂提供空穴的杂质(如3价的硼元素)的杂质半导体也称作空穴型半导体或P(positive，正)型半导体)时，能够改善本征半导体的导电性，通常载流子浓度越大，半导体的电阻率越低，导电性也越好，在本申请的实施例中，这一类杂质半导体也称为导电型半导体，例如，导电型衬底，InP掺杂的杂质 为氮N、硼B、铝Al等。此外，杂质半导体中掺入的杂质能够对杂质半导体进行杂质补偿时，施主电子刚好够填充受主能级，但是不能向导带和价带提供电子和空穴，使禁带较宽的半导体材料具有与绝缘体相近的电阻率。例如，对InP掺杂实现对InP的杂质补偿，从而提高InP的电阻率，这一类杂质半导体也称为半绝缘型半导体或半绝缘体，或者具有半绝缘体特性。
数字合金：堆叠的合金或元素的交替层组成的超晶格。
k值：电子空穴离化率比值，k值为空穴离化率与电子离化率的比值，或者电子离化率与空穴离化率的比值。需要说明的是，k值通常以空穴离化率与电子离化率中较大的作为分母，较小的作为分子，因此k值通常取值为小数值。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请的实施例应用于光信号接收机，光信号接收机包含光电转换器件和信号接收电路，光电转换器件的作用是将接收自光纤的光信号转化为电信号，信号接收电路从电信号中解出承载的数据。此外，本申请的实施例也可以应用于光模块，光模块的作用是光电转换。其中，光模块也称作光传输模块。参照图1所示，光模块包括光信号发射机11和光信号接收机12。光信号发射机11的作用是将电信号转化为光信号，并输入光纤13进行传输。光信号接收机12的作用是接收由光纤13传入的光信号，并对其进行电信号转化。图1中光信号发射机11和光信号接收机12可以复用光纤13。当然光信号发射机11和光信号接收机12的光信号也可以分别在两条光纤中传输。通常，发送端的光模块把电信号转换成光信号，通过光纤传送后，接收端的光模块再把光信号转换成电信号。其中，光信号接收机或光模块主要是应用于以太网、光纤到户(fibre to the home，FTTH)、光传输网络(optical transport network,OTN)、网络存储、数据中心等领域。基于上述的应用领域，光信号接收机或光模块主要应用上述各领域中的如：光线路终端(optical line terminal，OLT)、光网络单元(optical network unit，ONU)、交换机、光纤路由器、视频光端机、光纤收发器、光纤网卡等设备。其中，光信号接收机及光模块支持不同速率分类，例如：1G～10G低速率,25G,40G,50G,100G,200G/400G等。
本申请的实施例提供的光电转换器件可以为雪崩光电二极。该雪崩光电二极包括： 衬底以及设置于衬底上的多个外延层，多个外延层包括依次层叠设置的第一接触层、倍增层、电场调控层、吸收层以及第二接触层；其中，倍增层采用含锑元素Sb的数字合金。
例如：倍增层的k值小于预定值，其中k值为空穴离化率与电子离化率的比值，或者电子离化率与空穴离化率的比值。具体的k值可以介于0.0001至0.02之间。需要说明的是，k值通常以空穴离化率与电子离化率中较大的作为分母，较小的作为分子，因此k值通常取值为小数值。在一些示例中，倍增层采用，AlGaAsSb或AlInAsSb的数字合金形式。衬底通常采用例如磷化铟(InP)等材料。在一些示例中，倍增层也可以采用k值较小的含锑元素Sb的化合物、InAlAs的数字合金。锑元素Sb的化合物可以为上述的含锑元素Sb的数字合金，或者含锑元素Sb的本征合金晶体材料，例如：本征Al xGa 1-xAs ySb 1-y晶体材料，其本征载流子的浓度小于10 16cm -3。x取值范围为：0.01<＝x<＝0.99，y的取值范围为：0.01<＝y<＝0.99。倍增层的厚度介于10nm至2μm之间。在一个示例中倍增层在垂直于层叠方向上的宽度为10nm到2000nm。
在上述方案中，在上述方案中，当外部光线照射到雪崩光电二极管上时，吸收层能够吸收光子产生电子空穴对，在第一接触层和第二接触层上施加电压后，在电场调控层产生的电场下，两种载流子(电子和空穴)向相反的方向加速漂移，当漂移速度足够大时会与倍增层的晶格原子发生碰撞电离出新的电子空穴对，在倍增层产生的电子空穴对进一步与晶格原子发生碰撞再次电离出新的电子空穴对，从而产生碰撞离化效应，如果电子和空穴都参与碰撞离化，则会导致器件产生过量噪声，降低雪崩光电二极管的灵敏性和速率，本申请的实施例中，由于由于雪崩光电二极管的倍增层采用了含锑元素Sb的数字合金，因此倍增层的k值可以做到较低，例如k值可以做到0.001至0.02之间，这样，电子离化率或空穴离化率中的一者较高，从而使得倍增层中大部分的载流子离化效应是由一种载流子(空穴或电子)碰撞产生，从而降低器件产生的噪声，提高雪崩光电二极管的灵敏性和速率。
示例性的，参照图2所示，多个外延层包括堆叠设置于衬底21上依次层叠设置的第一缓冲层22、第一接触层23、倍增层24、电场调控层25、吸收层26、截止层27、第二缓冲层28以及第二接触层29。截止层27、第二缓冲层28以及第二接触层29的掺杂区域30掺杂有杂质元素离子。其中上述的，第一缓冲层22、第一接触层23可以采用N型杂质离子掺杂，例如磷(P)等产生电子的掺杂离子。电场调控层25可以采用P型杂质离子掺杂，例如，Be,C,Mg,Zn等产生空穴的掺杂离子，电场调控层25的掺杂浓度范围介于1e16cm -3至1e18cm -3之间。第一缓冲层22、第一接触层23、电场调控层25、截止层27、第二缓冲层28以及第二接触层29的材料可以是Al 1-x-yGa xIn yAs、In 1-xGa xAs yP 1-y、Al xGa 1-xAsySb 1-y(其中x,y取值大于等于0，小于等于1)等。吸收层26的材料可以为InGaAs等。在垂直于多个外延层堆叠方向的平面上，掺杂区域30与截止层27的边缘的最小距离大于等于第一阈值；和或，掺杂区域30与第二缓冲层28的边缘的最小距离大于等于第一阈值；和或，掺杂区域30与第二接触层29的边缘的最小距离大于等于第一阈值。其中第一阈值的范围为1-10μm。这样，对于截止层27、第二缓冲层28以及第二接触层29并不是整层进行掺杂，而是仅对于掺杂区域30进行掺杂，可以有效实现对器件电场的控制，显著降低器件的暗电流。其中，掺杂区域30 位于截止层27、第二缓冲层28以及第二接触层29形成的堆叠结构的中心区域。在图2示出的方案中，多个外延层还包括，设置于衬底21和第一接触层23之间的第一缓冲层22、设置于吸收层26与第二接触层29之间的第二缓冲层28、设置于吸收层26和第二缓冲层28之间的截止层27。其中，第一缓冲层22主要用于外延层与衬底21的晶格适配，以克服衬底的晶格缺陷。第二缓冲层28主要用于雪崩光电二极管的电场适配，截止层27主要用于外延形成的吸收层的表面控制。基于上述第一接触层23、截止层27以及第二缓冲层28的功能，需要说明的是，第一接触层23、截止层27以及第二缓冲层28均是可选的层结构，在包含这些层结构时，雪崩光电二极管能够取得更好的效果。即在一些实施例中也可以不包含这三层或者仅包含这三层中的任一一层或多层。当然在一些实施例中，根据需要多个外延层还可以包含更多的其他层结构。
此外，吸收层26上形成有第一台阶S1，第一台阶S1靠近第二接触层29的第一表面的宽度小于靠近电场调控层25的第二表面的宽度；第二接触层29的宽度等于第一表面的宽度；第一接触层23的宽度、倍增层24的宽度以及电场调控层25的宽度均等于第二表面的宽度。如图2所示，第一台阶S1的台阶厚度H1大于吸收层26厚度的十分之一，并且小于吸收层26厚度的二分之一。其中，各个外延层的宽度的方向垂直于外延层的堆叠方向。当然，当多个外延层包含截止层27以及第二缓冲层28时，截止层27的宽度、第二缓冲层28的宽度等于第一表面的宽度。当多个外延层包含第一缓冲层22时，第一缓冲层22的宽度等于第二表面的宽度。
衬底21上形成有第二台阶S2，第二台阶S2靠近第一接触层23的第一表面的宽度小于远离第一接触层23的第二表面的宽度；第一接触层23的宽度、倍增层24的宽度以及电场调控层25的宽度均等于第一表面的宽度。第二台阶H2的台阶厚度大于100nm。当多个外延层包含第一缓冲层22时，第一缓冲层22的宽度等于第一表面的宽度。
如图2所示，还包括第一电极层31和第二电极层32。第一电极层31形成于第二接触层29上远离衬底21的一侧，第二电极层32形成于衬底21上远离第一接触层23的一侧。其中第一电极层31和第二电极层32可以采用金属材料。衬底21的材料采用半导体，衬底21掺杂有提供载流子的杂质，即在该实施例中外延层均设置于导电型衬底上。此外，外延层(21-30)的外侧覆盖有钝化层33，钝化层33的材料可以为SiO 2或者SiN x等。其中钝化层33在第二接触层29上形成有窗口W，其中第一电极层31形成于该窗口W中，并且图2提供的一种顶入式的雪崩光电二极管，光线从该窗口W中入射。如图2所示，提供了光线的入射方向。
在图2提供的实施例中，由于雪崩光电二极管设置了两个台阶，这样可以尽量降低各层之间正对的面积，从而减少外延层之间寄生电容的大小，提高器件的特性。
在另一个示例中，参照图3所示，多个外延层包括堆叠设置于衬底21上的第一缓冲层22、第一接触层23、倍增层24、电场调控层25、吸收层26、截止层27、第二缓冲层28以及第二接触层29。截止层27、第二缓冲层28以及第二接触层29的掺杂区域30掺杂有杂质元素离子。其中外延层的具体材料和结构参数可以参照图2所示，这里不再赘述。
与上述图2的提供的实施例中的雪崩光电二极管的区别是,图3提供的雪崩光电二 极管的还包括第一接触层23形成有第三台阶S3；第三台阶S3靠近倍增层24的第一表面的宽度小于靠近衬底21的第二表面；衬底21的宽度等于第二表面的宽度；倍增层24的宽度、电场调控层25的宽度、吸收层26的第一台阶S1的第二表面的宽度均等于第三台阶S3的第一表面的宽度。
吸收层26上形成有第一台阶S1，衬底上形成有第二台阶S2，其中第一台阶和第二台阶的描述可以参照图2对应的实施例中的描述，此处不再赘述。
参照图3所示，还包括第一电极层31和第二电极层32，第一电极层31形成于第二接触层上远离衬底21的一侧，第二电极层32形成于第一接触层23上远离衬底21的一侧。其中第一电极层31和第二电极层32可以采用金属材料。衬底21的材料采用半绝缘体。此外，外延层(21-30)的外侧覆盖有钝化层33，钝化层33的材料可以为SiO 2或者SiN x等。其中钝化层22在第二接触层上形成有窗口W，其中第一电极层31形成于该窗口W中，并且图3提供的一种顶入式的雪崩光电二极管，光线从该窗口W中入射。如图3所示，提供了光线的入射方向。
其中，相对于图2提供的雪崩光电二极管，图3提供的雪崩光电二极管中外延层均设置在半绝缘体形成的衬底上，第一电极层和第二电极层位于雪崩光电二极管的同一个面，即共面电极，在制作工艺中可以采用一次沟通工艺在同一材料层上制作形成。此外，在图3提供的实施例中，由于雪崩光电二极管设置了三个台阶，这样可以尽量降低各层之间正对的面积，从而减少外延层之间寄生电容的大小，提高器件的特性。
在另一个示例中，参照图4所示，多个外延层包括堆叠设置于衬底21上的第一缓冲层22、第一接触层23、倍增层24、电场调控层25、吸收层26、截止层27、第二缓冲层28以及第二接触层29。截止层27、第二缓冲层28以及第二接触层29的掺杂区域30掺杂有杂质元素离子。其中外延层的具体材料和结构参数可以参照图2所示，这里不再赘述。
与上述图3的提供的实施例中的雪崩光电二极管的区别是在图4提供的雪崩光电二极管包括第一接触层23形成的第三台阶S3以及衬底上形成有第二台阶S2。第一接触层23形成有第三台阶S3；第三台阶S3靠近倍增层24的第一表面的宽度小于靠近衬底21的第二表面；第一缓冲层22的宽度等于第二表面的宽度；倍增层24的宽度、电场调控层25的宽度、吸收层26的宽度、截止层27、第二缓冲层28以及第二接触层29的宽度均等于第一表面的宽度。第二台阶的台阶厚度大于100nm。
参照图4所示，雪崩光电二极管还包括第一电极层31和第二电极层32，第一电极层31形成于第二接触层上远离衬底21的一侧，第二电极层32形成于第一接触层23上远离衬底21的一侧。其中第一电极层31和第二电极层32可以采用金属材料。衬底21的材料采用半绝缘体。此外，外延层(21-30)的外侧覆盖有钝化层33，钝化层33的材料可以为SiO 2或者SiN x等。其中钝化层22在第二接触层上形成有窗口W，其中第一电极层31形成于该窗口W中，并且图4提供的一种顶入式的雪崩光电二极管，光线从该窗口W中入射。如图4所示，提供了光线的入射方向。
在图4提供的方案中，相对于图3提供的雪崩光电二极管，减少了一个台阶能够减少制程工艺的复杂度。
本申请的实施例提供一种雪崩光电二极管的制作方法，包括如下步骤：
101、制作衬底。
其中，衬底可以采用InP材料，根据上述对衬底材料的不同要求，衬底可以是直接沉积工艺形成或生长工艺形成。例如衬底采用半绝缘体时，由于对衬底的制程工艺要求要求较高，可以采用高温化学气相沉积法(chemical vapor deposition，CVD)形成。当衬底采用对制程工艺要求较低的导电型衬底时，通常可以采用物理气相传输法(physical vapor transport process，PVT)的方法生长工艺制作晶体，将晶体再通过线切割，研磨和抛光等工艺加工得到衬底，由于衬底可以采用导电型的基底(例如基底掺杂有提供载流子的杂质)，因此对衬底的纯度，以及PVT的工艺复杂度要求较低。
102、在衬底上制作多个外延层，多个外延层包括第一接触层、倍增层、电场调控层、吸收层以及第二接触层；其中，倍增层采用含锑元素Sb的数字合金。
所有外延层采用分子束外延(molecular-beam epitaxy,MBE)技术生长生长于衬底之上。
在另一实施例中，本申请的实施例提供了如图2所示的雪崩光电二极管的制作方法，具体包括如下步骤：
201、制作衬底。
202、参照图5所示，在衬底21上制作多个外延层，多个外延层包括依次层叠设置的第一接触层、倍增层、电场调控层、吸收层以及第二接触层；其中，倍增层采用含锑元素Sb的数字合金。
具体的如图5所示，多个外延层包括堆叠设置于衬底21上依次层叠设置的第一缓冲层22、第一接触层23、倍增层24、电场调控层25、吸收层26、截止层27、第二缓冲层28以及第二接触层29。其中，如上所述第一接触层23、截止层27以及第二缓冲层28均是可选的层结构，在一些实施例中也可以不制作这三层或者仅制作这三层中的任一一层或多层。当然在一些实施例中，根据需要在多个外延层中制作更多的其他层结构。
203、参照图6所示，通过刻蚀工艺在多个外延层上制作台面，在吸收层上形成第一台阶S1。
刻蚀工艺可以为干法刻蚀，也可以为湿法刻蚀。第一台阶S1靠近第二接触层29第一表面的宽度小于靠近电场调控层25的第二表面的宽度；截止层27的宽度、第二缓冲层28的宽度以及第二接触层29的宽度均等于第一表面的宽度；第一缓冲层22的宽度、第一接触层23的宽度、倍增层24的宽度以及电场调控层25的宽度均等于第二表面的宽度。如图2所示，第一台阶S1刻蚀至大于吸收层26厚度的十分之一，并且小于吸收层26厚度的二分之一的位置。其中，各个外延层的宽度的方向垂直于外延层的堆叠方向。
204、参照图6所示，通过刻蚀工艺在所述多个外延层上制作台面，在衬底上形成第二台阶S2。
刻蚀工艺可以为干法刻蚀，也可以为湿法刻蚀。第二台阶S2靠近第一接触层23的第一表面的宽度小于远离第一接触层23的第二表面的宽度；第一缓冲层22的宽度、第一接触层23的宽度、倍增层24的宽度以及电场调控层25的宽度均等于第一表面的 宽度。第二台阶H2的刻蚀至大于100nm以上。其中宽度的方向垂直于所述外延层的堆叠方向。
其中，在本申请的实施例中并不限定步骤203和步骤204的顺序，即可以先刻蚀出第一台阶S1在刻蚀出第二台阶S2，或者先刻蚀出第二台阶S2再刻蚀出第一台阶S1。
205、参照图7所示，在多个外延层上形成钝化层33。
其次，通过薄膜生长工艺(如等离子增强化学气相沉积法)在外延层表面生长一层钝化层。
206、参照图7所示，在第二接触层29上的钝化层33上形成窗口W。
然后通过一次曝光工艺(例如：光刻和刻蚀工艺)将第二缓冲层28上所需要形成掺杂区域30地方的钝化层去除掉形成窗口W。
207、参照图8所示，通过窗口W在截止层27、第二缓冲层28以及第二接触层29的掺杂区域30掺杂杂质元素离子。
步骤207具体可以通过离子注入或者扩散的方法在截止层27、第二缓冲层28以及第二接触层29的掺杂区域30掺杂杂质元素离子形成掺杂区域30。掺杂区域30的深度小于等于截止层、第二缓冲层以及第二接触层的厚度，宽度如上述。
208、参照图2所示，在第二接触层29上远离衬底21的一侧形成第一电极层31，在衬底21上远离第一接触层23的一侧形成第二电极层32。
然后，通过光刻工艺、金属沉积和剥离工艺第一电极层31。并对对雪崩光电二极管进行减薄抛光(主要是对衬底的背面(远离第一缓冲层的表面))，在衬底背面溅射一层金属材料形成第二电极层。
在另一实施例中，本申请的实施例提供了如图4所示的雪崩光电二极管的制作方法，具体包括如下步骤：
301、制作衬底。
302、参照图5所示，在衬底21上制作多个外延层，多个外延层包括第一接触层、倍增层、电场调控层、吸收层以及第二接触层；其中，倍增层采用含锑元素Sb的数字合金。
具体的如图5所示，多个外延层包括堆叠设置于衬底21上的第一缓冲层22、第一接触层23、倍增层24、电场调控层25、吸收层26、截止层27、第二缓冲层28以及第二接触层29。其中，如上所述第一接触层23、截止层27以及第二缓冲层28均是可选的层结构，在一些实施例中也可以不制作这三层或者仅制作这三层中的任一一层或多层。当然在一些实施例中，根据需要在多个外延层中制作更多的其他层结构。
303、参照图9所示，通过刻蚀工艺在多个外延层上制作台面，在吸收层26上形成第一台阶S1。
其中，第一台阶S1靠近第二接触层29的第一表面的宽度小于靠近电场调控层25的第二表面的宽度；截止层27的宽度、第二缓冲层28的宽度以及第二接触层29的宽度均等于第一表面的宽度；第一接触层23的靠近倍增层24的表面的宽度、倍增层24的宽度以及电场调控层25的宽度均等于第二表面的宽度。其中宽度的方向垂直于所述外延层的堆叠方向。
304、参照图9所示，通过刻蚀工艺在多个外延层上制作台面，在所述第一接触 层23形成第三台阶S3。
第三台阶S3靠近倍增层24的第一表面的宽度小于靠近衬底21的第二表面；第一缓冲层22的宽度等于第二表面的宽度；倍增层24的宽度、电场调控层25的宽度、吸收层26的第一台阶S1的第二表面的宽度均等于第三台阶的第一表面的宽度，其中宽度的方向垂直于外延层的堆叠方向。
305、参照图9所示，通过刻蚀工艺在所述多个外延层上制作台面，在衬底21上形成第二台阶S2。
第二台阶S2靠近第一接触层23的第一表面的宽度小于远离第一接触层23的第二表面的宽度；第一缓冲层22的宽度、第一接触层23的第三台阶S3的第二表面的宽度均等于第二台阶S2的第一表面的宽度，其中宽度的方向垂直于外延层的堆叠方向。
其中，本申请的实施例中可以按照台阶S1-S3-S2的顺序进行刻蚀，或者按照S2-S3-S1的顺序刻蚀。
305、参照图10所示，在多个外延层上形成钝化层33。
306、参照图10所示，在第二接触层29上的钝化层33上形成窗口W。
307、参照图11所示，通过窗口W在截止层27、第二缓冲层28以及第二接触层29的掺杂区域30掺杂杂质元素离子。
308、参照图3所示，在第二接触层29上远离衬底21的一侧形成第一电极层31，在第一接触层23上远离衬底21的一侧形成第二电极层32。
其中第一电极层和第二电极层的制作工艺可以参考步骤208中第一电极层的制作工艺，不在赘述。
在制作本申请的实施例提供了如图4所示的雪崩光电二极管的制作方法，可以直接取消上述步骤301-308中的步骤303。其中当不包含第一台阶S1时，倍增层的宽度、电场调控层的宽度、吸收层的宽度、截止层的宽度、第二缓冲层的宽度以及第二接触层的宽度均等于第三台阶S1的第一表面的宽度。
此外，本申请的实施例中对图2提供的雪崩光电二极管以及采用InAlAs作为倍增层的传统雪崩光电二极管的增益与带宽进行了仿真。参照图12提供的增益与带宽曲线，可以看到，在增益大于10dB以后，本申请的实施例提供的雪崩光电二极管的增益和带宽的积明显大于传统雪崩光电二极管的增益与带宽的积，因此本申请的实施例提供的雪崩光电二极管可以明显改善增益和带宽的积。此外，本申请的实施例中对图2提供的雪崩光电二极管以及采用InAlAs作为倍增层的传统雪崩光电二极管的光电流和暗电流。参照图13、图14所示当反向偏置电压(reverse bias)在工作电压18V(-18V)附近时，本申请的实施例提供的雪崩光电二极管的暗电流比传统雪崩光电二极管的暗电流可以低一个数量级。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种雪崩光电二极管，其特征在于，包括：
    衬底以及设置于所述衬底上的多个外延层，所述多个外延层包括依次层叠设置的第一接触层、倍增层、电场调控层、吸收层以及第二接触层；
    其中，所述倍增层采用含锑元素Sb的数字合金。
  2. 根据权利要求1所述的雪崩光电二极管，其特征在于，所述倍增层的k值小于预定值，其中所述k值为空穴离化率与电子离化率的比值，或者电子离化率与空穴离化率的比值。
  3. 根据权利要求1或2所述的雪崩光电二极管，其特征在于，所述倍增层采用AlGaAsSb或AlInAsSb的数字合金形式。
  4. 根据权利要求1或2所述的雪崩光电二极管，其特征在于，所述多个外延层还包括以下一层或多层：设置于所述衬底和所述第一接触层之间的第一缓冲层、设置于所述吸收层与所述第二接触层之间的第二缓冲层。
  5. 根据权利要求4所述的雪崩光电二极管，其特征在于，所述多个外延层还包括设置于所述吸收层和所述第二缓冲层之间的截止层。
  6. 根据权利要求5所述的雪崩光电二极管，其特征在于，所述截止层、第二缓冲层以及第二接触层的掺杂区域掺杂有杂质元素离子。
  7. 根据权利要求6所述的雪崩光电二极管，其特征在于，在垂直于所述多个外延层堆叠方向的平面上，所述掺杂区域与所述截止层的边缘的最小距离大于等于第一阈值；
    和/或，所述掺杂区域与所述第二缓冲层的边缘的最小距离大于等于第一阈值；
    和/或，所述掺杂区域与所述第二接触层的边缘的最小距离大于等于第一阈值。
  8. 根据权利要求1-7任一项所述的雪崩光电二极管，其特征在于，所述吸收层上形成有第一台阶，其中，所述第一台阶靠近所述第二接触层的第一表面的宽度小于靠近所述电场调控层的第二表面的宽度；
    所述第二接触层的宽度等于所述第一表面的宽度；
    所述第一接触层的宽度、所述倍增层的宽度以及所述电场调控层的宽度均等于所述第二表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。
  9. 根据权利要求8所述的雪崩光电二极管，其特征在于，所述第一台阶的台阶厚度大于所述吸收层厚度的十分之一，并且小于所述吸收层厚度的二分之一，所述厚度的方向平行于所述外延层的堆叠方向。
  10. 根据权利要求1-7任一项所述的雪崩光电二极管，其特征在于，所述衬底上形成有第二台阶，所述第二台阶靠近所述第一接触层的第一表面的宽度小于远离所述第一接触层的第二表面的宽度；
    所述第一接触层的宽度、所述倍增层的宽度以及所述电场调控层的宽度均等于所述第一表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。
  11. 根据权利要求10所述的雪崩光电二极管，其特征在于，所述第二台阶的台阶厚度大于100nm，其中所述厚度的方向平行于所述外延层的堆叠方向。
  12. 根据权利要求1-11任一项所述的雪崩光电二极管，其特征在于，还包括第一 电极层和第二电极层；
    所述第一电极层形成于所述第二接触层上远离所述衬底的一侧，所述第二电极层形成于所述衬底上远离所述第一接触层的一侧。
  13. 根据权利要求12所述的雪崩光电二极管，其特征在于，所述衬底的材料采用半导体，所述衬底掺杂有提供载流子的杂质。
  14. 根据权利要求1-7任一项所述的雪崩光电二极管，其特征在于，所述第一接触层形成有第三台阶；
    所述第三台阶靠近所述倍增层的第一表面的宽度小于靠近所述衬底的第二表面；
    所以衬底的宽度等于所述第二表面的宽度；所述倍增层的宽度、电场调控层的宽度、吸收层的宽度以及第二接触层的宽度均等于所述第一表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。
  15. 根据权利要求14所述的雪崩光电二极管，其特征在于，还包括第一电极层和第二电极层，所述第一电极层形成于所述第二接触层上远离所述衬底的一侧，所述第二电极层形成于所述第一接触层上远离所述衬底的一侧。
  16. 根据权利要求15所述的雪崩光电二极管，其特征在于，所述衬底的材料采用半绝缘体。
  17. 一种雪崩光电二极管的制作方法，其特征在于，
    制作衬底；
    在所述衬底上制作多个外延层，所述多个外延层包括依次层叠设置的第一接触层、倍增层、电场调控层、吸收层以及第二接触层；其中，所述倍增层采用含锑元素Sb的数字合金。
  18. 根据权利要求17所述的方法，其特征在于，所述方法还包括：
    在所述第二接触层的掺杂区域掺杂杂质元素离子。
  19. 根据权利要求18所述的方法，其特征在于，所述多个外延层还包括设置于所述吸收层与所述第二接触层之间的第二缓冲层；
    所述方法还包括：
    在所述第二缓冲层的掺杂区域掺杂杂质元素离子。
  20. 根据权利要求17所述的方法，其特征在于，通过刻蚀工艺在所述多个外延层上制作台面，在所述吸收层上形成第一台阶，其中，所述第一台阶靠近所述第二接触层的第一表面的宽度小于靠近所述电场调控层的第二表面的宽度；
    所述第二接触层的宽度等于所述第一表面的宽度；所述第一接触层的宽度、所述倍增层的宽度以及所述电场调控层的宽度均等于所述第二表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。
  21. 根据权利要求17所述的方法，其特征在于，通过刻蚀工艺在所述多个外延层上制作台面，在所述衬底上形成第二台阶，所述第二台阶靠近所述第一接触层的第一表面的宽度小于远离所述第一接触层的第二表面的宽度；所述第一接触层的宽度、所述倍增层的宽度以及所述电场调控层的宽度均等于所述第一表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。
  22. 根据权利要求17所述的方法，其特征在于，通过刻蚀工艺在所述多个外延 层上制作台面，在所述第一接触层形成第三台阶；所述第三台阶靠近所述倍增层的第一表面的宽度小于靠近所述衬底的第二表面；所以衬底的宽度等于所述第二表面的宽度；所述倍增层的宽度、电场调控层的宽度、吸收层的宽度以及第二接触层的宽度均等于所述第一表面的宽度，其中所述宽度的方向垂直于所述外延层的堆叠方向。
  23. 根据权利要求19所述的方法，其特征在于，在所述第二接触层的掺杂区域掺杂杂质元素离子包括：
    制作覆盖所述多个外延层的钝化层；
    将所述第二接触层上对应所述掺杂区域的钝化层去除；
    在所述第二接触层的掺杂区域掺杂杂质元素离子。
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