WO2022127619A1 - 一种多层电路板的单张芯板对位方法 - Google Patents

一种多层电路板的单张芯板对位方法 Download PDF

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Publication number
WO2022127619A1
WO2022127619A1 PCT/CN2021/135377 CN2021135377W WO2022127619A1 WO 2022127619 A1 WO2022127619 A1 WO 2022127619A1 CN 2021135377 W CN2021135377 W CN 2021135377W WO 2022127619 A1 WO2022127619 A1 WO 2022127619A1
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Prior art keywords
single core
core board
area
board
target
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PCT/CN2021/135377
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English (en)
French (fr)
Inventor
龚丽丽
谢二堂
高峰
叶锦华
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华为技术有限公司
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Priority to EP21905548.0A priority Critical patent/EP4262331A4/en
Publication of WO2022127619A1 publication Critical patent/WO2022127619A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4679—Aligning added circuit layers or via connections relative to previous circuit layers

Definitions

  • the present application relates to the technical field of electronic equipment, and in particular, to a method for aligning a single core board of a multi-layer circuit board.
  • Figure 1a is a cross-sectional view of the design of the multilayer circuit board
  • Figure 1b is a schematic diagram of the influence of the layer deflection of the multilayer circuit board.
  • the actual layer deflection of the multilayer circuit board makes the conductive vias to the metal layers of different networks
  • the distances of the edges deviate from the design values h1, h2 of Fig. 1a, resulting in a short circuit risk.
  • the distance between h1 and h2 in the figure needs to be designed to be large enough to avoid the risk of short circuit between different networks, thereby hindering the evolution of multi-layer circuit boards to high density and miniaturization.
  • FIG. 3 is a schematic flow diagram of the prior art using rivets for positioning. As shown in the figure, the single core plate is first fabricated. The rivet hole, then select the appropriate single core board according to the needs, insert the above single core board into the riveting machine in sequence, use the riveting machine to rive the multiple single core boards, and then press the plate to realize the multi-layer circuit board. Lamination of individual core sheets.
  • the present application provides a single core board alignment method of a multilayer circuit board, so as to reduce the layer deviation between the single core boards, reduce the overall layer deviation of the multi-layer circuit board, and improve the outlet density of the multi-layer circuit board .
  • the present application provides a method for aligning a single core board of a multi-layer circuit board.
  • a method for aligning a single core board of a multi-layer circuit board When the method is applied to prepare a multi-layer circuit board, a plurality of single-sheet core boards used for preparing the multi-layer circuit board are aligned.
  • the method specifically includes: firstly determining a precision area and an auxiliary area of a set surface of a single core board, the precision area having a precision area target, and the auxiliary area including the auxiliary target; installing the single core board of the reference board to the stacking machine , the reference board refers to the single core board used as the alignment reference when the Nth layer single core board is installed; obtain the first coordinates of the precision area target of the single core board of the reference board and the second coordinate of the auxiliary target Coordinates, specifically, the surface topography of a single core board can be scanned through a lens, image processing and data analysis can be performed to obtain the above-mentioned first and second coordinates; then the Nth layer single core board is transported to the stacking machine, N ⁇ 2; Obtain the third coordinate of the precision area target of the single core board of the Nth layer and the fourth coordinate of the auxiliary target.
  • the above-mentioned third and fourth coordinates are obtained in a similar manner to the first and second
  • the surface topography image can be obtained by using the lens, and then calculated; then the Nth layer single core board and the N-1th layer single core board are superimposed, so that the deviation between the third coordinate and the first coordinate is not greater than the first one.
  • a set threshold A, and the deviation between the fourth coordinate and the second coordinate is not greater than the second set threshold B.
  • This solution can make the positioning method of the single core board of the multi-layer circuit board, and use the precision area as the alignment reference to carry out the alignment to ensure the alignment accuracy of the precision area, thereby improving the overall alignment accuracy of the multi-layer circuit board. Therefore, the solution can reduce the layer deviation between each single core board, reduce the overall layer deviation of the multi-layer circuit board, and improve the outlet density of the multi-layer circuit board.
  • the precision area and the auxiliary area of the set surface of the single core board are determined, the precision area has a precision area target, and the auxiliary area includes the auxiliary area target, which specifically includes: on the set surface of the single core board.
  • the above-mentioned precision area is used to make the precision area target, and the auxiliary target is made in the auxiliary area of the single core board.
  • the above-mentioned precision area target and the auxiliary target are made on the single core board according to the requirements, so as to facilitate the subsequent alignment process.
  • the above-mentioned precise area target and auxiliary target can be prepared by subsequent processes, and can also use the structure already possessed on a single core board, by defining a pattern with set characteristics as the target, to Formation of precision area targets and auxiliary targets. That is, the precise area target can be defined in the precise area of the set surface of the single core board, and the auxiliary target can be defined in the auxiliary area of the single core board.
  • the process for preparing the target is reduced, and the alignment efficiency of the single core board of the multi-layer circuit board is high.
  • the above-mentioned precise area for alignment is the most precise area.
  • Each single core board includes the position of a plurality of conductive through holes, and the distance between the conductive through holes and the edges of the metal layers of different networks is smaller. , that is, the precise area of a single core board, and the area with the smallest distance from the conductive through hole to the edge of the metal layer of the different network is the most precise area of the single core board.
  • the specific position of the above-mentioned auxiliary area is also not limited, it can be the edge of a single core board, or, the above-mentioned auxiliary area can also be a sub-precision area of a single core board, and the sub-precision area refers to the conductive through hole to the conductive through hole.
  • the distance between the through holes located at the edges of the metal layers of different networks is only greater than the above-mentioned distance of the most precise area.
  • the auxiliary area is a sub-precision area, using both the most precise area and the sub-precision area as the alignment reference, in addition to improving the most precise area.
  • the alignment accuracy of the precision area also improves the alignment accuracy of the sub-precision area, which can improve the overall alignment accuracy of the multilayer circuit board.
  • first set threshold value A and second set threshold value B satisfy: A ⁇ B, that is to say, during the alignment process, the alignment accuracy of the precise area should be preferentially guaranteed.
  • Each single core board includes two surfaces, and the above two surfaces are the first surface and the second surface respectively. You can first judge which surface has a higher density among the two surfaces, and then select this surface as the setting surface. That is, the surface is used for alignment, thereby improving the alignment accuracy. Specifically, the first minimum distance from the conductive via in the precision area of the first surface to the edge of the metal layer located in a different network with the conductive via can be calculated, and the conductive via in the precision area of the second surface to the conductive via located in the The second minimum distance between the edges of the metal layers of different networks; when the first minimum distance is less than the second minimum distance, the first surface is determined as the set surface; when the first minimum distance is greater than the second minimum distance, the second surface is determined to set the surface.
  • the precision areas on the two surfaces of the single core board can also be referred to for alignment, so as to improve the alignment of the multilayer circuit board.
  • precision calculate the first minimum distance from the conductive via in the precision area of the first surface to the edge of the conductive via located in the metal layer of a different network, and calculate the distance between the conductive via in the precision area of the second surface and the conductive via The second minimum distance between the edges of the metal layers of different networks; when the first minimum distance is equal to the second minimum distance, both the first surface and the second surface are set surfaces; the first and third coordinates are the leaflet The fitting center coordinates of the precision area target on the first surface of the core board and the precision area target on the second surface.
  • the above-mentioned fitting center coordinates may be the average value of the coordinates of the precision area target on the first surface and the coordinates of the precision area target on the second surface; or, the above-mentioned fitting center coordinates may also be the image of the first surface and the first After the images of the two surfaces are overlapped, the coordinates of the center of the precision area target.
  • the above-mentioned determination of the above-mentioned fitting center coordinates is determined by the precise area target of the first surface and the precise area target of the second surface.
  • the solution can take into account the alignment conditions of the precise areas of the two surfaces, which is beneficial to improve the alignment accuracy.
  • two adjacent surfaces can also be used as a relative reference for alignment.
  • the precise area target and the auxiliary target on the first surface of each single core board, and the precise area target and the auxiliary target on the second surface are obtained respectively.
  • the first and second coordinates of the side surface of the N-1th layer of the single core board facing the Nth layer of the single core board can be aligned with the Nth layer of the single core board facing the N-th
  • the third and fourth coordinates of one side surface of the single-layer single core board are aligned, thereby further improving the alignment accuracy.
  • Figure 1a is a design cross-sectional view of a multilayer circuit board
  • Figure 1b is a schematic diagram of the effect of layer bias on a multilayer circuit board
  • FIG. 2 is a schematic diagram of a surface structure of a single core board in the prior art
  • FIG. 3 is a flowchart of a method for aligning a single core board of a multilayer circuit board in an embodiment of the application
  • FIG. 4 is a schematic cross-sectional structure diagram of a multilayer circuit board in an embodiment of the application.
  • FIG. 5 is a schematic diagram of a surface structure of a single core board in an embodiment of the application.
  • FIG. 6 is an enlarged partial cross-sectional view of the multilayer circuit board in the embodiment of the application.
  • Fig. 7a and Fig. 7b are respectively partial enlarged views of the pattern of the single core board in the embodiment of the application;
  • FIG. 8 is another schematic diagram of the cooperation between the lens and the single core board in the embodiment of the application.
  • FIG. 9 is a schematic diagram of a stacking of a single core board of a multilayer circuit board in an embodiment of the application.
  • FIG. 10 is a schematic diagram of another surface structure of a single core board in the embodiment of the application.
  • FIG. 11 is a schematic cross-sectional structure diagram of a single core board in an embodiment of the application.
  • FIG. 13 is another schematic diagram of stacking a single core board of a multilayer circuit board in an embodiment of the application.
  • FIG. 14 is another schematic diagram of stacking a single core board of a multilayer circuit board in an embodiment of the application.
  • 15 is another schematic diagram of stacking a single core board of the multilayer circuit board shown in the embodiment of the application;
  • FIG. 16 is an enlarged partial cross-sectional view of the multilayer circuit board in the embodiment of the present application.
  • references in this specification to "one embodiment” or “a particular embodiment” or the like mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • the terms “including”, “including”, “having” and their variants mean “including but not limited to” unless specifically emphasized otherwise.
  • the board edge target 110 of the single core board 100 is used to simulate the board center of the single core board 100 120 is used as the alignment center to perform alignment.
  • the board center 120 of the single core board 100 is the position with the best alignment accuracy.
  • the precise area 130 of the single core board 100 may not be located in the center 120 of the board. Therefore, the alignment accuracy of the multilayer circuit board needs to be improved. Therefore, the present application proposes a single core board alignment method for the multilayer circuit board. , the following specific examples are given to illustrate the above method.
  • FIG. 3 is a flowchart of a method for aligning a single core board of a multilayer circuit board in an embodiment of the application. As shown in FIG. 3 , the method for aligning a single core board of a multilayer circuit board includes the following steps:
  • Step S101 determining the precision area of the set surface of the single core board, the above-mentioned precision area has a precision area target, and the above-mentioned auxiliary area includes an auxiliary target;
  • FIG. 4 is a schematic cross-sectional structure diagram of the multilayer circuit board in the embodiment of the application.
  • the multilayer circuit board includes a plurality of single core boards 100 , and there are also arranged between adjacent single core boards 100 . There are prepregs 200 to realize the fixation between adjacent single core boards 100 .
  • FIG. 5 is a schematic diagram of a surface structure of a single core board 100 in an embodiment of the application
  • FIG. 6 is a schematic diagram of a cross-sectional structure of a multi-layer circuit board in an embodiment of the application. Referring to FIG. 5 and FIG.
  • the surface has a metal layer 140 , and the metal layer 140 includes a plurality of copper sheets 141 and a plurality of traces 142 .
  • the plurality of copper sheets 141 and the plurality of traces 142 of the above-mentioned metal layer 140 can form a plurality of different networks, each conductive via 300 is located in one of the networks, and the distance between the conductive via 300 and the metal layer 140 in the same network It may not be limited, but it needs to ensure that the distance between the conductive via 300 and the metal layer 140 located in a different network with the conductive via 300 is greater than a set value.
  • 7a and 7b are respectively partial enlarged views of the metal layer 140 of the single core board 100 in the embodiment of the present application. With reference to FIGS.
  • h1 in the figure is the conductive via 300 to the conductive via
  • the distance between the hole 300 located at the edge of the copper sheet 141 of the metal layer 140 of different networks, h2 in the figure is the distance from the conductive via 300 to the edge of the trace 142 of the metal layer 140 of the different network with the conductive via 300 .
  • Each single core board 100 includes a plurality of positions of conductive vias 300 , and the conductive vias 300 to the area with a smaller distance from the edge of the conductive vias 300 located in the metal layers 140 of different networks is a single core board Precision area 130 of 100 is shown in FIG. 5 .
  • the precision areas 130 of the single core board 100 of the same multilayer circuit board overlap each other after stacking, that is to say, the above-mentioned precision areas 130 are the precision areas 130 of the multilayer circuit board, which are relative to the same Or the precise area 130 of the conductive vias 300 in the same group. Therefore, when each single core board 100 is aligned with the precise area 130, it can be ensured that the overall layer of the multi-layer circuit board is relatively small.
  • the above-mentioned precise area 130 may be the most precise area 131 , that is, the area with the smallest distance from the conductive via 300 to the edge of the metal layer 140 located in a different network with the conductive via 300 , so as to ensure the alignment of the area. The accuracy of the interlayer alignment of the entire multilayer circuit board can be improved.
  • Step S102 installing the single core board of the reference board to the stacking machine
  • Step S103 obtaining the first coordinate of the precision area target and the second coordinate of the auxiliary target of the single core plate of the reference plate;
  • FIG. 8 is another schematic diagram of the cooperation between the lens and the single core board in the embodiment of the application, as shown in FIG. 8 .
  • the above-mentioned stacking machine (not shown in the figure) has a lens 400 and a controller (not shown in the figure) connected with the lens 400, and the above-mentioned controller can control the lens 400 to take a picture of the single core board 100 of the above-mentioned reference board, Obtain the surface topography of the single core board 100 of the reference board, identify the precision area target 150 and the auxiliary target 160 , and calculate the first coordinate of the precision area target 150 and the second coordinate of the auxiliary target 160 .
  • Step S104 transporting the Nth layer single core board to the stacking machine, N ⁇ 2;
  • a manipulator can be used to transport a single core board to the worktable area of the stacking machine, and specifically, it can be transported to the area where the reference board is located.
  • Step S105 acquiring the third coordinate of the precision area target and the fourth coordinate of the auxiliary target of the Nth layer single core board;
  • the controller of the stacking machine can also control the lens 400 to take pictures of the above-mentioned N-th layer single core board 100 , obtain the surface topography of the N-th layer single core board 100 , and identify the precise area target 150 and the auxiliary target 160 , the third coordinate of the above-mentioned precise area target 150 and the fourth coordinate of the auxiliary target 160 are obtained by calculation.
  • Step S106 stacking the N-th layer of the single core board and the N-1-th layer of the single core board, so that the deviation between the third coordinate and the first coordinate is not greater than the first set threshold A, and the fourth coordinate and The deviation between the second coordinates is not greater than the second set threshold B.
  • FIG. 9 is a schematic diagram of stacking a single core board of a multi-layer circuit board in an embodiment of the application.
  • the controller controls the manipulator to move the single core board 100 so that the third coordinate is close to the first coordinate, and Make the deviation between the third coordinate and the first coordinate not greater than the first set threshold A, in addition, make the fourth coordinate close to the second coordinate, and make the deviation between the fourth coordinate and the second coordinate not greater than the second set Set the threshold B.
  • the alignment of the Nth layer single core board 100 and the reference board is completed, and the Nth layer single core board 100 and the N-1th layer single core board 100 are stacked to complete the Nth layer single core board 100
  • the stacking with the single core board 100 of the N-1th layer, and so on, completes the alignment of each single core board 100 of the multi-layer circuit board, and then can be pressed to assemble each layer of the single core board 100.
  • the board 100 is fixed into a multi-layer circuit board, and then the subsequent process of drilling is performed.
  • the precision area 130 of the single core board 100 has the precision area target 150
  • the auxiliary area has the auxiliary target 160 .
  • the precision area target 150 is specifically formed in the precision area 130 of the set surface of the single core board 100
  • the auxiliary target is formed in the auxiliary area.
  • the auxiliary area may be located at the edge of the single core 100 or in the less precise area 132 .
  • the auxiliary area is located at the edge of the single core board 100.
  • the single core board 100 includes the most precise area 131 and the less precise area 132 , the precise area target 150 is located in the most precise area 131 , and the auxiliary target 160 is located in the less precise area 132 .
  • the above-mentioned sub-precision area 132 refers to the distance from the conductive via 300 to the edge of the metal layer 140 of the single core board 100 that is located in a different network with the conductive via 300 that is only smaller than the above-mentioned most precise area 131.
  • the conductive vias 300 are located in the area of the distance from the edges of the metal layers 140 of different networks.
  • This solution can not only ensure the alignment accuracy of the most precise area 131, but also ensure the alignment accuracy of the sub-precision area 132.
  • the multi-layer circuit The interlayer alignment accuracy of the board as a whole is high. By using the precise area target 150 to cooperate with the auxiliary target 160 , the interlayer alignment accuracy of the multilayer circuit board can be improved.
  • additional targets can be made at corresponding positions; or, according to the pattern of the set surface of the single core board, a pattern with a suitable pattern can be selected as the target. That is to say, the precise area target can be defined in the precise area of the set surface of the single core board, and the auxiliary target can be defined in the auxiliary area of the single core board. That is, there is no need to make a structure other than a single core board, and it is enough to use its own structure to select an appropriate pattern as a target.
  • the solution reduces the technological process of preparing the target, which is beneficial to improve the process efficiency.
  • the first set threshold A and the second set threshold B can satisfy: A ⁇ B, that is, when performing interlayer alignment , when it is necessary to prioritize the alignment accuracy of the precision area 130 when multiple single core boards 100 of the multilayer circuit board are stacked, the area that requires the highest alignment accuracy between layers is the precision area 130 .
  • a ⁇ B that is, when performing interlayer alignment
  • the alignment accuracy of the precision area 130 can be ensured, thereby helping to improve the layers of the entire multilayer circuit board.
  • the single core board 100 alignment method of the above-mentioned multilayer circuit board is used to align the single core board 100 of the multilayer circuit board, for example, for a high-density BGA (Ball Grid Array, solder ball array package) multilayer
  • BGA All Grid Array, solder ball array package
  • FIG. 11 is a schematic cross-sectional structure diagram of a single core board 100 in an embodiment of the application. As shown in FIG. 11 , the single core board 100 includes two surfaces, and the two surfaces are the first surface 170 and the second surface respectively. 180.
  • each single core board 100 also has a corresponding precision area 130.
  • the first minimum distance from the conductive via 300 of the precise area 130 of the first surface 170 to the edge of the metal layer 140 of the different network with the conductive via 300 that is to say, the precise area 130 of the first surface 170 is calculated
  • Each distance from the conductive via 300 to the edge of the metal layer 140 in a different network with the conductive via 300 compare all the above distances, and select the minimum distance as the first minimum distance; in the same way, you can
  • a second minimum distance is calculated among the distances from the conductive via 300 of the precision area 130 of the second surface 180 to the edge of the metal layer 140 where the conductive via 300 is located in a different network.
  • the first surface 170 is the set surface, that is, the precision area target 150 set by the precision area 130 of the first surface 170 as an alignment standard.
  • the second surface 180 is the setting surface, that is, the precision area target 150 set by the precision area 130 of the second surface 180 is used as the alignment standard.
  • FIG. 12 is another schematic diagram of the cooperation between the lens and the single core board in the embodiment of the application. As shown in FIG. 12 , when steps S104 and S106 are performed, the stacking machine is on both surfaces of the single core board 100 . With the lens 400 provided, the surface on the side where the set surface is located can obtain the coordinates of the corresponding precise area target 150 and the auxiliary target 160 for realizing the alignment operation.
  • FIG. 13 is another schematic view of stacking the single core board of the multilayer circuit board in the embodiment of the application. As shown in FIG.
  • the upper surfaces of the first layer single core board 100 to the fifth layer single core board 100 are Set the surface, make the precision area target 150 on the precision area 130 on the upper surface as the alignment reference, the lower surface of the 6th layer single core board 100 to the ninth layer single core board 100 is the setting surface, and the bottom surface on the lower surface
  • the precision area 130 produces the precision area target 150 as an alignment reference.
  • the overall layer bias of the multi-layer circuit board can be increased by 20-40 ⁇ m, that is, the distance from the conductive via 300 to the edge of the metal layer 140 located in a different network with the conductive via 300 can be designed to be shortened by 20-40 ⁇ m. Maximize the density of multilayer circuit boards.
  • step S101 that is, when calculating the first minimum distance and the second minimum distance of the precision regions 130 of the two surfaces, there may be a situation that the first minimum distance is equal to the second minimum distance, and at this time, it can be considered that the first surface 170 and the second surface 180 are setting surfaces.
  • step S102 the precise area targets 150 are fabricated on both surfaces.
  • the stacking machine is provided with lenses 400 on both surfaces of the single core board 100 , and the controller uses the lenses 400 to obtain the precise area target 150 of the first surface 170 of the single core board 100 .
  • the fitting center coordinates can take the above-mentioned first The average coordinates of the coordinates of the precision area target 150 on one surface 170 and the coordinates of the precision area target 150 on the second surface 180 ; or, the controller uses the lens 400 to acquire the image of the first surface 170 and the second surface of the single core board 100 180 images, superimpose the two images, and calculate the coordinates of the center of the superimposed precision area targets 150 of the two surfaces as the fitting center coordinates.
  • FIG. 14 is another schematic diagram of stacking a single core board of the multilayer circuit board in the embodiment of the application. As shown in FIG. 14 , both sides of each single core board 100 have precision area targets 150 and auxiliary targets 160 , and use the fitting center coordinates for alignment.
  • the reference board can be the single core board 100 of the N-1th layer, that is to say, when the single core board 100 of the Nth layer is aligned, the N-1th layer that has been aligned and stacked needs to be obtained first.
  • the first and second coordinates of the single core board 100, and then the third and fourth coordinates of the Nth layer of the single core board 100 and the first and second coordinates of the N-1th layer of the single core board 100 The coordinates are aligned to realize the alignment of the single core board 100 of the multi-layer circuit board.
  • This solution can ensure that the precision areas 130 of adjacent layers are aligned more accurately, and can prevent the single core board 100 of the first layer from being displaced when the stacking machine is displaced, resulting in a large deviation of the aligned single core board 100 later.
  • This solution can better prevent the layer deviation caused by problems such as displacement of the first layer single core board 100 every time.
  • Fig. 15 is another schematic view of stacking a single core board of the multilayer circuit board shown in the embodiment of the application.
  • the surfaces on the opposite sides of the adjacent layers are used for alignment, That is, the third coordinate and the fourth alignment of the side surface of the N-th layer of the single core board 100 facing the N-1-th layer of the single-sheet core board 100 are the same as those of the N-1-th layer of the single-sheet core board 100 facing the N-th layer.
  • the first coordinates and the second coordinates of one side surface of the single core board 100 are aligned, so that the alignment accuracy of the opposite surfaces can be ensured.
  • This solution is based on the solution of fabricating the precise area target 150 and the auxiliary target 160 on both sides of the single core board 100 , and this application will not describe the process in detail.
  • FIG. 16 is an enlarged partial cross-sectional view of the multilayer circuit board in the embodiment of the application.
  • the metal layer 140 of the single core board includes traces 142 and copper sheets 141 , wherein the two layers of copper sheets 141 can be shielded
  • the signals of the traces 142 between the two layers of copper sheets 141 reduce the occurrence of crosstalk in the traces 142 of a single core board of different layers.
  • the above-mentioned copper sheet 141 needs to extend a set distance X relative to the edge of the trace 142 to prevent the signal of the trace 142 from being transmitted to the conductive via 300 .
  • the design distance Y Y-X
  • the layer deflection ability in the technical solution of the present application is relatively strong. Therefore, the value of ⁇ can be smaller. Therefore, the design distance Y can be designed to be relatively small. small, which is beneficial to increase the density of multilayer circuit boards.

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Abstract

本申请提供了一种多层电路板的单张芯板对位方法，包括：先确定单张芯板的设定表面的精密区域，单张芯板的设定表面的精密区域具有精密区域靶标，单张芯板的辅助区域具有辅助靶标；将参考板的单张芯板安装至叠板机；获取参考板的单张芯板的精密区域靶标的第一坐标与辅助靶标的第二坐标；然后将第N层单张芯板运送至叠板机，N≥2；获取第N层单张芯板的精密区域靶标的第三坐标和辅助靶标的第四坐标；然后将第N层单张芯板与第N-1层单张芯板叠置，使第三坐标与第一坐标之间的偏差不大于第一设定阈值A，且第四坐标与第二坐标之间的偏差不大于第二设定阈值B。以减少各单张芯板之间的层偏，减少多层电路板的整体层偏，提高多层电路板的出线密度。

Description

一种多层电路板的单张芯板对位方法
相关申请的交叉引用
本申请要求在2020年12月14日提交中国专利局、申请号为202011475890.3、申请名称为“一种多层电路板的单张芯板对位方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子设备技术领域，尤其涉及到一种多层电路板的单张芯板对位方法。
背景技术
随着科技的发展，电子设备的功能越来越丰富，也越来越趋于小型化，因此，单面电路板或者双面电路板已经无法满足需求。因此，多层电路板越来越多的应用到电子设备中，电路板内部也需要设置多层线路，以实现电路板的小型化。在多层电路板制备过程中，可以先制备具有电路图案的单张芯板，再将各个单张芯板叠压形成多层电路板。各单张芯板之间的对位精度，直接影响了多层电路板的整体层偏能力，进而影响高密出线设计。图1a为多层电路板的设计剖面图，图1b为多层电路板的层偏影响示意图，如图1b所示，多层电路板的实际层偏，使导电通孔到不同网络的金属层的边缘的距离偏离图1a的设计值h1、h2，造成短路风险。设计时为配合多层板的层偏能力，需要将图中h1、h2距离设计足够大，以避免不同网络间的短路风险，进而阻碍多层电路板向高密、小型化的演进。
在将各单张芯板进行叠压时，各层之间的对位精度是影响上述多层电路板的整体层偏能力的重要因素。现有技术中，采用铆钉等机械对位的方式对各单张芯板进行对位，图3为现有技术中采用铆钉定位的流程示意图，如图所示，先在单张芯板上制作铆钉孔、然后根据需求选择合适的单张芯板，按照顺序将上述单张芯板套入铆钉机，利用铆钉机铆合多个单张芯板，之后进行压板，以实现多层电路板的各个单张芯板的叠压。上述过程中，在各个单张芯板制作铆钉孔的重复精度，铆钉机上下模精度等都会影响单张芯板之间对位精度。导致现有技术中多层电路板的层偏较大，多层电路板的出线密度较低。
发明内容
本申请提供了一种多层电路板的单张芯板对位方法，以减少各单张芯板之间的层偏，减少多层电路板的整体层偏，提高多层电路板的出线密度。
本申请提供了一种多层电路板的单张芯板对位方法，该方法应用于制备多层电路板时，将用于制备多层电路板的多张单张芯板进行对位。该方法具体包括：先确定单张芯板的设定表面的精密区域和辅助区域，上述精密区域具有精密区域靶标，上述辅助区域包括辅助靶标；将参考板的单张芯板安装至叠板机，该参考板指的是安装第N层单张芯板时用于作为对位参考的单张芯板；获取参考板的单张芯板的精密区域靶标的第一坐标与辅助靶标的第二坐标，具体可以通过镜头扫描单张芯板的表面形貌，进行图像处理和数据分析，获取上述第一坐标和第二坐标；然后将第N层单张芯板运送至叠板机，N≥2；获取第N层单张 芯板的精密区域靶标的第三坐标和辅助靶标的第四坐标，上述第三坐标和第四坐标的获取方式与第一坐标和第二坐标获取方式类似，也可以采用镜头获取表面形貌图像，然后计算得到；然后将第N层单张芯板与第N-1层单张芯板叠置，使第三坐标与第一坐标之间的偏差不大于第一设定阈值A，且第四坐标与第二坐标之间的偏差不大于第二设定阈值B。该方案可以使多层电路板的单张芯板对位方法，将精密区域作为对位参考，进行对位，保证精密区域的对位精度，从而可以提高多层电路板整体的对位精度，因此该方案可以减少各单张芯板之间的层偏，减少多层电路板的整体层偏，提高多层电路板的出线密度。
一种技术方案中，确定单张芯板的设定表面的精密区域和辅助区域，上述精密区域具有精密区域靶标，上述辅助区域包括辅助区域靶标，具体包括：在单张芯板的设定表面的上述精密区域制作精密区域靶标，在单张芯板的辅助区域制作辅助靶标，该方案中，根据需求在单张芯板制作上述精密区域靶标和辅助靶标，以便于后续对位工艺。
或者，另一种技术方案中，上述精密区域靶标和辅助靶标除了可以通过后续工艺进行制备以外，还可以利用单张芯板上已经具有的结构，通过定义具有设定特征的图形作为靶标，来形成精密区域靶标和辅助靶标。也就是可以在单张芯板的设定表面的精密区域定义精密区域靶标，在单张芯板的辅助区域定义辅助靶标。该技术方案中，减少了制备靶标的工艺，多层电路板的单张芯板的对位效率较高。
上述对位用的精密区域为最精密区域，每个单张芯板包括多个导电通孔的位置，导电通孔到与该导电通孔位于不同网络的金属层的边缘的距离较小的区域，即为单张芯板的精密区域，上述导电通孔到与该导电通孔位于不同网络的金属层的边缘的距离最小的区域，即为单张芯板的最精密区域。上述辅助区域的具体位置也不做限制，可以为单张芯板的边缘，或者，上述辅助区域还可以为单张芯板的次精密区域，次精密区域指的是导电通孔到与该导电通孔位于不同网络的金属层的边缘的距离仅大于最精密区域上述距离的区域，当辅助区域为次精密区域时，以最精密区域和次精密区域都作为对位基准，则除了提升了最精密区域的对位精度，还提升了次精密区域的对位精度，可以提升多层电路板的整体对位精度。
上述第一设定阈值A与第二设定阈值B满足：A≤B，也就是说，在对位过程中，要优先保证精密区域的对位精度。
每个单张芯板包括两个表面，上述两个表面分别为第一表面和第二表面，可以先判断两个表面中，哪一个表面的密度较大，就选择该表面作为设定表面，也就是利用该表面进行对位，从而提高对位精度。具体可以计算第一表面的精密区域的导电通孔到与该导电通孔位于不同网络的金属层的边缘的第一最小距离，第二表面的精密区域的导电通孔到与该导电通孔位于不同网络的金属层的边缘的第二最小距离；当第一最小距离小于第二最小距离时，确定第一表面为设定表面；当第一最小距离大于第二最小距离时，确定第二表面为设定表面。
另一种技术方案中，当上述第一表面与第二表面的精密区域的密度相同时，还可以参考单张芯板两个表面的精密区域来进行对位，提高多层电路板的对位精度。具体的，计算第一表面的精密区域的导电通孔到与该导电通孔位于不同网络的金属层的边缘的第一最小距离，第二表面的精密区域的导电通孔到与该导电通孔位于不同网络的金属层的边缘的第二最小距离；当第一最小距离等于第二最小距离时，第一表面和第二表面都为设定表面；第一坐标和第三坐标为所在单张芯板的第一表面的精密区域靶标与第二表面的精密区域 靶标的拟合中心坐标。
该方案中，上述拟合中心坐标可以为第一表面精密区域靶标的坐标和第二表面的精密区域靶标的坐标的平均值；或者，上述拟合中心坐标还可以为第一表面的图像与第二表面的图像重叠后，精密区域靶标的中心的坐标。总之，上述确定上述拟合中心坐标是通过第一表面的精密区域靶标和第二表面的精密区域靶标确定的。该方案可以兼顾两个表面的精密区域的对位情况，有利于提高对位精度。
在对位过程中，将第N层单张芯板进行对位时，可以参考与第N层单张芯板相邻的第N-1层单张芯板，从而可以保证相邻的两层单张芯板的对位精度。防止在对位过程中，第一层单张芯板出现移动，导致出现由此产生的层偏。
另一种技术方案中，还可以使相邻的两个表面作为相对的参考，以进行对位。具体的，分别获取各个单张芯板的第一表面的精密区域靶标和辅助靶标，以及第二表面的精密区域靶标和辅助靶标。在进行对位时，可以使第N-1层单张芯板朝向第N层单张芯板的一侧表面的第一坐标和第二坐标，与第N层单张芯板朝向第N-1层单张芯板的一侧表面的第三坐标和第四坐标进行对位，从而进一步的提高对位精准。
附图说明
图1a为多层电路板的设计剖面图；
图1b为多层电路板的层偏影响示意图；
图2为现有技术中单张芯板的一种表面结构示意；
图3为本申请实施例中多层电路板的单张芯板对位方法的流程图；
图4为本申请实施例中多层电路板的一种截面结构示意图；
图5为本申请实施例中单张芯板的一种表面结构示意图；
图6为本申请实施例中多层电路板的一种局部截面放大图；
图7a和图7b分别为本申请实施例中单张芯板的图案的局部放大图；
图8为本申请实施例中镜头与单张芯板的另一种配合示意图；
图9为本申请实施例中多层电路板的单张芯板的一种层叠示意图；
图10为本申请实施例中单张芯板的另一种表面结构示意图；
图11为本申请实施例中单张芯板的一种截面结构示意图；
图12为本申请实施例中镜头与单张芯板的另一种配合示意图；
图13为本申请实施例中多层电路板的单张芯板另一种层叠示意图；
图14为本申请实施例中多层电路板的单张芯板另一种层叠示意图；
图15为本申请实施例中图多层电路板的单张芯板另一种层叠示意图；
图16为本申请实施例中多层电路板的局部截面放大图。
附图说明：
100-单张芯板；                        110-板边靶标；
120-板中心；                          130-精密区域；
131-最精密区域；                      132-次精密区域；
140-金属层；                          141-铜片；
142-走线；                            150-精密区域靶标；
160-辅助靶标；                        170-第一表面；
180-第二表面；                        200-半固化片；
300-导电通孔；                        400-镜头。
具体实施方式
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本说明书中描述的参考“一个实施例”或“具体的实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
为了方便理解本申请实施例提供的多层电路板的单张芯板对位方法，下面首先介绍一下其应用场景。随着多层电路板的需求越来越多，且对多层电路板的出线密度要求越来越高，对于多层电路板制备工艺也提出了越来越高的要求，以利于实现电子设备的小型化。具体制备多层电路板时，需要单独制备单张芯板，再将各个单张芯板叠压形成多层电路板，在将各个单张芯板叠压时，多层电路板的各个单张芯板的对位精度直接影响了多层电路板的出线密度。图2为现有技术中单张芯板的一种表面结构示意，如图2所示，现有技术中，利用单张芯板100的板边靶标110来模拟单张芯板100的板中心120作为对位中心，进行对位，该方法理论上单张芯板100的板中心120为对位精度最优的位置，然而，受单张芯板100的涨缩比不同的影响，与板中心120距离越远的区域，误差越大。而单张芯板100的精密区域130未必位于板中心120，因此，多层电路板的对位精度还有待提高，因此，本申请提出了一种多层电路板的单张芯板对位方法，下面列举具体的实施例来说明上述方法。
图3为本申请实施例中多层电路板的单张芯板对位方法的流程图，如图3所示，多层电路板的单张芯板对位方法包括以下步骤：
步骤S101、确定单张芯板的设定表面的精密区域，上述精密区域具有精密区域靶标，上述辅助区域包括辅助靶标；
图4为本申请实施例中多层电路板的一种截面结构示意图，如图4所示，多层电路板包括多个单张芯板100，相邻的单张芯板100之间还设置有半固化片200，以实现相邻单张芯板100之间的固定。为了实现多层电路板的各个单张芯板100之间实现导电连接，需要在多层电路板上制备导电通孔300，该导电通孔300与单张芯板100的金属层140的设定线路电连接。因此，在设计上述单张芯板100时，除了在单张芯板100表面设置金属层140的图案以外，还要设计上述导电通孔300的位置。因此，在将各个单张芯板100叠压的时候，需要使单张芯板100的上述导电通孔300所在的区域较为精准的对位，才可以在设计单张芯板100的走线142图案时，走线142图案设计的较为密集。图5为本申请实施例中单张芯板100的一种表面结构示意图，图6为本申请实施例中多层电路板的截面结构示意图，结合图5和图6，单张芯板100的表面具有金属层140，金属层140包括多个铜片141和多个走线142。上述金属层140的多个铜片141和多个走线142可以形成多个不同的网络，每个导电通孔300位于其中一个网络，该导电通孔300与同一网络中的金属层140的距离可以不限，但是需要保证导电通孔300到与导电通孔300位于不同网络的金属 层140的距离大于设定值。图7a和图7b分别为本申请实施例中单张芯板100的金属层140的局部放大图，结合图6、图7a和图7b，图中的h1为导电通孔300到与该导电通孔300位于不同网络的金属层140的铜片141边缘的距离，图中的h2为导电通孔300到与该导电通孔300位于不同网络的金属层140的走线142边缘的距离。每个单张芯板100包括多个导电通孔300的位置，导电通孔300到与该导电通孔300位于不同网络的金属层140的边缘的距离较小的区域，即为单张芯板100的精密区域130，如图5所示。值得说明的是，同一多层电路板的单张芯板100的精密区域130在堆叠之后相互覆盖，也就是说，上述精密区域130为多层电路板的精密区域130，是相对于同一个或者同一组的导电通孔300的精密区域130，因此，再将各个单张芯板100以精密区域130为对位标准时，才可以保证多层电路板的整体层偏较小。具体的实施例中，上述精密区域130可以为最精密区域131，即导电通孔300到与该导电通孔300位于不同网络的金属层140的边缘的距离最小的区域，保证该区域的对位精度，则可以提高整个多层电路板的层间对位精度。
步骤S102、将参考板的单张芯板安装至叠板机；
步骤S103、获取参考板的单张芯板的精密区域靶标的第一坐标与辅助靶标的第二坐标；
图8为本申请实施例中镜头与单张芯板的另一种配合示意图，如图8所示。上述叠板机(图中未示出)具有镜头400和与镜头400连接的控制器(图中未示出)，上述控制器可以控制镜头400对上述参考板的单张芯板100进行拍照，获取参考板的单张芯板100的表面形貌，并识别精密区域靶标150和辅助靶标160，计算得到上述精密区域靶标150的第一坐标与辅助靶标160的第二坐标。
步骤S104、将第N层单张芯板运送至叠板机，N≥2；
具体可以利用机械手将单张芯板运送至叠板机的工作台区域，具体可以搬运至参考板所在的区域。
步骤S105、获取第N层单张芯板的精密区域靶标的第三坐标和辅助靶标的第四坐标；
请继续参考图8，叠板机的控制器还可以控制镜头400对上述第N层单张芯板100进行拍照，获取第N层单张芯板100的表面形貌，并识别精密区域靶标150和辅助靶标160，计算得到上述精密区域靶标150的第三坐标与辅助靶标160的第四坐标。
步骤S106、将第N层单张芯板与第N-1层单张芯板叠置，使第三坐标与第一坐标之间的偏差不大于第一设定阈值A，且第四坐标与第二坐标之间的偏差不大于第二设定阈值B。
图9为本申请实施例中多层电路板的单张芯板的一种层叠示意图，如图所示，控制器控制机械手搬运单张芯板100运动，使第三坐标靠近第一坐标，且使第三坐标与第一坐标之间的偏差不大于第一设定阈值A，此外，使第四坐标靠近第二坐标，且使第四坐标与第二坐标之间的偏差不大于第二设定阈值B。从而认为第N层单张芯板100与参考板完成对位，将第N层单张芯板100与第N-1层单张芯板100叠置，从而完成第N层单张芯板100与第N-1层单张芯板100之间的叠置，依次类推，完成多层电路板的各个单张芯板100的对位，之后则可以进行压合，以将各层单张芯板100固定成多层电路板，再进行钻孔得后续工艺。
具体的实施例中，请继续参考图5，单张芯板100的精密区域130具有精密区域靶标150，辅助区域具有辅助靶标160。步骤S101具体通过在单张芯板100的设定表面的精密区域130制作精密区域靶标150，在辅助区域制作辅助靶标。则在后续步骤中实现层间对 位时，可以利用精密区域靶标150和辅助靶标作为对位基准。辅助区域可以位于单张芯板100的边缘或者次精密区域132。如图5所示的实施例中，辅助区域即位于单张芯板100的边缘，此外，图10为本申请实施例中单张芯板的另一种表面结构示意图，如图10所示，单张芯板100包括最精密区域131和次精密区域132，精密区域靶标150位于最精密区域131，辅助靶标160位于次精密区域132。上述次精密区域132指的是导电通孔300到单张芯板100的与该导电通孔300位于不同网络的金属层140的边缘距离仅小于上述最精密区域131的导电通孔300到与该导电通孔300位于不同网络的金属层140的边缘的距离的区域，该方案则除了可以保证最精密区域131的对位精度以外，还可以保证次精密区域132的对位精度，则多层电路板整体的层间对位精度较高。利用精密区域靶标150与辅助靶标160配合，则可以提高多层电路板的层间对位精度。
对于上述精密区域靶标和辅助靶标，可以在相应位置制作额外的靶标；或者，可以根据单张芯板的设定表面的图形，选择合适的图案的图形作为靶标。也就是说可以在单张芯板的设定表面的精密区域定义精密区域靶标，在单张芯板的辅助区域定义辅助靶标。即无需制作单张芯板以外的结构，利用其自身结构来选择合适的图形作为靶标即可。该方案减少了制备靶标的工艺流程，有利于提高工艺效率。
具体的，在设计上述第一设定阈值A与第二设定阈值B时，可以使第一设定阈值A与第二设定阈值B满足：A≤B，即在进行层间对位时，需要优先保证精密区域130的对位精度多层电路板的多个单张芯板100叠压时，层间对位精度要求最高的区域为精密区域130。本申请技术方案中，通过在精密区域130制作或定义靶标，利用精密区域130的靶标进行层间对位，因此可以保证精密区域130的对位精度，从而有利于提高整个多层电路板的层间对位精度，减少整体层偏，提高多层电路板的出线密度，有利于实现多层电路板的小型化。具体应用上述多层电路板的单张芯板100对位方法对多层电路板进行单张芯板100对位时，例如，对于高密的BGA(Ball Grid Array，焊球阵列封装)的多层电路板，以单张芯板100的涨缩量为50μm为例，采用本申请技术方案可以使整体层偏收益13μm。
单张芯板100的实际结构中，单张芯板100的两个表面的金属层140的图案不同，因此步骤S101时，可以计算两个表面的每个导电通孔300到与该导电通孔300位于不同网络的金属层140的边缘的距离，选取距离更小的作为对位用的精密区域130，该对位用的精密区域130所在的表面作为对位用的设定表面。图11为本申请实施例中单张芯板100的一种截面结构示意图，如图11所示，单张芯板100包括两个表面，上述两个表面分别为第一表面170和第二表面180。结合图6、图7a和图7b，已知多层电路板的精密区域130所在的位置，则每个单张芯板100也具有与之对应的精密区域130，计算每个单张芯板100上述第一表面170的精密区域130的导电通孔300到与该导电通孔300位于不同网络的金属层140的边缘的距离中的第一最小距离，也就是说计算第一表面170的精密区域130的导电通孔300到与该导电通孔300位于不同网络的金属层140的边缘的每个距离，将上述所有距离进行对比，选取最小值的距离为第一最小距离；以同样的方法，可以计算第二表面180的精密区域130的导电通孔300到与该导电通孔300位于不同网络的金属层140的边缘的距离中的第二最小距离。对比上述第一最小距离和第二最小距离，当第一最小距离小于第二最小距离时，第一表面170为设定表面，即以第一表面170的精密区域130设定的精密区域靶标150作为对位标准。当然，当第一最小距离大于第二最小距离时，第二表面180为设定表面，即以第二表面180的精密区域130设定的精密区域靶标150作为对位 标准。
图12为本申请实施例中镜头与单张芯板的另一种配合示意图，如图12所示，在执行步骤S104和S106时，叠板机在单张芯板100的两个表面侧均设置有镜头400，则位于设定表面所在一侧的表面可以获取对应的精密区域靶标150以及辅助靶标160的坐标，以用于实现对位操作。图13为本申请实施例中多层电路板的单张芯板另一种层叠示意图，如图13所示，第1层单张芯板100至第5层单张芯板100的上表面为设定表面，在上表面的精密区域130制作精密区域靶标150来作为对位基准，第6层单张芯板100至第9层单张芯板100的下表面为设定表面，在下表面的精密区域130制作精密区域靶标150来作为对位基准。
该方案中，考虑到每款多层电路板的单张芯板100的设计不同，可以考虑单张芯板100的两侧表面的实际布局情况，选择更为精密的一侧表面作为对位参与层来进行对位，可以优先保证更精密位置的层偏更佳，多层电路板的出线密度更高，产品的小型化程度也得到进一步的提升。具体的，多层电路板的整体层偏可以收益20～40μm，即导电通孔300到与该导电通孔300位于不同网络的金属层140的边缘的距离设计可缩短20～40μm，可以在较大程度上提高多层电路板的密度。
当执行步骤S101时，即在计算两个表面的精密区域130的第一最小距离和第二最小距离时，可能存在第一最小距离等于第二最小距离的情况，此时可以认为第一表面170和第二表面180均为设定表面。则在执行步骤S102时，在两个表面均制作精密区域靶标150。在执行步骤S104和S106时，叠板机在单张芯板100的两个表面侧均设置有镜头400，控制器利用镜头400获取单张芯板100的第一表面170的精密区域靶标150的坐标以及第二表面180的精密区域靶标150的坐标，计算上述第一表面170的精密区域靶标150的坐标以及第二表面180的精密区域靶标150的坐标的拟合中心坐标，例如可以取上述第一表面170的精密区域靶标150的坐标以及第二表面180的精密区域靶标150的坐标的平均坐标；或者，控制器利用镜头400获取单张芯板100的第一表面170的图像以及第二表面180的图像，将两个图像叠置，计算两个表面的精密区域靶标150叠置之后的中心的坐标作为拟合中心坐标。上述第一坐标为对应单张芯板100的拟合中心坐标，第三坐标也为对应单张芯板100的拟合中心坐标，用来进行对位操作。图14为本申请实施例中多层电路板的单张芯板另一种层叠示意图，如图14所示，每个单张芯板100的两侧表面均具有精密区域靶标150和辅助靶标160，利用拟合中心坐标进行对位。
一种技术方案中，可以使参考板为第N-1层单张芯板100，也就是说第N层单张芯板100对位时，需要先获取已经对位层叠的第N-1层单张芯板100的第一坐标和第二坐标，再使第N层单张芯板100的第三坐标和第四坐标与第N-1层单张芯板100的第一坐标和第二坐标进行对位，以实现多层电路板的单张芯板100的对位。该方案可以保证相邻层的精密区域130对位较为精准，可以防止第1层单张芯板100在叠板机出现移位时，导致之后对位的单张芯板100的偏差较大，该方案可以每次较好的防止第1层单张芯板100出现移位等问题导致的层偏。
图15为本申请实施例中图多层电路板的单张芯板另一种层叠示意图，如图15所示，再一种技术方案中，以相邻层的相对一侧表面进行对位，即第N层单张芯板100朝向第N-1层单张芯板100的一侧表面的第三坐标和第四对标，与第N-1层单张芯板100朝向第N层的单张芯板100的一侧表面的第一坐标和第二坐标进行对位，从而可以保证相对的表 面的对位精度。该方案基于在单张芯板100的两侧表面制作精密区域靶标150以及辅助靶标160的方案的基础上，本申请对此过程不进行赘述。
图16为本申请实施例中多层电路板的局部截面放大图，如图16所示，单张芯板的金属层140包括走线142和铜片141，其中，两层铜片141可以屏蔽两层铜片141之间的走线142的信号，减少不同层的单张芯板的走线142出现串扰的情况。此外，上述铜片141相对于走线142的边缘需要延伸设定距离X，以防止走线142的信号传递至导电通孔300。考虑到多层电路板的单张芯板100在对位时可能存在的层偏，通常需要设计上述铜片141相对于走线142的边缘延伸设计距离为Y，Y≥X，具体的，上述设计距离Y与设定距离X之间的差值为△＝Y-X，则Y＝X+△。其中，△的值很大程度上取决于多层电路板的层偏能力，本申请技术方案中的层偏能力较强，因此，△的值可以较小，因此，设计距离Y可以设计的较小，从而有利于提高多层电路板的密度。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (9)

  1. 一种多层电路板的单张芯板对位方法，其特征在于，包括：
    确定单张芯板的设定表面的精密区域和辅助区域，所述精密区域具有精密区域靶标，所述辅助区域具有辅助靶标；
    将参考板的所述单张芯板安装至叠板机；
    获取参考板的所述单张芯板的所述精密区域靶标的第一坐标与所述辅助靶标的第二坐标；
    将第N层所述单张芯板运送至所述叠板机，N≥2；
    获取第N层所述单张芯板的精密区域靶标的第三坐标和辅助靶标的第四坐标；
    将第N层所述单张芯板与第N-1层单张芯板叠置，使所述第三坐标与所述第一坐标之间的偏差不大于第一设定阈值A，且所述第四坐标与所述第二坐标之间的偏差不大于第二设定阈值B。
  2. 根据权利要求1所述的对位方法，其特征在于，所述精密区域为最精密区域，所述辅助区域包括单张芯板的边缘或者次精密区域。
  3. 根据权利要求2所述的对位方法，其特征在于，所述第一设定阈值A与第二设定阈值B满足：A≤B。
  4. 根据权利要求1～3任一项所述的对位方法，其特征在于，所述单张芯板的两个表面分别为第一表面和第二表面，计算所述第一表面的精密区域的导电通孔到与所述导电通孔位于不同网络的金属层的边缘的第一最小距离，所述第二表面的精密区域的导电通孔到与所述导电通孔位于不同网络的金属层的边缘的第二最小距离；
    当所述第一最小距离小于所述第二最小距离时，确定所述第一表面为设定表面；
    当所述第一最小距离大于所述第二最小距离时，确定所述第二表面为设定表面。
  5. 根据权利要求1～3任一项所述的对位方法，其特征在于，所述单张芯板的两个表面分别为第一表面和第二表面，计算所述第一表面的精密区域的导电通孔到与所述导电通孔位于不同网络的金属层的边缘的第一最小距离，所述第二表面的精密区域的导电通孔到与所述导电通孔位于不同网络的金属层的边缘的第二最小距离；
    当所述第一最小距离等于所述第二最小距离时，所述第一表面和所述第二表面都为设定表面；
    所述第一坐标和所述第三坐标为所在单张芯板的所述第一表面的精密区域靶标与所述第二表面的精密区域靶标的拟合中心坐标。
  6. 根据权利要求1～5任一项所述的对位方法，其特征在于，对于第N层所述单张芯板，所述参考板的所述单张芯板为第N-1层所述单张芯板。
  7. 根据权利要求6所述的对位方法，其特征在于，所述第一坐标和所述第二坐标位于所述第N-1层所述单张芯板朝向所述第N层所述单张芯板的一侧表面；所述第三坐标和所述第四坐标位于所述第N层所述单张芯板朝向所述第N-1层所述单张芯板的一侧表面。
  8. 根据权利要求1～7任一项所述的对位方法，其特征在于，所述确定单张芯板的设定表面的精密区域和辅助区域，所述单张芯板的设定表面的精密区域具有精密区域靶标，单张芯板的辅助区域具有辅助区域靶标，具体包括：
    在所述单张芯板的所述设定表面的所述精密区域制作精密区域靶标，在单张芯板的辅 助区域制作辅助靶标。
  9. 根据权利要求1～7任一项所述的对位方法，其特征在于，所述确定单张芯板的设定表面的精密区域和辅助区域，所述单张芯板的设定表面的精密区域具有精密区域靶标，单张芯板的辅助区域具有辅助区域靶标，具体包括：
    在所述单张芯板的所述设定表面的所述精密区域定义精密区域靶标，在所述单张芯板的辅助区域定义辅助靶标。
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