WO2022127512A1 - 高电子迁移率晶体管、制备方法、功率放大/开关器 - Google Patents

高电子迁移率晶体管、制备方法、功率放大/开关器 Download PDF

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WO2022127512A1
WO2022127512A1 PCT/CN2021/131765 CN2021131765W WO2022127512A1 WO 2022127512 A1 WO2022127512 A1 WO 2022127512A1 CN 2021131765 W CN2021131765 W CN 2021131765W WO 2022127512 A1 WO2022127512 A1 WO 2022127512A1
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layer
algan barrier
barrier layer
equal
hole
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PCT/CN2021/131765
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French (fr)
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姜腾
吴小祥
谭斯克
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华为技术有限公司
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Priority to EP21905441.8A priority Critical patent/EP4254507A4/en
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Priority to US18/336,060 priority patent/US20230352558A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present application relates to a high-electron-mobility transistor (HEMT), a preparation method thereof, a power amplifier and a power switch using the same.
  • HEMT high-electron-mobility transistor
  • GaN gallium nitride
  • 2DEG two-dimensional electron gas
  • GaN-based HEMT is a three-terminal device, and its source and drain are made of metal electrodes by ohmic contact (metal-semiconductor contact) process to realize the grounding function of the signal and the output function of the signal.
  • ohmic contact metal-semiconductor contact
  • the quality of ohmic contact performance will not only directly affect the key performance indicators such as the saturated output current, on-resistance, and breakdown voltage of the device, but also affect the performance and reliability of the device in high frequency and high temperature application scenarios.
  • a first aspect of the embodiments of the present application provides a high electron mobility transistor, which includes a substrate and a nucleation layer, a buffer layer, a GaN channel layer, and an AlGaN barrier layer sequentially stacked on the substrate.
  • the AlGaN barrier layer is provided with two through holes spaced apart from each other, each through hole penetrates the AlGaN barrier layer along the thickness direction of the AlGaN barrier layer, and the hole wall of each through hole has at least one level
  • each through hole has an upper opening away from the substrate and a lower opening close to the substrate, and the opening area of the upper opening is larger than the opening area of the lower opening.
  • the high electron mobility transistor further includes a source electrode and a drain electrode. The source electrode and the drain electrode respectively fill a through hole and directly contact and connect the GaN channel layer.
  • the ohmic metal material (the metal material of the source and the drain) and the AlGaN barrier layer are formed by designing a stepped structure on the hole wall of the through hole where the source and the drain are arranged. contact, which increases the contact area between the ohmic metal material and the AlGaN barrier, affects the shape of the barrier, thereby increasing the possibility of forming a tunneling current, reducing the ohmic contact resistance, and improving the GaN-based high electron mobility transistor. performance.
  • each through hole includes at least two hole portions that are connected in sequence along the thickness direction of the AlGaN barrier layer, and are located along the thickness direction of the AlGaN barrier layer and are directed toward the substrate.
  • the opening areas of the at least two hole portions are reduced one by one.
  • the above structure of the through hole ensures that along the thickness direction of the AlGaN barrier layer and the direction toward the substrate, the hole wall of the through hole has at least one step structure and the through hole gradually becomes smaller.
  • both the source electrode and the drain electrode are relatively protruded from the surface of the AlGaN barrier layer away from the substrate; and the source electrode and the drain electrode both extend into the GaN channel layer middle.
  • the source electrode and the drain electrode protrude from the surface of the AlGaN barrier layer away from the substrate, so as to facilitate subsequent electrical connection with the signal line.
  • the source electrode and the drain electrode respectively include a Ti layer, an Al layer, a metal isolation layer, and an Au layer sequentially attached to the hole wall of the through hole, and the material of the metal isolation layer is selected from At least one of Ni, Pt, Cr, Pd, and Mo metals.
  • the Ti layer undergoes a solid-phase chemical reaction with the GaN channel layer and the AlGaN barrier layer to form TiN;
  • the Al layer mainly acts as a catalyst to promote the solid-phase chemical reaction between nitrogen atoms and Ti, and should be able to form a low success function with Ti.
  • the dense alloy; Ti and Al are easy to form insulating oxides and hydroxides, so the Au layer needs to be added; and the metal isolation layer is used to block the mutual diffusion of the Au layer and the Al layer.
  • the thickness of the Ti layer is greater than or equal to 10 nm and less than or equal to 30 nm
  • the thickness of the Al layer is greater than or equal to 100 nm and less than or equal to 200 nm
  • the thickness of the metal isolation layer is greater than or equal to 200 nm.
  • the thickness of the Au layer is 30 nm or less and 60 nm or less
  • the thickness of the Au layer is 50 nm or more and 100 nm or less.
  • the high electron mobility transistor further includes a nucleation layer and a buffer layer sequentially stacked on the substrate; the nucleation layer is located between the substrate and the buffer layer; The buffer layer is located between the nucleation layer and the GaN channel layer.
  • the material of the nucleation layer is AlN, and the thickness of the nucleation layer is greater than or equal to 0.1 nm and less than or equal to 500 nm.
  • the purpose of disposing the nucleation layer is to provide a flat nucleation surface for the growth of the GaN epitaxial layer (including the buffer layer, the GaN channel layer and the AlGaN barrier layer) formed on the nucleation layer subsequently, and to reduce the contact for nucleation growth. angle, so that the GaN epitaxial layer is grown to form a flat film.
  • the material of the buffer layer is graded AlGaN or GaN/AlN superlattice; the content of Al in the graded AlGaN gradually increases along the direction of approaching the substrate; the thickness of the buffer layer is greater than or equal to 0.1 ⁇ m and less than or equal to 10 ⁇ m.
  • the provision of the buffer layer can buffer stress in the high electron mobility transistor.
  • the thickness of the GaN channel layer is greater than or equal to 0.1 ⁇ m and less than or equal to 10 ⁇ m, and the thickness of the AlGaN barrier layer is greater than or equal to 0.1 nm and less than or equal to 50 nm.
  • the thicknesses of the GaN channel layer and the AlGaN barrier layer By reasonably designing the thicknesses of the GaN channel layer and the AlGaN barrier layer, good performance of the high electron mobility transistor is ensured.
  • a second aspect of the embodiments of the present application provides a method for fabricating a high electron mobility transistor, including the following steps.
  • a substrate is provided on which a GaN channel layer and an AlGaN barrier layer are sequentially formed.
  • Two through holes are opened in the AlGaN barrier layer and are spaced apart from each other through the AlGaN barrier layer.
  • An upper opening and a lower opening close to the substrate, and the opening area of the upper opening is larger than the opening area of the lower opening.
  • a metal material is filled in each through hole to form a direct contact connection to the source electrode and the drain electrode of the GaN channel layer, respectively.
  • the preparation method of the GaN-based HEMT can realize the AlGaN barrier layer through multiple cycles of etching, realize the stepped structure of the through hole, form a multi-step contact between the ohmic contact metal and the barrier region, reduce the ohmic contact resistance, and improve the Performance of GaN-based HEMT devices.
  • forming the through hole includes the following steps.
  • a patterned photoresist layer is formed on the AlGaN barrier layer, so that the photoresist layer partially covers the upper surface of the AlGaN barrier layer away from the substrate, and the photoresist layer is not covered by the photoresist layer.
  • the area on the upper surface is the source-drain window area.
  • the AlGaN barrier layer is etched from the source-drain window region by dry etching, and the etching depth is less than the thickness of the AlGaN barrier layer. Parts of the photoresist layer surrounding the source-drain window area are partially removed to increase the source-drain window area.
  • the AlGaN barrier layer is further etched using dry etching from the increased source-drain window region to etch through the AlGaN barrier layer.
  • the wall of the via hole has a one-level stepped structure and the via hole is gradually reduced in size.
  • forming the through hole includes the following steps.
  • a patterned photoresist layer is formed on the AlGaN barrier layer, so that the photoresist layer partially covers the upper surface of the AlGaN barrier layer away from the substrate, and is not covered by the photoresist layer
  • the area of the upper surface is the source-drain window area.
  • the AlGaN barrier layer is etched from the source-drain window region by dry etching, and the etching depth is less than the thickness of the AlGaN barrier layer; the part of the photoresist layer surrounding the source-drain window region is partially removed to increase the source-drain window area.
  • the AlGaN barrier layer is further etched from the increased source-drain window region using dry etching and is not etched through the AlGaN barrier layer.
  • the steps of partially removing the part of the photoresist layer surrounding the source-drain opening region and the step of dry etching the AlGaN barrier layer are repeated at least once as described above until the AlGaN barrier layer is etched through.
  • the hole wall of the via hole has at least two-level stepped structure and the via hole is gradually reduced in size.
  • the dry etching uses a mixed gas of Cl 2 and BCl 3 as the etching gas; and the partial removal of the photoresist layer uses O 2 as the etching gas.
  • the etching gas By selecting the etching gas, the etching effect of the AlGaN barrier layer and the photoresist layer is guaranteed; the wall of the through hole has at least one step structure and the through hole becomes smaller step by step.
  • the preparation method further includes: after forming the through hole and before forming the source electrode and the drain electrode, using a wet method or plasma treatment on the hole wall of the through hole to remove all the holes. impurities on the hole wall of the through hole and roughening the hole wall of the through hole.
  • This step facilitates subsequent deposition of metal materials of the source and drain electrodes in the through hole, and improves the bonding strength of the metal material and the hole wall of the through hole.
  • the step of forming the source electrode and the drain electrode includes: sequentially depositing and forming a Ti layer, an Al layer, a metal isolation layer, and an Au layer on the hole wall of the through hole, and the metal isolation layer is formed.
  • the material of the layer is selected from at least one of Ni, Pt, Cr, Pd, and Mo metals; the deposited Ti layer, Al layer, metal isolation layer, and Au layer are annealed.
  • the Ti layer undergoes a solid-phase chemical reaction with the GaN channel layer and the AlGaN barrier layer to form TiN;
  • the Al layer mainly acts as a catalyst to promote the solid-phase chemical reaction between nitrogen atoms and Ti, and should be able to form a low success function with Ti.
  • the dense alloy; Ti and Al are easy to form insulating oxides and hydroxides, so the Au layer needs to be added; and the metal isolation layer is used to block the mutual diffusion of the Au layer and the Al layer.
  • the thickness of the Ti layer is greater than or equal to 10 nm and less than or equal to 30 nm
  • the thickness of the Al layer is greater than or equal to 100 nm and less than or equal to 200 nm
  • the thickness of the metal isolation layer is greater than or equal to 30 nm and less than or equal to 60 nm
  • the thickness of the Au layer is greater than or equal to 50 nm and less than or equal to 100 nm.
  • the annealing temperature of the annealing treatment is greater than or equal to 500°C and less than or equal to 800°C.
  • the source electrode and the drain electrode are made of annealed multi-layer metal material, which is beneficial to reduce contact resistance.
  • the preparation method further includes forming a stacked nucleation layer and a buffer layer on the substrate in sequence before forming the GaN channel layer and the AlGaN barrier layer; the nucleation layer A layer is located between the substrate and the buffer layer; the buffer layer is located between the nucleation layer and the GaN channel layer.
  • the purpose of disposing the nucleation layer is to provide a flat nucleation surface for the growth of the GaN epitaxial layer (including the buffer layer, the GaN channel layer and the AlGaN barrier layer) formed on the nucleation layer subsequently, and to reduce the contact for nucleation growth. angle, the GaN epitaxial layer is grown to form a flat film layer; the buffer layer can buffer the stress in the high electron mobility transistor.
  • a third aspect of the embodiments of the present application provides a power amplifier using the above-mentioned high electron mobility transistor.
  • the GaN-based high electron mobility transistor forms a good ohmic contact, which improves the performance of the GaN-based high electron mobility transistor. It can be used in power amplifiers in RF front-end modules, as well as microwave and Millimeter wave power amplifier.
  • a fourth aspect of the embodiments of the present application provides a power switch using the above-mentioned high electron mobility transistor.
  • GaN-based high electron mobility transistor of the present application will further reduce the on-resistance of the switching device and improve the switching efficiency of the device.
  • FIG. 1 is a schematic cross-sectional structure diagram of a HEMT according to Embodiment 1 of the present application.
  • FIG. 2 is a schematic cross-sectional structure diagram of the HEMT according to the second embodiment of the present application.
  • FIG. 3 is a flow chart of the preparation method of the HEMT of the present application.
  • FIG. 4 is a schematic diagram 1 of the preparation process of the HEMT of the present application.
  • FIG. 5 is a schematic diagram 2 of the preparation process of the HEMT of the present application.
  • FIG. 6 is a schematic diagram 3 of the preparation process of the HEMT of the present application.
  • FIG. 7 is a schematic diagram 4 of the preparation process of the HEMT of the present application.
  • FIG. 8 is a schematic diagram 5 of the preparation process of the HEMT of the present application.
  • FIG. 9 is a schematic diagram 6 of the preparation process of the HEMT of the present application.
  • FIG. 10 is a schematic diagram 7 of the preparation process of the HEMT of the present application.
  • FIG. 11 is a schematic diagram 8 of the preparation process of the HEMT of the present application.
  • FIG. 12 is a partial circuit diagram of a power amplifier to which the HEMT of the present application is applied.
  • FIG. 13 is a circuit diagram of a power switch to which the HEMT of the present application is applied.
  • HEMT 100, 200; Substrate: 10; Nucleation layer: 20; Buffer layer: 30; GaN channel layer: 40; AlGaN barrier layer: 50; Hole: 513; Upper opening: 512; Lower opening: 514; Upper surface: 52; Source: 60; Drain: 70; Ti layer: 61; Al layer: 62; Metal isolation layer: 63; Au layer: 64 ; Gate: 80; Photoresist layer: 90; Source-drain windowed area: 91; Compensator: 310; Input matching network: 330; Resistor: 350;
  • the key technology of 5G a large number of array antennas are used in base station transceivers.
  • This array antenna structure includes corresponding radio frequency transceiver units.
  • the high output power, linearity and power consumption requirements also promote the deployment of base stations.
  • the power amplifier is converted from LDMOS to GaN-based HEMT. Taking advantage of the small size and high power density of GaN-based HEMTs can realize highly integrated product solutions, such as modular RF front-end devices.
  • AlGaN in the AlGaN/GaN heterojunction HEMT structure has a large forbidden band width, and no suitable single metal material can directly form an ohmic contact with it with a small contact resistance.
  • the commonly used method in the industry is to use magnetron sputtering or electron beam evaporated metal Ti, and then anneal it to form an alloy effect with AlGaN, so that the contact resistance is reduced by increasing the probability of electron tunneling.
  • the optimization and improvement of the ohmic contact process of AlGaN/GaN heterojunction HEMTs also poses greater challenges to reduce ohmic contact resistance. To further reduce the series resistance, reduce parasitic effects, and improve the amplification capability and efficiency of the device is an important direction for the research of RF and power AlGaN/GaN heterojunction HEMT devices.
  • the present application provides a GaN-based HEMT, which can effectively reduce the ohmic contact resistance and improve the performance of the GaN-based HEMT device.
  • the GaN-based HEMTs of the present application can be applied to microwave and millimeter-wave power amplifiers for communications, instrumentation, military applications, etc., including but not limited to monolithic microwave integrated circuits (MMICs), radio frequency front-end modules, and the like.
  • MMICs monolithic microwave integrated circuits
  • radio frequency front-end modules and the like.
  • the GaN-based HEMT of the present application can be applied to low-voltage GaN-based HEMT power switching devices in the field of fast charging in terminal products such as mobile phones and tablets, in addition to the field of low-voltage GaN-based HEMT power amplifier devices in the radio frequency field. Since the operating voltage in this field is low, the breakdown voltage of the device is not high. Therefore, the use of the GaN-based HEMT of the present application will further reduce the on-resistance of the switching device and improve the switching efficiency of the device.
  • the HEMT 100 includes a substrate 10 and a GaN channel layer 40 and an AlGaN barrier layer 50 sequentially stacked on the substrate 10 .
  • the AlGaN barrier layer 50 is provided with two through holes 51 spaced apart from each other, each through hole 51 penetrates the AlGaN barrier layer 50 along the thickness direction of the AlGaN barrier layer 50
  • the hole wall has a one-level stepped structure.
  • Each through hole 51 has an upper opening 512 away from the substrate 10 and a lower opening 514 close to the substrate 10 , and the upper opening 512 is larger than the lower opening 514 .
  • the HEMT 100 further includes a source electrode 60 and a drain electrode 70 disposed on the upper surface 52 of the AlGaN barrier layer 50 away from the substrate 10 .
  • the source electrode 60 and the drain electrode 70 are spaced apart from each other, respectively fill a through hole 51 and directly contact and connect the GaN channel layer 40 . Both the source electrode 60 and the drain electrode 70 relatively protrude from the upper surface 52 of the AlGaN barrier layer 50 .
  • the through hole 51 has a first-level stepped structure, and the through hole 51 includes a first hole portion 511 and a second hole portion 513 that communicate with each other along the thickness direction of the AlGaN barrier layer 50 , wherein The second hole portion 513 is closer to the GaN channel layer 40 than the first hole portion 511 , and the opening area of the first hole portion 511 is larger than that of the second hole portion 513 .
  • the through hole 51 also extends into the GaN channel layer 40 after penetrating the AlGaN barrier layer 50 , that is, the source electrode 60 and the drain electrode 70 are further inserted into the GaN channel layer 40 .
  • the HEMT 100 further includes a nucleation layer 20 and a buffer layer 30 sequentially stacked on the substrate 10 ; the nucleation layer 20 is located between the substrate 10 and the buffer layer 30 ; The buffer layer 30 is located between the nucleation layer 20 and the GaN channel layer 40 .
  • the HEMT 200 shown in FIG. 2 is basically the same as the HEMT 100 shown in FIG. 1 , except that the through hole 51 of the HEMT 200 has a two-stage stepped structure.
  • each of the through holes 51 includes three holes (not shown) that are connected in sequence along the thickness direction of the AlGaN barrier layer 50 , and are directed along the thickness direction of the AlGaN barrier layer 50 and are directed to the liner The openings of the three holes in the direction of the bottom 10 decrease one by one.
  • the hole wall of the through hole 51 of the HEMT of the present application is not limited to have one-level steps or two-level steps, as long as it has one or more steps.
  • each through hole 51 includes at least two hole portions (not shown in the figure) that are connected in sequence along the thickness direction of the AlGaN barrier layer 50 , and along the AlGaN barrier layer 50 The openings of the at least two holes in the thickness direction and the direction toward the substrate 10 are gradually reduced; and the source electrode 60 and the drain electrode 70 are respectively thinner.
  • the AlGaN barrier layer 50 is used to match the GaN channel layer 40 and generate a two-dimensional electron gas (2DEG) through polarization in a region where the GaN channel layer 40 and the AlGaN barrier layer 50 meet. thereby conducting current. If the movement of electrons in a three-dimensional solid is blocked (restricted) in one direction (such as the z direction), the electrons can only move freely in the other two directions (x, y directions). Free electrons are called 2DEGs.
  • the source electrode 60 and the drain electrode 70 are used to make the 2DEG flow in the channel layer between the source electrode 60 and the drain electrode 70 under the effect of the electric field. Conduction occurs at the two-dimensional electron gas in the channel layer.
  • the metal material (ohmic contact metal) of the source electrode 60 and the drain electrode 70 is in contact with both the AlGaN barrier layer 50 and the GaN channel layer 40, and the ohmic contact metal and the barrier layer are in stepped contact, which The stepped contact structure makes the 2DEG form surface contact with the AlGaN barrier layer 50 and form line contact with the GaN channel layer 40.
  • This double contact mode further increases the tunneling probability of the 2DEG to the metal layer, thereby reducing the interface resistance. . It needs to be explained that since electrons exist in the GaN channel layer in the form of 2DEG, the thickness of electron transport in the GaN channel layer can be ignored.
  • the GaN channel Electrons in the layer enter directly from this region into the metal of source 60 and drain 70, defined as line contacts. It also needs to be explained that in the area where the ohmic contact metal is in contact with the AlGaN barrier layer 50 , the 2DEG enters the metal of the source electrode 60 and the drain electrode 70 from the GaN channel layer 40 through the AlGaN barrier layer 50 under the action of the electric field. , since the entire area is covered with metal, electrons can be transported over the entire area, which is defined as surface contact.
  • the source electrode 60 and the drain electrode 70 are arranged by designing the stepped through hole 51, so that the local area of the AlGaN barrier layer 50 is partially etched and does not penetrate the thickness direction of the AlGaN barrier layer 50, while the local area is completely etched Etch through the thickness direction of the AlGaN barrier layer 50, maintain the high concentration of two-dimensional electron gas in the channel by partially etching the AlGaN barrier layer 50 in the region, and completely etch the metal material in the region to contact the 2DEG line, reducing the Ohmic contact resistance.
  • the stepped side of the partially etched region of the AlGaN barrier layer 50 increases the contact area between the ohmic metal material and the AlGaN barrier, affects the shape of the barrier, and increases the possibility of forming a tunneling current, so it can be reduced Ohmic contact resistance.
  • the distance from the metal to the 2DEG in the partially etched area is reduced, thereby reducing the ohmic contact resistance.
  • the source electrode 60 and the drain electrode 70 respectively include a Ti layer 61 , an Al layer 62 , a metal isolation layer 63 , and an Au layer 64 , because during the process of preparing the source electrode 60 and the drain electrode 70 , Ti, Al, metal isolation material, and Au are sequentially deposited on the hole wall of the through hole 51 by physical vapor deposition, so the Ti layer 61, the Al layer 62, the metal isolation layer 63, and the Au layer 64 are sequentially attached to the on the hole wall of the through hole 51 .
  • the thickness of the Ti layer 61 is greater than or equal to 10 nm and less than or equal to 30 nm
  • the thickness of the Al layer 62 is greater than or equal to 100 nm and less than or equal to 200 nm
  • the thickness of the metal isolation layer 63 is greater than or equal to 30 nm and less than or equal to 30 nm. equal to 60 nm
  • the thickness of the Au layer 64 is greater than or equal to 50 nm and less than or equal to 100 nm.
  • FIG. 1 and FIG. 2 respectively show two different structures of the source electrode 60 and the drain electrode 70 due to the different steps of the through hole 51 .
  • the main purpose of setting the Ti layer 61 is to have a solid-phase chemical reaction with the GaN channel layer 40 and the AlGaN barrier layer 50 during the annealing process to form TiN, and at the same time, a high density of nitrogen vacancies is left in the GaN channel layer 40 to play
  • the shallow donor effect is favorable for the formation of ohmic contacts.
  • the Al layer 62 mainly acts as a catalyst to promote the solid-phase chemical reaction between nitrogen atoms and Ti, and the Al in the Al layer 62 can form a dense alloy with a low work function with Ti.
  • work function also known as work function, work function, the English name is Work function
  • work function refers to the minimum energy (usually in electron volts) that must be provided to make an electron escape from the solid surface immediately. unit).
  • intermediately here means that the final electron position is away from the surface on the atomic scale but still close to the solid on the macroscopic scale.
  • both Ti and Al are easy to form insulating oxides and hydroxides, so to add a cap layer, chemically stable Au is generally used; while Au and Al are prone to interdiffusion and reach the surface of the GaN channel layer 40 material , it is not conducive to forming a good ohmic contact, and a metal isolation layer 63 needs to be added to block the mutual diffusion of the Au layer 64 and the Al layer 62 .
  • the material of the metal isolation layer 63 is selected from at least one of Ni, Pt, Cr, Pd, and Mo metals. In this embodiment, the material of the metal isolation layer 63 is Ni.
  • Ti/Al/Ni/Au is a commonly used metal system for ohmic contact of GaN-based materials.
  • the substrate 10 can be a high-resistance silicon (Si) substrate or a silicon carbide (SiC) substrate.
  • the material of the nucleation layer 20 may be one or more of aluminum nitride (AlN), gallium nitride (GaN) and aluminum gallium nitride (AlGaN).
  • AlN aluminum nitride
  • GaN gallium nitride
  • AlGaN aluminum gallium nitride
  • the material of the nucleation layer 20 can be aluminum nitride, gallium nitride or aluminum gallium nitride
  • the material of the nucleation layer 20 can be any two of aluminum nitride, gallium nitride and aluminum gallium nitride
  • the material of the nucleation layer 20 can also be made of aluminum nitride, gallium nitride and aluminum gallium nitride.
  • the material of the nucleation layer 20 is AlN, and the thickness is 0.1 nm ⁇ 500 nm.
  • the function of the nucleation layer 20 is to provide a flat nucleation surface for the growth of the GaN epitaxial layer (including the buffer layer 30, the GaN channel layer 40 and the AlGaN barrier layer 50) formed on the nucleation layer 20 subsequently, reducing The contact angle of its nucleation growth enables the growth of the buffer layer 30 , the GaN channel layer 40 and the AlGaN barrier layer 50 to form a flat film layer.
  • the material of the buffer layer 30 is graded AlGaN or GaN/AlN superlattice (the superlattice material is two different components grown alternately in thin layers of several nanometers to several tens of nanometers and kept strictly periodic multilayer films).
  • the thickness of the buffer layer 30 is 0.1 ⁇ m ⁇ 10 ⁇ m.
  • Graded AlGaN means that the content of Al in the buffer layer 30 increases gradually along the direction of approaching the substrate 10 .
  • the buffer layer 30 is used for stress buffering of the HEMT 100 .
  • the thickness of the GaN channel layer 40 is 0.1 ⁇ m ⁇ 10 ⁇ m
  • the thickness of the AlGaN barrier layer 50 is 0.1 nm ⁇ 50 nm.
  • the HEMT 100 further includes a gate 80 whose orthographic projection on the substrate 10 is located between the source 60 and the drain 70 for allowing or blocking the passage of 2DEG.
  • the gate 80 is made of conductive metal material, for example, the gate 80 includes a Ni layer (not shown) and an Au layer (not shown) stacked on the upper surface 52 .
  • the gate 80 is located on the upper surface 52 of the AlGaN barrier layer 50 away from the substrate 10 . It can be understood that the position of the gate 80 is not limited to being disposed on the upper surface 52 of the AlGaN barrier layer 50 , and can also be disposed at other positions as required.
  • the HEMTs 100 and 200 may also include other layers (not shown).
  • the thickness range values listed for each layer herein are inclusive.
  • the preparation method of the HEMTs 100 and 200 includes the following steps (the following steps can be understood in conjunction with FIGS. 4 to 11 ).
  • Two through holes 51 are formed in the AlGaN barrier layer 50 penetrating the AlGaN barrier layer 50 and spaced apart from each other, the hole wall of each through hole has at least one step structure, and each through hole has a distance from The upper opening 512 of the substrate and the lower opening 514 close to the substrate, and the opening area of the upper opening is larger than the opening area of the lower opening;
  • the nucleation layer 20 , the buffer layer 30 , the GaN channel layer 40 and the AlGaN barrier layer 50 can adopt metal-organic chemical vapor deposition (Metal-organic Chemical Vapor Deposition, MOCVD) or molecular beam epitaxy (Molecular Beam Epitaxy, MBE) method is sequentially formed on the substrate 10 .
  • MOCVD Metal-organic Chemical Vapor Deposition
  • MBE molecular beam epitaxy
  • the thickness of the nucleation layer 20 is 0.1 nm to 500 nm
  • the thickness of the buffer layer 30 is 0.1 ⁇ m to 10 ⁇ m
  • the thickness of the GaN channel layer 40 is 0.1 ⁇ m to 10 ⁇ m
  • the thickness of the barrier layer 50 is 0.1 nm to 50 nm.
  • the opening of the through hole 51 is realized by etching the AlGaN barrier layer 50 at least twice in stages.
  • the steps of forming the through hole 51 include:
  • a patterned photoresist layer 90 is formed on the AlGaN barrier layer 50 , so that the photoresist layer 90 partially covers the AlGaN barrier layer 50 away from the substrate 10 .
  • the surface 52, the area of the upper surface 52 not covered by the photoresist layer 90 is the source-drain window area 91;
  • dry etching is used to etch the AlGaN barrier layer 50 from the source-drain window region 91, and the etching depth is less than the thickness of the AlGaN barrier layer 50;
  • the AlGaN barrier layer 50 is further etched from the increased source-drain window region 91 by dry etching, and the AlGaN barrier layer 50 is not etched through; each dry etching of AlGaN
  • the area of the barrier layer 50 (corresponding to the source-drain window region 91 ) is etched down to approximately the same depth, so that some parts of the AlGaN barrier layer 50 are dry-etched twice, and some areas are dry-etched once , the etching depth of the two regions is different, so that the etching surface is stepped;
  • the steps of partially removing the part of the photoresist layer 90 surrounding the source-drain window region 91 and the step of dry etching the AlGaN barrier layer 50 are repeated once respectively, Until the through hole 51 is obtained by etching through the AlGaN barrier layer 50, the hole wall of the through hole 51 is obtained in a stepped shape;
  • the remaining photoresist layer 90 is removed.
  • the number of steps of the stepped structure of the through hole 51 can be controlled by the steps of partially removing the photoresist layer 90 surrounding the source-drain window region 91 and dry etching the AlGaN barrier layer.
  • the number of steps of 50 is achieved.
  • the steps of forming the through hole 51 are basically similar to the above steps, but only need to dry-etch the AlGaN barrier layer 50 twice to etch through the
  • the AlGaN barrier layer 50 specifically includes:
  • a patterned photoresist layer 90 is formed on the AlGaN barrier layer 50, so that the photoresist layer 90 partially covers the upper surface 52 of the AlGaN barrier layer 50 away from the substrate 10, and is not covered by any
  • the area of the upper surface 52 covered by the photoresist layer 90 is the source-drain window area 91;
  • the AlGaN barrier layer 50 is etched from the source-drain window region 91 by dry etching, and the etching depth is less than the thickness of the AlGaN barrier layer 50;
  • the AlGaN barrier layer 50 is further etched by dry etching from the increased source-drain window region 91 to the through hole 51 obtained by etching through the AlGaN barrier layer 50; each dry etching of the AlGaN barrier layer 50 ( The area corresponding to the source-drain window area 91) is etched down to approximately the same depth, so that some parts of the AlGaN barrier layer 50 are dry-etched twice, some areas are dry-etched once, and the two areas are dry-etched once. The etching depth is different, so that the hole wall of the through hole 51 is stepped;
  • the remaining photoresist layer 90 is removed.
  • the etching depth of the first dry etching of the AlGaN barrier layer 50 may be half of the thickness of the AlGaN barrier layer 50 , but is not limited thereto.
  • the GaN channel layer 40 is also partially etched, but the GaN channel layer 40 is not penetrated.
  • the dry etching uses the mixed gas of Cl 2 and BCl 3 as the etching gas; the partial removal of the photoresist layer 90 uses O 2 for etching.
  • the stepped surface of the stepped structure is not limited to be perpendicular to the sidewall surface, and a certain inclination angle can also be set; in addition, the depth and width of each step of the through hole 51 can be adjusted by adjusting the etching parameters.
  • the specific process parameters for etching the through hole 51 are: in an ICP (Inductively Coupled Plasma) etcher, the AlGaN barrier layer 50 is first etched with a Cl 2 /BCl 3 mixed gas, and the etching depth is It is half the thickness of the AlGaN barrier layer 50, the ICP power is 30W, the radio frequency power is 100W, and the etching time is 2min ; then the vacuuming process is performed, and the remaining gas in the cavity is extracted for 1min; 90% of the etching, the ICP power is set to 50W, the lower electrode power is set to 0W, and the time is 3min; then the vacuuming process is performed for 1min, and the remaining O 2 is extracted; finally, the Cl 2 /BCl 3 mixed gas is introduced to etch through the AlGaN barrier layer 50 contact to the GaN layer.
  • ICP Inductively Coupled Plasma
  • a photoresist solvent such as N-methylpyrrolidone (NMP) can be used to remove the remaining photoresist layer 90 .
  • NMP N-methylpyrrolidone
  • the product is placed in NMP for ultrasonic cleaning for 10 minutes, then ultrasonically cleaned with alcohol for 5 minutes, and rinsed with deionized water for 1 minute.
  • the upper surface 52 of the AlGaN barrier layer 50 may also be cleaned to remove impurities and contamination on the upper surface 52 .
  • the cleaning method can be as follows: first, soak it in a HF solution with a concentration of 4 wt% for a certain period of time (for example, 10 seconds) to remove the surface oxide layer; The cleaning time of alcohol and deionized water can be 10min, 5min and 2mi respectively; finally drying to remove surface moisture, for example, baking on a 100°C hot stage for 5min.
  • the step of forming a partially covering photoresist layer 90 on the AlGaN barrier layer 50 may include: firstly forming a photoresist layer 90 completely covering the upper surface 52 on the upper surface 52 of the AlGaN barrier layer 50 Then, the photoresist layer 90 is exposed and developed to partially remove the photoresist layer 90 (patterning process).
  • the source-drain window area 91 includes a source window area and a drain window area spaced apart from each other.
  • the photoresist layer 90 may be formed by a coating method, which may specifically include: coating the upper surface 52 with a photoresist (AZ series No.
  • the coating speed is 4000 r/min and the time is 30 s to obtain a photoresist layer 90 with a thickness of 1.2 ⁇ m; and then it is cured by baking, for example, baking on a hot stage at 100° C. for 2 minutes.
  • the preparation method further includes: after the through hole 51 is formed and before the source electrode 60 and the drain electrode 70 are formed, the hole wall of the through hole 51 is treated by wet method or plasma to remove the through hole 51 . Impurities on the hole wall of the hole 51 and roughening the hole wall of the through hole 51 . This step facilitates subsequent deposition of metal materials of the source and drain electrodes in the through hole, and improves the bonding strength of the metal material and the hole wall of the through hole.
  • the wet method may employ an alkaline solution. For example, soak the product in a saturated ammonium hydroxide solution at 50°C for about 10 minutes to repair and clean the etched surface, then rinse it with deionized water, and dry it on a hot table.
  • the steps of forming the source electrode 60 and the drain electrode 70 include:
  • a Ti layer 61, an Al layer 62, a metal isolation layer 63, and an Au layer 64 are sequentially deposited on the hole wall of the through hole 51.
  • vapor deposition or sputtering of physical vapor deposition can be used.
  • Metal evaporation rate can be 0.2 ⁇ 0.5nm/s;
  • the deposited Ti layer 61, Al layer 62, metal isolation layer 63, and Au layer 64 are annealed to form a good ohmic contact.
  • the material of the metal isolation layer 63 is selected from at least one of Ni, Pt, Cr, Pd, and Mo metals.
  • the thickness of the Ti layer 61 is greater than or equal to 10 nm and less than or equal to 30 nm
  • the thickness of the Al layer 62 is greater than or equal to 100 nm and less than or equal to 200 nm
  • the thickness of the metal isolation layer 63 is greater than or equal to 200 nm.
  • the thickness of the Au layer 64 is 30 nm or less and 60 nm or less
  • the thickness of the Au layer 64 is 50 nm or more and 100 nm or less.
  • the annealing temperature is 500°C or more and 800°C or less.
  • the specific process of thermal annealing treatment can be as follows: filling the annealing furnace with N 2 to remove the air in the annealing furnace, setting the annealing temperature to be greater than or equal to 500 °C and less than or equal to 800 °C, heating time 20s, holding time 2min, cooling The time is set to 30s.
  • the preparation method also includes:
  • a shielding layer (not shown) is formed on the surface of the product after the through hole 51 is opened, and the light shielding layer does not cover the hole of the through hole 51 wall;
  • the masking layer on the surface of the product is stripped off.
  • the photoresist layer 90 in the above steps can be used as the shielding layer, which is used to shield the product where the source electrode 60 and the drain electrode 70 do not need to be deposited, but only the through holes 51 are relatively exposed, so that the subsequent steps can be used in the deposition process.
  • the metal material of the source electrode 60 and the drain electrode 70 is used, the metal material will be deposited into the through hole 51 and the surface of the shielding layer; after the deposition is completed, the shielding layer is peeled off and removed, the shielding layer And the metal material attached thereon will be removed, while the metal material in the through hole 51 remains.
  • the source electrode 60 and the drain electrode 70 are finally formed to protrude from the upper surface 52 of the AlGaN barrier layer 50 .
  • the specific process for peeling off the shielding layer on the surface of the product can be: heating with an NMP water bath at 50° C. for 30 minutes; then ultrasonically cleaning with acetone for 5 minutes, ultrasonicating alcohol for 3 minutes, and deionized water. Rinse for 1 min to ensure that the metal on the shielding layer is peeled off, and finally dry it on a hot table at 100 °C.
  • the etching process of the stepped through hole 51 has strong consistency and good stability, and is suitable for mass production.
  • the present application also provides a power amplifier applying the above HEMT.
  • the power amplifier includes the HEMTs 100 and 200 and other electronic components, and the other electronic components include resistors, inductors, capacitors, and the like.
  • the gate 80 of the HEMTs 100 and 200 is electrically connected to the input matching network 330
  • the source 60 is grounded
  • the drain 70 is electrically connected to the compensator 310 .
  • the compensator 310 includes a plurality of resistors 350 connected in series
  • the input matching network 330 includes a plurality of resistors 350 that are electrically connected.
  • the power amplifier is not limited to that shown in FIG. 12, and can be adjusted and designed according to the needs of the circuit design, and the electronic components connected to the drain 70 and the gate 80 of the HEMT can also be adjusted and designed according to the needs of the circuit design. .
  • An exemplary power switch as shown in FIG. 13 includes the HEMTs 100 and 200 and other electronic components, and the other electronic components may include power supplies, inductors, diodes, and the like.
  • the source 60 of the HEMTs 100 and 200 is grounded, the drain 70 is connected to a power source 410 , and the gate 80 is connected to the anode of a diode 420 and an inductor 430 .
  • the power switch is not limited to that shown in FIG. 13 , and can be adjusted and designed according to circuit design requirements.
  • the electronic components connected to the drain 70 and the gate 80 of the HEMTs 100 and 200 can also be designed according to the circuit. Adjustments and designs are required.

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Abstract

本申请提供一种高电子迁移率晶体管，包括衬底以及依次层叠在衬底上的GaN沟道层和AlGaN势垒层。AlGaN势垒层中开设有相互间隔的两个通孔，每一个通孔沿AlGaN势垒层的厚度方向贯穿AlGaN势垒层且每一个通孔的孔壁具有至少一级阶梯结构，每一个通孔具有远离衬底的上开口和靠近衬底的下开口，且上开口的开口面积大于下开口的开口面积。所述高电子迁移率晶体管还包括源极和漏极，源极和漏极分别填满一个通孔且直接接触连接GaN沟道层。本申请还提供该种高电子迁移率晶体管的制备方法和应用该种高电子迁移率晶体管的功率放大器和功率开关器。本申请设计阶梯状的通孔设置所述源极和漏极，有效减小欧姆接触电阻。

Description

高电子迁移率晶体管、制备方法、功率放大/开关器
相关申请的交叉引用
本申请要求在2020年12月18日提交中国专利局、申请号为202011511828.5、申请名称为“高电子迁移率晶体管、制备方法、功率放大/开关器”的中国专利的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种高电子迁移率晶体管(high-electron-mobility transistor，HEMT)及其制备方法，应用其的功率放大器和功率开关器。
背景技术
半导体技术是二十世纪至今最为重要的也是最具有影响力的高新技术之一。以氮化镓(GaN)为代表的第三代半导体材料具有禁带宽度大、击穿场强高、饱和电子漂移速度高等优异的特性，与AlGaN材料形成的异质结构中还可形成高浓度(10 13cm -2)的二维电子气(2DEG)，是高温、高压、高频、大功率微波器件的理想材料。通过二十多年快速发展，GaN基HEMT已经成为高性能射频系统的首选，不仅在军用装备中大显身手，在民用通信领域如4G和5G移动通信基站建设中也大放异彩。GaN基HEMT作为三端器件，其源极和漏极均采用欧姆接触(金属与半导体接触)工艺制作金属电极，以实现信号的接地功能和信号的输出功能。欧姆接触性能的好坏不仅会直接影响到器件的饱和输出电流、导通电阻、击穿电压等关键的性能指标，还会影响到器件在高频和高温等应用场景下的性能和可靠性。
发明内容
本申请实施例第一方面提供了一种高电子迁移率晶体管，包括衬底以及依次层叠在所述衬底上的成核层、缓冲层、GaN沟道层和AlGaN势垒层。所述AlGaN势垒层中开设有相互间隔的两个通孔，每一个通孔沿所述AlGaN势垒层的厚度方向贯穿所述AlGaN势垒层且每一个通孔的孔壁具有至少一级阶梯结构，每一个通孔具有远离所述衬底的上开口和靠近所述衬底的下开口，且所述上开口的开口面积大于所述下开口的开口面积。所述高电子迁移率晶体管还包括源极和漏极，所述源极和所述漏极分别填满一个通孔且直接接触连接所述GaN沟道层。
所述GaN基高电子迁移率晶体管，通过在设置源极和漏极的通孔的孔壁设计阶梯结构，形成欧姆金属材料(源极和漏极的金属材料)与AlGaN势垒层形成多阶梯接触，增大了欧姆金属材料与所述AlGaN势垒的接触面积，影响势垒形状，进而增大了形成隧穿电流的可能性，降低欧姆接触电阻，提升所述GaN基高电子迁移率晶体管的性能。
本申请实施方式中，每一个通孔包括沿所述AlGaN势垒层的厚度方向依次连通的至少两个孔部，且沿所述AlGaN势垒层的厚度方向且指向所述衬底的方向所述至少两个孔部的开口面积逐个减小。
通孔的上述结构保证了沿所述AlGaN势垒层的厚度方向且指向所述衬底的方向，所述通孔孔壁具有至少一级阶梯结构且通孔逐级变小。
本申请实施方式中，所述源极和漏极均相对突出于所述AlGaN势垒层远离所述衬底的表面；且所述源极和所述漏极均延伸进入所述GaN沟道层中。
所述源极和漏极突出于所述AlGaN势垒层远离所述衬底的表面，便于后续与信号线路实现电性连接。
本申请实施方式中，所述源极和所述漏极分别包括依次附着在所述通孔的孔壁上的Ti层、Al层、金属隔离层、Au层，所述金属隔离层的材料选自Ni、Pt、Cr、Pd、Mo金属中的至少一种。
Ti层在退火过程中与GaN沟道层和AlGaN势垒层发生固相化学反应，形成TiN；Al层主要作为催化剂促进氮原子与Ti的固相化学反应，另外应能够与Ti形成功函数低而致密的合金；Ti和Al均容易形成绝缘的氧化物和氢氧化物，所以需增加Au层；而金属隔离层用于阻挡Au层和Al层的相互扩散。
本申请实施方式中，所述Ti层的厚度为大于或等于10nm且小于或等于30nm，所述Al层的厚度为大于或等于100nm且小于或等于200nm，所述金属隔离层的厚度为大于或等于30nm且小于或等于60nm，所述Au层的厚度为大于或等于50nm且小于或等于100nm。
通过对源极和漏极的各层金属材料的厚度进行合理设计，保证源极和漏极均与GaN沟道层形成良好的欧姆接触。
本申请实施方式中，所述高电子迁移率晶体管还包括依次层叠在所述衬底上的成核层和缓冲层；所述成核层位于所述衬底与所述缓冲层之间；所述缓冲层位于所述成核层与所述GaN沟道层之间。
本申请实施方式中，所述成核层的材质为AlN，所述成核层的厚度为大于或等于0.1nm且小于或等于500nm。
设置所述成核层是为后续形成在成核层上的GaN外延层(包括缓冲层、GaN沟道层和AlGaN势垒层)的生长提供平整的成核表面，减少其成核生长的接触角，使GaN外延层生长形成平整的膜层。
本申请实施方式中，所述缓冲层的材质为渐变AlGaN或GaN/AlN超晶格；所述渐变AlGaN中Al的含量沿逐渐靠近所述衬底的方向逐渐变大；所述缓冲层的厚度为大于或等于0.1μm且小于或等于10μm。
所述缓冲层的设置可缓冲所述高电子迁移率晶体管中的应力。
本申请实施方式中，所述GaN沟道层的厚度为大于或等于0.1μm且小于或等于10μm，所述AlGaN势垒层的厚度为大于或等于0.1nm且小于或等于50nm。
通过对GaN沟道层和AlGaN势垒层的厚度进行合理设计，保证高电子迁移率晶体管的良好的性能。
本申请实施例第二方面提供了一种高电子迁移率晶体管的制备方法，包括如下步骤。提供衬底，在所述衬底上依次形成GaN沟道层和AlGaN势垒层。在所述AlGaN势垒层中开设贯穿所述AlGaN势垒层且相互间隔的两个通孔，每一个通孔的孔壁具有至少一级阶梯结构，每一个通孔具有远离所述衬底的上开口和靠近所述衬底的下开口，且所述上开口的开口面积大于所述下开口的开口面积。在每一个通孔中填充金属材料以分别形成直接接触连接所述 GaN沟道层的源极和漏极。
所述GaN基HEMT的制备方法，可通过多次循环刻蚀实现AlGaN势垒层，实现通孔的阶梯结构，形成欧姆接触金属与势垒区的多阶梯接触，降低欧姆接触电阻，提升所述GaN基HEMT器件的性能。
本申请实施方式中，当所述通孔的孔壁具有一级阶梯结构，形成所述通孔包括如下步骤。所述AlGaN势垒层上形成图案化的光刻胶层，使所述光刻胶层局部覆盖所述AlGaN势垒层远离所述衬底的上表面，未被所述光刻胶层覆盖的所述上表面的区域为源漏开窗区。采用干法蚀刻从所述源漏开窗区蚀刻所述AlGaN势垒层，蚀刻深度小于所述AlGaN势垒层的厚度。局部去除所述光刻胶层围绕所述源漏开窗区的部位以增大所述源漏开窗区。采用干法蚀刻从增大的源漏开窗区进一步蚀刻所述AlGaN势垒层至到蚀刻穿所述AlGaN势垒层。
通过两次干法蚀刻AlGaN势垒层和一次干法蚀刻光刻胶层，可实现通孔孔壁具有一级阶梯结构且通孔逐级变小。
本申请实施方式中，当所述通孔的孔壁具有至少两级阶梯结构，形成所述通孔包括如下步骤。在所述AlGaN势垒层上形成图案化的光刻胶层，使所述光刻胶层局部覆盖所述AlGaN势垒层远离所述衬底的上表面，未被所述光刻胶层覆盖的所述上表面的区域为源漏开窗区。采用干法蚀刻从所述源漏开窗区蚀刻所述AlGaN势垒层，蚀刻深度小于所述AlGaN势垒层的厚度；局部去除所述光刻胶层围绕所述源漏开窗区的部位以增大所述源漏开窗区。采用干法蚀刻从增大的所述源漏开窗区进一步蚀刻所述AlGaN势垒层，且不蚀刻穿所述AlGaN势垒层。参上重复进行局部去除所述光刻胶层围绕所述源漏开窗区的部位的步骤和干法蚀刻所述AlGaN势垒层的步骤至少一次，直到蚀刻穿所述AlGaN势垒层。
通过至少两次干法蚀刻AlGaN势垒层和至少一次干法蚀刻光刻胶层，可实现通孔孔壁具有至少两级阶梯结构且通孔逐级变小。
本申请实施方式中，所述干法蚀刻采用Cl 2和BCl 3的混合气体作为蚀刻气体；局部去除所述光刻胶层采用O 2作为蚀刻气体。
通过蚀刻气体的选择，保证对AlGaN势垒层和光刻胶层的蚀刻效果；实现通孔孔壁具有至少一级阶梯结构且通孔逐级变小。
本申请实施方式中，所述制备方法还包括：在形成所述通孔后，形成所述源极和所述漏极之前，采用湿法或者等离子处理所述通孔的孔壁，以去除所述通孔的孔壁上的杂质并粗糙化所述通孔的孔壁。
该步骤便于后续在所述通孔中沉积源极和漏极的金属材料，提升金属材料与通孔的孔壁的结合强度。
本申请实施方式中，形成所述源极和所述漏极的步骤包括：在所述通孔的孔壁上中依次沉积形成Ti层、Al层、金属隔离层、Au层，所述金属隔离层的材料选自Ni、Pt、Cr、Pd、Mo金属中的至少一种；对沉积形成的Ti层、Al层、金属隔离层、Au层进行退火处理。
Ti层在退火过程中与GaN沟道层和AlGaN势垒层发生固相化学反应，形成TiN；Al层主要作为催化剂促进氮原子与Ti的固相化学反应，另外应能够与Ti形成功函数低而致密的合金；Ti和Al均容易形成绝缘的氧化物和氢氧化物，所以需增加Au层；而金属隔离层用于阻挡Au层和Al层的相互扩散。本申请实施方式中，所述Ti层的厚度为大于或等于10nm且小于或等于30nm，所述Al层厚度为大于或等于100nm且小于或等于200nm，所述金属隔离 层厚度为大于或等于30nm且小于或等于60nm，所述Au层的厚度为大于或等于50nm且小于或等于100nm。
通过对源极和漏极的各层金属材料的厚度进行合理设计，保证源极和漏极均与GaN沟道层形成良好的欧姆接触。
本申请实施方式中，所述退火处理的退火温度为大于或等于500℃且小于或等于800℃。
所述源极和所述漏极采用经退火处理的多层金属材料，有利于减小接触电阻。
本申请实施方式中，所述制备方法还包括在形成所述GaN沟道层和所述AlGaN势垒层之前，在所述衬底上依次形成层叠的成核层和缓冲层；所述成核层位于所述衬底与所述缓冲层之间；所述缓冲层位于所述成核层与所述GaN沟道层之间。
设置所述成核层是为后续形成在成核层上的GaN外延层(包括缓冲层、GaN沟道层和AlGaN势垒层)的生长提供平整的成核表面，减少其成核生长的接触角，使GaN外延层生长形成平整的膜层；设置所述缓冲层可缓冲所述高电子迁移率晶体管中的应力。
本申请实施例第三方面提供了一种应用上述高电子迁移率晶体管的功率放大器。
GaN基高电子迁移率晶体管形成有良好的欧姆接触，提升了GaN基高电子迁移率晶体管的性能，可应用于射频前端模块中的功率放大器，也可用于通信、仪表、军事应用等的微波和毫米波的功率放大器。
本申请实施例第四方面提供了一种应用上述高电子迁移率晶体管的功率开关器。
采用本申请的GaN基高电子迁移率晶体管将进一步降低开关器件的导通电阻，提高器件的开关转换效率。
附图说明
图1是本申请实施例一的HEMT的剖面结构示意图。
图2是本申请实施例二的HEMT的剖面结构示意图。
图3是本申请HEMT的制备方法的流程图。
图4是本申请HEMT的制备过程的示意图一。
图5是本申请HEMT的制备过程的示意图二。
图6是本申请HEMT的制备过程的示意图三。
图7是本申请HEMT的制备过程的示意图四。
图8是本申请HEMT的制备过程的示意图五。
图9是本申请HEMT的制备过程的示意图六。
图10是本申请HEMT的制备过程的示意图七。
图11是本申请HEMT的制备过程的示意图八。
图12是应用本申请HEMT的功率放大器的局部电路图。
图13是应用本申请HEMT的功率开关器的电路图。
主要元件符号说明
HEMT：100、200；衬底：10；成核层：20；缓冲层：30；GaN沟道层：40；AlGaN势垒层：50；通孔：51；第一孔部：511；第二孔部：513；上开口：512；下开口：514；上表面：52；源极：60；漏极：70；Ti层：61；Al层：62；金属隔离层：63；Au层：64；栅极：80； 光刻胶层：90；源漏开窗区：91；补偿器：310；输入匹配网络：330；电阻：350；电源：410；二极管：420；电感：430。
具体实施方式
下面结合本申请实施例中的附图对本申请实施例进行描述。
5G的关键技术之大规模天线技术中，基站收发信机上使用了大量的阵列天线，这种阵列天线结构包括相应的射频收发单元，高输出功率、线性度和功耗要求也推动了基站部署的功率放大器从LDMOS转换为GaN基HEMT。利用GaN基HEMT的小尺寸和功率密度高的特点可以实现高度集成化的产品解决方案，如模块化射频前端器件。
AlGaN/GaN异质结HEMT结构中AlGaN的禁带宽度大，没有合适的单一金属材料可以与其直接形成接触电阻较小的欧姆接触。当前，业界普遍采用的方法是利用磁控溅射或者电子束蒸发的金属Ti，然后经过退火后与AlGaN形成合金效应，如此通过增加电子隧穿几率的方法来减少接触电阻。然而，随着器件性能需求的不断提升，特别是器件在低压场景的应用需求的出现，对AlGaN/GaN异质结HEMT的欧姆接触工艺的优化改进也提出了更大的挑战，降低欧姆接触电阻实现进一步的降低串联电阻，减小寄生效应，提升器件的放大能力和效率，是射频和功率AlGaN/GaN异质结HEMT器件研究的重要方向。
本申请提供一种GaN基HEMT，其可有效降低欧姆接触电阻，提升GaN基HEMT器件的性能。本申请的GaN基HEMT可应用于用于通信、仪表、军事应用等的微波和毫米波功率放大器，包括但不限于单片微波集成电路(MMIC)、射频前端模块等。
本申请的GaN基HEMT，除了可以应用于射频领域低压GaN基HEMT功放器件领域外，还可以应用于手机、平板等终端产品中快速充电领域低压GaN基HEMT功率开关器件。由于该领域的工作电压较低，对器件击穿电压要求不高，因此，采用本申请的GaN基HEMT将进一步降低开关器件的导通电阻，提高器件的开关转换效率。
如图1所示，所述HEMT100包括衬底10以及依次层叠在所述衬底10上的GaN沟道层40和AlGaN势垒层50。所述AlGaN势垒层50中开设有相互间隔的两个通孔51，每一个通孔51沿所述AlGaN势垒层50的厚度方向贯穿所述AlGaN势垒层50且每一个通孔51的孔壁具有一级阶梯结构。每一个通孔51具有远离所述衬底10的上开口512和靠近所述衬底10的下开口514，且所述上开口512大于所述下开口514。所述HEMT100还包括设置在所述AlGaN势垒层50远离所述衬底10的上表面52的源极60和漏极70。所述源极60和所述漏极70相互间隔，且分别填满一个通孔51且直接接触连接所述GaN沟道层40。所述源极60和所述漏极70均相对突出于所述AlGaN势垒层50的上表面52。
如图1所示，所述通孔51具有一级阶梯结构，所述通孔51包括沿所述AlGaN势垒层50的厚度方向相互连通的第一孔部511和第二孔部513，其中所述第二孔部513相对所述第一孔部511更靠近所述GaN沟道层40，所述第一孔部511的开口面积大于所述第二孔部513的开口面积。所述通孔51贯穿所述AlGaN势垒层50后还延伸进入所述GaN沟道层40中，即所述源极60和所述漏极70还延伸插入所述GaN沟道层40中。
如图1所示，所述HEMT100还包括依次层叠在所述衬底10上的成核层20和缓冲层30；所述成核层20位于所述衬底10与所述缓冲层30之间；所述缓冲层30位于所述成核层20与所述GaN沟道层40之间。图2所示的HEMT200，与图1的所示的HEMT100基本相同，不 同在于，HEMT200的通孔51具有两级阶梯结构。即，每一个通孔51包括沿所述AlGaN势垒层50的厚度方向依次连通设置的三个孔部(图未示)，且沿所述AlGaN势垒层50的厚度方向且指向所述衬底10的方向三个孔部的开口逐个减小。
可以理解的，本申请的HEMT的通孔51的孔壁不限于具有一级阶梯或两级阶梯，只要具有一级及以上阶梯即可。
可以理解的，本申请中，每一个通孔51包括沿所述AlGaN势垒层50的厚度方向依次连通设置的至少两个孔部(图未示)，且沿所述AlGaN势垒层50的厚度方向且指向所述衬底10的方向所述至少两个孔部的开口逐个减小；而所述源极60和所述漏极70分别逐级变细。
所述AlGaN势垒层50用于配合所述GaN沟道层40并在所述GaN沟道层40与所述AlGaN势垒层50相接区域通过极化作用产生二维电子气(2DEG)，从而导通电流。如果三维固体中，电子的运动在某一个方向(如z方向)上受到阻挡(限制)，电子只能在另外两个方向(x、y方向)上自由运动，这种具有两个自由度的自由电子就称为2DEG。所述源极60与所述漏极70用于在电场效应下使所述2DEG在源极60与漏极70之间的沟道层内流动，所述源极60与漏极70之间的导通发生在沟道层中的二维电子气处。
本申请中，所述源极60和漏极70的金属材料(欧姆接触金属)与AlGaN势垒层50和GaN沟道层40均接触，且欧姆接触金属与势垒层为阶梯式接触，这种阶梯式的接触结构使得2DEG和AlGaN势垒层50形成面接触，和GaN沟道层40形成线接触，这种双接触模式进一步增加了2DEG向金属层隧穿几率，从而减小了界面电阻。需要解释的是，因为电子在GaN沟道层以2DEG形式存在，可忽略电子在GaN沟道层内传输的厚度，因此，在欧姆接触金属与GaN沟道层40直接接触的区域，GaN沟道层中的电子直接从此区域进入源极60和漏极70的金属中，定义为线接触。还需要解释的是，在欧姆接触金属与AlGaN势垒层50接触的区域，2DEG在电场作用下，从GaN沟道层40穿过AlGaN势垒层50进入源极60和漏极70的金属中，因为整个区域都有金属覆盖，因此电子在整个区域都可以传输，定义为面接触。
本申请通过设计阶梯状的通孔51设置所述源极60和漏极70，实现AlGaN势垒层50局部区域被部分刻蚀未贯穿AlGaN势垒层50的厚度方向，而局部区域被完全刻蚀贯穿AlGaN势垒层50的厚度方向，通过部分刻蚀区域的AlGaN势垒层50来维持沟道的高浓度二维电子气，并通过完全刻蚀区域金属材料与2DEG的线接触，减小欧姆接触电阻。AlGaN势垒层50的部分刻蚀区域的台阶侧面增大了欧姆金属材料与所述AlGaN势垒的接触面积，影响势垒形状，进而增大了形成隧穿电流的可能性，因此可以减小欧姆接触电阻。部分刻蚀区域的金属到2DEG的距离减小，从而减小了欧姆接触电阻。
参见图1，所述源极60和所述漏极70分别包括Ti层61、Al层62、金属隔离层63、Au层64，由于制备所述源极60和所述漏极70的过程中，Ti、Al、金属隔离材料、Au是采用物理气相沉积的方法依次被沉积到通孔51的孔壁上，因此Ti层61、Al层62、金属隔离层63、Au层64依次附着在所述通孔51的孔壁上。所述Ti层61的厚度为大于或等于10nm且小于或等于30nm，所述Al层62厚度为大于或等于100nm且小于或等于200nm，所述金属隔离层63厚度为大于或等于30nm且小于或等于60nm，所述Au层64的厚度为大于或等于50nm且小于或等于100nm。图1和图2分别示出了由于通孔51的阶梯的级数不同而导致的所述源极60和所述漏极70的两种不同的结构。
设置Ti层61的主要目的是退火过程中与GaN沟道层40和AlGaN势垒层50发生固相化 学反应，形成TiN，同时GaN沟道层40中留下了高密度的氮空位，起到浅施主作用，有利于形成欧姆接触。Al层62主要作为催化剂促进氮原子与Ti的固相化学反应，另外Al层62中的Al能够与Ti形成功函数低而致密的合金。需要说明的是，功函数(又称功函、逸出功，英文名称为Work function)是指要使一粒电子立即从固体表面中逸出，所必须提供的最小能量(通常以电子伏特为单位)。这里“立即”一词表示最终电子位置从原子尺度上远离表面但从宏观尺度上依然靠近固体。然而，Ti和Al均容易形成绝缘的氧化物和氢氧化物，所以要增加一个帽层，一般采用化学性质稳定的Au；而Au和Al很容易发生相互扩散，到达GaN沟道层40材料表面，不利于形成良好的欧姆接触，需要增加金属隔离层63阻挡Au层64和Al层62的互相扩散。金属隔离层63的材料选自Ni、Pt、Cr、Pd、Mo金属中的至少一种。本实施例中，金属隔离层63的材料为Ni。Ti/Al/Ni/Au是目前GaN基材料欧姆接触常用的金属体系。
所述衬底10可采用高阻硅(Si)衬底或碳化硅(SiC)衬底。
所述成核层20的材质可为氮化铝(AlN)、氮化镓(GaN)和氮化镓铝(AlGaN)中的一种或多种。换句话说，成核层20的材质可以为氮化铝、氮化镓或氮化镓铝；成核层20的材质可以由氮化铝、氮化镓和氮化镓铝中的任意两种制成；成核层20的材质也可以由氮化铝、氮化镓和氮化镓铝这三种材质制成。本实施例中，所述成核层20的材质为AlN，厚度为0.1nm～500nm。所述成核层20的功能：为后续形成在成核层20上的GaN外延层(包括缓冲层30、GaN沟道层40和AlGaN势垒层50)的生长提供平整的成核表面，减少其成核生长的接触角，使缓冲层30、GaN沟道层40和AlGaN势垒层50生长形成平整的膜层。
本实施例中，所述缓冲层30的材质为渐变AlGaN或GaN/AlN超晶格(超晶格材料是两种不同组元以几个纳米到几十个纳米的薄层交替生长并保持严格周期性的多层膜)。所述缓冲层30的厚度为0.1μm～10μm。渐变AlGaN是指：所述缓冲层30中Al的含量沿逐渐靠近所述衬底10的方向逐渐变大。所述缓冲层30用于所述HEMT100的应力缓冲。
本实施例中，所述GaN沟道层40的厚度为0.1μm～10μm，所述AlGaN势垒层50的厚度为0.1nm～50nm。
所述HEMT100还包括栅极80，所述栅极80在所述衬底10上的正投影位于所述源极60与所述漏极70之间，用于允许或阻碍2DEG的通过。所述栅极80采用导电金属材料制成，例如所述栅极80包括层叠设置在所述上表面52的Ni层(图未示)和Au层(图未示)。本实施例中，所述栅极80位于所述AlGaN势垒层50远离所述衬底10的上表面52。可以理解的，所述栅极80的位置不限于设置于所述AlGaN势垒层50的上表面52，还可以根据需要设置在其他位置。
可以理解的是，所述HEMT100，200均还可包括其他的一些层(图未示)。本申请所列的各层的厚度范围值均包括端值。
如图3所示，本实施例中，所述HEMT100，200的制备方法包括如下步骤(理解如下步骤可以结合附图4至图11)。
S1：提供衬底，在所述衬底上依次形成成核层20、缓冲层30、GaN沟道层40和AlGaN势垒层50；
S2：在所述AlGaN势垒层50中开设贯穿所述AlGaN势垒层50且相互间隔的两个通孔51，每一个通孔的孔壁具有至少一级阶梯结构，每一个通孔具有远离所述衬底的上开口512 和靠近所述衬底的下开口514，且所述上开口的开口面积大于所述下开口的开口面积；
S3：在每一个通孔51中填充金属材料以分别形成源极60和漏极70。
步骤S1完成得到的产品请参图4。所述成核层20、所述缓冲层30、所述GaN沟道层40与所述AlGaN势垒层50可采用金属有机化合物化学气相沉淀(Metal-organic Chemical Vapor Deposition，MOCVD)或分子束外延(Molecular Beam Epitaxy，MBE)法依次形成在所述衬底10上。本实施例中，所述成核层20的厚度为0.1nm～500nm，所述缓冲层30的厚度为0.1μm～10μm，所述GaN沟道层40的厚度为0.1μm～10μm，所述AlGaN势垒层50的厚度为0.1nm～50nm。
步骤S2请参图5至图10。所述通孔51的开设采用分阶段至少两次蚀刻所述AlGaN势垒层50的方式实现。
当所述通孔51的孔壁具有至少两级阶梯结构，形成所述通孔51的步骤包括：
如图5所示，在所述AlGaN势垒层50上形成图案化的光刻胶层90，使所述光刻胶层90局部覆盖所述AlGaN势垒层50远离所述衬底10的上表面52，未被所述光刻胶层90覆盖的所述上表面52的区域为源漏开窗区91；
如图6所示，采用干法蚀刻从所述源漏开窗区91蚀刻所述AlGaN势垒层50，蚀刻深度小于所述AlGaN势垒层50的厚度；
如图7所示，局部去除所述光刻胶层90围绕所述源漏开窗区91的部位以增大所述源漏开窗区91；
如图8所示，采用干法蚀刻从增大的所述源漏开窗区91进一步蚀刻所述AlGaN势垒层50，且不蚀刻穿所述AlGaN势垒层50；每一次干法蚀刻AlGaN势垒层50(对应源漏开窗区91)的区域向下蚀刻的深度大致是相等的，如此AlGaN势垒层50的有的地方被干法蚀刻两次，有的区域被干法蚀刻一次，两个区域的蚀刻深度不一样，使蚀刻表面呈阶梯状；
如图9和图10所示，参上重复进行局部去除所述光刻胶层90围绕所述源漏开窗区91的部位的步骤和干法蚀刻所述AlGaN势垒层50的步骤各一次，直到蚀刻穿所述AlGaN势垒层50得到通孔51，如此得到通孔51的孔壁呈阶梯状；
去除剩下的光刻胶层90。
可以理解的，所述通孔51的阶梯结构的级数可以通过调控局部去除所述光刻胶层90围绕所述源漏开窗区91的部位的步骤和干法蚀刻所述AlGaN势垒层50的步骤的次数实现。
当所述通孔51的孔壁具有一级阶梯结构，形成所述通孔51的步骤与上述步骤基本相似，但只需要两次干法蚀刻所述AlGaN势垒层50至到蚀刻穿所述AlGaN势垒层50，具体包括：
在所述AlGaN势垒层50上形成图案化的光刻胶层90，使所述光刻胶层90局部覆盖所述AlGaN势垒层50远离所述衬底10的上表面52，未被所述光刻胶层90覆盖的所述上表面52的区域为源漏开窗区91；
采用干法蚀刻从所述源漏开窗区91蚀刻所述AlGaN势垒层50，蚀刻深度小于所述AlGaN势垒层50的厚度；
局部去除所述光刻胶层90围绕所述源漏开窗区91的部位以增大所述源漏开窗区91；
采用干法蚀刻从增大的源漏开窗区91进一步蚀刻所述AlGaN势垒层50至到蚀刻穿所述AlGaN势垒层50得到通孔51；每一次干法蚀刻AlGaN势垒层50(对应源漏开窗区91)的区域向下蚀刻的深度大致是相等的，如此AlGaN势垒层50的有的地方被干法蚀刻两次，有 的区域被干法蚀刻一次，两个区域的蚀刻深度不一样，使通孔51的孔壁呈阶梯状；
去除剩下的光刻胶层90。
首次干法蚀刻所述AlGaN势垒层50的蚀刻深度可为所述AlGaN势垒层50的厚度的一半，但不限于此。蚀刻过程中所述GaN沟道层40也被部分蚀刻，但未贯穿所述GaN沟道层40。
所述干法蚀刻采用Cl 2和BCl 3的混合气体作为蚀刻气体；局部去除所述光刻胶层90采用O 2进行蚀刻。
可以理解的，阶梯结构的台阶面不限于是与侧壁面垂直，还可设置一定的倾斜角度；另外通孔51的各级阶梯的深度、宽度均可通过蚀刻参数的调整而调整。
一实施例中，刻蚀通孔51的具体工艺参数为：在ICP(感应耦合等离子体)刻蚀机中，先通入Cl 2/BCl 3混合气体刻蚀AlGaN势垒层50，刻蚀深度为所述AlGaN势垒层50厚度的一半，ICP功率30W，射频功率100W，刻蚀时间2min；接着执行抽真空流程，抽取腔内剩余气体，时间1min；再通入O 2进行光刻胶层90的刻蚀，ICP功率设置50W，下电极功率设置0W，时间3min；然后执行抽真空流程1min，抽取剩余O 2；最后再通入Cl 2/BCl 3混合气体，蚀刻穿AlGaN势垒层50接触到GaN层。
去除剩下的光刻胶层90可采用光刻胶溶剂，例如N-甲基吡咯烷酮(NMP)。具体可为：将产品放入NMP中超声清洗10min，再用酒精超声清洗5min，去离子水冲洗1min。
在所述AlGaN势垒层50上形成光刻胶层90前，还可对所述AlGaN势垒层50的上表面52进行清洁，以除去所述上表面52的杂质和沾污。清洁方法具体可为：先放在浓度为4wt％的HF溶液中浸泡一定时间(例如10秒)，去除表面氧化层；然后依次采用丙酮、酒精、去离子水超声清洗去除表面沾污，丙酮、酒精、去离子水的清洗时间可分别为10min、5min和2mi；最后烘干去除表面水分，例如在100℃热台上烘烤5min。
在所述AlGaN势垒层50上形成局部覆盖的光刻胶层90的步骤可包括：先在所述AlGaN势垒层50的上表面52形成完全覆盖所述上表面52的光刻胶层90，然后对所述光刻胶层90进行曝光显影以局部去除光刻胶层90(图案化工艺)，光刻胶层90被去除的区域即形成为源漏开窗区91。所述源漏开窗区91包括相互间隔的源极开窗区和漏极开窗区。光刻胶层90可采用涂敷法形成，具体可包括：采用光刻胶(AZ系列214号)涂覆所述上表面52，设置匀胶参数，例如初始加速500r/min，加速时间9s，匀胶转速4000r/min，时间30s，得到1.2μm厚的光刻胶层90；然后烘烤固化，例如在100℃热台上烘烤2min。
所述制备方法还包括：在形成所述通孔51后，且形成所述源极60和所述漏极70之前，采用湿法或者等离子处理所述通孔51的孔壁，去除所述通孔51的孔壁上的杂质以及粗糙化所述通孔51的孔壁。该步骤便于后续在所述通孔中沉积源极和漏极的金属材料，提升金属材料与通孔的孔壁的结合强度。所述湿法可采用碱性溶液。例如将产品浸泡在50℃的氢氧化铵饱和溶液中约10min对刻蚀表面进行修复和清洁，然后再用去离子水冲洗干净，并在热台上烘干。
形成所述源极60和所述漏极70的步骤包括：
如图11所示，在所述通孔51的孔壁上中依次沉积形成Ti层61、Al层62、金属隔离层63、Au层64，具体可采用物理气相沉积的蒸镀或者溅射，金属蒸发速率可为0.2～0.5nm/s；
对沉积形成的Ti层61、Al层62、金属隔离层63、Au层64进行退火处理，以形成良好 的欧姆接触。金属隔离层63的材料选自Ni、Pt、Cr、Pd、Mo金属中的至少一种。
本实施例中，所述Ti层61的厚度为大于或等于10nm且小于或等于30nm，所述Al层62厚度为大于或等于100nm且小于或等于200nm，所述金属隔离层63厚度为大于或等于30nm且小于或等于60nm，所述Au层64的厚度为大于或等于50nm且小于或等于100nm。退火温度为大于或等于500℃且小于或等于800℃。
热退火处理具体的工艺可为：向退火炉中充入N 2排除退火炉中的空气，设定退火温度为大于或等于500℃且小于或等于800℃，升温时间20s，保温时间2min，降温时间设置30s。
所述制备方法还包括：
在形成所述源极60和所述漏极70的步骤前，在开设有通孔51后的产品表面形成遮蔽层(图未示)，所述光遮蔽层不覆盖所述通孔51的孔壁；
在形成所述源极60和所述漏极70的步骤后，剥离去除产品表面的遮蔽层。
所述遮蔽层可采用上述步骤的光刻胶层90，其用于遮蔽产品不需要沉积源极60和漏极70的区域，而仅使所述通孔51相对露出，这样后续步骤在沉积所述源极60和漏极70的金属材料时，金属材料会被沉积到所述通孔51中以及所述遮蔽层的表面；沉积完成后，将所述遮蔽层剥离去除，则所述遮蔽层以及附着在其上的金属材料均会被移除，而通孔51中的金属材料保留。
可以理解的，由于最后剥离掉上表面52上的遮蔽层和金属材料，最终形成所述源极60和所述漏极70均相对所述AlGaN势垒层50的上表面52突出。
当遮蔽层采用上述步骤的光刻胶层90，剥离去除产品表面的遮蔽层的具体的工艺可为：采用NMP水浴加热50℃，30min；再用丙酮超声清洗5min，酒精超声3min，去离子水冲洗1min，确保遮蔽层上的金属剥离干净，最后再100℃热台烘干。
本申请HEMT的制备方法，阶梯状通孔51的刻蚀工艺一致性强，稳定性好，适合量产。
本申请还提供一种应用上述HEMT的功率放大器。如图12所示的一示例性的功率放大器的局部，功率放大器包括所述HEMT100，200以及其他的电子元器件，其他的电子元器件包括电阻、电感、电容等。本实施例中，所述HEMT100，200的栅极80电性连接输入匹配网络330，源极60接地，漏极70电性连接补偿器310。本实施例中，补偿器310包括串联连接的多个电阻350，所述输入匹配网络330包括电性连接的多个电阻350。可以理解的，功率放大器不限于图12所示，可根据电路设计需要进行调整和设计，相应所述HEMT的漏极70和栅极80连接的电子元器件也可根据电路设计需要进行调整和设计。
本申请还提供一种应用上述HEMT的功率开关器。如图13所示的一示例性的功率开关器，包括所述HEMT100，200以及其他的电子元器件，其他的电子元器件可包括电源、电感、二极管等。所述HEMT100，200的源极60接地，漏极70连接一电源410，栅极80连接一二极管420的正极和一电感430。可以理解的，所述功率开关器不限于图13所示，可根据电路设计需要进行调整和设计，相应所述HEMT100，200的漏极70和栅极80连接的电子元器件也可根据电路设计需要进行调整和设计。
需要说明的是，以上仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内；在不冲突的情况下，本申请的实施方式及实施方式中的特征可以相互组合。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种高电子迁移率晶体管，其特征在于，包括衬底以及依次层叠在所述衬底上的GaN沟道层和AlGaN势垒层；
    所述AlGaN势垒层中开设有相互间隔的两个通孔，每一个通孔沿所述AlGaN势垒层的厚度方向贯穿所述AlGaN势垒层且每一个通孔的孔壁具有至少一级阶梯结构，每一个通孔具有远离所述衬底的上开口和靠近所述衬底的下开口，且所述上开口的开口面积大于所述下开口的开口面积；
    所述高电子迁移率晶体管还包括源极和漏极，所述源极和所述漏极分别填满一个通孔且直接接触连接所述GaN沟道层。
  2. 根据权利要求1所述的高电子迁移率晶体管，其特征在于，每一个通孔包括沿所述AlGaN势垒层的厚度方向依次连通的至少两个孔部，且沿所述AlGaN势垒层的厚度方向且指向所述衬底的方向所述至少两个孔部的开口面积逐个减小。
  3. 根据权利要求1或2所述的高电子迁移率晶体管，其特征在于，所述源极和漏极均相对突出于所述AlGaN势垒层远离所述衬底的表面；且所述源极和所述漏极均延伸进入所述GaN沟道层中。
  4. 根据权利要求1至3中任一项所述的高电子迁移率晶体管，其特征在于，所述源极和所述漏极分别包括依次附着在所述通孔的孔壁上的Ti层、Al层、金属隔离层、Au层；所述金属隔离层的材料选自Ni、Pt、Cr、Pd、Mo金属中的至少一种。
  5. 根据权利要求4所述的高电子迁移率晶体管，其特征在于，所述Ti层的厚度为大于或等于10nm且小于或等于30nm，所述Al层的厚度为大于或等于100nm且小于或等于200nm，所述金属隔离层的厚度为大于或等于30nm且小于或等于60nm，所述Au层的厚度为大于或等于50nm且小于或等于100nm。
  6. 根据权利要求1至5中任一项所述的高电子迁移率晶体管，其特征在于，所述高电子迁移率晶体管还包括依次层叠在所述衬底上的成核层和缓冲层；所述成核层位于所述衬底与所述缓冲层之间；所述缓冲层位于所述成核层与所述GaN沟道层之间。
  7. 根据权利要求6所述的高电子迁移率晶体管，其特征在于，所述成核层的材质为AlN，所述成核层的厚度为大于或等于0.1nm且小于或等于500nm。
  8. 根据权利要求6所述的高电子迁移率晶体管，其特征在于，所述缓冲层的材质为渐变AlGaN或GaN/AlN超晶格；所述渐变AlGaN中Al的含量沿靠近所述衬底的方向逐渐变大；所述缓冲层的厚度为大于或等于0.1μm且小于或等于10μm。
  9. 根据权利要求1至8中任一项所述的高电子迁移率晶体管，其特征在于，所述GaN沟道层的厚度为大于或等于0.1μm且小于或等于10μm，所述AlGaN势垒层的厚度为大于或等于0.1nm且小于或等于50nm。
  10. 一种高电子迁移率晶体管的制备方法，其特征在于，包括：
    提供衬底，在所述衬底上依次形成GaN沟道层和AlGaN势垒层；
    在所述AlGaN势垒层中开设贯穿所述AlGaN势垒层且相互间隔的两个通孔，每一个通孔的孔壁具有至少一级阶梯结构，每一个通孔具有远离所述衬底的上开口和靠近所述衬底的 下开口，且所述上开口的开口面积大于所述下开口的开口面积；
    在每一个通孔中填充金属材料以分别形成直接接触连接所述GaN沟道层的源极和漏极。
  11. 根据权利要求10所述的高电子迁移率晶体管的制备方法，其特征在于，
    当所述通孔的孔壁具有一级阶梯结构，形成所述通孔的步骤包括：
    在所述AlGaN势垒层上形成图案化的光刻胶层，使所述光刻胶层局部覆盖所述AlGaN势垒层远离所述衬底的上表面，未被所述光刻胶层覆盖的所述上表面的区域为源漏开窗区；
    采用干法蚀刻从所述源漏开窗区蚀刻所述AlGaN势垒层，蚀刻深度小于所述AlGaN势垒层的厚度；
    局部去除所述光刻胶层围绕所述源漏开窗区的部位以增大所述源漏开窗区；
    采用干法蚀刻从增大的源漏开窗区进一步蚀刻所述AlGaN势垒层至到蚀刻穿所述AlGaN势垒层。
  12. 根据权利要求10所述的高电子迁移率晶体管的制备方法，其特征在于，
    当所述通孔的孔壁具有至少两级阶梯结构，形成所述通孔的步骤包括：
    在所述AlGaN势垒层上形成图案化的光刻胶层，使所述光刻胶层局部覆盖所述AlGaN势垒层远离所述衬底的上表面，未被所述光刻胶层覆盖的所述上表面的区域为源漏开窗区；
    采用干法蚀刻从所述源漏开窗区蚀刻所述AlGaN势垒层，蚀刻深度小于所述AlGaN势垒层的厚度；
    局部去除所述光刻胶层围绕所述源漏开窗区的部位以增大所述源漏开窗区；
    采用干法蚀刻从增大的所述源漏开窗区进一步蚀刻所述AlGaN势垒层，且不蚀刻穿所述AlGaN势垒层；
    参上重复进行局部去除所述光刻胶层围绕所述源漏开窗区的部位的步骤和干法蚀刻所述AlGaN势垒层的步骤至少一次，直到蚀刻穿所述AlGaN势垒层。
  13. 根据权利要求11或12所述的高电子迁移率晶体管的制备方法，其特征在于，所述干法蚀刻采用Cl 2和BCl 3的混合气体作为蚀刻气体；局部去除所述光刻胶层采用O 2作为蚀刻气体。
  14. 根据权利要求10至13中的任意一项所述的高电子迁移率晶体管的制备方法，其特征在于，所述制备方法还包括：在形成所述通孔后，形成所述源极和所述漏极之前，采用湿法或者等离子处理所述通孔的孔壁，以去除所述通孔的孔壁上的杂质并粗糙化所述通孔的孔壁。
  15. 根据权利要求10至14中的任意一项所述的高电子迁移率晶体管的制备方法，其特征在于，形成所述源极和所述漏极的步骤包括：
    在所述通孔的孔壁上中依次沉积形成Ti层、Al层、金属隔离层、Au层，所述金属隔离层的材料选自Ni、Pt、Cr、Pd、Mo金属中的至少一种；
    对沉积形成的Ti层、Al层、金属隔离层、Au层进行退火处理。
  16. 根据权利要求15所述的高电子迁移率晶体管的制备方法，其特征在于，所述Ti层的厚度为大于或等于10nm且小于或等于30nm，所述Al层厚度为大于或等于100nm且小于或等于200nm，所述金属隔离层厚度为大于或等于30nm且小于或等于60nm，所述Au层的厚度为大于或等于50nm且小于或等于100nm。
  17. 根据权利要求15所述的高电子迁移率晶体管的制备方法，其特征在于，所述退火处 理的退火温度为大于或等于500℃且小于或等于800℃。
  18. 根据权利要求10所述的高电子迁移率晶体管的制备方法，其特征在于，所述制备方法还包括在形成所述GaN沟道层和所述AlGaN势垒层之前，在所述衬底上依次形成层叠的成核层和缓冲层；所述成核层位于所述衬底与所述缓冲层之间，所述缓冲层位于所述成核层与所述GaN沟道层之间。
  19. 一种功率放大器，其特征在于，包括如述权利要求1至9中任意一项所述的高电子迁移率晶体管和其他的电子元器件，所述高电子迁移率晶体管的源极接地，漏极连接一电子元器件，栅极连接另一电子元器件。
  20. 一种功率开关器，其特征在于，包括如权利要求1至9中任意一项所述的高电子迁移率晶体管和其他的电子元器件，所述高电子迁移率晶体管的源极接地，漏极连接一电子元器件，栅极连接另一电子元器件。
PCT/CN2021/131765 2020-12-18 2021-11-19 高电子迁移率晶体管、制备方法、功率放大/开关器 WO2022127512A1 (zh)

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