WO2022121306A1 - 高压非对称结构ldmos器件及其制备方法 - Google Patents

高压非对称结构ldmos器件及其制备方法 Download PDF

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WO2022121306A1
WO2022121306A1 PCT/CN2021/105687 CN2021105687W WO2022121306A1 WO 2022121306 A1 WO2022121306 A1 WO 2022121306A1 CN 2021105687 W CN2021105687 W CN 2021105687W WO 2022121306 A1 WO2022121306 A1 WO 2022121306A1
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region
gate dielectric
dielectric layer
drift
ldmos device
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PCT/CN2021/105687
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English (en)
French (fr)
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郁文
陈燕宁
付振
刘芳
王帅鹏
邓永峰
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北京芯可鉴科技有限公司
北京智芯微电子科技有限公司
国网信息通信产业集团有限公司
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Publication of WO2022121306A1 publication Critical patent/WO2022121306A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

Definitions

  • the invention relates to the technical field of semiconductor integrated circuits, in particular to a high-voltage asymmetric structure LDMOS device and a preparation method of a high-voltage asymmetric structure LDMOS device.
  • LDMOS Lateral Double-Diffused Metal Oxide Semiconductor Field Effect Transistor
  • LDMOS process characteristics of double diffusion enable LDMOS to make a very short channel without the need for high-precision photolithography process. Therefore, the transconductance and frequency characteristics of LDMOS are significantly improved.
  • the design of LDMOS mainly revolves around a reasonable compromise between breakdown voltage and characteristic on-resistance. Increasing the device's withstand voltage by increasing the length of the drift region will lead to a sharp increase in the device's on-resistance. Therefore, it is urgent to fully guarantee the electrical characteristics and reliability of the device through the optimized design and process improvement of the device.
  • the purpose of the embodiments of the present invention is to provide a high-voltage asymmetric structure LDMOS device and a preparation method thereof.
  • the LDMOS device is provided with a double-layer gate dielectric structure in the main part of the drift region, and the gate structure formed by superimposing the polysilicon gate on the drift region.
  • the surface electric field plays the role of field plate modulation, improves the breakdown voltage of the device, and ensures the reliability of the device under high voltage and high current conditions; the source-drain asymmetric structure is set, and the junction depth of the drain region is greater than that of the source region, which effectively improves the leakage of the device.
  • This preparation method expands the ion implantation depth, forming a junction depth of the drain region that is greater than the junction depth of the source region, thereby effectively improving the control ability of the drain region to the conductive channel. It is ensured that the carriers can still be effectively collected by the drain region from the source region through the body region and the drift region, thereby significantly improving the electrical characteristics of the device.
  • a first aspect of the present invention provides a high-voltage asymmetric structure LDMOS device
  • the LDMOS device includes: the LDMOS device has: a drift region and a body region; the surface of the drift region is divided into a first region and a body region.
  • the second region the surface of the body region is divided into a third region and a fourth region, the second region and the fourth region are extended and covered by the first gate dielectric layer; the surface of the first gate dielectric layer is divided There is a seventh region, the seventh region is located above the drift region and is covered by the second gate dielectric layer; the surface of the second gate dielectric layer is divided into a sixth region and a fifth region, the fifth region and The first gate dielectric layer other than the seventh region is extended and covered by the polysilicon gate; the first region of the drift region is formed with a drain region from the surface inward; the third region of the body region is formed from the surface inward In the active region, the depth of the drain region is greater than the depth of the source region.
  • the LDMOS device further includes a substrate, and the substrate is divided into a ninth region, a tenth region for forming the drift region, and an eighth region for forming the body region; the first region Ten regions are in contact with the eighth region or spaced apart from the ninth region.
  • the drift region is a drift region of a first conductivity type
  • the body region is a body region of a second conductivity type
  • the substrate is a substrate of the second conductivity type.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the LDMOS device is an N-type device under this configuration
  • the first conductivity type is P-type
  • the The second conductivity type is N-type
  • the LDMOS device is a P-type device in this configuration.
  • the first gate dielectric layer is a SiO 2 layer
  • the second gate dielectric layer is a high dielectric constant gate dielectric layer.
  • the growth thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer, and it can only cover part of the drift region in the longitudinal view.
  • a double-layer gate dielectric structure is proposed to help improve the device’s performance at high voltage and high voltage. Reliability under high current stress.
  • a second aspect of the present invention provides a preparation method of a high-voltage asymmetric structure LDMOS device, the preparation method comprising:
  • S1 divide the eighth region on the substrate to form the body region; divide the tenth region to form the drift region;
  • S2 dividing a first region and a second region on the surface of the drift region; dividing a third region and a fourth region on the surface of the body region, and the second region is adjacent to the fourth region;
  • a source region is formed in the third region of the body region from the surface inward, and a drain region is formed in the first region of the drift region from the surface inward, and the depth of the drain region is greater than the depth of the source region.
  • the drift region and the body region are formed by an ion implantation process; the source region and the drain region are formed by a heavily doped ion implantation process.
  • the substrate is a substrate of the second conductivity type
  • the drift region is implanted with ions of the first conductivity type
  • the body region is implanted with ions of the second conductivity type
  • the source region and the drain region are respectively Ions of the first conductivity type are implanted.
  • the ion implantation amount in the drain region is greater than the ion implantation amount in the source region, and the ion implantation energy in the drain region is increased by three energy gradients compared with the ion implantation energy in the source region.
  • a larger junction depth can be obtained by increasing the ion implantation dose and energy in the drain region.
  • step S4 a portion of the first gate dielectric located outside the second region and outside the fourth region is removed to obtain a first gate dielectric layer, including:
  • the second area and the fourth area are defined by photolithography, and the part of the first gate dielectric located outside the second area and outside the fourth area is removed by an etching process to obtain a first gate dielectric Floor;
  • step S7 the part of the second gate dielectric outside the seventh region is removed to obtain a second gate dielectric layer, including:
  • the seventh region is defined by photolithography, and the portion of the second gate dielectric located outside the seventh region is removed by an etching process to obtain a second gate dielectric layer;
  • step S10 the part of the polysilicon located outside the fifth region and outside the surface of the first gate dielectric layer is removed to obtain a polysilicon gate, including:
  • a fifth region is defined by photolithography, and an etching process is used to remove the part of the polysilicon outside the fifth region and outside the surface of the first gate dielectric layer to obtain a polysilicon gate.
  • the gate dielectric layer of the LDMOS device is designed in a targeted manner, and a double-layer gate dielectric layer is used in the main part of the drift region.
  • the first gate dielectric is SiO 2
  • the second gate dielectric is high dielectric. Constant gate dielectric.
  • the material in contact with the drift region and the body region is SiO 2 , which makes full use of the good interface contact characteristics of SiO 2 and silicon-based materials. A higher field effect is generated between the silicon bottom channels.
  • the gate structure formed by the superposition of the double-layer gate dielectric and the polysilicon gate in the drift region plays a field plate modulation effect on the surface electric field of the drift region, thereby improving the breakdown voltage of the device and ensuring the performance of the entire power integrated circuit in a complex stress environment. performance.
  • the formation process of the drain region is innovated, and the ion implantation depth is enlarged by adjusting the ion implantation energy and dose of the drain region, so that the junction depth of the drain region is larger than that of the source region, thereby effectively improving the control ability of the drain region to the conductive channel and ensuring the load
  • the electrons can still be effectively collected by the drain region from the source region through the body region and the drift region, thereby significantly improving the electrical characteristics of the device.
  • FIG. 1 is a schematic structural diagram of a high-voltage asymmetric structure LDMOS device provided by a first embodiment of the present invention
  • FIG. 2 is an exploded schematic diagram A of the high-voltage asymmetric structure LDMOS device provided by the first embodiment of the present invention
  • FIG. 3 is an exploded schematic diagram B of a high-voltage asymmetric structure LDMOS device provided by the first embodiment of the present invention
  • FIG. 4 is an exploded schematic diagram C of a high-voltage asymmetric structure LDMOS device provided by the first embodiment of the present invention
  • FIG. 5 is an exploded schematic diagram D of the high-voltage asymmetric structure LDMOS device provided by the first embodiment of the present invention.
  • FIG. 6 is an exploded schematic diagram E of the high-voltage asymmetric structure LDMOS device provided by the first embodiment of the present invention.
  • Fig. 7 is the exploded schematic diagram F of the high-voltage asymmetric structure LDMOS device provided by the first embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a high-voltage asymmetric structure LDMOS device provided by the second embodiment of the present invention.
  • FIG. 9 is a flowchart of a method for fabricating a high-voltage asymmetric structure LDMOS device provided by an embodiment of the present invention.
  • the directional words used such as “up, down, left and right", generally refer to the azimuth or positional relationship shown in the drawings.
  • the terms “first”, “second”, “third”, etc. are only used to differentiate the description and should not be construed as indicating or implying relative importance.
  • FIG. 1 is a schematic structural diagram of a high-voltage asymmetric structure LDMOS device according to a first embodiment of the present invention.
  • the drift region 2 and the body region 3 of the LDMOS device are in lateral contact.
  • the LDMOS device has: a drift region 2 and a body region 3; the surface of the drift region 2 is divided into a first region 201 and a second region 202; the surface of the body region 3 A third area 301 and a fourth area 302 are divided, and the second area 202 and the fourth area 302 are extended and covered by the first gate dielectric layer 4; the surface of the first gate dielectric layer 4 is divided into a seventh area 401 , the seventh region 401 is located above the drift region 2 and is covered by the second gate dielectric layer 5 ; the surface of the second gate dielectric layer 5 is divided into a sixth region 502 and a fifth region 501 .
  • the first gate dielectric layer 4 other than the fifth region 501 and the seventh region 401 is extended and covered by the polysilicon gate 6; the first region 201 of the drift region 2 is formed with a drain region 8 from the surface inward; the body region The third region 301 of 3 forms the active region 7 inward from the surface, and the depth of the drain region 8 is greater than the depth of the source region 7 .
  • the source region 7 and the drain region 8 adopt an asymmetric structure, and the source region 7 and the drain region 8 are not implanted at the same time.
  • the ion implantation dose and energy of the drain region 8 are increased on the basis of the source region 7, and a larger junction can be obtained. Therefore, the control ability of the drain region 8 to the conductive channel is effectively improved, ensuring that the carriers can still be effectively collected by the drain region 8 from the source region 7 through the body region 3 and the drift region 2, thereby significantly improving the electrical characteristics of the device.
  • the LDMOS device further includes a substrate 1, and the substrate 1 is divided into a ninth region 103, a tenth region 101 for forming the drift region 2, and an eighth region 102 for forming the body region 3; In this embodiment, the tenth area 101 is in contact with the eighth area 102 .
  • the drift region 2 is a drift region of a first conductivity type
  • the body region 3 is a body region of a second conductivity type
  • the substrate 1 is a substrate of the second conductivity type.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the LDMOS device is an N-type device under this configuration
  • the first conductivity type is P-type
  • the second conductivity type It is an N-type device
  • the LDMOS device is a P-type device under this configuration.
  • the first gate dielectric layer 4 is a SiO 2 layer grown by high temperature thermal oxidation, which is in contact with the surfaces of the drift region 2 and the body region 3 and covers the second region 202 and the fourth region 302 .
  • the second gate dielectric layer 5 is a high dielectric constant gate dielectric layer.
  • the high dielectric constant gate dielectric can be selected from Al 2 O 3 , and Al 2 O 3 is grown on the first gate dielectric 4 by an atomic layer deposition process.
  • the growth thickness of the second gate dielectric 5 is smaller than that of the first gate dielectric 4, and can only cover part of the drift region 2 in the longitudinal view.
  • a double-layer gate dielectric structure is formed in the local area above the drift region. The design helps to improve the reliability of the device under high voltage and high current stress.
  • FIG. 8 is a schematic structural diagram of a high-voltage asymmetric structure LDMOS device provided by the second embodiment of the present invention.
  • the drift region 2 and the body region 3 of the LDMOS device are laterally spaced apart by the ninth region 103 of the substrate 1 .
  • FIG. 9 is a flowchart of a method for preparing a high-voltage asymmetric structure LDMOS device provided by an embodiment of the present invention. As shown in FIG. 9 , the preparation method includes:
  • a first region 201 and a second region 202 are divided on the surface of the drift region 2; a third region 301 and a fourth region 302 are divided on the surface of the body region 3, the second region 202 and the The fourth area 302 is adjacent to each other;
  • the second area 202 and the fourth area 302 are defined by photolithography, and the part of the first gate dielectric located outside the second area 202 and outside the fourth area 302 is removed by an etching process, and the result is obtained the first gate dielectric layer 4;
  • the seventh region 401 is defined by photolithography, and the portion of the second gate dielectric located outside the seventh region 401 is removed by an etching process to obtain a second gate dielectric layer 5;
  • a fifth region 501 is defined by photolithography, and an etching process is used to remove the part of the polysilicon located outside the fifth region 501 and outside the surface of the first gate dielectric layer 4 to obtain a polysilicon gate 6;
  • a source region 7 is formed in the third region 301 of the body region 3 from the surface inward, and a drain region 8 is formed in the first region 201 of the drift region 2 from the surface inward, and the depth of the drain region 8 is greater than The depth of the source region 7 is described.
  • the drift region 2 and the body region 3 are formed by an ion implantation process; the source region 7 and the drain region 8 are formed by a heavily doped ion implantation process.
  • the substrate 1 is a substrate of the second conductivity type
  • the drift region 2 is implanted with ions of the first conductivity type
  • the body region 3 is implanted with ions of the second conductivity type
  • the ion implantation amount of the drain region 8 is greater than the ion implantation amount of the source region 7 , and the ion implantation energy of the drain region 8 is increased by three energy gradients compared with the ion implantation energy of the source region 7 .
  • a larger junction depth is obtained by increasing the ion implantation dose and energy of the drain region 8 .
  • the gate dielectric layer of the LDMOS device is designed in a targeted manner, and a double-layer gate dielectric layer is used in the main part of the drift region.
  • the first gate dielectric is SiO 2
  • the second gate dielectric is high dielectric. Constant gate dielectric.
  • the material in contact with the drift region and the body region is SiO 2 , which makes full use of the good interface contact characteristics of SiO 2 and silicon-based materials. A higher field effect is generated between the silicon bottom channels.
  • the gate structure formed by the superposition of the double-layer gate dielectric and the polysilicon gate in the drift region plays a field plate modulation effect on the surface electric field of the drift region, thereby improving the breakdown voltage of the device and ensuring the performance of the entire power integrated circuit in a complex stress environment. performance.
  • the formation process of the drain region is innovated, and the ion implantation depth is enlarged by adjusting the ion implantation energy and dose of the drain region, so that the junction depth of the drain region is larger than that of the source region, thereby effectively improving the control ability of the drain region to the conductive channel and ensuring the load
  • the electrons can still be effectively collected by the drain region from the source region through the body region and the drift region, thereby significantly improving the electrical characteristics of the device.
  • Figures 1-8 show a typical example of an LDMOS device, the specific drift region, body region, first gate dielectric coverage region, second gate dielectric coverage region, polysilicon gate coverage region, source region And the specific size of the drain region is different according to the requirement parameters of the LDMOS device.
  • the ion implantation process, the heavily doped ion implantation process, the high temperature thermal oxidation growth process, the atomic layer deposition process, the photolithography and the etching process used in the present invention are all existing process methods. Not elaborated.

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Abstract

本发明提供一种高压非对称结构LDMOS器件及其制备方法。该LDMOS器件包括：漂移区和体区；漂移区的表面划分有第一区域和第二区域；体区的表面划分有第三区域和第四区域，第二区域和第四区域被第一栅介质层延伸覆盖；第一栅介质层的表面划分有第七区域，第七区域位于漂移区上方且被第二栅介质层覆盖；第二栅介质层的表面划分有第六区域和第五区域，第五区域以及第七区域以外的第一栅介质层被多晶硅栅延伸覆盖；漂移区的第一区域由表面向内形成有漏区；体区的第三区域由表面向内形成有源区，漏区深度大于源区深度。双层栅介质结构保障器件在高电压大电流条件下的工作可靠性。漏区结深大于源区结深，有效提升漏区对导电沟道的控制能力。

Description

高压非对称结构LDMOS器件及其制备方法 技术领域
本发明涉及半导体集成电路技术领域，具体地涉及一种高压非对称结构LDMOS器件以及一种高压非对称结构LDMOS器件的制备方法。
背景技术
随着时代发展，如今功率半导体器件已经渗透进了国民经济生活的各个方面。近年来，节能环保已成为全球日益关注的话题，半导体的应用领域也已从传统的工业控制、通信、计算机、消费电子扩展到了新能源、智能电网、轨道交通、汽车电子等新领域。功率半导体器件追求的是对电能的处理，要求其本身具有高耐压和大电流特性。
横向双扩散金属氧化物半导体场效应管(Lateral Double-Diffused MOSFET，LDMOS)作为一种横向功率器件，其电极均位于器件表面，易于通过内部连接实现与低压信号电路以及其它器件的单片集成，同时又具有耐压高、增益大、线性度好、效率高、宽带匹配性能好等优点，如今已被广泛应用于功率集成电路中，尤其是低功耗和高频电路。尤为关键的是，LDMOS结构设计的优劣以及LDMOS自身工作的可靠性决定了整个功率集成电路的性能。
双扩散的工艺特点使得LDMOS在不需要高精度的光刻工艺的时候依然能做出很短的沟道，因此，LDMOS的跨导和频率特性显著提高。LDMOS的设计主要围绕着击穿电压和特征导通电阻之间的合理折衷来进行，通过增长漂移区长度来提高器件耐压会导致器件导通电阻急剧增加。因此，亟需通过器件的优化设计和工艺改进全面保障器件的电特性和可靠性。
发明内容
本发明实施方式的目的是提供一种高压非对称结构LDMOS器件及其制备方法，该LDMOS器件在漂移区主体部分设置双层栅介质结构，并且和多晶硅栅叠加而成的栅极结构对漂移区的表面电场起到场板调制作用，提高器件击穿电压，保障器件在高电压大电流条件下的工作可靠性；设置了源漏非对称结构，漏区结深大于源区结深，有效提升漏区对导电沟道的控制能力，从而显著提升器件的电特性，该制备方法扩大离子注入深度，形成漏区结深要大于源区结深，从而有效提升漏区对导电沟道的控制能力，保证载流子从源区出发经由体区和漂移区依然能够被漏区有效收集，从而显著提升器件的电特性。
为了实现上述目的，本发明第一方面提供一种高压非对称结构LDMOS器件，所述LDMOS器件包括：所述LDMOS器件具有：漂移区和体区；所述漂移区的表面划分有第一区域和第二区域；所述体区的表面划分有第三区域和第四区域，所述第二区域和所述第四区域被第一栅介质层延伸覆盖；所述第一栅介质层的表面划分有第七区域，所述第七区域位于所述漂移区上方且被第二栅介质层覆盖；所述第二栅介质层的表面划分有第六区域和第五区域，所述第五区域以及所述第七区域以外的所述第一栅介质层被多晶硅栅延伸覆盖；所述漂移区的第一区域由表面向内形成有漏区；所述体区的第三区域由表面向内形成有源区，所述漏区深度大于所述源区深度。
可选的，所述LDMOS器件还包括衬底，所述衬底划分有第九区域、用于形成所述漂移区的第十区域以及用于形成所述体区的第八区域；所述第十区域与所述第八区域相接触或由所述第九区域间隔开。
进一步地，所述漂移区为第一导电类型的漂移区，所述体区为第二导电类型的体区，所述衬底为第二导电类型的衬底。
可选地，所述第一导电类型为N型，所述第二导电类型为P型，在这种配型下LDMOS器件为N型器件；或者所述第一导电类型为P型，所述第二导电类型 为N型，在这种配型下LDMOS器件为P型器件。
可选的，所述第一栅介质层为SiO 2层，所述第二栅介质层为高介电常数栅介质层。第二栅介质层生长厚度小于第一栅介质层，且仅纵向来看仅能覆盖漂移区的部分区域，针对漂移区的耐压设计提出双层栅介质结构有助于提升器件在大电压和大电流应力下的可靠性。
本发明第二方面提供一种高压非对称结构LDMOS器件的制备方法，所述制备方法包括：
S1：在衬底上划分出第八区域，形成体区；划分出第十区域，形成漂移区；
S2：在所述漂移区表面划分出第一区域和第二区域；在所述体区的表面划分出第三区域和第四区域，所述第二区域与所述第四区域相临接；
S3：在与所述漂移区和所述体区相接触一侧的所述衬底表面生长第一栅介质；
S4：去除所述第一栅介质位于所述第二区域之外且位于第四区域之外的部分，得到第一栅介质层；
S5：在所述第一栅介质层表面划分出第七区域；
S6：在所述第一栅介质层表面一侧生长第二栅介质；
S7：去除所述第二栅介质位于所述第七区域之外的部分，得到第二栅介质层；
S8：在所述第二栅介质层表面划分出第五区域和第六区域；
S9：在所述第二栅介质层表面一侧生长多晶硅；
S10：去除所述多晶硅位于第五区域之外且位于第一栅介质层表面之外的部分，得到多晶硅栅；
S11：在所述体区的第三区域由表面向内形成源区，在所述漂移区的第一区域由表面向内形成漏区，所述漏区深度大于所述源区深度。
可选的，所述漂移区和所述体区通过离子注入工艺形成；所述源区和所述漏区通过重掺杂离子注入工艺形成。
进一步地，所述衬底为第二导电类型的衬底，所述漂移区注入第一导电类型的离子，所述体区注入第二导电类型的离子，所述源区和所述漏区分别注入第一导电类型的离子。
进一步地，所述漏区离子注入量大于所述源区离子注入量，且所述漏区离子注入能量相比所述源区离子注入能量上升三个能量梯度。通过加大漏区的离子注入剂量和能量获得较大的结深。
可选的，步骤S4中，去除所述第一栅介质位于所述第二区域之外且位于第四区域之外的部分，得到第一栅介质层，包括：
光刻定义出所述第二区域和所述第四区域，采用刻蚀工艺去除第一栅介质位于所述第二区域之外且位于所述第四区域之外的部分，得到第一栅介质层；
步骤S7中，去除所述第二栅介质位于所述第七区域之外的部分，得到第二栅介质层，包括：
光刻定义出所述第七区域，采用刻蚀工艺去除所述第二栅介质位于所述第七区域之外的部分，得到第二栅介质层；
步骤S10中，去除所述多晶硅位于第五区域之外且位于第一栅介质层表面之外的部分，得到多晶硅栅，包括：
光刻定义出第五区域，采用刻蚀工艺去除所述多晶硅位于第五区域之外且位于第一栅介质层表面之外的部分，得到多晶硅栅。
通过上述技术方案，对LDMOS器件的栅介质层进行了有针对性的设计，在漂移区的主体部分采用了双层栅介质层，第一栅介质为SiO 2，第二栅介质为高介电常数栅介质。与漂移区和体区相接触的材料采用SiO 2，充分利用SiO 2和硅基材料良好的界面接触特性，第二栅介质则充分利用high-k材料较好的绝缘属性，且能够在栅和硅底层通道之间产生较高的场效应。
通过双层栅介质结构的设置，和现有结构相比，保障器件在高电压大电流条件下的工作可靠性。此外，位于漂移区的双层栅介质和多晶硅栅叠加而成的栅极 结构对漂移区的表面电场起到场板调制作用，从而提高器件击穿电压，保障整个功率集成电路在复杂应力环境下的性能。
创新了漏区的形成工艺，通过调整漏区的离子注入能量和剂量扩大离子注入深度，形成漏区结深要大于源区结深，从而有效提升漏区对导电沟道的控制能力，保证载流子从源区出发经由体区和漂移区依然能够被漏区有效收集，从而显著提升器件的电特性。
本发明实施方式的其它特征和优点将在随后的具体实施方式部分予以详细说明。
附图说明
附图是用来提供对本发明实施方式的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明实施方式，但并不构成对本发明实施方式的限制。在附图中：
图1是本发明第一种实施方式提供的高压非对称结构LDMOS器件结构示意图；
图2是本发明第一种实施方式提供的高压非对称结构LDMOS器件分解示意图A；
图3是本发明第一种实施方式提供的高压非对称结构LDMOS器件分解示意图B；
图4是本发明第一种实施方式提供的高压非对称结构LDMOS器件分解示意图C；
图5是本发明第一种实施方式提供的高压非对称结构LDMOS器件分解示意图D；
图6本发明第一种实施方式提供的高压非对称结构LDMOS器件分解示意图E；
图7本发明第一种实施方式提供的高压非对称结构LDMOS器件分解示意图 F；
图8是本发明第二种实施方式提供的高压非对称结构LDMOS器件结构示意图；
图9是本发明一种实施方式提供的高压非对称结构LDMOS器件的制备方法流程图。
附图标记说明
图中，1-衬底，101-第十区域，102-第八区域，103-第九区域，2-漂移区，201-第一区域，202-第二区域，3-体区，301-第三区域，302-第四区域，4-第一栅介质层，401-第七区域，5-第二栅介质层，501-第五区域，502-第六区域，6-多晶硅栅，7-源区，8-漏区。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
在本申请实施例中，在未作相反说明的情况下，使用的方位词如“上、下、左、右”通常是指基于附图所示的方位或位置关系。术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
实施例一
图1是本发明第一种实施方式提供的高压非对称结构LDMOS器件结构示意图。在本实施例中，LDMOS器件的漂移区2和体区3横向接触。
具体参考图1到图7所示，所述LDMOS器件具有：漂移区2和体区3；所述漂移区2的表面划分有第一区域201和第二区域202；所述体区3的表面划分有第三区域301和第四区域302，所述第二区域202和所述第四区域302被第一栅介质层4延伸覆盖；所述第一栅介质层4的表面划分有第七区域401，所述第七区域401位于所述漂移区2上方且被第二栅介质层5覆盖；所述第二栅介质层 5的表面划分有第六区域502和第五区域501，所述第五区域501以及所述第七区域401以外的所述第一栅介质层4被多晶硅栅6延伸覆盖；所述漂移区2第一区域201由表面向内形成有漏区8；所述体区3的第三区域301由表面向内形成有源区7，所述漏区8深度大于所述源区7深度。源区7和漏区8采用非对称结构，且源区7和漏区8不是同时注入形成，漏区8离子注入剂量和能量都在源区7的基础上加大，能够获得较大的结深，从而有效提升漏区8对导电沟道的控制能力，保证载流子从源区7出发经由体区3和漂移区2依然能够被漏区8有效收集，从而显著提升器件的电特性。
所述LDMOS器件还包括衬底1，所述衬底1划分有第九区域103、用于形成所述漂移区2的第十区域101以及用于形成所述体区3的第八区域102；在本实施例中所述第十区域101与所述第八区域102相接触。
进一步地，所述漂移区2为第一导电类型的漂移区，所述体区3为第二导电类型的体区，所述衬底1为第二导电类型的衬底。
所述第一导电类型为N型，所述第二导电类型为P型，在这种配型下LDMOS器件为N型器件；或者所述第一导电类型为P型，所述第二导电类型为N型，在这种配型下LDMOS器件为P型器件。
所述第一栅介质层4为高温热氧化生长的SiO 2层，与漂移区2和体区3的表面接触并覆盖第二区域202和第四区域302。所述第二栅介质层5为高介电常数栅介质层。高介电常数栅介质可选用Al 2O 3，Al 2O 3通过原子层沉积工艺生长在第一栅介质4上。第二栅介质5生长厚度小于第一栅介质4，且仅纵向来看仅能覆盖漂移区2的部分区域，针对提升器件的耐压特性，在漂移区上方局部区域进行了双层栅介质结构的设计，有助于提升器件在大电压和大电流应力下的可靠性。
实施例二
图8是本发明第二种实施方式提供的高压非对称结构LDMOS器件结构示意 图。在本实施例中，LDMOS器件的漂移区2和体区3横向相间隔，通过衬底1的第九区域103间隔开。
图9是本发明一种实施方式提供的高压非对称结构LDMOS器件的制备方法流程图，如图9所示，所述制备方法包括：
S1：在衬底上划分出第八区域102，形成体区3；划分出第十区域101，形成漂移区2；
S2：在所述漂移区2表面划分出第一区域201和第二区域202；在所述体区3的表面划分出第三区域301和第四区域302，所述第二区域202与所述第四区域302相临接；
S3：在与所述漂移区2和所述体区3接触一侧的所述衬底1表面生长第一栅介质；
S4：去除所述第一栅介质位于所述第二区域202之外且位于第四区域302之外的部分，得到第一栅介质层4，包括：
光刻定义出所述第二区域202和所述第四区域302，采用刻蚀工艺去除第一栅介质位于所述第二区域202之外且位于所述第四区域302之外的部分，得到第一栅介质层4；
S5：在所述第一栅介质层4表面划分出第七区域401；
S6：在所述第一栅介质层4表面一侧生长第二栅介质；
S7：去除所述第二栅介质位于所述第七区域401之外的部分，得到第二栅介质层5，包括：
光刻定义出所述第七区域401，采用刻蚀工艺去除所述第二栅介质位于所述第七区域401之外的部分，得到第二栅介质层5；
S8：在所述第二栅介质层5表面划分出第五区域501和第六区域502；
S9：在所述第二栅介质层5表面一侧生长多晶硅；
S10：去除所述多晶硅位于第五区域501之外且位于第一栅介质层4表面之 外的部分，得到多晶硅栅6，包括：
光刻定义出第五区域501，采用刻蚀工艺去除所述多晶硅位于第五区域501之外且位于第一栅介质层4表面之外的部分，得到多晶硅栅6；
S11：在所述体区3的第三区域301由表面向内形成源区7，在所述漂移区2的第一区域201由表面向内形成漏区8，所述漏区8深度大于所述源区7深度。
所述漂移区2和所述体区3通过离子注入工艺形成；所述源区7和所述漏区8通过重掺杂离子注入工艺形成。
所述衬底1为第二导电类型的衬底，所述漂移区2注入第一导电类型的离子，所述体区3注入第二导电类型的离子，所述源区7和所述漏区8分别注入第一导电类型的离子。
所述漏区8离子注入量大于所述源区7离子注入量，且所述漏区8离子注入能量相比所述源区7离子注入能量上升三个能量梯度。通过加大漏区8的离子注入剂量和能量获得较大的结深。
通过上述技术方案，对LDMOS器件的栅介质层进行了有针对性的设计，在漂移区的主体部分采用了双层栅介质层，第一栅介质为SiO 2，第二栅介质为高介电常数栅介质。与漂移区和体区相接触的材料采用SiO 2，充分利用SiO 2和硅基材料良好的界面接触特性，第二栅介质则充分利用high-k材料较好的绝缘属性，且能够在栅和硅底层通道之间产生较高的场效应。
通过双层栅介质结构的设置，和现有结构相比，保障器件在高电压大电流条件下的工作可靠性。此外，位于漂移区的双层栅介质和多晶硅栅叠加而成的栅极结构对漂移区的表面电场起到场板调制作用，从而提高器件击穿电压，保障整个功率集成电路在复杂应力环境下的性能。
创新了漏区的形成工艺，通过调整漏区的离子注入能量和剂量扩大离子注入深度，形成漏区结深要大于源区结深，从而有效提升漏区对导电沟道的控制能力，保证载流子从源区出发经由体区和漂移区依然能够被漏区有效收集，从而显著提 升器件的电特性。
需要说明的是，图1-图8所示为LDMOS器件的一种典型示例，具体的漂移区、体区、第一栅介质覆盖区域、第二栅介质覆盖区域、多晶硅栅覆盖区域、源区以及漏区的具体尺寸根据LDMOS器件的需求参数不同而不同。另一方面，本发明中所使用的离子注入工艺、重掺杂离子注入工艺、高温热氧化生长工艺、原子层沉积工艺、光刻、刻蚀工艺均为现有的工艺方法，在本发明中不作详细阐述。
以上结合附图详细描述了本发明的可选实施方式，但是，本发明实施方式并不限于上述实施方式中的具体细节，在本发明实施方式的技术构思范围内，可以对本发明实施方式的技术方案进行多种简单变型，这些简单变型均属于本发明实施方式的保护范围。另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合。为了避免不必要的重复，本发明实施方式对各种可能的组合方式不再另行说明。
此外，本发明的各种不同的实施方式之间也可以进行任意组合，只要其不违背本发明实施方式的思想，其同样应当视为本发明实施方式所公开的内容。

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  1. 一种高压非对称结构LDMOS器件，其特征在于，所述LDMOS器件具有：漂移区和体区；所述漂移区的表面划分有第一区域和第二区域；所述体区的表面划分有第三区域和第四区域，所述第二区域和所述第四区域被第一栅介质层延伸覆盖；所述第一栅介质层的表面划分有第七区域，所述第七区域位于所述漂移区上方且被第二栅介质层覆盖；所述第二栅介质层的表面划分有第六区域和第五区域，所述第五区域以及所述第七区域以外的所述第一栅介质层被多晶硅栅延伸覆盖；所述漂移区的第一区域由表面向内形成有漏区；所述体区的第三区域由表面向内形成有源区，所述漏区深度大于所述源区深度。
  2. 根据权利要求1所述的高压非对称结构LDMOS器件，其特征在于，所述LDMOS器件还包括衬底，所述衬底划分有第九区域、用于形成所述漂移区的第十区域以及用于形成所述体区的第八区域；所述第十区域与所述第八区域相接触或由所述第九区域间隔开。
  3. 根据权利要求2所述的高压非对称结构LDMOS器件，其特征在于，所述漂移区为第一导电类型的漂移区，所述体区为第二导电类型的体区，所述衬底为第二导电类型的衬底。
  4. 根据权利要求3所述的高压非对称结构LDMOS器件，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型；或者所述第一导电类型为P型，所述第二导电类型为N型。
  5. 根据权利要求1所述的高压非对称结构LDMOS器件，其特征在于，所述第一栅介质层为SiO 2层，所述第二栅介质层为高介电常数栅介质层。
  6. 一种高压非对称结构LDMOS器件的制备方法，其特征在于，所述制备方法包括：
    S1：在衬底上划分出第八区域，形成体区；划分出第十区域，形成漂移区；
    S2：在所述漂移区表面划分出第一区域和第二区域；在所述体区的表面划分出第三区域和第四区域，所述第二区域与所述第四区域相临接；
    S3：在与所述漂移区和所述体区相接触一侧的所述衬底表面生长第一栅介质；
    S4：去除所述第一栅介质位于所述第二区域之外且位于第四区域之外的部分，得到第一栅介质层；
    S5：在所述第一栅介质层表面划分出第七区域；
    S6：在所述第一栅介质层表面一侧生长第二栅介质；
    S7：去除所述第二栅介质位于所述第七区域之外的部分，得到第二栅介质层；
    S8：在所述第二栅介质层表面划分出第五区域和第六区域；
    S9：在所述第二栅介质层表面一侧生长多晶硅；
    S10：去除所述多晶硅位于第五区域之外且位于第一栅介质层表面之外的部分，得到多晶硅栅；
    S11：在所述体区的第三区域由表面向内形成源区，在所述漂移区的第一区域由表面向内形成漏区，所述漏区深度大于所述源区深度。
  7. 根据权利要求6所述的高压非对称结构LDMOS器件的制备方法，其特征在于，所述漂移区和所述体区通过离子注入工艺形成；所述源区和所述漏区通过重掺杂离子注入工艺形成。
  8. 根据权利要求7所述的高压非对称结构LDMOS器件的制备方法，其特征在于，所述衬底为第二导电类型的衬底，所述漂移区注入第一导电类型的离子，所述体区注入第二导电类型的离子，所述源区和所述漏区分别注入第一导电类型 的离子。
  9. 根据权利要求8所述的高压非对称结构LDMOS器件的制备方法，其特征在于，所述漏区离子注入量大于所述源区离子注入量，且所述漏区离子注入能量相比所述源区离子注入能量上升三个能量梯度。
  10. 根据权利要求6所述的高压非对称结构LDMOS器件的制备方法，其特征在于，步骤S4中，去除所述第一栅介质位于所述第二区域之外且位于第四区域之外的部分，得到第一栅介质层，包括：
    光刻定义出所述第二区域和所述第四区域，采用刻蚀工艺去除第一栅介质上位于所述第二区域之外且位于所述第四区域之外的部分，得到第一栅介质层；
    步骤S7中，去除所述第二栅介质位于所述第七区域之外的部分，得到第二栅介质层，包括：
    光刻定义出所述第七区域，采用刻蚀工艺去除所述第二栅介质位于所述第七区域之外的部分，得到第二栅介质层；
    步骤S10中，去除所述多晶硅位于第五区域之外且位于第一栅介质层表面之外的部分，得到多晶硅栅，包括：
    光刻定义出第五区域，采用刻蚀工艺去除所述多晶硅位于第五区域之外且位于第一栅介质层表面之外的部分，得到多晶硅栅。
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