WO2022116263A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

Info

Publication number
WO2022116263A1
WO2022116263A1 PCT/CN2020/136300 CN2020136300W WO2022116263A1 WO 2022116263 A1 WO2022116263 A1 WO 2022116263A1 CN 2020136300 W CN2020136300 W CN 2020136300W WO 2022116263 A1 WO2022116263 A1 WO 2022116263A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
data line
display panel
color resist
substrate layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/136300
Other languages
English (en)
French (fr)
Inventor
葛先进
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US17/254,928 priority Critical patent/US11860493B2/en
Publication of WO2022116263A1 publication Critical patent/WO2022116263A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines

Definitions

  • the present invention relates to the field of display technology, in particular to a display panel and a display device.
  • liquid crystal display panels have been widely used. Most of the liquid crystal display panels on the market are backlit liquid crystal display panels, which include liquid crystal panels and backlight modules. Module).
  • the working principle of the liquid crystal display panel is to inject liquid crystal molecules between the thin film transistor array substrate and the color filter substrate, and apply a driving voltage on the two substrates to control the rotation direction of the liquid crystal molecules, so as to refract the light from the backlight module to generate screen.
  • the thin film transistor array substrate includes a plurality of gate lines and data lines, and a plurality of gate lines and a plurality of data lines perpendicular to each other form a plurality of pixel units, and each pixel unit is provided with a thin film transistor, a pixel electrode and a storage capacitors, etc.
  • the gate line is driven, the thin film transistor is in an on state, and a gray-scale voltage signal is sent to the corresponding data and loaded to the pixel electrode, so that a corresponding electric field is generated between the pixel electrode and the common electrode.
  • the liquid crystal molecules change their orientation under the action of an electric field to achieve different image displays.
  • the crosstalk phenomenon usually occurs in the existing liquid crystal display panel.
  • the main reason is that the Cpd (coupling capacitance) of the pixel electrode and the data signal line is too large, so that the Pixel (pixel) potential is affected by the data signal, resulting in brightness changes.
  • the pixel size becomes smaller and smaller, especially for the 8K display panel, the thickness of the data signal trace increases, which increases the Cpd and the vertical crosstalk phenomenon will be more serious; by increasing the data signal trace
  • the method of reducing the Cpd by the distance between the line and the pixel electrode will seriously lose the aperture ratio of the pixel, resulting in a decrease in the transmittance of the liquid crystal display of the panel.
  • the present invention provides a display panel and a display device, which improve the vertical crosstalk problem of the display panel and improve the aperture ratio of pixels.
  • the present invention provides a display panel, comprising:
  • a color resist layer disposed on the substrate layer, located on both sides of the data line, and having a groove, and the groove is located at least on one side of the data line;
  • the pixel electrode layer is disposed above the color resist layer and the shielding layer.
  • the color resist layer is located on both sides of the data line and extends above the data line, covering the data line.
  • the number of the trenches is greater than or equal to 1, and the trenches are at least correspondingly located above one side of the data line.
  • the shielding layer closely covers at least part of the inner wall of the groove according to the shape of the groove.
  • the projection of the shielding layer on the substrate layer covers at least part of the projection of the data lines on the substrate layer.
  • the projection of the shielding layer on the substrate layer covers the projection of all the data lines on the substrate layer.
  • the depth of the trench is smaller than the thickness of the color resist layer located on both sides of the data line.
  • the pixel electrode layer includes a plurality of pixel electrodes, and the projections of the plurality of pixel electrodes on the substrate layer are at least partially the projection of the shielding layer on the substrate layer. overlapping.
  • the display panel further includes a passivation layer, the passivation layer is disposed between the shielding layer and the pixel electrode layer, and covers the shielding layer and the color barrier layer.
  • the display panel further includes a protective layer, and the protective layer is disposed on the substrate layer and covers the data lines.
  • the present invention also provides a display device, the display device includes a display panel, and the display panel includes:
  • a color resist layer disposed on the substrate layer, located on both sides of the data line, and having a groove, and the groove is located at least on one side of the data line;
  • the pixel electrode layer is disposed above the color resist layer and the shielding layer.
  • the color resist layer is located on both sides of the data line and extends above the data line, covering the data line.
  • the number of the trenches is greater than or equal to 1, and the trenches are at least correspondingly located above one side of the data line.
  • the shielding layer closely covers at least part of the inner wall of the groove according to the shape of the groove.
  • the projection of the shielding layer on the substrate layer covers at least part of the projection of the data lines on the substrate layer.
  • the projection of the shielding layer on the substrate layer covers the projection of all the data lines on the substrate layer.
  • the depth of the trench is smaller than the thickness of the color resist layer located on both sides of the data line.
  • the pixel electrode layer includes a plurality of pixel electrodes, and the projections of the plurality of pixel electrodes on the substrate layer are at least partially the projection of the shielding layer on the substrate layer. overlapping.
  • the display panel further includes a passivation layer, the passivation layer is disposed between the shielding layer and the pixel electrode layer, and covers the shielding layer and the color barrier layer.
  • the display panel further includes a protective layer, and the protective layer is disposed on the substrate layer and covers the data lines.
  • the color resist layer is thinned by arranging grooves in the color resist layer on at least one side of the data line, and a shielding layer is provided above the data line. , effectively reducing the coupling capacitance, thereby improving the vertical crosstalk problem of the display panel; and the passivation layer is arranged between the shielding layer and the pixel electrode layer, separating the shielding layer and the pixel electrode layer, and improving the aperture ratio of the pixel.
  • FIG. 1 is a schematic top-view structural diagram of a pixel unit of a display panel according to an embodiment of the present invention
  • Fig. 2 is a partial enlarged schematic diagram at A in Fig. 1;
  • FIG. 3 is a schematic cross-sectional view at A in FIG. 1 .
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • the present invention aims at the problem that vertical crosstalk tends to be serious as the pixel size shrinks in the existing display panel, and the aperture ratio of the pixel will be seriously lost by increasing the distance between the data line and the pixel electrode to reduce the coupling capacitance.
  • the embodiments of the present invention are used to solve this problem.
  • FIG. 1 is a schematic top view of a pixel unit of a display panel according to an embodiment of the present invention
  • FIG. 2 is a partial enlarged schematic diagram of part A in FIG. 1
  • FIG. 3 is a schematic cross-sectional schematic diagram of part A in FIG. 1 .
  • an embodiment of the present invention provides a display panel, including: a substrate layer 101 ; a data line 102 disposed on the substrate layer 101 ; a color resist layer 104 disposed on the substrate layer 101 , located on both sides of the data line 102, and has grooves 1041, the grooves 1041 are located at least on one side of the data line 102; the shielding layer 105 is disposed on the color resist layer 104 and located in the data Above the line 102 ; and the pixel electrode layer 107 , disposed above the color resist layer 104 and the shielding layer 105 .
  • the substrate layer 101 may include a TFT device, and the TFT device includes a source electrode, a drain electrode, an active layer and a gate electrode.
  • the data line 102 is connected to the source electrode, and the pixel electrode layer 107 is connected to the drain electrode.
  • the color resist layer 104 may include a plurality of sub color resist layers, and the sub color resist layers may be a red color resist layer, a green color resist layer or a blue color resist layer.
  • the density of the filling pattern can indicate different sub-color resistance layers.
  • the sub-color-resistance layer on the left side of the figure is a red color-resist layer
  • the sub-color-resistance layer on the right side of the figure is Green color resist layer.
  • the color resist layer 104 is located on both sides of the data line 102 and extends above the data line 102 to cover the data line 102 .
  • the sub-color resist layers located on both sides of the data line 102 extend above the data line 102 and cover the data line 102 .
  • the number of the trenches disposed on the color resist layer 104 is greater than or equal to 1, and the trenches 1041 are at least correspondingly located above one side of the data line 102 . As shown in FIG. 3 , in this embodiment, the number of the trenches 1041 is 2, and the trenches 1041 are symmetrically distributed above the two sides of the data line 102 . Those skilled in the art can understand that, in other embodiments of the present invention, the number of the trenches 1041 is not limited, and the trenches 1041 may be located asymmetrically on at least one side of the data line 102 .
  • the display panel provided in this embodiment further includes a passivation layer 106 , and the passivation layer 106 is disposed between the shielding layer 105 and the pixel electrode layer 107 and covers the shielding layer 105 and the pixel electrode layer 107 . the color resist layer 104 .
  • the color resist layer 104 is provided with the grooves 1041 , and the grooves 1041 are at least correspondingly located above one side of the data lines 102 , so as to realize The color resist layer 104 on at least one side of the data line 102 is thinned, the shielding effect of the shielding layer 105 on the data line 102 is improved, and the data line 102 and the pixel electrode layer 107 are reduced.
  • the coupling capacitance between them can improve the vertical crosstalk problem of the display panel; and the passivation layer 106 is arranged between the shielding layer 105 and the pixel electrode layer 107 to connect the shielding layer 105 and the pixel electrode layer.
  • 107 is separated from each other to effectively avoid short circuit between the shielding layer 105 and the pixel electrode layer 107 , thereby effectively reducing the distance between the shielding layer 105 and the pixel electrode layer 107 and increasing the pixel aperture ratio.
  • the pixel electrode layer 107 includes a plurality of pixel electrodes 1071 , and the projections of the plurality of pixel electrodes 1071 on the substrate layer 101 at least partially overlap with the projections of the shielding layer 105 on the substrate layer 101 .
  • both the shielding layer 105 and the pixel electrode layer 107 can be made of ITO (Indium Tin Oxide).
  • the shielding layer 105 and the pixel electrode layer 107 are generally made of the same layer of ITO film. It is ensured that the distance between the shielding layer 105 and the pixel electrode layer 107 is greater than or equal to 4um. This limitation reduces the aperture ratio of the pixel.
  • the shielding layer 105 and the pixel electrode layer 107 are separated by the passivation layer 106, so that the shielding layer 105 and the pixel electrode layer 107 are in different layers.
  • the probability of a short circuit between the two is also greatly reduced, so it is no longer necessary to meet the original limitation of the distance between the two ⁇ 4um, and the pixel electrode layer 107 and the shielding layer can be designed to overlap in the vertical direction. That is, the projections of the pixel electrode 1071 and the shielding layer 105 on the substrate layer 101 may at least partially overlap, such as the structure shown in FIG. 3 , so that the pixel aperture ratio can be greatly improved.
  • the passivation layer 106 is preferably an organic passivation protection layer, and the material of the passivation layer 106 can be made of an organic material with acrylic as the main material.
  • the shielding layer 105 closely covers at least part of the inner wall of the groove 1041 according to the shape of the groove 1041 .
  • the thickness of the color resist layer 104 where the trenches 1041 are provided is reduced, that is, the thickness of the color resist layer 104 at the corresponding position is reduced by arranging the trenches 1041 .
  • the size of the coupling capacitance Cpd between the data line 102 and the pixel electrode layer 107 is mainly affected by the lateral capacitance.
  • the thinner the color resist layer 104 laterally covering the data line 102 is, the better the lateral shielding effect of the shielding layer 105 on the data line 102 is, and thus the better the shielding effect is. Therefore, according to the shape of the groove 1041 , the shielding layer 105 closely covers at least part of the inner wall of the groove 1041 , so as to achieve a better shielding effect on the data line 102 .
  • the projection of the shielding layer 105 on the substrate layer 101 covers at least part of the projection of the data lines 102 on the substrate layer 101 , so as to realize the shielding layer 105 to the data lines 102 shading effect.
  • the projection of the shielding layer 105 on the substrate layer 101 covers all the projections of the data lines 102 on the substrate layer 101 , thereby ensuring that the shielding layer 105 fully shields the data lines 102 Mask for better shielding.
  • the number of the trenches 1041 is 2, which are located above both sides of the data line 102 , and the length of the trenches 1041 is the same as the length of the pixel electrode 1071 . equal length. Since the pixel electrodes 1071 are arranged symmetrically, the two grooves 1041 are also arranged symmetrically.
  • the depth of the trench 1041 is smaller than the thickness of the color resist layer 104 located on both sides of the data line 102 .
  • the number of the grooves 1041 on both sides of the data line 102 can be different , the position can also be asymmetric.
  • the length of the trench 1041 is not limited to be the same length as the pixel electrode 1071 , and the trench 1041 can be segmented according to actual requirements, and even a plurality of the trenches located on the same side of the data line 102 The width and length of the grooves 1041 may also vary.
  • the formation of the trenches 1041 can be realized by adjusting the exposure amount of the corresponding position during the manufacturing process of the color resist layer 104 .
  • the color resist is a negative photoresist.
  • a slit pattern is designed on the mask to reduce the exposure amount at the corresponding position.
  • the groove 1041 is described.
  • the width of the slit pattern should be smaller than the resolution of the exposure machine, so as to avoid copying the slit pattern onto the color resist layer 104, that is, the color resist at the corresponding position is not changed after developing. All layers 104 are removed, but only to reduce the exposure of the corresponding positions of the slit pattern, forming the trenches 1041 with a depth smaller than the thickness of the color resist layer 104 in the areas on both sides of the data line 102 .
  • the color resist layer 104 at the corresponding position of the slit pattern will be thinned and removed entirely, but the color resist layer 104 at the corresponding position will be removed due to the development process
  • the color-resist layer 104 is gradually removed by the developer treatment. If the thickness of the color-resist layer 104 is too thin or the entire thickness of the color-resist layer is thinned, the color-resist layer in the adjacent display area may also be thinned, thereby affecting the thickness. Chroma effect for pixel units. Therefore, by adjusting the width, length and light intensity of the slit pattern, the grooves 1041 with various widths, lengths and different thinning depths can be finally obtained after exposure and development.
  • the formation of the grooves 1041 can be realized by designing a mask pattern with different light transmittances at corresponding positions in addition to the above-mentioned realization of designing the slit pattern in the mask, but is not limited thereto.
  • the display panel further includes a protective layer 103 , and the protective layer 103 is disposed on the substrate layer 101 and covers the data lines 102 .
  • the protective layer 103 can be made of insulating material, such as silicon oxide and/or silicon nitride.
  • the data line 102 is not affected.
  • an embodiment of the present invention also provides a display device, where the display device includes the display panel described in any one of the above.
  • the color resist layer is thinned by arranging grooves in the color resist layer on at least one side of the data line, and a shielding layer is provided above the data line , effectively reducing the coupling capacitance, thereby improving the vertical crosstalk problem of the display panel; and the passivation layer is arranged between the shielding layer and the pixel electrode layer, separating the shielding layer and the pixel electrode layer, and improving the aperture ratio of the pixel.
  • a display panel and a display device provided by the embodiments of the present invention have been introduced in detail above.
  • the principles and implementations of the present invention are described in this paper by using specific examples. The descriptions of the above embodiments are only used to help understand the present invention.
  • Those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements to some of the technical features; and these modifications or replacements, and The essence of the corresponding technical solutions is not deviated from the scope of the technical solutions of the embodiments of the present invention.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板和显示装置。显示面板包括：衬底层（101）；数据线（102），设于衬底层上；色阻层（104），设于衬底层上，位于数据线两侧且具有沟槽（1041），沟槽至少对应位于数据线一侧；屏蔽层（105），设于色阻层上并位于数据线上方；像素电极层（107），设于屏蔽层上方；钝化层（106），设于屏蔽层与像素电极层之间，覆盖屏蔽层和色阻层。

Description

显示面板和显示装置 技术领域
本发明涉及显示技术领域，具体涉及一种显示面板和显示装置。
 背景技术
随着科技的发展和进步，液晶显示面板得到了广泛应用。市场上的液晶显示面板大部分为背光型液晶显示面板，其包括液晶面板及背光模组(Backlight Module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板与彩膜基板之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
薄膜晶体管阵列基板包括多条栅极线和数据线，相互垂直的多条栅极线和多条数据线形成了多个像素单元，且每个像素单元内均设置有薄膜晶体管、像素电极及存储电容等。当栅极线被驱动时，薄膜晶体管处于导通状态，对应的数据下送入灰阶电压信号并将其加载至像素电极，从而使得像素电极与公共电极之间产生相应的电场，液晶层中的液晶分子则在电场的作用下发生取向变化，以实现不同的图像显示。
现有液晶显示面板通常会发生串扰现象，其主要原因是像素电极与数据信号走线的Cpd（耦合电容）过大，使Pixel（像素点）电位受到数据信号的影响从而产生亮度变化。随着液晶显示面板的分辨率逐渐升高，像素尺寸越来越小，特别对于8K显示面板，数据信号走线的厚度增加，使得Cpd增加，垂直串扰现象将更严重；而通过增加数据信号走线和像素电极之间的距离来减小Cpd的方式，将严重损失像素的开口率，造成面板的液晶显示穿透率降低。
 技术问题
本发明提供了一种显示面板和显示装置，改善了显示面板的垂直串扰问题，并提升了像素的开口率。
 技术解决方案
本发明提供了一种显示面板，包括：
衬底层；
数据线，设置于所述衬底层上；
色阻层，设置于所述衬底层上，位于所述数据线两侧，且具有沟槽，所述沟槽至少对应位于所述数据线一侧；
屏蔽层，设置于所述色阻层上并位于所述数据线上方；以及
像素电极层，设置于所述色阻层以及所述屏蔽层上方。
在本发明的一种实施例中，所述色阻层位于所述数据线两侧并延伸至所述数据线上方，覆盖所述数据线。
在本发明的一种实施例中，所述沟槽的数量大于或等于1，且所述沟槽至少对应位于所述数据线一侧的上方。
在本发明的一种实施例中，所述屏蔽层依据所述沟槽的形貌，贴合地覆盖所述沟槽的至少部分内壁。
在本发明的一种实施例中，所述屏蔽层在所述衬底层上的投影，覆盖至少部分所述数据线在所述衬底层上的投影。
在本发明的一种实施例中，所述屏蔽层在所述衬底层上的投影，覆盖全部所述数据线在所述衬底层上的投影。
在本发明的一种实施例中，所述沟槽的深度小于位于所述数据线两侧区域的所述色阻层的厚度。
在本发明的一种实施例中，所述像素电极层包括多个像素电极，多个所述像素电极在所述衬底层上的投影与所述屏蔽层在所述衬底层上的投影至少部分重叠。
在本发明的一种实施例中，所述显示面板还包括钝化层，所述钝化层设置于所述屏蔽层与所述像素电极层之间，并覆盖所述屏蔽层和所述色阻层。
在本发明的一种实施例中，所述显示面板还包括保护层，所述保护层设置于所述衬底层上并覆盖所述数据线。
本发明还提供了一种显示装置，所述显示装置包括显示面板，所述显示面板包括：
衬底层；
数据线，设置于所述衬底层上；
色阻层，设置于所述衬底层上，位于所述数据线两侧，且具有沟槽，所述沟槽至少对应位于所述数据线一侧；
屏蔽层，设置于所述色阻层上并位于所述数据线上方；以及
像素电极层，设置于所述色阻层以及所述屏蔽层上方。
在本发明的一种实施例中，所述色阻层位于所述数据线两侧并延伸至所述数据线上方，覆盖所述数据线。
在本发明的一种实施例中，所述沟槽的数量大于或等于1，且所述沟槽至少对应位于所述数据线一侧的上方。
在本发明的一种实施例中，所述屏蔽层依据所述沟槽的形貌，贴合地覆盖所述沟槽的至少部分内壁。
在本发明的一种实施例中，所述屏蔽层在所述衬底层上的投影，覆盖至少部分所述数据线在所述衬底层上的投影。
在本发明的一种实施例中，所述屏蔽层在所述衬底层上的投影，覆盖全部所述数据线在所述衬底层上的投影。
在本发明的一种实施例中，所述沟槽的深度小于位于所述数据线两侧区域的所述色阻层的厚度。
在本发明的一种实施例中，所述像素电极层包括多个像素电极，多个所述像素电极在所述衬底层上的投影与所述屏蔽层在所述衬底层上的投影至少部分重叠。
在本发明的一种实施例中，所述显示面板还包括钝化层，所述钝化层设置于所述屏蔽层与所述像素电极层之间，并覆盖所述屏蔽层和所述色阻层。
在本发明的一种实施例中，所述显示面板还包括保护层，所述保护层设置于所述衬底层上并覆盖所述数据线。
 有益效果
相较于现有技术，本发明提供的显示面板和显示装置，通过在数据线至少一侧的色阻层中设置沟槽，以实现将色阻层减薄，并在数据线上方设置屏蔽层，有效减小了耦合电容，从而改善显示面板的垂直串扰问题；而钝化层设置于屏蔽层与像素电极层之间，将屏蔽层与像素电极层隔开，提升了像素的开口率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的显示面板的像素单元的俯视结构示意图；
图2为图1中A处局部放大示意图；
图3为图1中A处截面示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本发明针对现有的显示面板中随着像素尺寸缩小，垂直串扰问题趋于严重，而通过增加数据线与像素电极之间的距离来减小耦合电容，将严重损失像素的开口率的问题，本发明实施例用以解决该问题。
图1为本发明实施例提供的显示面板的像素单元的俯视结构示意图；图2为图1中A处局部放大示意图；图3为图1中A处截面示意图。参见图1至图3，本发明实施例提供了一种显示面板，包括：衬底层101；数据线102，设置于所述衬底层101上；色阻层104，设置于所述衬底层101上，位于所述数据线102两侧，且具有沟槽1041，所述沟槽1041至少对应位于所述数据线102一侧；屏蔽层105，设置于所述色阻层104上并位于所述数据线102上方；以及像素电极层107，设置于所述色阻层104以及所述屏蔽层105上方。
在本实施例中，所述衬底层101可包括TFT器件，所述TFT器件包括源极、漏极、有源层和栅极。其中，所述数据线102与源极连接，所述像素电极层107与漏极连接。
可选的，所述色阻层104可以包括多个子色阻层，所述子色阻层可以为红色色阻层、绿色色阻层或蓝色色阻层。参见图3，填充图案的密度不同可表示不同的所述子色阻层，例如图示左侧的所述子色阻层为红色色阻层，图示右侧的所述子色阻层为绿色色阻层。
优选的，所述色阻层104位于所述数据线102两侧并延伸至所述数据线102上方，覆盖所述数据线102。具体地，即位于所述数据线102两侧的所述子色阻层延伸至所述数据线102上方，并覆盖所述数据线102。
进一步地，设置于所述色阻层104上的所述沟槽的数量大于或等于1，且所述沟槽1041至少对应位于所述数据线102一侧的上方。如图3所示，在本实施例中，所述沟槽1041的数量为2，且对称分布于所述数据线102两侧的上方。本领域技术人员可以理解，在本发明的其他实施例中，所述沟槽1041的数量不限，且可以非对称地位于所述数据线102至少一侧的上方。
优选的，本实施例提供的所述显示面板还包括钝化层106，所述钝化层106设置于所述屏蔽层105与所述像素电极层107之间，并覆盖所述屏蔽层105和所述色阻层104。
在本实施例提供的所述显示面板中，通过在所述色阻层104中设置有所述沟槽1041，且所述沟槽1041至少对应位于所述数据线102一侧的上方，从而实现将位于所述数据线102至少一侧的所述色阻层104减薄，提高所述屏蔽层105对所述数据线102的屏蔽作用，减小所述数据线102与所述像素电极层107之间的耦合电容，改善显示面板的垂直串扰问题；而在所述屏蔽层105与所述像素电极层107之间设置所述钝化层106，将所述屏蔽层105与所述像素电极层107隔开，有效避免所述屏蔽层105与所述像素电极层107之间发生短路，因而可有效减小所述屏蔽层105与所述像素电极层107之间的间距，提升像素开口率。
进一步地，所述像素电极层107包括多个像素电极1071，多个所述像素电极1071在所述衬底层101上的投影与所述屏蔽层105在所述衬底层101上的投影至少部分重叠。
具体地，所述屏蔽层105与所述像素电极层107的材料均可为ITO（氧化铟锡）。在现有的显示面板中，所述屏蔽层105与所述像素电极层107一般采用同一层ITO薄膜制成，为防止所述屏蔽层105与所述像素电极层107发生短路造成显示异常，需要确保所述屏蔽层105与所述像素电极层107之间的距离≥4um，这一限制使得像素的开口率降低。而在本发明实施例中，所述屏蔽层105与所述像素电极层107之间由所述钝化层106隔开，使得所述屏蔽层105与所述像素电极层107处于不同层，二者之间发生短路的概率也大大降低，故而无需再满足原有的二者之间的距离≥4um的限制，可实现将所述像素电极层107与所述屏蔽层在垂直方向交叠设计，也即所述像素电极1071与所述屏蔽层105在所述衬底层101上的投影可有至少部分是重叠的，例如图3中所示的结构，故而可大大提高像素开口率。
其中，所述钝化层106优选为有机钝化保护层，所述钝化层106的材料可为以丙烯酸为材料主体的有机材料制成。
优选的，所述屏蔽层105依据所述沟槽1041的形貌贴合地覆盖所述沟槽1041的至少部分内壁。
设置有所述沟槽1041处的所述色阻层104的厚度减小，也即通过设置所述沟槽1041实现对应位置的所述色阻层104减薄。
在显示面板中，所述数据线102与所述像素电极层107之间的耦合电容Cpd的大小，主要受侧向电容影响。参见图3所示，侧向覆盖所述数据线102的所述色阻层104越薄，所述屏蔽层105对所述数据线102的侧向遮蔽效果越好，因此屏蔽效果越好。故所述屏蔽层105依据所述沟槽1041的形貌，贴合地覆盖在所述沟槽1041的至少部分内壁，实现了对所述数据线102更好的屏蔽作用。
进一步地，所述屏蔽层105在所述衬底层101上的投影，覆盖至少部分所述数据线102在所述衬底层101上的投影，从而实现所述屏蔽层105对所述数据线102的遮蔽作用。
更进一步地，所述屏蔽层105在所述衬底层101上的投影，覆盖全部所述数据线102在所述衬底层101上的投影，从而确保所述屏蔽层105将所述数据线102充分遮蔽，以获得更好的屏蔽效果。
参见图1至图3，在本实施例中，所述沟槽1041的数量为2，对应位于所述数据线102两侧的上方，且所述沟槽1041的长度与所述像素电极1071的长度相等。由于所述像素电极1071对称设置，故两条所述沟槽1041亦呈对称设置。
进一步地，所述沟槽1041的深度小于位于所述数据线102两侧区域的所述色阻层104的厚度。
在本发明其他实施例中，当各像素单元有特殊需求需要调整所述数据线102左右两侧的耦合电容的大小时，位于所述数据线102两侧的所述沟槽1041的数量可以不同，位置也可不对称。并且，所述沟槽1041的长度不限于与所述像素电极1071等长，可根据实际需求将所述沟槽1041分段设置，而即使位于所述数据线102同一侧的多条所述沟槽1041的宽度和长度也可各不相同。
其中，所述沟槽1041的形成可通过在所述色阻层104制作过程中调整对应位置的曝光量实现。
具体地，色阻为负性光阻。在所述色阻层104需要减薄的位置，也即在所述沟槽1041的形成位置，通过在掩膜版上设计狭缝图案以减小对应位置的曝光量，经显影后可形成所述沟槽1041。其中，所述狭缝图案的宽度应小于曝光机的分辨率，以避免将所述狭缝图案复制到所述色阻层104上，也即经显影后并未将对应位置的所述色阻层104全部去除，而是仅起到减小所述狭缝图案对应位置的曝光量的作用，形成深度小于所述数据线102两侧区域的所述色阻层104厚度的所述沟槽1041。
进一步地，当所述狭缝图案的宽度大于曝光机的分辨率时，所述狭缝图案对应位置的所述色阻层104将被全部减薄去除，然而由于显影过程去除对应位置的所述色阻层104是经显影液处理逐步去除的，若所述色阻层104减薄的深度过大或是全部减薄，将可能导致相邻显示区的色阻层也被减薄，进而影响像素单元的色度效果。故而可通过调整所述狭缝图案的宽度、长度以及光照强度，使得最终经曝光显影后得到多种宽度、长度以及不同减薄深度的所述沟槽1041。
更进一步地，所述沟槽1041的形成除上述的在掩膜版设计所述狭缝图案实现以外，还可以在对应位置设计光线透过率不同的光罩图案实现，且不限于此。
优选的，所述显示面板还包括保护层103，所述保护层103设置于所述衬底层101上并覆盖所述数据线102。所述保护层103可由绝缘材料制成，例如可以由氧化硅和/或氮化硅制成，所述保护层103覆盖所述数据线102，以使在所述色阻层104形成过程中所述数据线102不受影响。
进一步地，本发明实施例还提供了一种显示装置，所述显示装置包括上述任一项所述的显示面板。
综上所述，本发明实施例提供的显示面板和显示装置，通过在数据线至少一侧的色阻层中设置沟槽，以实现将色阻层减薄，并在数据线上方设置屏蔽层，有效减小了耦合电容，从而改善显示面板的垂直串扰问题；而钝化层设置于屏蔽层与像素电极层之间，将屏蔽层与像素电极层隔开，提升了像素的开口率。
以上对本发明实施例所提供的一种显示面板和显示装置进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，所述显示面板包括：
    衬底层；
    数据线，设置于所述衬底层上；
    色阻层，设置于所述衬底层上，位于所述数据线两侧，且具有沟槽，所述沟槽至少对应位于所述数据线一侧；
    屏蔽层，设置于所述色阻层上并位于所述数据线上方；以及
    像素电极层，设置于所述色阻层以及所述屏蔽层上方。
  2. 根据权利要求1所述的显示面板，其中，所述色阻层位于所述数据线两侧并延伸至所述数据线上方，覆盖所述数据线。
  3. 根据权利要求2所述的显示面板，其中，所述沟槽的数量大于或等于1，且所述沟槽至少对应位于所述数据线一侧的上方。
  4. 根据权利要求1所述的显示面板，其中，所述屏蔽层依据所述沟槽的形貌，贴合地覆盖所述沟槽的至少部分内壁。
  5. 根据权利要求1所述的显示面板，其中，所述屏蔽层在所述衬底层上的投影，覆盖至少部分所述数据线在所述衬底层上的投影。
  6. 根据权利要求5所述的显示面板，其中，所述屏蔽层在所述衬底层上的投影，覆盖全部所述数据线在所述衬底层上的投影。
  7. 根据权利要求1所述的显示面板，其中，所述沟槽的深度小于位于所述数据线两侧区域的所述色阻层的厚度。
  8. 根据权利要求1所述的显示面板，其中，所述像素电极层包括多个像素电极，多个所述像素电极在所述衬底层上的投影与所述屏蔽层在所述衬底层上的投影至少部分重叠。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板还包括钝化层，所述钝化层设置于所述屏蔽层与所述像素电极层之间，并覆盖所述屏蔽层和所述色阻层。
  10. 根据权利要求1所述的显示面板，其中，所述显示面板还包括保护层，所述保护层设置于所述衬底层上并覆盖所述数据线。
  11. 一种显示装置，所述显示装置包括显示面板，所述显示面板包括：
    衬底层；
    数据线，设置于所述衬底层上；
    色阻层，设置于所述衬底层上，位于所述数据线两侧，且具有沟槽，所述沟槽至少对应位于所述数据线一侧；
    屏蔽层，设置于所述色阻层上并位于所述数据线上方；以及
    像素电极层，设置于所述色阻层以及所述屏蔽层上方。
  12. 根据权利要求11所述的显示装置，其中，所述色阻层位于所述数据线两侧并延伸至所述数据线上方，覆盖所述数据线。
  13. 根据权利要求12所述的显示装置，其中，所述沟槽的数量大于或等于1，且所述沟槽至少对应位于所述数据线一侧的上方。
  14. 根据权利要求11所述的显示装置，其中，所述屏蔽层依据所述沟槽的形貌，贴合地覆盖所述沟槽的至少部分内壁。
  15. 根据权利要求11所述的显示装置，其中，所述屏蔽层在所述衬底层上的投影，覆盖至少部分所述数据线在所述衬底层上的投影。
  16. 根据权利要求15所述的显示装置，其中，所述屏蔽层在所述衬底层上的投影，覆盖全部所述数据线在所述衬底层上的投影。
  17. 根据权利要求11所述的显示装置，其中，所述沟槽的深度小于位于所述数据线两侧区域的所述色阻层的厚度。
  18. 根据权利要求11所述的显示装置，其中，所述像素电极层包括多个像素电极，多个所述像素电极在所述衬底层上的投影与所述屏蔽层在所述衬底层上的投影至少部分重叠。
  19. 根据权利要求11所述的显示装置，其中，所述显示面板还包括钝化层，所述钝化层设置于所述屏蔽层与所述像素电极层之间，并覆盖所述屏蔽层和所述色阻层。
  20. 根据权利要求11所述的显示装置，其中，所述显示面板还包括保护层，所述保护层设置于所述衬底层上并覆盖所述数据线。
PCT/CN2020/136300 2020-12-01 2020-12-15 显示面板和显示装置 Ceased WO2022116263A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/254,928 US11860493B2 (en) 2020-12-01 2020-12-15 Display panel and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011385623.7A CN112433414A (zh) 2020-12-01 2020-12-01 显示面板和显示装置
CN202011385623.7 2020-12-01

Publications (1)

Publication Number Publication Date
WO2022116263A1 true WO2022116263A1 (zh) 2022-06-09

Family

ID=74697589

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/136300 Ceased WO2022116263A1 (zh) 2020-12-01 2020-12-15 显示面板和显示装置

Country Status (3)

Country Link
US (1) US11860493B2 (zh)
CN (1) CN112433414A (zh)
WO (1) WO2022116263A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114660866B (zh) * 2022-03-25 2024-01-30 Tcl华星光电技术有限公司 阵列基板及显示面板
CN115097959B (zh) * 2022-07-08 2026-01-16 武汉华星光电技术有限公司 显示面板
CN115167709B (zh) 2022-07-26 2026-01-23 京东方科技集团股份有限公司 触控面板及显示装置
WO2024182924A1 (zh) * 2023-03-03 2024-09-12 京东方科技集团股份有限公司 阵列基板、其制作方法及显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120129644A (ko) * 2011-05-20 2012-11-28 엘지디스플레이 주식회사 칼라 필터 층을 포함하는 고 투과율 박막 트랜지스터 기판 및 그 제조 방법
CN103293802A (zh) * 2012-02-27 2013-09-11 乐金显示有限公司 液晶显示器件及其制造方法
CN104238207A (zh) * 2014-08-22 2014-12-24 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN207265054U (zh) * 2017-10-24 2018-04-20 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN108231850A (zh) * 2018-01-03 2018-06-29 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板
CN110858037A (zh) * 2018-08-22 2020-03-03 三星显示有限公司 液晶显示器及其制造方法
CN111090203A (zh) * 2020-03-22 2020-05-01 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN111290182A (zh) * 2020-03-16 2020-06-16 深圳市华星光电半导体显示技术有限公司 液晶显示面板

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110116803A (ko) * 2010-04-20 2011-10-26 삼성전자주식회사 표시 기판, 이를 포함하는 액정 표시 장치 및 이의 제조 방법
TW201241529A (en) * 2011-04-11 2012-10-16 Hannstar Display Corp Liquid crystal display panel
US9594282B2 (en) * 2013-03-12 2017-03-14 Sharp Kabushiki Kaisha Active-matrix substrate and display device
US9041002B2 (en) * 2013-07-11 2015-05-26 Shenzhen China Star Optoelectronics Technology Co., Ltd TFT-LCD array substrate and display device each with data line on common electrode line having larger dimension than the data line
CN104614910B (zh) * 2015-02-13 2017-11-14 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104880879A (zh) * 2015-06-19 2015-09-02 京东方科技集团股份有限公司 Coa阵列基板及其制造方法、显示装置
KR102607407B1 (ko) * 2016-06-03 2023-11-28 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
CN208848008U (zh) * 2018-10-29 2019-05-10 惠科股份有限公司 基板及显示面板
US20210286221A1 (en) * 2020-03-16 2021-09-16 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Liquid crystal display panel
CN111983854A (zh) * 2020-08-07 2020-11-24 深圳市华星光电半导体显示技术有限公司 像素电极、显示面板以及显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120129644A (ko) * 2011-05-20 2012-11-28 엘지디스플레이 주식회사 칼라 필터 층을 포함하는 고 투과율 박막 트랜지스터 기판 및 그 제조 방법
CN103293802A (zh) * 2012-02-27 2013-09-11 乐金显示有限公司 液晶显示器件及其制造方法
CN104238207A (zh) * 2014-08-22 2014-12-24 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN207265054U (zh) * 2017-10-24 2018-04-20 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN108231850A (zh) * 2018-01-03 2018-06-29 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板
CN110858037A (zh) * 2018-08-22 2020-03-03 三星显示有限公司 液晶显示器及其制造方法
CN111290182A (zh) * 2020-03-16 2020-06-16 深圳市华星光电半导体显示技术有限公司 液晶显示面板
CN111090203A (zh) * 2020-03-22 2020-05-01 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板

Also Published As

Publication number Publication date
US20230024337A1 (en) 2023-01-26
CN112433414A (zh) 2021-03-02
US11860493B2 (en) 2024-01-02

Similar Documents

Publication Publication Date Title
US6424397B1 (en) Method of forming wide-viewing angle liquid crystal display
CN113985662B (zh) 显示面板、阵列基板及其制造方法
JP5437971B2 (ja) 液晶表示装置
WO2022116263A1 (zh) 显示面板和显示装置
TWI228187B (en) MVA-LCD device with color filters on a TFT array substrate
TWI401512B (zh) 陣列基板及其製造方法與具有該陣列基板之液晶顯示裝置
CN107132710B (zh) 一种阵列基板及其制备方法、显示面板
CN104483790A (zh) 主动元件阵列基板与显示面板
CN106896587B (zh) 液晶显示设备及其制造方法
US8405807B2 (en) Liquid crystal display
KR101274703B1 (ko) 박막 트랜지스터 어레이 기판 및 이의 제조 방법
CN108108059A (zh) 一种显示面板及其制备方法和显示装置
WO2025077248A1 (zh) 阵列基板、显示面板及显示装置
WO2020124896A1 (zh) 液晶显示面板
JP2004085720A (ja) アクティブマトリクス基板、反射透過型液晶表示パネル、および反射透過型液晶表示装置
CN110308596B (zh) 显示装置
US7528411B2 (en) Display panel and method of manufacturing the same
WO2023184426A1 (zh) 阵列基板、显示面板及显示装置
CN111627935B (zh) 一种显示面板及显示装置
KR102043862B1 (ko) 액정표시장치 및 그 제조방법
CN115616817B (zh) 显示面板和电子装置
JPH0682824A (ja) 液晶パネル
CN115097675A (zh) 一种阵列基板及其制作方法、液晶显示面板、显示装置
US12057456B2 (en) Array substrate and display panel
CN111736399A (zh) 一种阵列基板及显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20964108

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20964108

Country of ref document: EP

Kind code of ref document: A1