WO2022114258A1 - Modulateur de fréquence fmcw large bande à haute vitesse et son procédé de compensation de non-linéarité - Google Patents

Modulateur de fréquence fmcw large bande à haute vitesse et son procédé de compensation de non-linéarité Download PDF

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WO2022114258A1
WO2022114258A1 PCT/KR2020/016894 KR2020016894W WO2022114258A1 WO 2022114258 A1 WO2022114258 A1 WO 2022114258A1 KR 2020016894 W KR2020016894 W KR 2020016894W WO 2022114258 A1 WO2022114258 A1 WO 2022114258A1
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signal
dlf
fmcw
chirp
output
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PCT/KR2020/016894
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Korean (ko)
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이성호
주하람
장성천
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한국전자기술연구원
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Publication of WO2022114258A1 publication Critical patent/WO2022114258A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
    • G01S13/06—Systems determining position data of a target
    • G01S13/08—Systems for measuring distance only
    • G01S13/32—Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
    • G01S13/34—Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28—Details of pulse systems
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/40—Means for monitoring or calibrating
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Definitions

  • the present invention relates to a FMCW frequency modulator, and more particularly, a high-speed chirp for grasping characteristics (motion, state, etc.) of a target object, a wideband FMCW frequency modulator, adaptive gain control of the modulator, nonlinearity compensation, and initial correction method is about
  • FMCW frequency modulated continuous wave
  • a frequency modulator including a phase-locked loop also requires a high bandwidth to generate a high-speed chirp and wideband FMCW signal when the division ratio modulation method is used.
  • -Sigma modulator's quantization noise is not well filtered, so the jitter performance of the output clock is poor.
  • the direct VCO (Voltage Controlled Oscillator) modulation type frequency modulator may have a low bandwidth of the phase synchronization loop, but is sensitive to the VCO gain and is vulnerable to PVT (Process-Voltage-Temperature) change.
  • the chirp performance of conventional frequency modulators is greatly affected by the nonlinearity of a Digitally Controlled Oscillator (DCO) or a Digital to Analog Converter (DAC) due to the characteristics of wideband modulation. As a result, there is a problem that the accuracy of target object detection is lowered.
  • DCO Digitally Controlled Oscillator
  • DAC Digital to Analog Converter
  • the present invention has been devised to solve the above problems, and an object of the present invention is to provide a high-speed chirp, wideband FMCW frequency modulator using multiple modulation, and an adaptive gain control, nonlinearity compensation and initial correction method of the modulator. is in providing.
  • the FMCW frequency modulator includes: a Frequency Modulation Profile Generator (FMPG) for generating a chirp signal and applying it to a Digital Loop Filter (DLF) and a Multi-Modulus Divider (MMD); AGC (Automatic Gain Controller) for adjusting the gain of the chirp signal generated in the FMPG and applied to the DLF; BBPFD (Bang-Bang Phase-Frequency Detector) for calculating the difference between the reference signal and the output signal of the MMD; DLF that accumulates the difference signal output from the BBPFD, and uses a chirp signal whose gain is adjusted by the AGC when accumulating; Digitally-Controlled Oscillator (DCO) for generating a chirp signal based on the output signal of the DLF and outputting it as a Frequency Modulated Continuous Wave (FMCW) signal; and an MMD that divides the chirp signal generated by the DCO, and modulates a
  • FMPG Frequency Modulation Profile Generator
  • the FMCW frequency modulator may further include a Delta-Sigma Modulator (DSM) for delta-sigma-modulating a chirp signal generated from the FMPG and applied to the MMD.
  • DSM Delta-Sigma Modulator
  • the AGC may adjust the gain of the chirp signal generated from the FMPG based on the difference signal output from the chirp signal generated from the FMPG and the BBPFD.
  • the AGC includes: a first accumulator for accumulating the difference signal output from the BBPFD; a first switch for outputting a first accumulated value of the first accumulator in a section in which the division ratio is positive; a second switch for outputting a second accumulated value of the first accumulator in a section in which the division ratio is negative; a subtractor for calculating a difference between the second accumulated value output by the second switch and the first accumulated value output by the first switch; a determiner that determines the sign of the subtractor; When the sign determined by the determiner is +, a second accumulator for reducing the gain; may be included.
  • the second accumulator may increase the gain if the sign determined by the determiner is -. Gain adjustment may be made for each period of the division ratio.
  • the DLF is accumulated by applying a first weight to the difference signal output from the BBPFD, and during accumulation, the chirp signal generated from the FMPG whose gain is adjusted by the AGC may be accumulated together.
  • the DLF may be further accumulated by applying a second weight to the difference signal output from the BBPFD.
  • the FMCW frequency modulator further includes a compensator for linearly compensating the output signal of the DLF, and the DCO generates a chirp signal based on the signal compensated by the compensator and converts it to an FMCW signal. can be printed out.
  • the FMCW frequency modulation method the FMPG, generating a chirp signal to apply to the DLF and the MMD; adjusting, by the AGC, a gain of the chirp signal generated in the FMPG and applied to the DLF; calculating, by the BBPFD, a difference between the reference signal and the output signal of the MMD; A DLF accumulating the difference signal output from the BBPFD, using a chirp signal whose gain is adjusted by the AGC when accumulating; DCO, based on the output signal of the DLF, generating a chirp signal and outputting it as an FMCW signal;
  • the MMD divides the chirp signal generated by the DCO, and modulates a division ratio based on the chirp signal generated by the FMPG.
  • the FMCW frequency modulator, BBPFD for calculating the difference between the reference signal and the output signal of the MMD; DLF for accumulating the difference signal output from the BBPFD; a compensator for linearly compensating the output signal of the DLF; DCO for generating a chirp signal based on the signal compensated by the compensator and outputting it as an FMCW signal; MMD that divides the chirp signal generated by the DCO; includes.
  • FMCW frequency modulation method BBPFD, calculating the difference between the reference signal and the output signal of the MMD; accumulating, by the DLF, a difference signal output from the BBPFD; Compensating, linearly compensating the output signal of the DLF; DCO, based on the signal compensated by the compensator, generating a chirp signal and outputting it as an FMCW signal; and MMD, dispensing the chirp signal generated by the DCO.
  • FIG. 1 Examples of FMCW radar transmission and reception signals.
  • Fig. 4 The overall structural diagram of the high-speed chirped, wideband FMCW frequency modulator.
  • Phase-locked loop output waveform (a) high gain (b) low gain (c) coincidence as a function of division ratio of direct modulation path gain to correlation to modulation path gain.
  • the target detection technology using the FMCW radar signal is a technology that extracts information (movement, distance, etc.) from an object by using the time and phase difference between the transmitted FMCW radar signal and the radar signal that is reflected after the signal collides with the object.
  • the FMCW signal frequency-modulated signals in the form of sine wave, sawtooth wave, triangle wave, and square wave are mainly used.
  • the triangle wave and the sawtooth wave are most widely used among them, and when the radar signal of the sawtooth wave is applied, the phase difference between the transmitted radar signal and the received radar signal is shown in FIG. 1 .
  • the actual frequency modulation time is called chirp time (t CHIRP )
  • the amount of the modulated frequency is called modulation bandwidth (BW CHIRP ).
  • the frequency difference between the transmitted radar signal and the received radar signal at the same time is referred to as an intermediate frequency (IF) frequency.
  • IF intermediate frequency
  • the IF frequency is expressed as the following equation when the distance between the radar source and the object is R and the speed of the object is v.
  • the down-converted IF frequency signal passes through the bandpass filter and is transmitted to the radar signal processing unit, but as the chirp time increases, the IF frequency decreases, so that the high-pass corner of the bandpass filter must be lowered. Therefore, if the chirp time is reduced as shown in FIG. 2, the high-pass corner of the bandpass filter can be relaxed, which brings a systemic gain.
  • the IF signal can have a high signal-to-noise ratio (SNR) without being buried by the oscillator flicker noise, which has the advantage of increasing the SNR of the entire radar system.
  • SNR signal-to-noise ratio
  • the modulation bandwidth increases for the same chirp time, it becomes a relatively high-speed chirp, so it is necessary to implement a high-speed chirp and wideband FMCW frequency modulator for high-resolution radar object detection technology.
  • FIG. 4 The overall structure of a high-speed chirped, wideband FMCW modulator according to an embodiment of the present invention is shown in FIG. 4 .
  • an FMCW modulator was constructed using a multi-modulation-type phase synchronization loop.
  • a high-speed chirped, wideband FMCW frequency modulator according to an embodiment of the present invention, as shown in FIG. 4, BBPFD (Bang-Bang Phase-Frequency Detector) 105, DLF (Digital Loop Filter) 110, DSM ( Delta-Sigma Modulator(115), DEC(row & column DECoder)(120), DCO(Digitally-Controlled Oscillator)(125), AGC(Automatic Gain Controller)(130), Multiplier(135), FMPG(Frequency Modulation) Profile Generator) 140 , DSM 145 , and MMD (Multi-Modulus Divider) 150 are included.
  • BBPFD Beang-Bang Phase-Frequency Detector
  • DLF Digital Loop Filter
  • DSM Delta-Sigma Modulator(115), DEC(row & column DECoder)(120), DCO(Digitally-Controlled Oscillator)(125), AGC(Automatic Gain Controller)(130), Multiplier(135), FMPG
  • the high-speed chirp, wideband FMCW frequency modulator is a phase-locked loop composed of all-digital except for blocks such as the BBPFD 105, the DCO 125, and the MMD 150, and a frequency modulation path It consists of a 'Direct DCO Modulation Path' that can be said to be 'Direct DCO Modulation Path' and a 'Division Ratio Modulation Path' that can be called a phase modulation path.
  • the FMPG 140 generates a chirp signal and applies it to the DLF 110 through the Multiplier 135 and to the MMD 150 through the DSM 145 .
  • the chirp signal generated by the FMPG 140 by the DSM 145 is delta-sigma modulated and applied to the MMD 150 .
  • the AGC 130 adjusts the gain of the chirp signal generated by the FMPG 140 and applied to the DLF. To this end, the AGC 130 generates a gain for adjusting the gain of the chirp signal generated by the FMPG 140 based on the difference signal output from the chirp signal generated from the FMPG 140 and the BBPFD 105 . . A detailed configuration of the AGC 130 will be described later in detail.
  • the multiplier 135 multiplies the chirp signal generated by the FMPG 140 and the gain generated by the AGC 130 , and applies the gain-adjusted chirp signal to the DLF 110 .
  • the BBPFD 105 calculates a difference (error) between the reference signal and the output signal of the MMD 150 and outputs it to the DLF 110 .
  • the DLF 110 accumulates the difference signal output from the BBPFD 150 , and uses a chirp signal whose gain is adjusted by the AGC 130 during accumulation. Specifically, the DLF 110 applies a weight ⁇ to the difference signal output from the BBPFD 105 and accumulates it, but during accumulation, the chirp signal whose gain is adjusted by the AGC 130 is accumulated together. In addition, the DLF 110 further accumulates a value obtained by applying a weight ⁇ to the difference signal output from the BBPFD 105 to the accumulation result.
  • the DSM 115 modulates the output signal of the DLF 110 by delta-sigma and transmits it to the DCO 125 through the DEC 120 .
  • the DCO 125 generates a chirp signal based on the output signal of the DLF 110 and outputs it as an FMCW signal.
  • the MMD 150 divides the chirp signal generated by the DCO 125 . At this time, the MMD 150 modulates the division ratio based on the chirp signal generated by the FMPG 140 .
  • the frequency modulation path has a high-pass characteristic and the phase modulation path has a low-pass characteristic. Only then can the correlation between jitter be broken.
  • an embodiment of the present invention proposes a new real-time adaptive gain control method.
  • Fig. 5 shows the divided clock frequency and phase error according to the gain mismatch, and the BBPFD (105).
  • the frequency deviation of the output clock is greater than the ideal FMCW frequency deviation. Accordingly, the frequency waveform of the divided clock is also a triangular wave, and its average value is the same as the frequency of the reference clock.
  • the phase error detected at the input of the BBPFD 105 is obtained as a value obtained by integrating the frequency difference between the reference clock and the divided clock.
  • the output of the BBPFD 105 alternates between +1 and -1 periodically depending on whether the frequency waveform slope of the divided clock is positive or negative. Therefore, the sign of the output of the BBPFD 105 is changed when the slope value is changed.
  • the output of the BBPFD 105 changes earlier according to the Bang-Bang phase/frequency tracking characteristics.
  • the proportional gain of the DLF 110 is sufficiently larger than the integral gain, the phase synchronization loop tracks the input phase error in the shape of a triangular wave, and at the point where the Bang-Bang tracking phase meets the phase error in the open loop, the BBPFD (105) ) output is changed. If the direct modulation gain is smaller than the division ratio modulation gain, the opposite waveform is shown as shown in FIG. 5(b).
  • the output clock has an ideal FMCW frequency waveform and frequency deviation is minimized.
  • FIGS. 6 and 7 A block diagram of the AGC 130 for matching the gains of the two paths in real time and a timing diagram thereof are shown in FIGS. 6 and 7 .
  • the AGC 130 includes an accumulator #1 (131), a switch #1 (132), a switch #2 (133), a subtractor 134, a determiner 135, and an accumulator #2 (136). ) is included.
  • the output of the BBPFD 105 is accumulated during a half cycle of the mclk clock. This gives the average phase error over that period.
  • the accumulated value is sampled and reset.
  • sum_n is the accumulated value when mclk is low
  • sum_p is the accumulated value when mclk is high. If the subtraction value of these two values is positive, the direct modulation gain is small, and if it is negative, the direct modulation gain is large.
  • the accumulator #1 (131) accumulates the difference signal output from the BBPFD (105).
  • the switch #1(132) outputs the accumulated value #1 of the accumulator #1(131) in the section where the division ratio is positive, and the switch #2(133) accumulates the accumulator #1(131) in the section where the division ratio is negative. Print the value #2.
  • the subtractor 134 calculates a difference between the accumulated value #2 output by the switch #2 (133) and the accumulated value #1 output by the switch #1 (132).
  • the determiner 135 determines the sign of the subtractor 134 .
  • Accumulator #2 decreases the gain if the sign determined by the determiner 135 is +, and increases the gain if the sign determined by the determiner 135 is negative. Gain adjustment is made every cycle of the divide ratio.
  • the actual FMCW modulated waveform is not linear like an ideal sawtooth waveform but has a non-linear characteristic. This phenomenon is due to the nonlinearity of the DCO or DAC within the FMCW modulator.
  • the chirp signal is non-linear in this way, the IF frequency has different values in real time as shown in FIG. 8 . As a result, the accuracy of object detection is greatly reduced.
  • the nonlinearity compensation is in front of the Row & Column Decoder 120 to be applied to the DCO 125 after passing through the DLF 110 and the DSM 115.
  • it may be implemented in the form of a nonlinearity compensation (NC) mapping module 117 .
  • the NC (Nonlinearity Compensation) Mapping module 117 is a LUT type that receives a total of N-bit input codes and maps them to N-bit output codes.
  • LUT-based mapping divided into four sections is simply described as an example as shown in FIG. 10 .
  • the x-axis is the input code of mapping and the left y-axis is the output code. Both can have a value from 0 to a maximum of 2 N -1.
  • the right y-axis is a normalized value of the DCO output frequency according to the input code.
  • the ideal DCO line has a slope of 1. Assume that the approximated trend line is the same as S 1 ⁇ S 4 when modeling is performed by dividing the output frequency of the actual DCO according to the input code into four straight sections as shown in FIG. 10 . At this time, the O 1 , O 2 , O 3 codes are the quadrant values (the slope is If normalized to be 1, these are the DCO input code values when having I 1 , I 2 , I 3 ).
  • F min , F max , I 1 , I 2 , and I 3 are all values that can be obtained through actual DCO measurement, so O 1 , O 2 , O 3 can also be obtained, and normalized DCO frequency curves (S 1 ⁇ S 4 ) ), the slopes of S 1 , S 2 , S 3 , and S 4 can also be obtained.
  • the reciprocal values of the slope, W 1 , W 2 , W 3 , and W 4 can also be calculated.
  • the entire input code is divided into 4 equal sections so that the slope becomes W 1 , W 2 , W 3 , W 4 , so that Mapping functions (W 1 ⁇ W 4 ) can be obtained.
  • NC Mapping structure which is extended to a LUT having M sections, can be represented as shown in FIG. 11 .
  • the Frequency Measure block and Controller block can be implemented as digital IP within the DUT or can be configured with firmware or software outside the DUT.
  • the tradeoff correlation between the chirp bandwidth and the clock jitter of the FMCW frequency modulator is broken and the performance of both is improved by utilizing the digital phase synchronization loop of the multiple modulation method.
  • a new real-time adaptive gain control method is presented for gain matching between the phase modulation path and the frequency modulation path, which can be said to be the key to implementing a multi-modulation phase synchronization loop.

Abstract

L'invention concerne un modulateur de fréquence FMCW large bande à haute vitesse et son procédé de compensation de non-linéarité. Un modulateur de fréquence FMCW selon un mode de réalisation de la présente invention comprend : un FMPG permettant de générer un signal de modulation de fréquence et d'appliquer le signal de modulation de fréquence à un DLF et un MMD ; un AGC permettant de régler un gain du signal de modulation de fréquence généré par le FMPG et appliqué au DLF ; un BBPFD permettant de calculer une différence entre un signal de référence et un signal de sortie du MMD ; un DLF permettant d'accumuler un signal de différence émis en sortie par le BBPFD, à l'aide du signal de modulation de fréquence dont le gain est réglé par l'AGC, pendant l'accumulation ; un DCO permettant de générer un signal de modulation de fréquence en fonction d'un signal de sortie du DLF, et d'émettre en sortie le signal de modulation de fréquence sous la forme d'un signal FMCW ; et un MMD permettant de diviser le signal de modulation de fréquence généré par le DCO, tout en modulant un rapport de division en fonction du signal de modulation de fréquence généré par le FMPG. Ainsi, la présente invention permet d'obtenir de bonnes performances de gigue d'horloge tout en mettant en œuvre une modulation de fréquence à grande vitesse et une large bande à l'aide d'une boucle de synchronisation de phase numérique d'un schéma de modulation multiple dans le modulateur de fréquence.
PCT/KR2020/016894 2020-11-26 2020-11-26 Modulateur de fréquence fmcw large bande à haute vitesse et son procédé de compensation de non-linéarité WO2022114258A1 (fr)

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KR10-2020-0160594 2020-11-26
KR1020200160594A KR102470031B1 (ko) 2020-11-26 2020-11-26 고속 광대역 fmcw 주파수 변조기 및 그 비선형성 보상 방법

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EP3190704A1 (fr) * 2016-01-06 2017-07-12 Nxp B.V. Boucles numériques à verrouillage de phase
KR20180131017A (ko) * 2017-05-31 2018-12-10 전자부품연구원 광대역 fmcw를 지원하는 이중 경로를 가진 주파수 합성기
KR20190000024A (ko) * 2017-06-21 2019-01-02 삼성전자주식회사 디지털 위상 고정 루프 및 디지털 위상 고정 루프의 동작 방법

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US20100141313A1 (en) * 2008-12-09 2010-06-10 Qualcomm Incorporated Digital phase-locked loop with two-point modulation and adaptive delay matching
US20150372690A1 (en) * 2014-06-23 2015-12-24 Intel IP Corporation Circuit, a time-to-digital converter, an integrated circuit, a transmitter, a receiver and a transceiver
EP3190704A1 (fr) * 2016-01-06 2017-07-12 Nxp B.V. Boucles numériques à verrouillage de phase
KR20180131017A (ko) * 2017-05-31 2018-12-10 전자부품연구원 광대역 fmcw를 지원하는 이중 경로를 가진 주파수 합성기
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