WO2022114258A1

WO2022114258A1 - High-speed wideband fmcw frequency modulator and nonlinearity compensation method thereof

Info

Publication number: WO2022114258A1
Application number: PCT/KR2020/016894
Authority: WO
Inventors: 이성호; 주하람; 장성천
Original assignee: 한국전자기술연구원
Priority date: 2020-11-26
Filing date: 2020-11-26
Publication date: 2022-06-02
Also published as: KR102470031B1; KR20220072978A

Abstract

A high-speed wideband FMCW frequency modulator and a nonlinearity compensation method thereof are provided. A FMCW frequency modulator according to an embodiment of the present invention comprises: an FMPG for generating a chirp signal and applying the chirp signal to a DLF and an MMD; an AGC for adjusting a gain of the chirp signal generated by the FMPG and applied to the DLF; a BBPFD for calculating a difference between a reference signal and an output signal of the MMD; a DLF for accumulating a difference signal output from the BBPFD, using the chirp signal, the gain of which is adjusted by the AGC, during accumulation; a DCO for generating a chirp signal on the basis of an output signal of the DLF, and outputting the chirp signal as an FMCW signal; and an MMD for dividing the chirp signal generated by the DCO, while modulating a division ratio on the basis of the chirp signal generated by the FMPG. Accordingly, the present invention can obtain good clock jitter performance while implementing high-speed chirp and wideband by utilizing a digital phase synchronization loop of a multi-modulation scheme in the frequency modulator.

Description

High-speed wideband FMCW frequency modulator and its nonlinearity compensation method

The present invention relates to a FMCW frequency modulator, and more particularly, a high-speed chirp for grasping characteristics (motion, state, etc.) of a target object, a wideband FMCW frequency modulator, adaptive gain control of the modulator, nonlinearity compensation, and initial correction method is about

Recently, many studies have been conducted on a method of detecting a target in real time using a frequency modulated continuous wave (FMCW) radar signal and extracting information such as distance and speed.

In particular, in order to obtain high-resolution target information, frequency modulation with a very narrow pulse width and a wide bandwidth is required. Since the DDS (Direct Digital Synthesizer) type frequency modulator, which has been widely used in the past, does not have a phase synchronization loop, a high-speed, linear chirp signal is generated. There is great difficulty in creating it. In addition, since a high-performance DAC (Digital-to-Analog-Converter) and filter are required, it has disadvantages in terms of power consumption and size.

On the other hand, a frequency modulator including a phase-locked loop also requires a high bandwidth to generate a high-speed chirp and wideband FMCW signal when the division ratio modulation method is used. -Sigma modulator's quantization noise is not well filtered, so the jitter performance of the output clock is poor. In addition, the direct VCO (Voltage Controlled Oscillator) modulation type frequency modulator may have a low bandwidth of the phase synchronization loop, but is sensitive to the VCO gain and is vulnerable to PVT (Process-Voltage-Temperature) change.

In addition, the chirp performance of conventional frequency modulators is greatly affected by the nonlinearity of a Digitally Controlled Oscillator (DCO) or a Digital to Analog Converter (DAC) due to the characteristics of wideband modulation. As a result, there is a problem that the accuracy of target object detection is lowered.

Therefore, in order to implement a high-speed chirped, wideband FMCW frequency modulator to have high linearity, new nonlinearity compensation techniques are required.

The present invention has been devised to solve the above problems, and an object of the present invention is to provide a high-speed chirp, wideband FMCW frequency modulator using multiple modulation, and an adaptive gain control, nonlinearity compensation and initial correction method of the modulator. is in providing.

According to an embodiment of the present invention for achieving the above object, the FMCW frequency modulator includes: a Frequency Modulation Profile Generator (FMPG) for generating a chirp signal and applying it to a Digital Loop Filter (DLF) and a Multi-Modulus Divider (MMD); AGC (Automatic Gain Controller) for adjusting the gain of the chirp signal generated in the FMPG and applied to the DLF; BBPFD (Bang-Bang Phase-Frequency Detector) for calculating the difference between the reference signal and the output signal of the MMD; DLF that accumulates the difference signal output from the BBPFD, and uses a chirp signal whose gain is adjusted by the AGC when accumulating; Digitally-Controlled Oscillator (DCO) for generating a chirp signal based on the output signal of the DLF and outputting it as a Frequency Modulated Continuous Wave (FMCW) signal; and an MMD that divides the chirp signal generated by the DCO, and modulates a division ratio based on the chirp signal generated by the FMPG.

The FMCW frequency modulator according to an embodiment of the present invention may further include a Delta-Sigma Modulator (DSM) for delta-sigma-modulating a chirp signal generated from the FMPG and applied to the MMD.

The AGC may adjust the gain of the chirp signal generated from the FMPG based on the difference signal output from the chirp signal generated from the FMPG and the BBPFD.

The AGC includes: a first accumulator for accumulating the difference signal output from the BBPFD; a first switch for outputting a first accumulated value of the first accumulator in a section in which the division ratio is positive; a second switch for outputting a second accumulated value of the first accumulator in a section in which the division ratio is negative; a subtractor for calculating a difference between the second accumulated value output by the second switch and the first accumulated value output by the first switch; a determiner that determines the sign of the subtractor; When the sign determined by the determiner is +, a second accumulator for reducing the gain; may be included.

The second accumulator may increase the gain if the sign determined by the determiner is -. Gain adjustment may be made for each period of the division ratio.

The DLF is accumulated by applying a first weight to the difference signal output from the BBPFD, and during accumulation, the chirp signal generated from the FMPG whose gain is adjusted by the AGC may be accumulated together.

The DLF may be further accumulated by applying a second weight to the difference signal output from the BBPFD.

The FMCW frequency modulator according to an embodiment of the present invention further includes a compensator for linearly compensating the output signal of the DLF, and the DCO generates a chirp signal based on the signal compensated by the compensator and converts it to an FMCW signal. can be printed out.

On the other hand, according to another embodiment of the present invention, the FMCW frequency modulation method, the FMPG, generating a chirp signal to apply to the DLF and the MMD; adjusting, by the AGC, a gain of the chirp signal generated in the FMPG and applied to the DLF; calculating, by the BBPFD, a difference between the reference signal and the output signal of the MMD; A DLF accumulating the difference signal output from the BBPFD, using a chirp signal whose gain is adjusted by the AGC when accumulating; DCO, based on the output signal of the DLF, generating a chirp signal and outputting it as an FMCW signal; The MMD divides the chirp signal generated by the DCO, and modulates a division ratio based on the chirp signal generated by the FMPG.

On the other hand, according to another embodiment of the present invention, the FMCW frequency modulator, BBPFD for calculating the difference between the reference signal and the output signal of the MMD; DLF for accumulating the difference signal output from the BBPFD; a compensator for linearly compensating the output signal of the DLF; DCO for generating a chirp signal based on the signal compensated by the compensator and outputting it as an FMCW signal; MMD that divides the chirp signal generated by the DCO; includes.

On the other hand, according to another embodiment of the present invention, FMCW frequency modulation method, BBPFD, calculating the difference between the reference signal and the output signal of the MMD; accumulating, by the DLF, a difference signal output from the BBPFD; Compensating, linearly compensating the output signal of the DLF; DCO, based on the signal compensated by the compensator, generating a chirp signal and outputting it as an FMCW signal; and MMD, dispensing the chirp signal generated by the DCO.

As described above, according to the embodiments of the present invention, it is possible to have good clock jitter performance while realizing high-speed chirp and wide bandwidth by using a digital phase-locking loop of a multi-modulation method for a frequency modulator.

In addition, according to embodiments of the present invention, it is possible to increase the gain matching performance between two modulation paths by grafting the real-time adaptive gain control method in the multi-modulation method, so that it is possible to generate a chirp signal with high linearity.

Furthermore, according to embodiments of the present invention, it is possible to generate a chirp signal with high linearity by linearizing performance degradation due to nonlinearity of DCO or DAC through compensation mapping (Nbit-to-Nbit), With a digital implementation based on a divided LUT (Look-up Table), the mapping structure is simple and the initial calibration procedure is relatively simple.

Figure 1. Examples of FMCW radar transmission and reception signals.

Figure 2. Example of relaxed bandpass bandwidth when high-speed chirp is possible compared to low-speed chirp

Fig. 3. Relationship between IF frequency and flicker noise according to chirp speed

Fig. 4. The overall structural diagram of the high-speed chirped, wideband FMCW frequency modulator.

Figure 5. Phase-locked loop output waveform (a) high gain (b) low gain (c) coincidence as a function of division ratio of direct modulation path gain to correlation to modulation path gain.

Fig. 6. Block diagram of AGC

Fig. 7. Timing diagram of AGC

Fig. 8. Effect of nonlinearity of FMCW radar transmitted/received signal

Figure 9. Example of Nbit-to-Nbit NC Mapping in FMCW modulator

Figure 10. Example of LUT-based NC Mapping (Nbit-to-Nbit) divided into 4 sections

11. LUT-based NC Mapping (Nbit-to-Nbit) extended to M sections

12. Initial correction method of M coefficients of N-bit NC Mapping

Hereinafter, the present invention will be described in more detail with reference to the drawings.

The target detection technology using the FMCW radar signal is a technology that extracts information (movement, distance, etc.) from an object by using the time and phase difference between the transmitted FMCW radar signal and the radar signal that is reflected after the signal collides with the object.

As the FMCW signal, frequency-modulated signals in the form of sine wave, sawtooth wave, triangle wave, and square wave are mainly used. In particular, the triangle wave and the sawtooth wave are most widely used among them, and when the radar signal of the sawtooth wave is applied, the phase difference between the transmitted radar signal and the received radar signal is shown in FIG. 1 . In this case, the actual frequency modulation time is called chirp time (t _CHIRP ), and the amount of the modulated frequency is called modulation bandwidth (BW _CHIRP ). In addition, the frequency difference between the transmitted radar signal and the received radar signal at the same time is referred to as an intermediate frequency (IF) frequency.

At this time, the IF frequency is expressed as the following equation when the distance between the radar source and the object is R and the speed of the object is v.

Target IF frequency, f _IF (t)

On the other hand, the down-converted IF frequency signal passes through the bandpass filter and is transmitted to the radar signal processing unit, but as the chirp time increases, the IF frequency decreases, so that the high-pass corner of the bandpass filter must be lowered. Therefore, if the chirp time is reduced as shown in FIG. 2, the high-pass corner of the bandpass filter can be relaxed, which brings a systemic gain.

In addition, if high-speed chirp is possible, since the IF frequency is high, as shown in FIG. 3, the IF signal can have a high signal-to-noise ratio (SNR) without being buried by the oscillator flicker noise, which has the advantage of increasing the SNR of the entire radar system. As the modulation bandwidth increases for the same chirp time, it becomes a relatively high-speed chirp, so it is necessary to implement a high-speed chirp and wideband FMCW frequency modulator for high-resolution radar object detection technology.

The overall structure of a high-speed chirped, wideband FMCW modulator according to an embodiment of the present invention is shown in FIG. 4 . In order to break the trade-off correlation between chirp bandwidth and clock jitter and to improve the performance of both, an FMCW modulator was constructed using a multi-modulation-type phase synchronization loop.

A high-speed chirped, wideband FMCW frequency modulator according to an embodiment of the present invention, as shown in FIG. 4, BBPFD (Bang-Bang Phase-Frequency Detector) 105, DLF (Digital Loop Filter) 110, DSM ( Delta-Sigma Modulator(115), DEC(row & column DECoder)(120), DCO(Digitally-Controlled Oscillator)(125), AGC(Automatic Gain Controller)(130), Multiplier(135), FMPG(Frequency Modulation) Profile Generator) 140 , DSM 145 , and MMD (Multi-Modulus Divider) 150 are included.

The high-speed chirp, wideband FMCW frequency modulator according to an embodiment of the present invention is a phase-locked loop composed of all-digital except for blocks such as the BBPFD 105, the DCO 125, and the MMD 150, and a frequency modulation path It consists of a 'Direct DCO Modulation Path' that can be said to be 'Direct DCO Modulation Path' and a 'Division Ratio Modulation Path' that can be called a phase modulation path.

The FMPG 140 generates a chirp signal and applies it to the DLF 110 through the Multiplier 135 and to the MMD 150 through the DSM 145 . The chirp signal generated by the FMPG 140 by the DSM 145 is delta-sigma modulated and applied to the MMD 150 .

The AGC 130 adjusts the gain of the chirp signal generated by the FMPG 140 and applied to the DLF. To this end, the AGC 130 generates a gain for adjusting the gain of the chirp signal generated by the FMPG 140 based on the difference signal output from the chirp signal generated from the FMPG 140 and the BBPFD 105 . . A detailed configuration of the AGC 130 will be described later in detail.

The multiplier 135 multiplies the chirp signal generated by the FMPG 140 and the gain generated by the AGC 130 , and applies the gain-adjusted chirp signal to the DLF 110 .

The BBPFD 105 calculates a difference (error) between the reference signal and the output signal of the MMD 150 and outputs it to the DLF 110 .

The DLF 110 accumulates the difference signal output from the BBPFD 150 , and uses a chirp signal whose gain is adjusted by the AGC 130 during accumulation. Specifically, the DLF 110 applies a weight α to the difference signal output from the BBPFD 105 and accumulates it, but during accumulation, the chirp signal whose gain is adjusted by the AGC 130 is accumulated together. In addition, the DLF 110 further accumulates a value obtained by applying a weight β to the difference signal output from the BBPFD 105 to the accumulation result.

The DSM 115 modulates the output signal of the DLF 110 by delta-sigma and transmits it to the DCO 125 through the DEC 120 . The DCO 125 generates a chirp signal based on the output signal of the DLF 110 and outputs it as an FMCW signal.

The MMD 150 divides the chirp signal generated by the DCO 125 . At this time, the MMD 150 modulates the division ratio based on the chirp signal generated by the FMPG 140 .

In the multi-modulation phase synchronization loop, gain matching and delay matching between two modulation paths are very important for an optimized operation. With respect to the triangular or sawtooth chirp signal generated by the FMPG 140, the frequency modulation path has a high-pass characteristic and the phase modulation path has a low-pass characteristic. Only then can the correlation between jitter be broken.

In general, when the digital loop is configured, the delay mismatch between the two paths is not large and the effect thereof is insignificant. On the other hand, since the gain mismatch can cause a large side effect, an embodiment of the present invention proposes a new real-time adaptive gain control method.

Fig. 5 shows the divided clock frequency and phase error according to the gain mismatch, and the BBPFD (105).

As shown in FIG. 5( a ), when the gain of the direct modulation path is larger than the gain of the division ratio modulation path, the frequency deviation of the output clock is greater than the ideal FMCW frequency deviation. Accordingly, the frequency waveform of the divided clock is also a triangular wave, and its average value is the same as the frequency of the reference clock. At this time, the phase error detected at the input of the BBPFD 105 is obtained as a value obtained by integrating the frequency difference between the reference clock and the divided clock.

In the open loop operation, the output of the BBPFD 105 alternates between +1 and -1 periodically depending on whether the frequency waveform slope of the divided clock is positive or negative. Therefore, the sign of the output of the BBPFD 105 is changed when the slope value is changed.

On the other hand, in closed loop operation, the output of the BBPFD 105 changes earlier according to the Bang-Bang phase/frequency tracking characteristics. In general, if the proportional gain of the DLF 110 is sufficiently larger than the integral gain, the phase synchronization loop tracks the input phase error in the shape of a triangular wave, and at the point where the Bang-Bang tracking phase meets the phase error in the open loop, the BBPFD (105) ) output is changed. If the direct modulation gain is smaller than the division ratio modulation gain, the opposite waveform is shown as shown in FIG. 5(b).

On the other hand, if the gains of the two paths are matched because of the good gain matching, the frequency deviation of the divided clock becomes small, so that the BBPFD (105) output is more randomly +1 and -1 as shown in FIG. 5(c). As a result, the output clock has an ideal FMCW frequency waveform and frequency deviation is minimized.

A block diagram of the AGC 130 for matching the gains of the two paths in real time and a timing diagram thereof are shown in FIGS. 6 and 7 .

As shown in FIG. 6 , the AGC 130 includes an accumulator #1 (131), a switch #1 (132), a switch #2 (133), a subtractor 134, a determiner 135, and an accumulator #2 (136). ) is included.

As shown in FIG. 7 , the output of the BBPFD 105 is accumulated during a half cycle of the mclk clock. This gives the average phase error over that period. At the edge of mclk, the accumulated value is sampled and reset. sum_n is the accumulated value when mclk is low, and sum_p is the accumulated value when mclk is high. If the subtraction value of these two values is positive, the direct modulation gain is small, and if it is negative, the direct modulation gain is large.

Specifically, the accumulator #1 (131) accumulates the difference signal output from the BBPFD (105). The switch #1(132) outputs the accumulated value #1 of the accumulator #1(131) in the section where the division ratio is positive, and the switch #2(133) accumulates the accumulator #1(131) in the section where the division ratio is negative. Print the value #2.

The subtractor 134 calculates a difference between the accumulated value #2 output by the switch #2 (133) and the accumulated value #1 output by the switch #1 (132). The determiner 135 determines the sign of the subtractor 134 .

Accumulator #2 (136) decreases the gain if the sign determined by the determiner 135 is +, and increases the gain if the sign determined by the determiner 135 is negative. Gain adjustment is made every cycle of the divide ratio.

On the other hand, as shown in FIG. 8 , the actual FMCW modulated waveform is not linear like an ideal sawtooth waveform but has a non-linear characteristic. This phenomenon is due to the nonlinearity of the DCO or DAC within the FMCW modulator. When the chirp signal is non-linear in this way, the IF frequency has different values in real time as shown in FIG. 8 . As a result, the accuracy of object detection is greatly reduced.

Therefore, in order to compensate for such nonlinearity, as shown in FIG. 9 , in an embodiment of the present invention, a method of adding a nonlinearity compensator 117 to the FMCW frequency modulator shown in FIG. 4 is proposed.

As can be seen in FIG. 9, in the FMCW frequency modulator using a multi-phase synchronization loop, the nonlinearity compensation is in front of the Row & Column Decoder 120 to be applied to the DCO 125 after passing through the DLF 110 and the DSM 115. However, it may be implemented in the form of a nonlinearity compensation (NC) mapping module 117 . The NC (Nonlinearity Compensation) Mapping module 117 is a LUT type that receives a total of N-bit input codes and maps them to N-bit output codes.

In order to easily explain LUT-based NC mapping divided into M sections, LUT-based mapping divided into four sections is simply described as an example as shown in FIG. 10 . The x-axis is the input code of mapping and the left y-axis is the output code. Both can have a value from 0 to a maximum of 2 ^N -1. On the other hand, the right y-axis is a normalized value of the DCO output frequency according to the input code.

The ideal DCO line has a slope of 1. Assume that the approximated trend line is the same as S ₁ ~ S ₄ when modeling is performed by dividing the output frequency of the actual DCO according to the input code into four straight sections as shown in FIG. 10 . At this time, the ^O ₁ , O ₂ , O ₃ codes are the _quadrant values (the _slope is If normalized to be 1, these are the DCO input code values when having I ₁ , I ₂ , I ₃ ). Therefore, F _min , F _max , I ₁ , I ₂ , and I ₃ are all values that can be obtained through actual DCO measurement, so O ₁ , O ₂ , O ₃ can also be obtained, and normalized DCO frequency curves (S ₁ ~ S ₄ ) ), the slopes of S ₁ , S ₂ , S ₃ , and S ₄ can also be obtained. Through this, the reciprocal values of the slope, W ₁ , W ₂ , W ₃ , and W ₄ can also be calculated. Finally, the entire input code is divided into 4 equal sections so that the slope becomes W ₁ , W ₂ , W ₃ , W ₄ , so that Mapping functions (W ₁ ~ W ₄ ) can be obtained.

The detailed calculation of S ₁ ~ S ₄ and W ₁ ~ W ₄ is as follows.

The NC Mapping structure, which is extended to a LUT having M sections, can be represented as shown in FIG. 11 .

At this time, the method of determining the values of W ₁ to W _M , which are the M LUT coefficients, is the same as the method described above. A summary of the initial correction method of such NC Mapping is shown in FIG. 12 . The Frequency Measure block and Controller block can be implemented as digital IP within the DUT or can be configured with firmware or software outside the DUT.

When the initial correction process of N-bit NC Mapping is completed through the steps ①~④, it is possible to compensate the nonlinearity of the FMCW modulator derived from the DCO or DAC and make a linear chirp signal despite the high-speed broadband.

Up to now, the high-speed wideband FMCW frequency modulator and its nonlinearity compensation mapping technology and initial correction method have been described in detail with reference to a preferred embodiment.

In the embodiment of the present invention, the tradeoff correlation between the chirp bandwidth and the clock jitter of the FMCW frequency modulator is broken and the performance of both is improved by utilizing the digital phase synchronization loop of the multiple modulation method.

In addition, a new real-time adaptive gain control method is presented for gain matching between the phase modulation path and the frequency modulation path, which can be said to be the key to implementing a multi-modulation phase synchronization loop.

In addition, a new non-linearity compensation mapping method was added, and a method for initial correction of the linearity compensation mapping was presented because the detection accuracy may decrease or the real-time adaptive gain control function may malfunction due to the high nonlinearity of the DCO or DAC.

In addition, although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention as claimed in the claims In addition, various modifications are possible by those of ordinary skill in the art, and these modifications should not be individually understood from the technical spirit or perspective of the present invention.

Claims

a Frequency Modulation Profile Generator (FMPG) that generates a chirp signal and applies it to a Digital Loop Filter (DLF) and a Multi-Modulus Divider (MMD);

AGC (Automatic Gain Controller) for adjusting the gain of the chirp signal generated in the FMPG and applied to the DLF;

BBPFD (Bang-Bang Phase-Frequency Detector) for calculating the difference between the reference signal and the output signal of the MMD;

DLF that accumulates the difference signal output from the BBPFD, and uses a chirp signal whose gain is adjusted by the AGC when accumulating;

Digitally-Controlled Oscillator (DCO) for generating a chirp signal based on the output signal of the DLF and outputting it as a Frequency Modulated Continuous Wave (FMCW) signal;

FMCW frequency modulator comprising: an MMD that divides the chirp signal generated by the DCO, and modulates a division ratio based on the chirp signal generated by the FMPG.
The method according to claim 1,

FMCW frequency modulator further comprising a; delta-sigma modulator (DSM) for delta-sigma-modulating the chirp signal generated from the FMPG and applied to the MMD.
The method according to claim 1,

AGC,

FMCW frequency modulator, characterized in that the gain of the chirp signal generated by the FMPG is adjusted based on the difference signal output from the chirp signal generated from the FMPG and the BBPFD.
4. The method according to claim 3,

AGC,

a first accumulator for accumulating the difference signal output from the BBPFD;

a first switch for outputting a first accumulated value of the first accumulator in a section in which the division ratio is positive;

a second switch for outputting a second accumulated value of the first accumulator in a section in which the division ratio is negative;

a subtractor for calculating a difference between the second accumulated value output by the second switch and the first accumulated value output by the first switch;

a determiner that determines the sign of the subtractor;

and a second accumulator for reducing a gain when the sign determined by the determiner is +.
5. The method of claim 4,

The second accumulator is

FMCW frequency modulator, characterized in that if the sign determined by the determiner is -, the gain is increased.
6. The method of claim 5,

FMCW frequency modulator, characterized in that the gain adjustment is made for each period of the division ratio.
4. The method according to claim 3,

DLF,

An FMCW frequency modulator, characterized in that the difference signal output from the BBPFD is accumulated by applying a first weight, and when accumulating, the chirp signal generated from the FMPG whose gain is adjusted by the AGC is accumulated together.
8. The method of claim 7,

DLF,

FMCW frequency modulator, characterized in that the difference signal output from the BBPFD is further accumulated by applying a second weight.
The method according to claim 1,

Compensation unit for linearly compensating the output signal of the DLF; further comprising,

DCO,

FMCW frequency modulator, characterized in that based on the signal compensated by the compensator, generating a chirp signal and outputting it as an FMCW signal.
A Frequency Modulation Profile Generator (FMPG), generating a chirp signal and applying it to a Digital Loop Filter (DLF) and a Multi-Modulus Divider (MMD);

AGC (Automatic Gain Controller) adjusting the gain of the chirp signal generated in the FMPG and applied to the DLF;

Calculating, by a Bang-Bang Phase-Frequency Detector (BBPFD), a difference between the reference signal and the output signal of the MMD;

A DLF accumulating a difference signal output from the BBPFD, using a chirp signal whose gain is adjusted by the AGC when accumulating;

A digitally-controlled oscillator (DCO), based on the output signal of the DLF, generating a chirp signal and outputting it as a frequency modulated continuous wave (FMCW) signal;

FMCW frequency modulation method comprising the; the MMD divides the chirp signal generated by the DCO, and modulates a division ratio based on the chirp signal generated by the FMPG.
BBPFD (Bang-Bang Phase-Frequency Detector) for calculating the difference between the reference signal and the output signal of the MMD;

DLF (Digital Loop Filter) for accumulating the difference signal output from the BBPFD;

a compensator for linearly compensating the output signal of the DLF;

a digitally-controlled oscillator (DCO) for generating a chirp signal based on the signal compensated by the compensator and outputting it as an FMCW signal;

FMCW frequency modulator comprising a; MMD (Multi-Modulus Divider) for dividing the chirp signal generated by the DCO.
Calculating, by a Bang-Bang Phase-Frequency Detector (BBPFD), a difference between a reference signal and an output signal of the MMD;

accumulating, by a digital loop filter (DLF), a difference signal output from the BBPFD;

Compensating, linearly compensating the output signal of the DLF;

A digitally-controlled oscillator (DCO), based on the signal compensated by the compensator, generating a chirp signal and outputting it as an FMCW signal;

FMCW frequency modulation method comprising a; by a Multi-Modulus Divider (MMD), dividing the chirp signal generated by the DCO.