WO2022111118A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2022111118A1
WO2022111118A1 PCT/CN2021/124085 CN2021124085W WO2022111118A1 WO 2022111118 A1 WO2022111118 A1 WO 2022111118A1 CN 2021124085 W CN2021124085 W CN 2021124085W WO 2022111118 A1 WO2022111118 A1 WO 2022111118A1
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WO
WIPO (PCT)
Prior art keywords
light
emitting unit
sub
column
display area
Prior art date
Application number
PCT/CN2021/124085
Other languages
English (en)
French (fr)
Inventor
杜丽丽
黄耀
龙跃
王本莲
黄炜赟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/914,660 priority Critical patent/US11915634B2/en
Publication of WO2022111118A1 publication Critical patent/WO2022111118A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate and a display device.
  • Under-screen camera means that the front camera is located at the bottom of the screen but does not affect the display function of the screen.
  • the screen above the camera can still display images normally. From the appearance point of view, the under-screen camera will not have any camera hole, which truly achieves the full-screen display effect.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate, including a first display area and a second display area, the first display area including a plurality of first light-emitting units and a plurality of first sub-pixels circuit, the plurality of first light-emitting units include adjacent first light-emitting unit columns and second light-emitting unit columns, each light-emitting unit column is connected to a corresponding column of first sub-pixel circuits, and the second display area includes a plurality of a second light-emitting unit and a plurality of second sub-pixel circuits, the plurality of second light-emitting units include a third light-emitting unit column and a fourth light-emitting unit column arranged adjacently, and each light-emitting unit in the second display area
  • the columns are connected to a column of first sub-pixel circuit pairs, and each column of first sub-pixel circuit pairs includes two adjacent columns of second sub-pixel circuits; a plurality of first sub-data lines and
  • each of the fourth sub-data lines is connected to each of the fourth light-emitting cell columns, and the second direction intersects the first direction.
  • the arrangement direction of the first light-emitting unit column and the second light-emitting unit column is the same as the arrangement direction of the third light-emitting unit column and the fourth light-emitting unit column, and a column connected to the first light-emitting unit column
  • a first sub-pixel circuit and a column of second sub-pixel circuits connected to the third light-emitting unit column are located in the same column, and the first sub-data line and the third sub-data line extend along the second direction and One continuous data line;
  • the two columns of the second sub-pixel circuits connected to the fourth column of light-emitting units and the column of first sub-pixel circuits connected to the second column of light-emitting units are located in different columns, and the The second sub-data line and the fourth sub-data line are connected by a data line connecting portion
  • a column of first sub-pixel circuits connected to the second column of light-emitting units and another column of second sub-pixel circuits connected to the third column of light-emitting units are located in the same column.
  • the first display area further includes a fifth light-emitting unit column and a sixth light-emitting unit column adjacently arranged, the first light-emitting unit column, the second light-emitting unit column, the sixth light-emitting unit column
  • the fifth light-emitting unit column and the sixth light-emitting unit column are repeatedly arranged along the first direction, the third light-emitting unit column and the fourth light-emitting unit column are alternately arranged along the first direction
  • the display substrate further includes a A plurality of fifth sub-data lines and a plurality of sixth sub-data lines extending in the second direction, each fifth sub-data line is connected to each fifth light-emitting unit column, and each sixth sub-data line is connected to each sixth light-emitting unit
  • a column of first sub-pixel circuits connected to the fifth column of light-emitting units and a column of second sub-pixel circuits connected to the fourth column of light-emitting units are located in the same column, and a
  • a column of first sub-pixel circuits and another column of second sub-pixel circuits connected to the fourth light-emitting unit column are located in the same column, the sixth sub-data line or the fifth sub-data line and the fourth sub-data line Spaces are set between the lines.
  • the first display area includes a plurality of first sub-light-emitting unit groups and a plurality of second sub-light-emitting unit groups arranged alternately along the first direction and the second direction
  • the first sub-light-emitting unit group includes light-emitting units in the first light-emitting unit column and the second light-emitting unit column
  • the second sub-light-emitting unit group includes the fifth light-emitting unit column and the sixth light-emitting unit column
  • the second display area includes a plurality of third sub-light-emitting unit groups, each of which includes a first-color light-emitting unit, a second-color light-emitting unit pair, and a third light-emitting unit pair Color light-emitting units, the first-color light-emitting units and the third-color light-emitting units are arranged along the second direction, and the second-color light-e
  • the base substrate further includes a third display area
  • the second display area further includes a plurality of third sub-pixel circuits
  • the third display area includes a plurality of third light-emitting circuits unit
  • the plurality of third light-emitting units include a seventh light-emitting unit column and an eighth light-emitting unit column arranged adjacently, and the arrangement direction of the first light-emitting unit column and the second light-emitting unit column is the same as that of the seventh light-emitting unit column.
  • each light-emitting unit column in the third display area is connected to a column of second sub-pixel circuit pairs, and each column of second sub-pixel circuit pairs includes two adjacent ones.
  • a third sub-pixel circuit in a row the display substrate further includes a plurality of seventh sub-data lines and a plurality of eighth sub-data lines extending along the second direction, each seventh sub-data line and each seventh light-emitting unit column connection, each eighth sub-data line is connected to each eighth light-emitting unit column, and at least one of the seventh sub-data line and the eighth sub-data line is arranged on the third sub-data line and the fourth sub-data line between the sub data lines.
  • the seventh sub-data line and the eighth sub-data line are both disposed between the third sub-data line and the fourth sub-data line, and the third sub-data line A space is provided between the eight sub-data lines and the fifth sub-data line to provide the sub-data line connecting portion.
  • the plurality of third sub-pixel circuits are respectively configured to be connected to a plurality of fourth sub-light-emitting unit groups, and the relative positions of the light-emitting units in each of the fourth sub-light-emitting unit groups
  • the distribution is the same as the relative position distribution of each light-emitting unit in the third sub-light-emitting unit group, and the first sub-pixel circuit pair connected to the third sub-light-emitting unit group and the fourth light-emitting unit group are connected.
  • the second sub-pixel circuit pairs are alternately arranged along the first direction and the second direction.
  • the third display area includes a center area and an edge area surrounding the center area, and the edge area includes a plurality of arrays arranged along the first direction and the second direction dummy pixel circuits to form a plurality of dummy pixel circuit columns and a plurality of dummy pixel circuit rows.
  • the plurality of dummy pixel circuit columns in the third display area include a dummy pixel circuit column group composed of four adjacent columns, and each dummy pixel circuit column group includes a first dummy pixel circuit column, a second dummy pixel circuit column, a third dummy pixel circuit column and a fourth dummy pixel circuit column arranged in sequence in the first direction, the display substrate further includes a first dummy data line, a second dummy data line line, a third dummy data line and a fourth dummy data line, the first dummy data line is connected to the first dummy pixel circuit column, the second dummy data line is connected to the second dummy pixel circuit column, The third dummy data line is connected to the third dummy pixel circuit column, and the fourth dummy data line is connected to the fourth dummy pixel circuit column.
  • Sub-pixel circuits and the first dummy pixel circuit column are located in the same column, and a column of first sub-pixel circuits connected to the second light-emitting unit column and the second dummy pixel circuit column are located in the same column, and the fifth column is located in the same column.
  • a row of first sub-pixel circuits connected to a row of light-emitting units is located in the same column as the third dummy pixel circuit row, and a row of first sub-pixel circuits connected to the sixth row of light-emitting units is located in a row of the fourth dummy pixel circuit.
  • the two sub-data lines connected to the first light-emitting unit group and the corresponding two dummy data lines are two continuous sub-data lines, or the two sub-data lines connected to the second light-emitting unit group are the corresponding two sub-data lines.
  • the two dummy data lines are two consecutive data lines.
  • the display substrate further includes a peripheral area located on a side of the third display area away from the first display area, which is connected to the first light-emitting unit group or the second light-emitting unit group.
  • the two dummy data lines connected by cell groups bypass the central area to connect the seventh sub-data line and the eighth sub-data line in the peripheral area, respectively.
  • the first dummy data line and the first sub-data line are a continuous data line
  • the second dummy data line and the second sub-data line are a continuous data line
  • a space is set between the third dummy data line and the fifth sub-data line
  • a space is set between the fourth dummy data line and the sixth sub-data line.
  • the first dummy data line bypasses the central area to connect the seventh sub data line in the peripheral area
  • the second dummy data line bypasses the center area to connect the eighth sub data line in the peripheral area
  • Another embodiment of the present disclosure provides a display device including the above-mentioned display substrate.
  • FIG. 1 is a schematic partial plan structure diagram of a display substrate provided according to an embodiment of the present disclosure
  • FIG. 2 is an equivalent diagram of a pixel circuit of at least one of the second pixel circuit group and the third pixel circuit group shown in FIG. 1;
  • 3A is a schematic partial planar structure diagram of an active semiconductor layer of a pixel circuit in a second display region provided according to an embodiment of the present disclosure
  • 3B is a schematic diagram of an active semiconductor layer and a first conductive stack in the second display area provided according to an embodiment of the present disclosure
  • 3C is a schematic partial planar structure diagram of the second conductive layer in the second display area provided according to an embodiment of the present disclosure
  • 3D is a schematic diagram of stacking an active semiconductor layer, a first conductive layer, and a second conductive layer in the second display area according to an embodiment of the present disclosure
  • 3E is a schematic partial planar structure diagram of a source-drain metal layer of a second display region according to an embodiment of the present disclosure
  • 3F is a schematic stacking diagram of an active semiconductor layer, a first conductive layer, a second conductive layer, and a source-drain metal layer in the second display area provided according to an embodiment of the present disclosure
  • 4A is a schematic diagram of a connection relationship between a second light-emitting unit group and a second pixel circuit group in a second display area according to an embodiment of the present disclosure
  • FIG. 4B is a schematic layer structure diagram of a light-emitting unit in FIG. 4A;
  • FIG. 4C is a schematic diagram of the positional relationship between the second light-emitting unit group and the via hole in the second display area shown in FIG. 4A;
  • 5A is a schematic structural diagram of a partial pixel circuit at the junction of the first display area and the second display area according to an embodiment of the present disclosure
  • FIG. 5B is a schematic diagram of the structure of the film layer where the data line connection portion at the position shown in FIG. 5A is located;
  • FIG. 5C is a schematic diagram of the structure of the film layer where the data lines at the position shown in FIG. 5A are located;
  • 5D is a partial plan view of the first display area and the second display area in the display substrate shown in FIG. 1;
  • 5E is a partial plan view of a first display area and a second display area in a display substrate provided according to another example of an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a partial pixel circuit at the junction of the edge area of the first display area and the third display area according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a second electrode of a light-emitting unit group located in a first display area according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a second electrode of a light-emitting unit group located at a non-edge of the second display area according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a second electrode of a light-emitting unit group located in a third display area according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of the second electrode of each light-emitting unit in the two-row light-emitting unit group of the second display area bordering the first display area provided according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a second electrode of each light-emitting unit in a two-column light-emitting unit group of a second display area bordering the first display area according to an embodiment of the present disclosure.
  • the inventors of the present application found that: at present, in the organic light emitting diode display device designed with the under-screen camera, the display brightness and current of the low-density display area (L area) are at least lower than those of the high-density display area (H area). Twice, it will affect the display effect.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate, including a first display area and a second display area, the first display area includes a plurality of first light-emitting units and a plurality of first sub-pixel circuits, and the plurality of first light-emitting units include adjacently arranged first light-emitting units.
  • a light-emitting unit column and a second light-emitting unit column each light-emitting unit column is connected to a corresponding column of first sub-pixel circuits
  • the second display area includes a plurality of second light-emitting units and a plurality of second sub-pixel circuits, a plurality of second
  • the light-emitting unit includes a third light-emitting unit column and a fourth light-emitting unit column arranged adjacently, each light-emitting unit column in the second display area is connected to a column of first sub-pixel circuit pairs, and each column of first sub-pixel circuit pairs includes adjacent Two columns of second sub-pixel circuits; a plurality of first sub-data lines, a plurality of second sub-data lines, a plurality of third sub-data lines and a plurality of fourth sub-data lines extending along the second direction, each of the first sub-data lines Each data line is connected to each first light-emitting unit column, each second sub-data line is connected to each second light-emit
  • the arrangement direction of the first light emitting unit column and the second light emitting unit column is the same as the arrangement direction of the third light emitting unit column and the fourth light emitting unit column.
  • a column of second sub-pixel circuits connected to the cell column is located in the same column, the first sub-data line and the third sub-data line are a continuous data line extending along the second direction; the two columns connected to the fourth light-emitting unit column are The sub-pixel circuits and a column of first sub-pixel circuits connected to the second light-emitting unit column are located in different columns, the second sub-data line and the fourth sub-data line are connected through a data line connection portion, and the extension direction of the data line connection portion is the same as that of the data line connection portion.
  • the second direction intersects.
  • the second sub-data line and the fourth sub-data line are not connected, and are connected through the data line connecting part
  • the second sub-data line and the fourth sub-data line are connected to ensure the matching of the data signal transmitted from the data line to the light-emitting unit in the first display area and the data signal transmitted from the data line to the light-emitting unit in the second display area.
  • FIG. 1 is a schematic partial plan structure diagram of a display substrate provided according to an embodiment of the present disclosure.
  • the display substrate includes a base substrate 10 .
  • the display substrate includes a first display area 100 and a second display area 200 .
  • the display substrate further includes a third display area 300 .
  • the second display area 200 is located around the third display area 300 , for example, on both sides of the third display area 300 along the X direction, and the first display area 100 is located around the second display area 200 and the third display area 300 .
  • the second display area 200 and the third display area 300 are located at the edge of the display area, that is, the display substrate includes the display area and a peripheral area surrounding the display area, and the second display area 200 and the third display area 300 are far away from the first display area 100
  • the edge is connected to the surrounding area. That is, the first display area 100 is only located on one side of the third display area 300 along the Y direction.
  • the shape of the third display area 300 may be a rectangle, two edges of the rectangle extending in the Y direction are respectively connected to the second display area 200 located on both sides of the rectangle, and one edge of the rectangle extending in the X direction is connected to the peripheral area The other edge is connected to the first display area 100 .
  • the second display area 200 is located between the first display area 100 and the third display area 300 arranged along the X direction, and one of the two edges of the second display area 200 extending along the X direction is in contact with the peripheral area, The other edge is in contact with the first display area 100 .
  • the first display area 100 includes a plurality of first light-emitting unit groups 110 and a plurality of first pixel circuit groups 120 respectively connected to the plurality of first light-emitting unit groups 110 .
  • a first light-emitting unit group 110 may be connected to a first pixel circuit group 120 to drive the first light-emitting unit group 110 to emit light
  • the first light-emitting unit group 110 and a first pixel circuit group that drives the first light-emitting unit group 110 to emit light 120 are all located in the first display area 100 .
  • the second display area 200 includes a plurality of second light-emitting unit groups 210 and a plurality of second pixel circuit groups 220, and the plurality of second light-emitting unit groups 210 are respectively connected with the plurality of second pixel circuit groups 220.
  • the second display area 200 further includes a plurality of third pixel circuit groups 230 .
  • one second light-emitting unit group 210 can be connected to one second pixel circuit group 220 to drive the second light-emitting unit group 210 to emit light
  • the second light-emitting unit group 210 and the second pixel circuit group that drives the second light-emitting unit group 210 to emit light 220 are all located in the second display area 200 .
  • the third display area 300 includes a plurality of third light-emitting unit groups 310, and the plurality of third light-emitting unit groups 310 are respectively connected to the plurality of third pixel circuit groups 230, that is, the third light-emitting units located in the third display area 300
  • the unit group 310 is connected to the third pixel circuit group 230 located in the second display area 200, and the third light-emitting unit group 310 and the third pixel circuit group 230 driving the third light-emitting unit group 310 to emit light are located in different display areas.
  • the central area 301 of the third display area 300 is only provided with a transparent third light-emitting unit group 310 without a non-transparent pixel circuit group.
  • the central area 301 can be used as an under-screen camera area, both It can have high light transmittance to realize the camera function, and can realize light emission by connecting with the pixel circuit group in other areas, without affecting the display function of the screen.
  • the density of the plurality of second light-emitting unit groups 210 is smaller than the density of the plurality of first light-emitting unit groups 110 .
  • the density of the plurality of third light-emitting unit groups 310 is smaller than the density of the plurality of first light-emitting unit groups 110 .
  • the density (ie pixel density) of the light-emitting unit group in the under-screen camera area (central area of the third display area) is lower than the density of the light-emitting unit group in the normal display area (the first display area), then the camera can be set to allow more Below areas of low pixel density where much light is transmitted.
  • the density of the plurality of second light-emitting unit groups 210 and the density of the plurality of third light-emitting unit groups 310 are both smaller than the density of the plurality of first light-emitting unit groups 110” means that the number of the second light-emitting unit groups under the same area is smaller than that of the first light-emitting unit group The number of lighting unit groups.
  • the first display area 100 is the main display area and has a relatively high resolution (PPI, Pixel Per Inch), that is, the first display area 100 is arranged with sub-pixels with high density for display.
  • Each sub-pixel includes a light-emitting unit and a pixel circuit for driving the light-emitting unit.
  • the third display area 300 can allow light incident from the display side of the display substrate to pass through the display substrate to reach the back side of the display substrate, so that components such as sensors located on the back side of the display substrate can work normally.
  • the third display area 300 may also allow light emitted from the backside of the display substrate to pass through the display substrate to reach the display side of the display substrate.
  • the third display area 300 and the second display area 200 also include a plurality of sub-pixels for display.
  • the pixel circuit of the sub-pixel is usually opaque to light, in order to improve the light-transmittance of the central area 301 of the third display area 300, the light-emitting unit of the sub-pixel of the third display area 300 and the pixel circuit driving the light-emitting unit can be connected Separate from physical location.
  • the pixel circuits connected to the light-emitting unit group in the third display area 300 eg, as shown by the block in the third display area 300 in FIG.
  • each pixel in the second display area 200 A dot-filled box represents a pixel.
  • the pixels in the second display area 200 and the third pixel circuit group 230 connected to the third light emitting unit group 310 in the third display area 300 are arranged in an array in the second display area 200 .
  • the resolutions of the third display area 300 and the second display area 200 are lower than the resolutions of the first display area 100 , that is, the resolution of the pixels used for display arranged in the third display area 300 and the second display area 200 is lower than that of the first display area 100 .
  • the density is smaller than the pixel density of the first display area 100 .
  • FIG. 2 is an equivalent diagram of pixel circuit pairs in the second pixel circuit group and the third pixel circuit group shown in FIG. 1 .
  • each pixel circuit group includes a plurality of pixel circuits 600 .
  • the second pixel circuit group 220 includes a plurality of first pixel circuit units 610 , and the first pixel circuit unit 610 includes at least a first pixel circuit 611 and a second pixel circuit 612 .
  • the first pixel circuit unit 610 may include two pixel circuits, and the first pixel circuit unit 610 may be referred to as a pixel circuit pair 610 .
  • the first pixel circuit unit includes two pixel circuits, but is not limited thereto, and may also include three pixel circuits or more pixel circuits.
  • each light-emitting unit group includes a plurality of light-emitting units
  • the first pixel circuit group 210 includes a plurality of pixel circuits
  • each pixel circuit is configured to be connected to a light-emitting unit to drive the light-emitting unit to emit light
  • the second pixel circuit group 220 includes a plurality of pixel circuits.
  • There are pixel circuit pairs 610 and each pixel circuit pair 610 of the second pixel circuit group 220 is configured to be connected to one light-emitting unit to drive the light-emitting unit to emit light.
  • the third pixel circuit group has 230 multiple second pixel circuit units, each second pixel circuit unit includes at least a third pixel circuit and a fourth pixel circuit, and at least two pixel circuits in the second pixel circuit unit are configured as It is connected with the same light-emitting unit to drive the light-emitting unit to emit light.
  • the second pixel circuit unit may include two pixel circuits, and the second pixel circuit unit may also be referred to as a pixel circuit pair 610 .
  • the embodiment of the present disclosure schematically shows that the second pixel circuit unit includes two pixel circuits, but is not limited thereto, and may also include three pixel circuits or more pixel circuits.
  • each pixel circuit 600 includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2 and a first reset control transistor T7.
  • the first pole of the threshold compensation transistor T2 is connected to the first pole of the driving transistor T3.
  • the second pole of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3
  • the first pole of the first reset control transistor T7 is connected to the reset power supply signal line to receive the reset signal Vinit
  • the second pole of the first reset control transistor T7 Connected to the light emitting unit, the first pole of the data writing transistor T4 is connected to the second pole of the driving transistor T3.
  • the pixel circuit of each sub-pixel further includes a storage capacitor C, a first light emission control transistor T6, a second light emission control transistor T5 and a second reset transistor T1.
  • the gate of the data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; the first pole of the storage capacitor C is electrically connected to the power signal line, and the second pole of the storage capacitor C is electrically connected to the gate of the drive transistor T3
  • the gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive the compensation control signal;
  • the gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset;
  • the first reset transistor T1 The pole of the second reset transistor T1 is electrically connected to the reset power signal line to receive the reset signal Vinit, the second pole of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive reset control signal Reset;
  • the gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM;
  • the second pole of T5 is electrically connected to the second pole of the driving transistor T3, and the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM.
  • the above-mentioned power signal line refers to the signal line for outputting the voltage signal VDD, and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.
  • the scan signal and the compensation control signal may be the same, that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 may be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines.
  • the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 may also be electrically connected to different signal lines respectively, that is, the gate of the data writing transistor T3 is electrically connected to the first scanning signal line, and the threshold compensation transistor
  • the gate of T2 is electrically connected to the second scan signal line, and the signals transmitted by the first scan signal line and the second scan signal line may be the same or different, so that the gate of the data writing transistor T3 and the threshold compensation transistor T2 It can be controlled separately, increasing the flexibility of controlling the pixel circuit.
  • the light emission control signals input to the first light emission control transistor T6 and the second light emission control transistor T5 may be the same, that is, the gate of the first light emission control transistor T6 and the gate of the second light emission control transistor T5 may be electrically connected to the same One signal line to receive the same signal, reducing the number of signal lines.
  • the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 may also be electrically connected to different light-emitting control signal lines, respectively, and the signals transmitted by the different light-emitting control signal lines may be the same or different. .
  • the reset control signals input to the first reset transistor T7 and the second reset transistor T1 may be the same, that is, the gate of the first reset transistor T7 and the gate of the second reset transistor T1 may be electrically connected to the same signal line to To receive the same signal, reduce the number of signal lines.
  • the gate of the first reset transistor T7 and the gate of the second reset transistor T1 may also be electrically connected to different reset control signal lines, respectively.
  • the signals on different reset control signal lines may be the same or different.
  • the second reset transistor T1 when the display substrate is working, in the first stage of screen display, the second reset transistor T1 is turned on to initialize the voltage of the N1 node; in the second stage, the same data signal Data is written through two connected data The input transistor T4, the two drive transistors T3 and the two threshold compensation transistors T2 respectively connected to the two connected data write transistors T4 are stored in the two N1 nodes of the two pixel circuits 600; in the third light-emitting stage, the two The second light-emitting control transistor T5, the driving transistor T3, and the first light-emitting control transistor T6 in each pixel circuit 600 (ie, the pixel circuit pair 610 composed of the first pixel circuit 611 and the second pixel circuit 612) are all turned on, so that the same The data signal is transmitted to the two N4 nodes. At this time, the N4 nodes of the two pixel circuits 600 are connected to jointly drive the same light-emitting unit 20 to emit light, which can achieve the purpose of increasing current and brightness.
  • the pixel circuit of the sub-pixel may be a structure including other numbers of transistors in addition to the 7T1C (ie, seven transistors and one capacitor) structure shown in FIG. 2 ,
  • a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure which is not limited in this embodiment of the present disclosure. It is only necessary to connect the data writing transistors T4 of the two pixel circuits and connect the N4 nodes of the two pixel circuits to jointly drive the same light-emitting unit to emit light.
  • FIG. 3A is a schematic partial planar structure diagram of an active semiconductor layer of a pixel circuit in a second display region provided according to an embodiment of the present disclosure.
  • the active semiconductor layer 3100 may be formed by patterning a semiconductor material.
  • the active semiconductor layer 3100 can be used to fabricate the above-mentioned second reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, second light-emitting control transistor T5, first light-emitting control transistor T6 and first reset control transistor Active layer of T7.
  • the active semiconductor layer 3100 includes an active layer pattern (channel region) and a doping region pattern (source-drain doping region) of each transistor of each sub-pixel, and the active layer pattern and doping region of each transistor in the same pixel circuit.
  • the miscellaneous area pattern is set as one.
  • the active layer may include an integrally formed low temperature polysilicon layer, and the source region and the drain region may be conductive by doping or the like to achieve electrical connection of each structure. That is, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed of p-silicon, and each transistor in the same pixel circuit includes a pattern of doped regions (ie, source and drain regions) and an active layer. pattern, and the active layers of different transistors are separated by doping structures.
  • the active semiconductor layer 3100 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • FIG. 3B is a schematic diagram of an active semiconductor layer and a first conductive stack in the second display region provided according to an embodiment of the present disclosure.
  • the display substrate includes a gate insulating layer on the side of the active semiconductor layer away from the base substrate, for insulating the above-mentioned active semiconductor layer 3100 from the subsequently formed first conductive layer 3200 (ie, the gate metal layer).
  • FIG. 3B shows the first conductive layer 3200 included in the display substrate.
  • the first conductive layer 3200 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 3100 .
  • the first conductive layer 320 may include the second pole CC2 of the capacitor C, a plurality of scan signal lines 430 extending along a first direction (X direction in the figure), a plurality of reset control signal lines 440, and a plurality of light emission control signal lines 450 and gates of the second reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the second light emission control transistor T5, the first light emission control transistor T6 and the first reset control transistor T7.
  • the gate of the data writing transistor T3 may be the portion where the scanning signal line 430 and the active semiconductor layer 3100 overlap; the gate of the first light-emitting control transistor T6 may be the light-emitting control signal line 450 and the active semiconductor layer 3100.
  • the gate of the second light emitting control transistor T5 may be the second portion where the light emitting control signal line 450 overlaps with the active semiconductor layer 3100 .
  • the gate of the second reset transistor T1 is the first portion where the reset control signal line 440 overlaps the active semiconductor layer 3100
  • the gate of the first reset control transistor T7 is the second portion where the reset control signal line 440 overlaps the active semiconductor layer 3100 .
  • the threshold compensation transistor T2 may be a thin film transistor with a double gate structure, the first gate of the threshold compensation transistor T2 may be the portion where the scanning signal line 430 and the active semiconductor layer 3100 overlap, and the second gate of the threshold compensation transistor T2 It may be a portion where the protruding structure P protruding from the scan signal line 430 overlaps with the active semiconductor layer 3100 .
  • the gate of the driving transistor T1 can be the second electrode CC2 of the capacitor C. As shown in FIG.
  • each dotted rectangle in FIG. 3B shows each portion where the first conductive layer 3200 and the active semiconductor layer 3100 overlap.
  • the active semiconductor layers on both sides of each channel region are conductorized by processes such as ion doping to serve as the first and second electrodes of the respective transistors.
  • the source and drain of the transistor may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in physical structure.
  • one of the gate electrodes is directly described as the first electrode and the other electrode is the second electrode.
  • the first and second poles are interchangeable as required.
  • the scan signal lines 430 , the reset control signal lines 440 and the light emission control signal lines 450 are arranged in the second direction (Y direction).
  • the scan signal line 430 is located between the reset control signal line 440 and the light emission control signal line 450 .
  • the first direction and the second direction in the embodiments of the present disclosure are directions that intersect with each other, for example, the first direction is perpendicular to the second direction.
  • the first direction and the second direction in the embodiments of the present disclosure may be interchanged.
  • the second pole CC2 of the capacitor C ie, the gate of the driving transistor T1
  • the second pole CC2 of the capacitor C is located between the scan signal line 430 and the light emission control signal line 450 .
  • the protruding structure P protruding from the scan signal line 430 is located on the side of the scan signal line 430 away from the light emission control signal line 450 .
  • a first insulating layer is formed on the above-mentioned first conductive layer 3200 for insulating the above-mentioned first conductive layer 3200 from the second conductive layer 3300 formed subsequently.
  • FIG. 3C is a schematic partial plan structure diagram of the second conductive layer in the second display area provided according to an embodiment of the present disclosure
  • FIG. 3D is an active semiconductor layer, a first conductive layer in the second display area provided according to an embodiment of the present disclosure Schematic of the stack of layers and the second conductive layer.
  • the second conductive layer 330 includes the first pole CC1 of the capacitor C and a plurality of reset power signal lines 410 extending along the first direction.
  • the first pole CC1 of the capacitor C and the second pole CC2 of the capacitor C at least partially overlap to form the capacitor C.
  • the display substrate provided by the embodiment of the present disclosure further includes a plurality of first connection parts 510 , at least part of the first ends of the first connection parts 510 and the first pixel circuit in the first pixel circuit unit
  • the second pole of the data writing transistor T4 of 611 is connected, and the second end of the first connection part 510 is connected to the second pole of the data writing transistor T4 of the second pixel circuit 612 in the first pixel circuit unit, so that the first At least two data writing transistors T4 of the pixel circuit unit are connected to the same data line, and along the second direction, the first connection portion 510 is located at the second pole of the data writing transistor T2 in the first pixel circuit 611 and the first between the first poles of the reset control transistor T7.
  • the second electrodes of the data writing transistors of at least two pixel circuits in the second display area are connected through the first connection part to drive one light-emitting unit to emit light, which can increase the current of the light-emitting unit in the second display area and brightness, for example, the current and brightness of the light-emitting unit in the second display area can be increased to 1.8 to 2 times that in the case of driving with one pixel circuit, which solves the problem of low current and brightness in the second display area and achieves more uniformity.
  • the full-screen visual display effect can be used to increase the current of the light-emitting unit in the second display area and brightness, for example, the current and brightness of the light-emitting unit in the second display area can be increased to 1.8 to 2 times that in the case of driving with one pixel circuit, which solves the problem of low current and brightness in the second display area and achieves more uniformity.
  • the first end of part of the first connection part 510 is connected to the second pole of the data writing transistor T4 of the third pixel circuit in the second pixel circuit unit, and the second end of the first connection part 510 is connected to the second pixel circuit
  • the second pole of the data writing transistor T4 of the fourth pixel circuit in the unit is connected so that at least two data writing transistors T4 of the second pixel circuit unit are connected to the same data line, and along the second direction, the first connection The section 510 is located between the second pole of the data writing transistor T2 and the first pole of the first reset control transistor T7 in the third pixel circuit.
  • the first pixel circuit unit and the second pixel circuit unit in the present disclosure are collectively referred to as a pixel circuit pair, and the two pixel circuits included in each pixel circuit unit are both referred to as a first pixel circuit and a second pixel
  • the circuit that is, the third pixel circuit in the second pixel circuit unit may be referred to as a first pixel circuit, and the fourth pixel circuit in the second pixel circuit unit may be referred to as a second pixel circuit.
  • the first connection part 510 is located between the second pole of the threshold compensation transistor T3 and the first pole of the first reset control transistor T7 in the first pixel circuit 611 .
  • the first connection portion 510 is provided on the same layer as the reset power signal line 410 .
  • a second insulating layer is formed on the above-mentioned second conductive layer 3300 to insulate the above-mentioned second conductive layer 3300 from the source-drain metal layer 3400 formed subsequently.
  • FIG. 3E is a schematic partial plan structure diagram of a source-drain metal layer in the second display area provided according to an embodiment of the present disclosure
  • FIG. 3F is an active semiconductor layer, a first A schematic diagram of the stacking of the conductive layer, the second conductive layer and the source-drain metal layer.
  • the source-drain metal layer 3400 includes a data line 420 and a power signal line 460 extending along the second direction.
  • the data line 420 is electrically connected to the second electrode of the data writing transistor T2 through a via hole penetrating the gate insulating layer, the first insulating layer and the second insulating layer.
  • the power signal line 460 is electrically connected to the first electrode of the second light emission control transistor T5 through a via hole penetrating the gate insulating layer, the first insulating layer and the second insulating layer.
  • the power signal lines 460 and the data lines 420 are alternately arranged along the first direction.
  • the power signal line 460 is electrically connected to the first electrode CC1 of the capacitor C through a via hole penetrating the second insulating layer.
  • a passivation layer and a flat layer may be provided on the side of the above-mentioned source-drain metal layer 3400 away from the base substrate to protect the above-mentioned source-drain metal layer 3400 .
  • FIGS. 3D to 3F schematically illustrate some pixel circuits in the second pixel circuit group 220 and some pixel circuits in the third pixel circuit group 230 .
  • the embodiment of the present disclosure schematically shows that the second pixel circuit group 220 and the third pixel circuit group 230 each include a pixel circuit pair, and the pixel circuit pair includes a first pixel circuit 611 and a second pixel circuit 612 arranged along a first direction,
  • the second electrodes of the data writing transistors T4 of the two pixel circuits in each pixel circuit pair are connected through the first connection portion 510 to drive the same light-emitting unit to emit light.
  • the embodiment of the present disclosure is not limited thereto, for example, only the second pixel circuit group may include the above-mentioned pixel circuit pair, or only the third pixel circuit group may include the above-mentioned pixel circuit pair.
  • the second pixel circuit group 220 and the third pixel circuit group 230 may include eight pixel circuits arranged in two rows, ie, four pixel circuit pairs arranged in a two-dimensional array.
  • the first pixel circuit group does not include the above-mentioned pixel circuit pair (not shown), but only includes four pixel circuits arranged in a two-dimensional array, and two adjacent pixel circuits in the first pixel circuit group are arranged along the first direction.
  • Each of the light-emitting units is driven to emit light, and the two data writing transistors in the two adjacent pixel circuits are independent of each other and are respectively connected to different data lines.
  • the layout difference between the first pixel circuit group and the second pixel circuit group in the embodiment of the present disclosure mainly lies in whether the first connection part is provided, and the setting of the position of the second pole of the data writing transistor connected to the first connection part .
  • the display substrate provided in the embodiment of the present disclosure may adopt a quarter full-height definition (QHD), but due to the difference between the pixel circuits designed with this resolution
  • QHD quarter full-height definition
  • the distance along the second direction between the second pole of the threshold compensation transistor and the first pole of the first reset control transistor is very small, for example, less than 2 microns, for example, 1.4-1.8 microns. Therefore, the second pole of the threshold compensation transistor is It is difficult to provide a first connection portion connecting the second electrodes (data input nodes) of the two data writing transistors of the pixel circuit pair with the first electrodes of the first reset control transistors.
  • the pixel circuit with QHD resolution is designed to have a pixel pitch with FHD resolution (pixel pitch), thereby increasing the distance along the second direction between the second pole of the threshold compensation transistor T2 and the first pole of the first reset control transistor T7 in each pixel circuit to ensure that the two The data input node of the pixel circuit is connected by punching through the first connection part.
  • the second display area includes a plurality of light-emitting units and a plurality of pixel circuits connected to the plurality of light-emitting units in a one-to-one correspondence, and the adjacent pixel circuits are
  • the first connection part is used to connect the dummy pixel circuit and the pixel circuit connected to the light-emitting unit in the second display area, and the pixel circuit can be changed as little as possible.
  • the dummy pixel circuit is effectively used, so that the current and brightness of the light-emitting unit in the second display area (and at least one of the third display area) can be increased to achieve a more uniform full-screen visual display effect.
  • the distance in the second direction between the second pole of the threshold compensation transistor T2 and the first pole of the first reset control transistor T7 is 7-12 microns, so that the distance between the second pole of the threshold compensation transistor T2 and the first reset A first connection part 510 is provided between the first electrodes of the control transistor T7.
  • each pixel circuit further includes: a second connection part 520 and a third connection part 530 arranged in the same layer as the data line 420 , and the second connection part 520 is configured to connect the threshold compensation transistor T2
  • the second electrode of the first reset control transistor T7 and the gate of the driving transistor T3, the third connection part 530 is configured to connect the first electrode of the first reset control transistor T7 and the reset power signal line 410.
  • one end of the second connection part 520 is electrically connected to the second electrode of the threshold compensation transistor T2 through a via hole penetrating the gate insulating layer, the first insulating layer and the second insulating layer, and the other end of the second connection part 520 is electrically connected through
  • the via hole penetrating through the first insulating layer and the second insulating layer is electrically connected to the gate electrode of the driving transistor T3 (ie, the second electrode CC2 of the capacitor C).
  • One end of the third connection part 530 is electrically connected to the reset power signal line 410 through a via hole passing through the second insulating layer, and the other end of the third connection part 530 is passed through the gate insulating layer, the first insulating layer and the second insulating layer.
  • the via hole in is electrically connected to the first pole of the first reset control transistor T7.
  • the distance in the second direction between the edges of the second connection part 520 and the third connection part 530 that are close to each other is 7-12 ⁇ m to
  • the first connection part 510 is provided between the second connection part 520 and the third connection part 530 .
  • the distance in the second direction between the edges of the second connection part 520 and the third connection part 530 that are close to each other may be 8 ⁇ 11 ⁇ m.
  • the first connection parts 510 and the data lines 420 are located in different layers, and along the third direction perpendicular to the base substrate, each of the first connection parts 510 and the data lines 420 and the power signal lines 460 has overlap.
  • a data line 410 and a power supply signal line 460 are provided between the two data writing transistors T4 included in the pixel circuit pair 610 , and the first connection part 510 of the two data writing transistors T4 is connected to the data lines 410 and 460 .
  • the power signal lines 460 all overlap.
  • each pixel circuit further includes a fourth connection part 540 provided at the same layer as the data line 420 , and the fourth connection part 540 is configured to connect the first connection part 510 and the data writing transistor T4
  • the second pole of the pixel circuit pair 610 (for example, the second pixel circuit 612 ) has a space between the fourth connection portion 540 and the adjacent data line 420
  • the other pixel circuit pair 610 (for example, the first pixel circuit 611 ) ) of the fourth connection portion 540 and the data line 420 are integrally structured to realize that the pixel circuit pair 610 is only connected to one data line 420 .
  • the data line next to each other means that there is no other data line between the fourth connection part 540 and the data line 420 .
  • the plurality of first pixel circuit groups 210 are arranged in an array along the first direction and the second direction.
  • the plurality of second pixel circuit groups 220 and the plurality of third pixel circuit groups 230 are alternately arranged, and along the second direction, the plurality of second pixel circuit groups 220 and the plurality of third pixel circuit groups 230 are alternately arranged, And the second pixel circuit group 220 and the third pixel circuit group 230 are connected to different data lines 420 .
  • a straight line extending in the first direction passes through the second poles of the two data writing transistors in the pixel circuit pair, and the entirety of the first connection portion extends in the first direction.
  • different pixel circuit groups are connected to different data lines, so the lengths of the first connection parts in the different pixel circuit groups along the first direction may be different.
  • the lengths of the first connection portions in the first direction in different pixel circuit pairs may also be different.
  • the fourth connecting portion 540 integrated with the data line 420 is the first sub-portion 541
  • the fourth connecting portion 540 that is spaced from the data line 420 is the second sub-portion 542 .
  • the two-pixel circuit group includes eight pixel circuits arranged in an array (four pixel circuits arranged in the row direction and two pixel circuits arranged in the column direction), then in the second pixel circuit group, the two first subsections 541 are arranged in the second direction (for example, in a column), the two second subsections 542 are arranged in the second direction (for example, in a column), and the first subsection 541 and the second subsection 542 are in the first direction (for example, in a row).
  • the arrangement of the first sub-section and the second sub-section in the third pixel circuit group is the same as the arrangement of the first sub-section and the second sub-section in the second pixel circuit group.
  • the first subsection in the second pixel circuit group and the second subsection in the third pixel circuit group are located in different columns so that the second The pixel circuit group and the third pixel circuit group are connected to different data lines.
  • the fourth connection parts in two adjacent pixel circuits in the first pixel circuit group arranged in the first direction or the second direction are all integrated with the data lines. In order to realize the electrical connection between each pixel circuit and the corresponding data line.
  • the display substrate further includes a plurality of covering parts S disposed in the same layer as the first connection part 510 , and each threshold compensation transistor T2 includes two gates T2-g1 and T2-g2 and a Active semiconductor layer 3100 between two gates.
  • the covering portion S overlaps with the active semiconductor layer 3100 , the data line 420 and the power signal line 460 between the two gates.
  • the active semiconductor layer between the two channels of the double-gate threshold compensation transistor T2 is in a floating state when the threshold compensation transistor T2 is turned off, and is easily affected by the surrounding line voltage and jumps, which will affect The threshold value compensates for the leakage current of the transistor T2, thereby affecting the light-emitting brightness.
  • the cover part S is designed to form a capacitor with the active semiconductor layer between the two channels of the threshold compensation transistor T2, and the cover part S can be connected to To the power signal line 460 to obtain a constant voltage, the voltage of the active semiconductor layer in the floating state can be kept stable.
  • the covering portion S overlaps with the active semiconductor layer between the two channels of the double-gate threshold compensation transistor T2, which can also prevent the active semiconductor layer between the two gates from being illuminated to change the characteristics, such as preventing this part
  • the voltage of the active semiconductor layer is changed to prevent crosstalk.
  • the power signal line 460 may be electrically connected to the cover part S through a via hole penetrating the second insulating layer to supply the cover part S with a constant voltage.
  • the orthographic projection of the covering portion S overlapping the active semiconductor layer on the first straight line extending in the first direction overlaps the orthographic projection of the first connecting portion 510 on the first straight line
  • the fourth connection The orthographic projection of the portion 540 on the second straight line extending along the second direction overlaps with the orthographic projection of the covering portion S on the second straight line.
  • the entirety of the portion 510 is arranged in a non-linear shape, such as a zigzag shape.
  • the first connection portion 510 includes a main body connection portion 511 extending in the first direction and two end portions 512 located at both ends of the main body connection portion 511 and extending in the second direction.
  • the end portions 512 are respectively connected to the two fourth connection portions 540 of the pixel circuit pair 610 , and the orthographic projections of the two end portions 512 on the second straight line overlap with the orthographic projection of the covering portion S on the second straight line.
  • the main body connecting portion and both end portions are formed in a zigzag shape to keep a distance from the covering portion.
  • the distance between the covering part S and the second pole of the threshold compensation transistor T2 is smaller than the distance between the covering part S and the first pole of the first reset control transistor T7, that is, the covering part S is closer Threshold compensation transistor T2. Therefore, in order to facilitate the design and keep a certain interval between the first connection part 510 and the cover part S, the first connection part 510 is disposed closer to the first pole of the first reset transistor T7, that is, in the Y direction, The distance between the main body connection part 511 and the second pole of the threshold compensation transistor T2 in the first pixel circuit 611 is greater than the distance between the main body connection part 511 and the first pole of the first reset control transistor T7 in the first pixel circuit 611 . distance.
  • FIG. 4A is a schematic diagram of the connection relationship between the second light-emitting unit group and the second pixel circuit group in the second display area provided according to an embodiment of the present disclosure
  • FIG. 4B is a schematic layer structure diagram of one light-emitting unit in FIG. 4A .
  • each light-emitting unit group includes a plurality of light-emitting units 20 .
  • each light-emitting unit group includes a first-color light-emitting unit 201, a second-color light-emitting unit pair 202, and a third-color light-emitting unit 203, and the first-color light-emitting units 201 and the third-color light-emitting units 203 are arranged in the second direction
  • the second-color light-emitting unit pair 202 includes two second-color light-emitting units arranged along the second direction, a first light-emitting unit block 202-1 and a second light-emitting unit block 202-2, a first-color light-emitting unit 201 and a second light-emitting unit block 202-1
  • the color light-emitting unit pairs 202 are arranged along the first direction.
  • the orthographic projection of the second electrode of the first color light-emitting unit 201 on a straight line extending in the Y direction overlaps with the orthographic projection of the second electrode of the first light-emitting unit block 202-1 on the straight line; the third color The orthographic projection of the second electrode of the light-emitting unit 203 on the straight line extending in this direction overlaps the orthographic projection of the interval between the second electrodes of the two second-color light-emitting units on the straight line.
  • the orthographic projection of the main body electrode of the third-color light-emitting unit 203 (described later) on a straight line extending in this direction does not overlap with the orthographic projections of the main body electrodes of the two second-color light-emitting units on the straight line.
  • each light-emitting unit 20 includes a first electrode 21 , a light-emitting layer 23 and a second electrode 22 arranged in sequence along a direction perpendicular to the base substrate 10 .
  • the display substrate further includes a pixel-defining layer 24, and the pixel-defining layer 24 includes an opening for defining a light-emitting region of a sub-pixel, and the opening exposes the second electrode 22 of the light-emitting unit 20.
  • the light emitting layer 23 of the subsequent light-emitting unit 20 When the light-emitting layer 23 of the subsequent light-emitting unit 20 is formed on the above-mentioned When in the opening of the pixel defining layer 24, the light emitting layer 23 is in contact with the second electrode 22, so that this part can drive the light emitting layer 23 to emit light to form an effective light emitting region.
  • the "effective light-emitting area" here may refer to a two-dimensional planar area, the planar area being parallel to the base substrate. It should be noted that, due to process reasons, the size of the opening of the pixel defining layer is slightly larger than that of the portion close to the base substrate, or the size of the opening from the side close to the base substrate to the side away from the base substrate is slightly larger.
  • the size is gradually increased, so the size of the effective light-emitting area may be slightly different from the size of different positions of the opening of the pixel defining layer, but the overall area shape and size are basically the same.
  • the orthographic projection of the effective light-emitting region on the base substrate substantially coincides with the orthographic projection of the opening of the corresponding pixel defining layer on the base substrate.
  • the orthographic projection of the effective light-emitting area on the base substrate completely falls within the orthographic projection of the opening of the corresponding pixel-defining layer on the base substrate, and the shapes of the two are similar, and the projected area of the effective light-emitting area on the base substrate Compared with the corresponding pixel defining layer, the projected area of the opening on the base substrate is slightly smaller.
  • the first color light emitting unit may be one of the red light emitting unit and the blue light emitting unit
  • the third color light emitting unit may be the other of the red light emitting unit and the blue light emitting unit
  • the second color light emitting unit pair may be a green light emitting unit pair.
  • the present disclosure schematically shows that the first color light emitting unit is a red light emitting unit, and the second color light emitting unit is a green light emitting unit.
  • each pixel circuit further includes a fifth connection part 550 disposed in the same layer as the data line 420 , and the second electrode of the light emitting unit 20 located in the first display area 100 and the second display area 200 22 may be directly electrically connected to the second pole of the first light-emitting control transistor T6 through the fifth connection part 550 .
  • the second poles of the light-emitting units 20 in the first light-emitting unit group 110 may directly communicate with the first light-emitting units through the fifth connection parts 550 of the corresponding pixel circuits 600 in the first pixel circuit group 120 .
  • the second pole of the control transistor T6 is electrically connected.
  • the second poles of the light-emitting units 20 in the second light-emitting unit group 210 may directly pass through the fifth connection portion 550 of the corresponding pixel circuit 600 in the second pixel circuit group 220 and the first light-emitting control transistor.
  • the second pole of T6 is electrically connected.
  • the second poles of each light emitting unit 20 in the second light emitting unit group 210 may be connected to the fifth connection portion 550 through the passivation layer and the first via 561 in the flat layer.
  • the second pixel circuit group 220 includes a plurality of pixel circuit pairs 610
  • the second electrodes 22 of each light-emitting unit 20 of the second light-emitting unit group 210 include a main body electrode and a connection electrode.
  • the main body electrode The shape is substantially the same as the shape of the effective light-emitting area of each light-emitting unit 20, and the connection electrodes are configured to be directly electrically connected to the fifth connection portion 550 to electrically connect to the second electrodes of the two first light-emitting control transistors T6 of the pixel circuit pair 610. connect.
  • the display substrate further includes a plurality of transparent traces 700 located between the second electrode 22 and the film layer where the data lines 420 are located, and each transparent trace 700 extends along the first direction.
  • the third pixel circuit group 230 includes a plurality of pixel circuit pairs 610 , and the transparent traces 700 are configured to connect the second electrodes 22 of the light emitting units 20 in the third light emitting unit group 310 and the fifth connection part 550 so that the third The second electrode 22 of each light-emitting unit 20 of the light-emitting unit group 310 is electrically connected to the second electrodes of the two first light-emitting control transistors T6 of the pixel circuit pair 610 of the third pixel circuit group 230 .
  • the transparent wiring 700 is electrically connected to the fifth connection part 550 in the third pixel circuit group 310 through the passivation layer and the second via 562 in the flat layer; in the third display area 300 , the second electrode 22 of the light emitting unit 20 is connected to the transparent trace 700 through the third insulating layer between the transparent trace 700 and the second electrode 22 , thereby realizing the connection with the pixel circuit 600 in the second display area 200 .
  • FIG. 4C is a schematic diagram of the positional relationship between the second light-emitting unit group and the via hole in the second display area shown in FIG. 4A .
  • a first via group 5610 composed of a plurality of first vias 561 connecting a second light-emitting unit group 210 and a second pixel circuit group 220 is connected to a third light-emitting unit group 310 and a plurality of second via holes 562 of a third pixel circuit group 230 form a second via hole group 5620 .
  • the plurality of first via groups 5610 and the plurality of second via groups 5620 are alternately arranged; along the second direction, the plurality of first via groups 5610 and the plurality of second via groups 5620 are alternately arranged.
  • the second electrode of the light-emitting unit of the second light-emitting unit group is directly connected to the fifth connection portion.
  • the fifth connection part is connected, and the second electrode of the light emitting unit of the third light emitting unit group is connected to the fifth connection part through a transparent wire, so that more space can be reserved for the transparent wire to prevent signal crosstalk.
  • FIG. 5D is a partial plan view of the first display area and the second display area in the display substrate shown in FIG. 1 .
  • the first display area 100 and the second display area 200 in the display substrate include a plurality of pixel circuits 030 arranged along the first direction and the second direction to form a plurality of pixel circuits 030 .
  • pixel circuit columns 32 and a plurality of pixel circuit rows 31 are arranged along the first direction and the second direction to form a plurality of pixel circuits 030 .
  • the plurality of pixel circuits 030 located in the first display area 100 include a plurality of first sub-pixel circuits 031
  • the plurality of pixel circuits 030 located in the second display area 200 include a plurality of second sub-pixel circuits 032 .
  • the plurality of first light-emitting units correspond one-to-one with the plurality of first sub-pixel circuits 031
  • each second light-emitting unit of the second display area 200 (that is, the three-color light-emitting units included in the second light-emitting unit group 210, such as R, G1, G2, and B shown in the figure) is connected to at least two second light-emitting units.
  • the two sub-pixel circuits 032 are connected.
  • the third display area 300 includes a center area 301 and an edge area 302 surrounding the center area 301 , and the edge area 302 of the third display area 300 is connected to the first display area 100 in the Y direction.
  • FIG. 1 schematically shows that the shape of the third display area 300 is a rectangle, the shape of the center area 301 of the third display area 300 is a circle, and the edge area 302 is an area located in the rectangle except for the center area of the circle. .
  • the embodiments of the present disclosure are not limited thereto, and the shapes of the center area and the edge area of the third display area may be set according to actual product requirements.
  • a third light-emitting unit group 310 is provided in both the central area 301 and the edge area 302 of the third display area 300 , and the plurality of third light-emitting unit groups 310 in the third display area 300 are transparently
  • the lines 700 are respectively electrically connected to the plurality of third pixel circuit groups 230 in the second display area 200 to drive the third light emitting unit group 310 to emit light.
  • the central area 301 of the third display area 300 is only provided with light-emitting unit groups, and no pixel circuit group is provided, so that the metal coverage area can be reduced to achieve higher light transmittance, while the edge area 302 of the third display area 300 is provided with light-emitting units.
  • a light-blocking structure is also provided outside the group so that the third display area 300 forms a light-transmitting area (ie, the central area 301 ) having a predetermined shape.
  • the light blocking structure disposed in the peripheral area 302 of the third display area 300 may be a plurality of dummy pixel circuit groups 320 , and the plurality of dummy pixel circuit groups 320 include the third light emitting unit group 310 and the substrate.
  • each dummy pixel circuit group 320 is not connected with any light-emitting unit group, but is only a floating pixel circuit.
  • the edge region 302 is a ring-shaped routing region.
  • the data lines, scan signal lines, power signal lines, reset control lines, light emission control signal lines, reset power signal lines and other lines connected to the third pixel circuit group are all located in the annular line area.
  • the third light-emitting unit group 310 in the third display area 300 can be controlled in half left and right, and the two third display areas 300 are axially symmetrical with respect to the center line extending along the Y direction of the third display area 300 .
  • the third pixel circuit groups 230 in the two display areas 200 are controlled respectively.
  • the third light emitting unit group 310 located on the left side of the center line is controlled by the third pixel circuit group 230 in the second display area 200 located on the left side of the center line, and the third light emitting unit group 310 located on the right side of the center line. It is controlled by the third pixel circuit group 230 located in the second display area 200 to the right of the center line.
  • the traces for driving the light emitting units in the circular central area 301 are arranged in the edge area 302 in a dense arrangement, so that the circular central area 301 serving as the under-screen display area can have as large an area as possible.
  • the first display area 100 and the second display area 200 include a plurality of pixel circuits arranged in a first direction and a second direction to form a plurality of pixel circuit columns 32 and a plurality of pixel circuit rows 31 .
  • the edge area 302 of the third display area 300 includes a plurality of dummy pixel circuits 034 arranged in the first direction and the second direction to form a plurality of dummy pixel circuit columns and a plurality of dummy pixel circuit rows.
  • the dummy pixel circuit in the third display area 300 is also referred to as a pixel circuit here.
  • the dummy pixel circuit is not connected to any light-emitting unit, its structure can be roughly the same as that of the pixel circuits in other areas. seven transistors and one capacitor) structure.
  • a plurality of data lines 420 extending in the Y direction are respectively connected to a plurality of pixel circuit columns 32 .
  • each pixel circuit column 32 includes a pixel circuit column group composed of four adjacent columns, and each pixel circuit column group includes a direction along the X direction (ie, a direction intersecting with the extending direction of the data line 420 ). ) of the first pixel circuit column 321 , the second pixel circuit column 322 , the third pixel circuit column 323 and the fourth pixel circuit column 324 arranged in sequence.
  • the first pixel circuit column 321 , the second pixel circuit column 322 , the third pixel circuit column 323 and the fourth pixel circuit column 324 in the first display area 100 are respectively connected to the first data lines 421 , the first data lines 421 , the first data lines 421 , the first data lines 421 , the first data lines 421 , the second pixel circuit column 323 and the fourth pixel circuit column 324 in the first display area 100 .
  • the second data line 422 , the third data line 423 and the fourth data line 424 are connected.
  • each pixel circuit column group in the second display area includes a first pixel circuit pair and a second pixel circuit pair as an example for description, but it is not limited to this, and can be set according to actual product requirements .
  • the first display area 100 , the second display area 200 and the third display area 300 each include a plurality of light-emitting units 20 , and the plurality of light-emitting units 20 in the first display area 100 are respectively connected to the first display area 100 .
  • the plurality of pixel circuits 600 of the display area 100 are connected.
  • the plurality of light emitting units 20 of the second display area 200 are respectively connected to a part of the pixel circuits 600 of the second display area 200
  • the plurality of light emitting units 20 of the third display area 300 are respectively connected to another part of the pixel circuits 600 of the second display area 200 .
  • the light-emitting units 20 in the second light-emitting unit group 210 are connected to the pixel circuits 600 in the second pixel circuit group 220; the light-emitting units in the third light-emitting unit group 310 in the third display area 300 emit light
  • the unit 20 is connected to the pixel circuits 600 in the third pixel circuit group 230 in the second display area 200 .
  • the embodiment of the present disclosure schematically shows that the second display area only includes the second pixel circuit group and the third pixel circuit group, but is not limited to this. According to factors such as space design requirements in the product, the second display area may also include other pixels.
  • a circuit group such as a dummy pixel circuit group (not connected to the light-emitting unit), etc.
  • the second pixel circuit group 220 and the third pixel circuit group 230 in the second display area 200 both include a first pixel circuit pair 601 and a second pixel circuit pair 602 , then the second pixel circuit group 220 and the third pixel circuit group 230 in the second display area 200
  • the plurality of light emitting units 20 are respectively connected to the plurality of first pixel circuit pairs 601 and the plurality of second pixel circuit pairs 602 in the second display area 200 .
  • the light-emitting unit provided in the first display area may be referred to as the first light-emitting unit
  • the light-emitting unit provided in the second display area may be referred to as the second light-emitting unit
  • the light-emitting unit provided in the third display area may be referred to as the second light-emitting unit the third light-emitting unit.
  • the second pixel circuit group 220 and the third pixel circuit group 230 are alternately arranged in the X direction and the Y direction, and the second pixel circuit group 220 and the third pixel circuit group 230 in the same column arranged in the Y direction are connected to different data lines 420 connections. Therefore, some pixel circuits in the first pixel circuit column 321 in the second display area 200 are connected to the first data line 421 , for example, the pixel circuits in the second pixel circuit group 220 in the first pixel circuit column 321 are connected to the first data line 421 . The first data lines 421 are connected, and the pixel circuits in the third pixel circuit group 230 in the first pixel circuit column 321 are not connected with the first data lines 421 .
  • some pixel circuits in the second pixel circuit column 322 in the second display area 200 are connected to the second data line 422 , for example, pixel circuits in the third pixel circuit group 230 in the second pixel circuit column 322
  • the second data line 422 is connected, and the pixel circuits in the second pixel circuit group 220 in the second pixel circuit column 322 are not connected with the second data line 422 .
  • Some pixel circuits in the third pixel circuit column 323 located in the second display area 200 are connected to the third data line 423 , for example, the pixel circuits in the third pixel circuit group 230 located in the third pixel circuit column 323 are connected to the third data line 423 .
  • the data lines 423 are connected, and the pixel circuits in the second pixel circuit group 220 in the third pixel circuit column 323 are not connected with the third data lines 423 .
  • Some pixel circuits in the fourth pixel circuit column 324 located in the second display area 200 are connected to the fourth data line 424, for example, the pixel circuits in the second pixel circuit group 220 located in the fourth pixel circuit column 324 are connected to the fourth data line 424.
  • the data line 422 is connected, and the pixel circuits in the third pixel circuit group 230 in the fourth pixel circuit column 324 are not connected with the fourth data line 424 .
  • a plurality of first pixel circuit pairs 601 connected to the plurality of light emitting units 20 of the second display area 200 are connected to the first data lines 421 , and are connected to the plurality of first pixel circuit pairs 601 of the second display area 200
  • the plurality of second pixel circuit pairs 602 connected to the light-emitting unit 20 are connected to the fourth data line 424
  • the plurality of first pixel circuit pairs 601 connected to the plurality of light-emitting units 20 of the third display area 300 are connected to the second data line 422
  • a plurality of second pixel circuit pairs 601 connected to the plurality of light emitting units 20 of the third display area 300 are connected to the third data lines 423 .
  • two pixel circuits in the first pixel circuit pair 601 are connected to the first data line 421
  • two pixel circuits in the second pixel circuit pair 602 are connected to the fourth data line 424
  • the third pixel circuit group 230 two pixel circuits in the first pixel circuit pair 601 are connected to the second data line 422
  • two pixel circuits in the second pixel circuit pair 602 are connected to the third data line 423 .
  • the first pixel circuit pair 601 connected to the first color light emitting unit 201 and the third color light emitting unit 203 in the second light emitting unit group 210 is connected to the first data line 421
  • the second pixel circuit pair 602 to which the second color light-emitting unit pair 202 in the second light-emitting unit group 210 is connected is connected to the fourth data line 424 .
  • FIG. 5A is a schematic diagram of a partial pixel circuit structure at the junction of the first display area and the second display area provided according to an embodiment of the present disclosure
  • FIG. 5B is a schematic diagram of the film layer structure where the data line connection portion at the position shown in FIG. 5A is located
  • FIG. 5C is a schematic diagram of 5A is a schematic diagram of the structure of the film layer where the data line is located. As shown in FIG. 1 to FIG.
  • the junction of the first display area 100 and the second display area 200 that is, at the interval between the first sub-pixel circuit 031 and the second sub-pixel circuit 032 , and at least one pixel circuit
  • the second data line 422 , the third data line 423 and the fourth data line 424 connected by the column group are disconnected to form the first fracture 4201 , and the first data line 421 remains continuous without fracture. That is, the part of the second data line 422 located in the second display area 200 and the part located in the first display area 100 are not connected at the junction of the first display area 100 and the second display area 200 .
  • the part of the third data line 423 located in the second display area 200 and the part located in the first display area 100 are not connected at the junction of the first display area 100 and the second display area 200;
  • the part of the second display area 200 and the part located in the first display area 100 are not connected at the junction of the first display area 100 and the second display area 200 .
  • the part of the second data line 422 located in the first display area 100 is close to the end point 4220 of the second display area 200 and is connected to the end point 4240 of the fourth data line 424 located in the second display area 200 and close to the first display area 100 through the data line connection part 560 , the data line connecting portion 560 passes through the first fracture 4201 of the third data line 423 .
  • first data line 421, the second data line 422, the third data line 423 and the fourth data line 424 may refer to a continuous data line, for example, the first data line 421 is a continuous data line; it may also refer to the same Column pixel circuits are connected to discontinuous data lines, such as the second data line 422, the third data line 423, and the fourth data line 424. Therefore, the second data line 422 connected to the first sub-pixel circuit and the second data line 422 are connected to the second sub-pixel circuit.
  • the second data line 422 connected to the sub-pixel circuit is configured to transmit different signals; the third data line 423 connected to the first sub-pixel circuit and the third data line 423 connected to the second sub-pixel circuit are configured to transmit different signals.
  • the fourth data line 424 connected to the first sub-pixel circuit and the fourth data line 424 connected to the second sub-pixel circuit are configured to transmit different signals.
  • the second data line 422 connected to the first sub-pixel circuit 031 and the second data line 422 connected to the second sub-pixel circuit 032 are configured to transmit different signals;
  • the data line 423 and the third data line 423 connected with the second sub-pixel circuit 032 are configured to transmit different signals;
  • the fourth data line 424 is configured to transmit different signals.
  • the data lines located in the same straight line in the first display area and the second display area are referred to as second data lines, third data lines or fourth data lines in this application, the second data lines located in different display areas (The third data line or the fourth data line) is configured to transmit different signals.
  • the embodiment of the present disclosure schematically shows that the end point of the second data line in the first display area close to the second display area is connected to the fourth data line in the second display area through the data line connection part close to the first display area.
  • the end points are connected, but not limited to this, the end point of the second data line in the first display area close to the second display area can also be connected to the end point of the first display area with the third data line in the second display area through the data line connection part connect.
  • the pixel circuit located in the first display area is called the first sub-pixel circuit
  • the pixel circuit connected to the light-emitting unit located in the second display area is called the second sub-pixel circuit
  • the pixel circuit located in the third display area is called the second sub-pixel circuit.
  • the pixel circuit to which the light emitting cells in the region are connected is referred to as a third sub-pixel circuit.
  • the plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the first display area 100 includes a first-color light-emitting unit and a third-color light-emitting unit, which are the same as the first color light-emitting unit.
  • the plurality of light-emitting units 20 connected to the second pixel circuit column 322 in the display area 100 include pairs of light-emitting units of the second color, and the plurality of light-emitting units 20 connected to the third pixel circuit column 323 in the first display area 100 include the first color light-emitting unit pair.
  • the color light-emitting unit and the third-color light-emitting unit, the plurality of light-emitting units 20 connected to the fourth pixel circuit column 324 in the first display area 100 include the second-color light-emitting unit pair.
  • the data signal is transmitted from the source driving integrated circuit located on the side of the first display area away from the second display area to the pixel circuits in the first display area and the second display area through the data line, and transmitted to the pixel circuits in the first display area and the second display area.
  • the data signal of the pixel circuit connected to the light-emitting unit of one color in the two display areas should be the same as the data signal transmitted to the pixel circuit connected to the light-emitting unit of the same color in the first display area.
  • the same pixel circuit column in the first display area is connected to the same data line, and the pixel circuit pair in the second display area is connected to the same data line, it is easy to transmit to the first color light-emitting unit in the first display area.
  • the data signals of the connected pixel circuits have the same problem as the data signals transmitted to the pair of pixel circuits connected to the pair of light emitting units of the second color in the second display area, resulting in a mismatch between the data signals of the first display area and the second display area.
  • each first light-emitting unit group 110 includes a first-color light-emitting unit, a second-color light-emitting unit pair, and a third-color light-emitting unit
  • each second-color light-emitting unit pair includes a first light-emitting unit A cell block and a second light-emitting cell block.
  • the first color light emitting unit and the third color light emitting unit are arranged along a direction (Y direction) parallel to the extending direction of the data line
  • the first light emitting unit block and the second light emitting unit block are arranged along the Y direction
  • the first color light emitting unit and the second light emitting unit block are arranged along the Y direction.
  • the color light emitting unit pairs are arranged along the X direction intersecting the Y direction, and the first color light emitting units in the adjacent two first light emitting unit groups point to the third color light emitting unit in opposite directions. That is, the light-emitting units connected to the pixel circuits in one row of pixel circuits in the first display area close to the second display area and located in the pixel circuit column group are the first-color light-emitting unit, the first light-emitting unit block, the third A color light-emitting unit and a second light-emitting unit block.
  • the four light-emitting units connected to the pixel circuits in the second row of the pixel circuit column group and located in the first display area and close to the second display area are the third-color light-emitting unit, the second light-emitting unit block, and the first-color light-emitting unit in sequence. unit and a first light emitting unit block. Therefore, the arrangement of the first-color light-emitting units and the third-color light-emitting units connected to the pixel circuits of the first pixel circuit column and the pixel circuits of the third pixel circuit column is different from that of the second pixel circuit column and the fourth pixel circuit column. The arrangement of the first light-emitting unit block and the second light-emitting unit block connected to the pixel circuit is different.
  • the data signals transmitted by the data lines are related to the arrangement of light-emitting units of corresponding colors, and both the first display area and the second display area should transmit matching data signals according to the above-mentioned arrangement of light-emitting units.
  • the plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the second display area 200 include alternately arranged first-color light-emitting units 201 and third-color light-emitting units 203 , and
  • the light-emitting unit located in a row of the second display area 200 close to the first display area 100 and connected to the pixel circuits of the first pixel circuit column 321 is, for example, the third-color light-emitting unit 203 .
  • the plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the first display area 100 include alternately arranged first-color light-emitting units and third-color light-emitting units, and are located in the first display area 100 close to the second display area 200 .
  • the light-emitting units connected to the pixel circuits of the first pixel circuit column 321 in a row are the light-emitting units of the first color.
  • the pixel circuits in a row of pixel circuits in the first display area close to the second display area and connected to the first data line are connected to the first color light-emitting unit, and the pixels in a row of pixels in the second display area close to the first display area
  • the pixel circuit in the circuit row and connected to the same first data line is connected to the light-emitting unit of the third color, and the arrangement of the light-emitting unit matches the data signal transmitted by the first data line, then the first data line can be in the first data line.
  • the junction of the display area and the second display area remains connected, and there is no need to disconnect at the junction of the two display areas.
  • the plurality of second-color light-emitting unit pairs 202 connected to the fourth pixel circuit column 324 in the second display area 200 include alternately arranged first light-emitting unit blocks 202-1 and second light-emitting unit blocks 202-1.
  • the light emitting unit block 202-2, the light emitting unit connected to the pixel circuit located in the row of the second display area 200 close to the first display area 100 and which is the fourth pixel circuit column 324 is, for example, the second light emitting unit block 202-2.
  • the plurality of second-color light-emitting unit pairs connected to the fourth pixel circuit column 324 in the first display area 100 include alternately arranged first light-emitting unit blocks and second light-emitting unit blocks, and are located in the first display area 100 close to the second display unit A row of the region 200 and the light-emitting units connected to the pixel circuits of the fourth pixel circuit column 324 are also the second light-emitting unit block.
  • the light-emitting unit connected to the pixel circuit row of the pixel circuit row of the first display area close to the second display area and the pixel circuit of the fourth pixel circuit column and the pixel circuit row of the second display area close to the first display area and the pixel circuit row of the fourth pixel circuit column The light-emitting units connected to the pixel circuits of the fourth pixel circuit column are of the same light-emitting unit, then the data signal of the fourth data line connected to the fourth pixel circuit column of the first display area and the fourth pixel circuit of the second display area
  • the data signals of the fourth data lines connected by the columns do not match, therefore, the fourth data lines should be disconnected at the junction of the first display area and the second display area.
  • the plurality of second-color light-emitting unit pairs connected to the second pixel circuit column 322 in the first display area 100 include alternately arranged first light-emitting unit blocks and second light-emitting unit blocks, And the light-emitting unit connected to the pixel circuit located in a row of the first display area 100 close to the second display area 200 and being the second pixel circuit column 322 is a first light-emitting unit block.
  • the data signal of the fourth data line connected to the fourth pixel circuit column of the second display area matches the data signal of the second data line connected to the second pixel circuit column of the first display area, then the second The part of the data line located in the first display area and the part located in the second display area are disconnected at the junction of the two display areas, and the second data line located in the first display area is connected to the second display area through the data line connection part.
  • the fourth data line of the display area is connected to satisfy the unified algorithm processing of the integrated circuit (IC) in the first display area and the second display area.
  • the second data line, the third data line and the fourth data line are disconnected at the intersection of the first display area and the second display area, and the second data line is connected through the data line connecting part.
  • a part of a display area is close to the end point of the second display area and the fourth data line is located at the end point of the second display area close to the first display area, so as to ensure that the data signal transmitted from the data line to the light-emitting unit in the first display area and the Matching of data signals transmitted by the data lines to the light emitting cells in the second display area.
  • the data line connecting portion 560 and the plurality of data lines 420 are located on different layers.
  • the data line connection portion 560 overlaps with the power signal line 460 . Because the data line connection part needs to pass through the first fracture of the third data line and the two power signal lines to connect the end point of the second data line and the end point of the fourth data line, therefore, the data line connection part needs to be connected with the data line set on different layers.
  • the data line connection portion 560 and the reset power signal line 410 are located on the same layer to facilitate design.
  • a data line connection part 560 is provided between the second pole of the threshold compensation transistor T2 and the first pole of the first reset control transistor T7 in the two pixel circuits of the two pixel circuits.
  • the boundary between the first display area 100 and the second display area 200 refers to the first pole of the first reset transistor of the pixel circuit in the pixel circuit row 31 of the row of pixel circuits in the first display area 100 close to the second display area 200 and the second pole of the data writing transistor.
  • the distance between the second pole of the threshold compensation transistor T2 and the second pole of the first reset control transistor T7 is in the second direction
  • the distance is 7 ⁇ 12 ⁇ m to set the data line connection part 560 between the second pole of the threshold compensation transistor T2 and the first pole of the first reset control transistor T7 .
  • the distance in the second direction between the edges of the second connection part 520 and the third connection part 530 that are close to each other is 7-12 ⁇ m, so that the distance between the edges of the second connection part 520 and the third connection part 530 in the second direction
  • a data line connecting portion 560 is provided between the third connecting portion 530 and the third connecting portion 530 .
  • the second pole of the compensation transistor is adjusted to the threshold value of the pixel circuit by adjusting the threshold value of the pixel circuit.
  • the distance of the space between the first poles of the first reset control transistor can be that both the first connection part and the data line connection part can be set at the second pole of the threshold compensation transistor of the pixel circuit and the first pole of the first reset control transistor A large space is reserved between them to prevent interference with other signals.
  • FIG. 6 is a schematic structural diagram of a partial pixel circuit at the border of the edge region of the first display area and the third display area according to an embodiment of the present disclosure.
  • the plurality of dummy pixel circuit columns in the third display area include a dummy pixel circuit column group composed of four adjacent columns, and each dummy pixel circuit column group includes first and second pixel circuit columns arranged in sequence along the second direction.
  • At least a part of the dummy pixel circuits 034 of the column 0342, at least a part of the dummy pixel circuits 034 of the third dummy pixel circuit column 0343, and at least a part of the dummy pixel circuits 034 of the fourth dummy pixel circuit column 0344 are respectively associated with the first dummy pixel circuits 034 arranged in sequence along the second direction.
  • the data line 421, the second data line 422, the third data line 423 and the fourth data line 424 are connected, and the interval between the dummy pixel circuit 034 and the first pixel circuit 031 (for example, the edge area 302 of the third display area 300 and the first pixel circuit 031) the junction of the display area 100 ), the third data line 423 and the fourth data line 424 are disconnected to form the second fracture 4202 .
  • the first dummy pixel circuit column 0341, the second dummy pixel circuit column 0342, the third dummy pixel circuit column 0343, and the fourth dummy pixel circuit column 0344 may also be referred to as the first pixel circuit column and the second pixel circuit column, respectively.
  • column, a third column of pixel circuits, and a fourth column of pixel circuits may also be referred to as the first pixel circuit column and the second pixel circuit column.
  • the pixel circuit pair connected to the first color light emitting unit and the third color light emitting unit in the third light emitting unit group 310 may be the first pixel circuit pair 601 and the second pixel circuit pair One of 602
  • the pixel circuit pair connected to the second color light emitting unit pair in the third light emitting unit group 310 may be the other of the first pixel circuit pair 601 and the second pixel circuit pair 602 .
  • a pixel circuit pair connected to the first color light emitting unit and the third color light emitting unit of the third light emitting unit group 310 may be connected to one of the second data line 422 and the third data line 423 to connect with the third light emitting unit group 310
  • the pixel circuit pair to which the first light emitting unit block and the second light emitting unit block are connected may be connected to the other of the second data line 422 and the third data line 423 .
  • the pixel circuit pair connected to the first color light emitting unit and the third color light emitting unit of the third light emitting unit group 310 may be connected to the third data line 423 to connect with the first light emitting unit block and the third light emitting unit block of the third light emitting unit group 310.
  • the pixel circuit pairs connected with the two light-emitting unit blocks may be connected with the second data line 422 . Since both the second data line and the third data line are disconnected at the junction of the first display area and the second display area, the pixel circuits connected to the third light-emitting unit group cannot be displayed by the first display area connected to the second display area.
  • the data lines in the area input matching data signals. Therefore, in the embodiment of the present disclosure, the continuous first data line and the second data line at the border of the third display area and the first display area are used to connect the first light-emitting unit blocks and the first light-emitting unit blocks of the third light-emitting unit group 310 respectively.
  • the pair of pixel circuits connected to the second light-emitting unit block and the pair of pixel circuits connected to the first-color light-emitting unit and the third light-emitting unit of the third light-emitting unit group 310 to achieve input matching to the pixel circuits connected to the third light-emitting unit group The data signal satisfies the unified algorithm processing of the integrated circuit in the first display area and the third display area.
  • the plurality of light-emitting units connected to the third pixel circuit column 323 of the second display area 200 in the third display area 300 include alternately arranged first-color light-emitting units and third-color light-emitting units, and are located in the second display area.
  • the light-emitting units connected to the pixel circuits of the first row 200 away from the first display area 100 and the third pixel circuit column 323 are light-emitting units of the third color.
  • the plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the first display area 100 include alternately arranged first-color light-emitting units and third-color light-emitting units, and the third display area 300 located close to the first display area 100
  • a row of data lines connected to the pixel circuits of the first color light-emitting units is a first data line.
  • the plurality of light-emitting units connected to the second pixel circuit column 322 of the second display area 200 in the third display area 300 include alternately arranged first light-emitting unit blocks and second light-emitting unit blocks, and are located in the second display area.
  • the light-emitting units connected to the pixel circuits in the first row and the second pixel circuit column 322 away from the first display area 100 are the second light-emitting unit blocks.
  • the plurality of light-emitting units 20 connected to the second pixel circuit column 322 in the first display area 100 include alternately arranged first light-emitting unit blocks and second light-emitting unit blocks, and a third display area 300 located close to the first display area 100
  • a row of data lines connected to the pixel circuits of the first light-emitting unit block is a second data line. Therefore, the data signals on the first data line and the second data line in the area where the first display area and the edge area of the third display area are connected are respectively connected with the third data line and the second data line in the second display area.
  • the data signals on the lines match, and the data signals transmitted by the third and fourth data lines in the area where the first display area and the edge area of the third display area meet the third data line in the second display area does not match the data signal on the second data line, then at the junction of the edge area of the third display area and the first display area, the first data line and the second data line remain connected, while the third data line and the fourth data line line disconnected.
  • the display substrate further includes a peripheral area 303 located on the side of the third display area 300 away from the first display area 100 , and a first data line 421 located at the edge area 302 of the third display area 300 .
  • a peripheral area 303 located on the side of the third display area 300 away from the first display area 100
  • a first data line 421 located at the edge area 302 of the third display area 300 .
  • the embodiment of the present disclosure schematically shows that the first data line 421 located in the edge area 302 of the third display area 300 bypasses the central area 301 to connect to the third data line of the second display area 200 in the peripheral area 303 423, the second data line 422 located in the edge area 302 of the third display area 300 bypasses the central area 301 to be connected to the second data line 422 of the second display area 200 in the peripheral area 303, thereby facilitating the third display area and the second data line 422 of the second display area 200.
  • the routing of the data lines in the display area is a predefined area.
  • FIGS. 1-6 another embodiment of the present disclosure provides a display substrate including a first display area 100 and a second display area 200 .
  • the first display area 100 includes a plurality of first light-emitting units 110-1 and a plurality of first sub-pixel circuits 031, and the plurality of first light-emitting units 110-1 includes a first light-emitting unit column 110-11 and a second light-emitting unit column 110-11 arranged adjacently.
  • each light-emitting unit column is connected to a corresponding column of first sub-pixel circuits 031
  • the second display area 120 includes a plurality of second light-emitting units 120-1 and a plurality of second sub-pixel circuits 032, a plurality of The second light-emitting unit 120-1 includes a third light-emitting unit column 120-11 and a fourth light-emitting unit column 120-12 that are adjacently arranged, and each light-emitting unit column in the second display area 200 and a column of first sub-pixel circuit pairs 032 -1 connection, each column of first sub-pixel circuit pairs 032-1 includes two adjacent columns of second sub-pixel circuits 032.
  • the display substrate further includes a plurality of first sub-data lines 4210, a plurality of second sub-data lines 4220, a plurality of third sub-data lines 4230, and a plurality of third sub-data lines 4230 extending along the second direction.
  • each of the first sub-data lines 4210 is connected to each of the first light-emitting cell columns 110-11
  • each of the second sub-data lines 4220 is connected to each of the second light-emitting cell columns 110-12
  • each of the third sub-data lines 4210 The line 4230 is connected to each of the third light emitting cell columns 120-11
  • each of the fourth sub-data lines 4240 is connected to each of the fourth light emitting cell columns 120-12, and the second direction intersects the first direction.
  • the arrangement direction of the first light emitting unit column 110-11 and the second light emitting unit column 110-12 is the same as that of the third light emitting unit column 120-11 and the fourth light emitting unit column 120-12.
  • the arrangement direction is the same, a column of first sub-pixel circuits 031 connected to the first light-emitting unit column 110-11 and a column of second sub-pixel circuits 032 connected to the third light-emitting unit column 120-11 are located in the same column, and the first sub-data line 4210 and the third sub-data line 4230 are a continuous data line extending along the second direction; two columns of second sub-pixel circuits 032 connected with the fourth light-emitting unit column 120-12 and two columns with the second light-emitting unit column 110-12 The connected first sub-pixel circuits 031 are located in different columns.
  • the second sub-data line 4220 and the fourth sub-data line 4240 are connected through the data line connecting portion 560 , and the extending direction of the data line connecting portion 5
  • the first sub-data line 4210, the second sub-data line 4220, the third sub-data line 4230 and the fourth sub-data line 4240 here are the same as the first data line 421, the second data line 422, the third data line 421 and the third data line in the above-mentioned embodiment.
  • Line 423 and the fourth data line 424 refer to different meanings.
  • the first sub-data line 4210 here only refers to the data line connecting the pixel circuits in the first display area in the first data line 421 in the above-mentioned embodiment.
  • the two sub data lines 4220 refer to the data lines connected to the pixel circuits in the first display area in the second data lines 422 in the above embodiment
  • the third sub data lines 4230 here only refer to the first data lines 421 in the above embodiment.
  • the data lines connected to the pixel circuits in the second display area, the fourth sub-data lines 4240 here only refer to the data lines connected to the pixel circuits in the second display area among the fourth data lines 424 in the above embodiment
  • the data line can ensure the matching of the data signal transmitted from the data line to the light-emitting unit in the first display area and the data signal transmitted from the data line to the light-emitting unit in the second display area.
  • a column of first sub-pixel circuits 031 connected to the second column of light-emitting units 110-12 and another column of second sub-pixel circuits 032 connected to the third column of light-emitting units 120-11 are located in the same column.
  • the first display area 100 further includes a fifth light-emitting unit column 110-13 and a sixth light-emitting unit column 110-14 arranged adjacently, the first light-emitting unit column 110-11, the second light-emitting unit column 110-11, the second The light-emitting unit column 110-12, the fifth light-emitting unit column 110-13, and the sixth light-emitting unit column 110-14 are repeatedly arranged along the first direction, and the third light-emitting unit column 120-11 and the fourth light-emitting unit column 120-12 are arranged along the first direction. Alternate in one direction.
  • the display substrate further includes a plurality of fifth sub-data lines 4250 and a plurality of sixth sub-data lines 4260 extending along the second direction, each fifth sub-data line 4250 and each fifth sub-data line 4250
  • the light emitting cell columns 110-13 are connected, and each sixth sub-data line 4260 is connected with each sixth light emitting cell column 110-14.
  • a column of first sub-pixel circuits 031 connected to the fifth light-emitting unit column 110-13 and a column of second sub-pixel circuits 032 connected to the fourth light-emitting unit column 120-12 are located in the same column Column
  • one column of first sub-pixel circuits 031 connected to the sixth light-emitting unit column 110-14 and another column of second sub-pixel circuits 032 connected to the fourth light-emitting unit column 120-12 are located in the same column
  • the sixth sub-data line 4260 Or a space is provided between the fifth sub data line 4250 and the fourth sub data line 4240 .
  • 5D schematically shows that the pixel circuit connected to the sixth sub-data line 4260 and the pixel circuit connected to the fourth sub-data line 4240 are located in the same column, then the sixth sub-data line 4260 and the fourth sub-data line 4240 are located between There is an interval, but not limited to this, the pixel circuit connected to the fourth sub-data line and the pixel circuit connected to the fifth sub-data line are located in the same column, and an interval is set between the fourth sub-data line and the fifth sub-data line .
  • the fifth sub-data line 4250 here only refers to the data line connecting the pixel circuits in the first display area in the third data line 423 in the above-mentioned embodiment
  • the sixth sub-data line 4260 here refers to the fourth data line in the above-mentioned embodiment.
  • the lines 424 are connected to the data lines of the pixel circuits in the first display area.
  • FIG. 5E is a partial plan view of a first display area and a second display area in a display substrate provided according to another example of embodiments of the present disclosure.
  • the difference between the example shown in FIG. 5E and the example shown in FIG. 5D lies in the arrangement of pixels.
  • the pixel arrangement is a GGRB arrangement
  • the pixel arrangement is a realRGB arrangement.
  • every six RGB light-emitting units in the first display area 100 is a repetition period.
  • the data line 420 connected to the first column of R light-emitting units in the first display area 100 and the data line 420 connected to the first column of R light-emitting units in the second display area 100 are the same continuous data line; 100
  • the data lines 420 connected to the second column G light-emitting units and the data lines 420 connected to the second column R light-emitting units of the second display area 100 have a space between them, and are connected to the second column G light-emitting units of the first display area 100
  • the data line 420 is connected to the data line 420 connected to the third column G (or fourth column G) light-emitting unit of the second display area 100 through the data line connecting portion 560; There is a space between the connected data line 420 and the data line 420 connected to the third column G light-emitting unit of the second display area 100, and the data line 420 connected to the third column B light-emitting unit of the first display area 100 passes through the data line
  • the connection part 560 is connected to the data line
  • the embodiments of the present disclosure are not limited to the above connections, as long as one R light-emitting unit in the first display area and one R light-emitting unit in the second display area are connected to the same data line, one B light-emitting unit in the first display area and the second One B light-emitting unit in the display area is connected to the same data line, and one G light-emitting unit in the first display area and one G light-emitting unit in the second display area may be connected to the same data line.
  • the first display area 100 includes a plurality of first sub-light-emitting unit groups 1-1 and a plurality of second sub-light-emitting unit groups 1- which are alternately arranged along the first direction and the second direction.
  • the first sub-light-emitting unit group 1-1 includes light-emitting units in a first light-emitting unit column 110-11 and a second light-emitting unit column 110-12
  • the second sub-light-emitting unit group 1-2 includes a fifth light-emitting unit column 110 -13 and the light-emitting cells in the sixth light-emitting cell column 110-14
  • the second display area 200 includes a plurality of third sub-light-emitting cell groups 1-3.
  • each sub-light-emitting unit group includes a first-color light-emitting unit R, a second-color light-emitting unit pair G1 and G2, and a third-color light-emitting unit B, and the first-color light-emitting unit R and the third color light emitting unit B are arranged along the second direction, the second color light emitting unit pair G1 and G2 include two second color light emitting units arranged along the second direction, the first color light emitting unit R and the second color light emitting unit pair G1 and G2 are arranged along the first direction, and the arrangement direction of the first color light-emitting unit R and the third color light-emitting unit B in the first sub-light-emitting unit group 1-1 is the same as that of the first color in the second sub-light-emitting unit group 1-2
  • the light-emitting units R and the third-color light-emitting units B are arranged in opposite directions, and the relative position distribution of each light-e
  • the first color light emitting unit is a red light emitting unit
  • the second color light emitting unit pair is a green light emitting unit pair
  • the third color light emitting unit is a blue light emitting unit, for example, but not limited thereto.
  • the first color light emitting unit may be a blue light emitting unit
  • the second color light emitting unit pair may be a green light emitting unit pair
  • the third color light emitting unit may be a red light emitting unit.
  • the first color light emitting unit is a green light emitting unit
  • the second color light emitting unit pair is a red light emitting unit pair
  • the third color light emitting unit is a blue light emitting unit.
  • the base substrate further includes a third display area 300
  • the second display area 200 further includes a plurality of third sub-pixel circuits 033
  • the third display area 300 includes a plurality of third light-emitting units 130-1
  • the plurality of third light emitting units 130-1 include a seventh light emitting unit column 130-11 and an eighth light emitting unit column 130-12, a first light emitting unit column 110-11 and a second light emitting unit column 130-12, which are adjacently arranged
  • the arrangement direction of 110-12 is the same as the arrangement direction of the seventh light-emitting unit column 130-11 and the eighth light-emitting unit column 130-12
  • each column of second sub-pixel circuit pairs 033-1 includes two adjacent columns of third sub-pixel circuits 033.
  • the display substrate further includes a plurality of seventh sub-data lines 4270 and a plurality of eighth sub-data lines 4280 extending along the second direction, each seventh sub-data line 4270 and each seventh sub-data line 4270
  • the light emitting cell columns 130-11 are connected
  • each eighth sub-data line 4280 is connected with each eighth light emitting cell column 130-12.
  • the seventh sub data line 4270 and the eighth sub data line 4280 is disposed between the third sub data line 4230 and the fourth sub data line 4240 .
  • the seventh sub-data line 4270 here only refers to the data line connecting the pixel circuits in the second display area in the second data line 422 in the above-mentioned embodiment
  • the eighth sub-data line 4280 here refers to the third data line in the above-mentioned embodiment.
  • the line 423 is connected to the data line of the pixel circuit in the second display area.
  • the seventh sub data line 4270 and the eighth sub data line 4280 are both disposed between the third sub data line 4230 and the fourth sub data line 4240, and the eighth sub data line 4280 A space is provided between the fifth sub data line 4250 to provide the data line connection part 560 .
  • the data lines of the eighth sub-data line 4280 and the fifth sub-data line 4250 have a break at the spaced position between the pixel circuit of the first display area and the pixel circuit of the second display area, and the connection part 560 is provided at the break.
  • the plurality of third sub-pixel circuits 033 are configured to be connected with the plurality of fourth sub-light-emitting unit groups 1-4, and the respective light-emitting units in the fourth sub-light-emitting unit groups 1-4
  • the relative position distribution is the same as the relative position distribution of each light-emitting unit in the third sub-light-emitting unit group 1-3.
  • the second sub-pixel circuit pairs 033-1 connected by the groups 1-4 are alternately arranged in the first direction and the second direction.
  • the third display area 300 includes a center area 301 and an edge area 302 surrounding the center area 301 , and the edge area 302 includes a plurality of dummy pixel circuits arranged along the first direction and the second direction to A plurality of dummy pixel circuit columns 320-1 and a plurality of dummy pixel circuit rows 320-2 are formed.
  • the plurality of dummy pixel circuit columns 320 - 1 in the third display area 300 include a dummy pixel circuit column group 3201 composed of four adjacent columns, and each dummy pixel circuit column group 3201 includes A first dummy pixel circuit column 0341, a second dummy pixel circuit column 0342, a third dummy pixel circuit column 0343, and a fourth dummy pixel circuit column 0343 are sequentially arranged in the first direction.
  • the display substrate further includes a first dummy data line 431, a second dummy data line 432, a third dummy data line 433 and a fourth dummy data line 434.
  • the first dummy data line 431 and the The first dummy pixel circuit column 0341 is connected
  • the second dummy data line 432 is connected to the second dummy pixel circuit column 0342
  • the third dummy data line 433 is connected to the third dummy pixel circuit column 0343
  • the fourth dummy data line 434 is connected to the third dummy pixel circuit column 0343.
  • Four dummy pixel circuit columns 0344 are connected.
  • a column of first sub-pixel circuits 031 and first dummy pixel circuit columns 0341 connected to the first light-emitting unit column 110-11 are located in the same column, and are located in the same column as the second light-emitting unit column 110-12.
  • a column of connected first sub-pixel circuits 031 and a second dummy pixel circuit column 0342 are located in the same column, and a column of first sub-pixel circuits 031 connected to the fifth light-emitting unit column 110-13 and a third dummy pixel circuit column 0343 are located in the same column , a column of first sub-pixel circuits 031 connected to the sixth light-emitting unit column 110-14 and the fourth dummy pixel circuit column 0344 are located in the same column.
  • the two data lines connected to the first light-emitting unit group 1-1 and the corresponding two dummy data lines are two continuous data lines, or the two data lines connected to the second light-emitting unit group 1-2 are the corresponding two data lines.
  • the two dummy data lines are two consecutive data lines.
  • FIG. 6 schematically shows that the two data lines connected to the first light-emitting unit group 1-1 and the corresponding two dummy data lines are two continuous data lines.
  • the display substrate further includes a peripheral area 400 located on the side of the third display area 300 away from the first display area 100 , which is connected with the first light-emitting unit group 1-1 or the second light-emitting unit group 1
  • the two dummy data lines connected by -2 bypass the central area 301 to connect the seventh sub data line 4270 and the eighth sub data line 4280 in the peripheral area 400, respectively.
  • the first dummy data line 431 and the first sub-data line 4210 are a continuous data line
  • the second dummy data line 432 and the second sub-data line 4220 are a continuous data line
  • a space is set between the third dummy data line 433 and the fifth sub-data line 4250
  • a space is set between the fourth dummy data line 434 and the sixth sub-data line 4260 .
  • the first dummy data line 431 bypasses the central area 301 to connect the seventh sub-data line 4270 in the peripheral area 400
  • the second dummy data line bypasses the central area to connect the seventh sub-data line 4270 in the peripheral area Eight data lines.
  • FIG. 7 is a schematic diagram of the second electrode of the light-emitting unit group located in the first display area according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of the light-emitting unit group located at a non-edge of the second display area according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of the second electrode of the light-emitting unit group located in the third display area according to an embodiment of the present disclosure. As shown in FIGS.
  • the second electrode 22 of each light-emitting unit 20 includes a main electrode 22 - 1 and a connecting electrode 22 - 2 , and the shape of the main electrode 22 - 1 is basically the same as the shape of the effective light-emitting area of each light-emitting unit 20 .
  • the connection electrode 22 - 2 is configured to be electrically connected to the second electrode of the first light emission control transistor T6 of the pixel circuit through the fifth connection portion 550 .
  • Each light-emitting unit group in the display area includes a plurality of light-emitting units of different colors.
  • each light-emitting unit group includes a first-color light-emitting unit 201 , a second-color light-emitting unit pair 202 and a third-color light-emitting unit 203 .
  • the area of the main electrode 22 - 1 of the light emitting unit of one color located in at least one of the non-edge area of the second display area 200 and the third display area 300 is larger than that located in the first display area 300 .
  • the area of the main electrode of each color light-emitting unit is related to the area of its effective light-emitting area.
  • the area of the main body electrode is set to be larger than the area of the main body electrode of the light-emitting unit located in the first display area and having the same color as the light-emitting unit of the above-mentioned one color, which can make the non-edge area of the second display area and the third display area.
  • the area of the effective light emitting area of at least one color light emitting unit is designed to be larger than the area of the effective light emitting area of the light emitting unit located in the first display area and having the same color as the one color light emitting unit.
  • the densities of the light emitting unit groups in the second display area and the third display area are both smaller than the densities of the light emitting unit groups in the first display area, by dividing at least one of the second display area and the third display area
  • the area of the main body electrode in the light-emitting unit is set to be larger than the area of the main body electrode in the light-emitting unit of the first display area so that one color light-emitting unit located in at least one of the non-edge area of the second display area and the third display area
  • the area of the effective light-emitting area is designed to be larger than the area of the effective light-emitting area of the light-emitting unit located in the first display area and the same color as the light-emitting unit of the above-mentioned one color, which can increase the second display on the basis of ensuring the life of the light-emitting unit light-emitting material.
  • the brightness of at least one of the display area and the third display area can achieve a more uniform full
  • the embodiment of the present disclosure schematically shows that in the non-edge area of the second display area 200 and the third display area 300 , the area of the main electrode 22 - 1 of the light-emitting unit of one color is larger than that in the first display area 100 .
  • the area of the main electrode 22-1 of the light-emitting unit 20 with the same color as the above-mentioned one-color light-emitting unit is such that the area of the effective light-emitting area of the one-color light-emitting unit located in the non-edge area of the second display area and the third display area is It is designed to be larger than the area of the effective light-emitting area of the light-emitting unit located in the first display area and having the same color as the light-emitting unit of the above-mentioned one color, so that the second display area and the second display area can be increased on the basis of ensuring the life of the light-emitting unit light-emitting unit.
  • the brightness of the three display areas achieves a more uniform full-screen visual display effect.
  • each light-emitting unit in the first display area, the second display area, and the third display area is connected to one pixel circuit, that is, each of the second display area and the third display area is connected to one pixel circuit.
  • the light emitting unit may not be connected with the pair of pixel circuits, but only with one pixel circuit.
  • the densities of the light-emitting unit groups in the second display area and the third display area are both smaller than the density of the light-emitting unit groups in the first display area.
  • the area of the main body electrode is set to be larger than the area of the main body electrode in the light-emitting unit of the first display area so that the effective light-emitting area of the light-emitting unit of one color in at least one of the non-edge area of the second display area and the third display area
  • the area is designed to be larger than the area of the effective light-emitting area of the light-emitting unit located in the first display area and having the same color as the above-mentioned one-color light-emitting unit, so as to make the display effect of each display area as uniform as possible.
  • each pixel circuit group includes a plurality of pixel circuits, and at least one of the second pixel circuit group and the third pixel circuit group in the second display area includes a plurality of pixel circuit pairs, The two pixel circuits included in each pixel circuit pair are configured to be electrically connected to the second electrode of the same light-emitting unit.
  • both the second pixel circuit group and the third pixel circuit group in the second display area include a plurality of pixel circuit pairs, and each pixel circuit pair in the second pixel circuit group is connected to each light-emitting unit in the second light-emitting unit group , each pixel circuit pair in the third pixel circuit group is connected to each light emitting unit in the third light emitting unit group.
  • the densities of the light-emitting unit groups in the second display area and the third display area are both smaller than the density of the light-emitting unit groups in the first display area, and the pixel circuits connected to the light-emitting units in the second display area and the third display area are designed as pixel circuits
  • the right solution is combined with the solution of setting the area of the main electrode in the light-emitting units of the second display area and the third display area to be larger than the area of the main electrode in the light-emitting unit of the first display area, which can ensure the life of the light-emitting material of the light-emitting unit.
  • the current and brightness of the light-emitting units in the second display area and the third display area will be increased to 1.8 to 2 times that in the case of one pixel circuit driving, which solves the problem of the current and the brightness in the second display area and the third display area.
  • the problem of low brightness can achieve a more uniform full-screen visual display effect.
  • each light-emitting unit group includes a first-color light-emitting unit 201 , and each first-color light-emitting unit located in at least one of the non-edge area of the second display area 200 and the third display area 300 emits light
  • the ratio of the area of the main electrode 2011 of the unit 201 to the area of the main electrode 2011 of each first color light-emitting unit 201 in the first display area 100 is 1.5 ⁇ 2.5, for example, 1.9 ⁇ 2.1.
  • the area of the effective light-emitting area of each first-color light-emitting unit 201 located in at least one of the non-edge area of the second display area 200 and the third display area 300 and the area of each first-color light-emitting area located in the first display area 100 The area ratio of the effective light-emitting region of the cell 201 is 2.
  • the shape of the main body electrode 2011 and the effective light-emitting area of the first-color light-emitting unit 201 in each display area are both hexagonal, and the shapes of the body electrodes 2011 and the effective light-emitting area of the first-color light-emitting unit 201 in each display area are both hexagonal, and are located at the first non-edge of the second display area 200 .
  • the area of the connection electrode 2012 of the color light-emitting unit 201 may be larger than the area of the connection electrode 2012 of the first color light-emitting unit 201 in the first display area 100 to realize the connection with the pixel circuit pair.
  • the area of the main electrode 2021 of each second-color light-emitting unit pair 202 located in at least one of the non-edge area of the second display area 200 and the third display area 300 is the same as the area of the main electrode 2021 located in the second-color light-emitting unit pair 202
  • the area ratio of the main electrodes 2021 of each second color light emitting unit pair 202 in a display area 100 is 1.5 ⁇ 2.5, for example, 1.9 ⁇ 2.1.
  • the area of the effective light-emitting area of each second-color light-emitting unit pair 202 located in the non-edge area of the second display area 200 and the third display area 300 is the same as the area of each second-color light-emitting unit pair 202 located in the first display area 100
  • the area ratio of the effective light-emitting region was 2.
  • the area of the body electrode 2021 - 1 of each first light emitting unit block 202 - 1 located in at least one of the non-edge area of the second display area 200 and the third display area 300 The area ratio to the body electrodes 2021-1 of the first light emitting unit blocks 202-1 in the first display area 100 is 1.5 ⁇ 2.5, for example, 1.9 ⁇ 2.1.
  • the area of the main body electrodes 2021 - 2 of the second light emitting unit blocks 202 - 2 located in at least one of the non-edge area of the second display area 200 and the third display area 300 is the same as that of each of the second light emitting unit blocks 202 - 2 located in the first display area 100 .
  • the area ratio of the body electrode 2021-2 of the second light emitting unit block 202-2 is 1.5 to 2.5, for example, 1.9 to 2.1.
  • the area of the connection electrodes 2022-1 of the first light emitting unit blocks 202-1 located in the non-edge region of the second display area 200 is larger than that of the connection electrodes of the first light emitting unit blocks 202-1 located in the first display area 100 2022-1 area.
  • the area of the connection electrodes 2022-2 of the second light-emitting unit blocks 202-2 located in the non-edge region of the second display area 200 is larger than that of the connection electrodes of the second light-emitting unit blocks 202-2 located in the first display area 100 2022-2 area to facilitate connection with pixel circuit pairs.
  • the area of the main body electrode 2031 of each third-color light-emitting unit 203 located in at least one of the non-edge area of the second display area 200 and the third display area 300 and the area of each third-color light-emitting unit located in the first display area 100 The area ratio of the body electrode 2031 of the cell 203 is 1.5 to 2.5, for example, 1.9 to 2.1.
  • the area of the main electrode 2031 of each third-color light-emitting unit 203 located in the non-edge region of the second display area 200 and the third-color light-emitting unit 203 in the 2031 has an area ratio of 2.
  • the area ratio of the area is 2.
  • connection electrode 2032 of each third-color light-emitting unit 203 located in the non-edge area of the second display area 200 is larger than the area of the connection electrode 2032 of each third-color light-emitting unit 203 located in the first display area 100 to achieve the same Connection of pixel circuit pairs.
  • the shapes of the main electrode and the effective light-emitting area of the third-color light-emitting unit of each display area are both hexagonal.
  • the second electrodes of the light-emitting units of the light-emitting unit group in the second display area are directly connected to the pixel circuit pair, so the area of the connection electrodes of the light-emitting units in the second display area is larger, while the The second electrodes of the light emitting units of the light emitting unit group in the third display area are connected to the pixel circuit pairs in the second display area through transparent wires, so the area of the connecting electrodes of the light emitting units in the third display area can be set to be smaller.
  • FIG. 10 is a schematic diagram of a second electrode of each light-emitting unit in a two-row light-emitting unit group of a second display area bordering the first display area provided according to an embodiment of the present disclosure.
  • the shape and area of the main electrode 2011 of each first-color light-emitting unit 201 in a row of light-emitting unit groups adjacent to the first display area 100 in the Y direction of the second display area 200 are the same as
  • the shapes and areas of the main electrodes 2011 of the first-color light-emitting units 201 in the first display area 100 are substantially the same.
  • the shapes and areas of the main electrodes of the first-color light-emitting units in the two-row light-emitting unit groups of the second display area and the first display area adjacent to each other in the Y direction are set to be approximately the same, that is, The area of the main electrode of the light-emitting unit of the first color located at the edge of the second display area and the area of the main electrode of the light-emitting unit of the first color located in the non-edge area of the second display area are designed to be different, so that most of the second display area can be used.
  • the brightness of the light-emitting units of the first color is increased to achieve a uniform full-screen display effect, and at the same time, the main electrodes of the two rows of light-emitting units are prevented from conflicting in space.
  • the main electrodes 2021 of each second-color light-emitting unit pair 202 in a row of light-emitting unit groups of the second display area 200 adjacent to the first display area 100 in the first direction The ratio of the area to the area of the main electrode 2021 of each second-color light-emitting unit pair 202 located in the first display area 100 is 0.9 ⁇ 1.1.
  • the areas of the main electrodes of the light-emitting units of each second color in the two-row light-emitting unit groups of the second display area and the first display area adjacent to each other in the Y direction are set to be approximately the same, that is, the area of the main electrodes in the second display area is set to be approximately the same.
  • the area of the main electrode of the light-emitting unit of the second color at the edge of the display area is designed to be different from the area of the main electrode of the light-emitting unit of the second color located in the non-edge area of the second display area.
  • the brightness of the light-emitting unit is increased to achieve a uniform full-screen display effect, and at the same time, the main electrodes of the two rows of light-emitting units are prevented from conflicting in space.
  • the shape of the body electrodes 2021 of the two second-color sub-pixels included in the second-color sub-pixel pair 202 in the first display area 100 is the same as that of the second display area 200 and the first The shapes of the two body electrodes 2021 of each second-color light-emitting unit pair 202 of a row of light-emitting unit groups adjacent to each other in the first direction of the display area 100 are different.
  • the size of the gap (PDL gap) of the pixel defining layer between two adjacent light-emitting units located in the non-edge region of the second display area is the same as that of the two adjacent light-emitting units located in the edge region of the second display area.
  • the size of the PDL gap between the light-emitting units is approximately the same, so that the second display area displays the uniformity of image light.
  • the shapes of the body electrodes 2021 of the two second color subpixels included in the second color subpixel pair 202 in the first display area 100 are both pentagons, and each The shape includes a first side 1 extending along the X direction, two second sides 2 extending along the Y direction, and two third sides 3 connected with the two second sides 2, and the two third sides 3 intersect to form a sharp point corners, the two sharp corners of the body electrodes 2021 of the two second color sub-pixels are close to each other.
  • Each main body electrode 2021 of each second-color light-emitting unit pair 202 of a row of light-emitting unit groups adjacent to the first display area 100 in the Y direction of the second display area 200 includes a fourth side 4 extending along the X direction, along Two fifth sides 5 extending in the Y direction, two sixth sides 6 connected to the two fifth sides 5, and a seventh side 7 connecting the two sixth sides 6, the body electrodes of the two second color sub-pixels
  • the two seventh sides 7 of 2021 are close to each other.
  • the length of the second side 2 of the main electrode 2021 of the second color light-emitting unit of the first display area 100 is smaller than the length of the main electrode 2021 of the second color light-emitting unit of the second display area 200 edge
  • the length of the fifth side 5 ensures that the area of the main electrode of the second color light emitting unit in the first display area is approximately equal to the area of the main electrode of the second color light emitting unit at the edge of the second display area.
  • the area of the body electrode 2021 of the second color light emitting unit at the edge of the second display area 200 is set to be the same as the area of the body electrode 2021 of the second color light emitting unit of the first display area 100 .
  • the PDL gap between the second color light emitting unit and the first color light emitting unit (or the third color light emitting unit) at the edge of the second display area 200 and the second color of the non-edge area of the second display area 200 The PDL gap between the light-emitting unit and the first-color light-emitting unit (or the third-color light-emitting unit);
  • the central connection lines of the two main body electrodes of the two-color light-emitting unit pairs are not parallel to the central connection lines of the two main body electrodes of each second-color light-emitting unit pair in the first display area.
  • the area of the main body electrode 2021 of the light emitting unit of the second color at the edge of the second display area 200 is set to be the same as the area of the main electrode 2021 of the light emitting unit of the second color of the first display area 100 , in order to ensure the second display area 200
  • the PDL gap between the second color light emitting unit and the first color light emitting unit (or the third color light emitting unit) at the edge and the second color light emitting unit and the first color light emitting unit (or the first color light emitting unit (or the first color light emitting unit) in the non-edge area of the second display area 200 is set to be the same as the area of the main electrode 2021 of the light emitting unit of the second color of the first display area 100 , in order to ensure the second display area 200
  • the shape of the body electrode of the second-color light-emitting unit is a pentagon including sharp corners, and the shape of the body electrode of the second-color light-emitting unit (or the third-color light-emitting unit)
  • the connection electrodes of the color light-emitting unit have spatial conflicts. Therefore, the shape of the main electrode of the second color light-emitting unit at the edge of the second display area no longer includes sharp corners.
  • the shape of the main electrode of the two-color light-emitting unit is compensated by adding two sixth sides 6 and a seventh side 7 connecting the two sixth sides 6, so as to ensure the main electrode of the second-color light-emitting unit at the edge of the second display area. Under the condition that there is no conflict in space, the area of the light emitting unit of the second color in the first display area is equal to that of the first display area.
  • the shape of the main electrode 2031 of each third-color light-emitting unit 203 in a row of light-emitting unit groups adjacent to the first display area 100 in the Y direction of the second display area 200 The shape and area of the body electrodes 2031 of the third-color light-emitting units 203 in the first display area 100 are substantially the same.
  • the shapes and areas of the main electrodes of the light-emitting units of each third color in the two-row light-emitting unit groups of the second display area and the first display area adjacent to each other in the Y direction are set to be approximately the same, that is,
  • the area of the main electrode of the light-emitting unit of the third color located at the edge of the second display area is designed to be different from the area of the main electrode of the light-emitting unit of the third color located in the non-edge area of the second display area.
  • the brightness of the light-emitting units of the third color is increased to achieve a uniform full-screen display effect, and at the same time, the main electrodes of the two rows of light-emitting units are prevented from colliding in space.
  • FIG. 11 is a schematic diagram of a second electrode of each light-emitting unit in a two-column light-emitting unit group of a second display area bordering the first display area provided according to an embodiment of the present disclosure. As shown in FIG.
  • the second-color light-emitting unit pair 202 is located in the first-color light-emitting unit 201 and the third-color light-emitting unit 201
  • the area and shape of the main electrode 2021 of each second-color light-emitting unit pair 202 in this column of light-emitting unit groups are the same as those of each second-color light-emitting unit pair located in the first display area 100 .
  • the area and shape of the body electrode 2021 of 202 are substantially the same.
  • the shapes and areas of the main electrodes of each second-color light-emitting unit pair in the two-column light-emitting unit groups of the second display area and the first display area adjacent to each other in the X direction are set to be substantially the same, That is, the area of the main electrode of the pair of light-emitting units of the second color located at the edge of the second display area is designed to be different from the area of the main electrode of the pair of light-emitting units of the second color located in the non-edge area of the second display area.
  • the brightness of most of the second-color light-emitting unit pairs is increased to achieve a uniform full-screen display effect, and at the same time, space conflicts between the main electrodes of the two columns of light-emitting units are prevented.
  • a third pixel circuit group is disposed between two adjacent second light-emitting unit groups arranged in the Y direction, so that the interval between the two adjacent second light-emitting unit groups arranged in the Y direction is not Set the lighting unit group.
  • an interval is provided between two adjacent first light-emitting unit groups in a column of the plurality of first light-emitting unit groups that are close to the second display area 200 in the X-direction.
  • One of the first pixel circuit groups, and along the X direction, the first pixel circuit group and the light-emitting unit group in the second light-emitting unit group in a row adjacent to the first display area 100 are located on the same straight line, so that the balance can be The luminance distribution of the first display area and the second display area in the X direction.
  • the area of the main electrode 2011 of each first-color light-emitting unit 201 is 1.5 ⁇ 2.5, for example, 1.9 ⁇ 2.1.
  • the area of the effective light-emitting area of each first-color light-emitting unit 201 is the same as the area of each light-emitting unit located in the first display area 100
  • the area ratio of the effective light-emitting region of a color light-emitting unit 201 is 2.
  • the electrodes located in the second display area The shape and area of the main electrode of the first color light-emitting unit at the edge of the area are approximately the same as the shape and area of the main electrode of the first color light-emitting unit located in the non-edge area of the second display area.
  • the brightness of the light-emitting units of the first color is increased to achieve a uniform full-screen display effect, and at the same time, the main electrodes of the two columns of light-emitting units are prevented from colliding in space.
  • the area of the main electrode 2031 of each third-color light-emitting unit 203 is 1.5-2.5, for example, 1.9-2.1.
  • the area of the effective light-emitting area of each third-color light-emitting unit 203 is the same as the area of each light-emitting unit located in the first display area 100
  • the area ratio of the effective light-emitting regions of the three-color light-emitting units 203 is 2.
  • the electrodes located in the second display area The shape and area of the main electrode of the third-color light-emitting unit at the edge of the area are approximately the same as the shape and area of the main electrode of the third-color light-emitting unit located in the non-edge area of the second display area.
  • the brightness of the light-emitting units of the third color is increased to achieve a uniform full-screen display effect, and at the same time, conflicts between the main electrodes of the two columns of light-emitting units are prevented in space.
  • Another embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
  • two pixel circuits in the second display area drive one light-emitting unit to emit light, which can increase the current and brightness of the light-emitting units in at least one of the second display area and the third display area , to achieve a more uniform full-screen visual display effect.
  • the area of the main electrode in the light-emitting unit of at least one of the second display area and the third display area is set to be larger than the area of the main electrode in the light-emitting unit of the first display area.
  • the area is designed so that the area of the effective light-emitting area of the light-emitting unit of one color located in at least one of the non-edge area of the second display area and the third display area is larger than that located in the first display area and emitting light with the above-mentioned one color
  • the area of the effective light-emitting area of the light-emitting unit with the same unit color can increase the brightness of at least one of the second display area and the third display area on the basis of ensuring the life of the light-emitting unit light-emitting material, and achieve a more uniform full-screen visual display effect.
  • the integrated circuit can meet the requirements in the first display area.
  • One display area and the second display area unified algorithm processing.

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Abstract

一种显示基板以及显示装置。该显示基板中，第一显示区（100）包括第一发光单元列（110-11）和第二发光单元列（110-12），各发光单元列与一列第一子像素电路（031）连接，第二显示区（200）包括第三发光单元列（120-11）和第四发光单元列（120-12），各发光单元列与一列第一子像素电路对（032-1）连接；第一子数据线（4210）与第一发光单元列（110-11）连接，第二子数据线（4220）与第二发光单元列（110-12）连接，第三子数据线（4230）与第三发光单元列（120-11）连接，第四子数据线（4240）与第四发光单元列（120-12）连接。与第四发光单元列（120-12）连接的第一子像素电路对（032-1）和与第二发光单元列（110-12）连接的第一子像素电路（031）均位于不同列，第二子数据线（4220）与第四子数据线（4240）通过数据线连接部（560）连接，可保证第一显示区（100）中数据信号与第二显示区（200）中数据信号的匹配。

Description

显示基板以及显示装置
本申请要求于2020年11月27日递交的中国专利申请第202011362429.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一个实施例涉及一种显示基板以及显示装置。
背景技术
随着人们对显示产品视觉效果的不断追求，窄边框甚至全屏显示成为当前有机发光二极管(OLED)显示产品发展的新趋势。随着许多手机的屏占比逐步稳定提高，全面屏已经成为了当下的潮流趋势。前置摄像头是设计全面屏的关键，为了达到更高的屏占比，陆续出现了具有刘海屏、水滴屏、挖孔屏等屏幕的显示产品，这几种全面屏形态通过牺牲手机外观而提高了屏占比。由此，屏下摄像头的设计既能保证手机外观，又可以提高屏占比。屏下摄像头指前置摄像头位于屏幕下方但并不影响屏幕显示功能，不使用前置摄像头的时候，相机上方的屏幕仍可以正常显示图像。从外观上看，屏下摄像头不会有任何相机孔，真正的达到了全面屏显示效果。
发明内容
本公开的至少一实施例提供一种显示基板以及显示装置。
本公开的至少一实施例提供一种显示基板，包括：衬底基板，包括第一显示区和第二显示区，所述第一显示区包括多个第一发光单元和多个第一子像素电路，所述多个第一发光单元包括相邻设置的第一发光单元列和第二发光单元列，各发光单元列与相应的一列第一子像素电路连接，所述第二显示区包括多个第二发光单元和多个第二子像素电路，所述多个第二发光单元包括相邻设置的第三发光单元列和第四发光单元列，所述第二显示区中的各发光单元列与一列第一子像素电路对连接，各列第一子像素电路对包括相邻两列第二子像素电路；沿第二方向延伸的多条第一子数据线、多条第二子数据线、多条第三子数 据线以及多条第四子数据线，各第一子数据线与各第一发光单元列连接，各第二子数据线与各第二发光单元列连接，各第三子数据线与各第三发光单元列连接，各第四子数据线与各第四发光单元列连接，所述第二方向与所述第一方向相交。所述第一发光单元列和所述第二发光单元列的排列方向与所述第三发光单元列和所述第四发光单元列的排列方向相同，与所述第一发光单元列连接的一列第一子像素电路和与所述第三发光单元列连接的一列第二子像素电路位于同一列，所述第一子数据线和所述第三子数据线为沿所述第二方向延伸且连续的一条数据线；与所述第四发光单元列连接的两列所述第二子像素电路和与所述第二发光单元列连接的一列第一子像素电路均位于不同列，所述第二子数据线与所述第四子数据线通过数据线连接部连接，且所述数据线连接部的延伸方向与所述第二方向相交。
例如，在本公开的实施例中，与所述第二发光单元列连接的一列第一子像素电路和与所述第三发光单元列连接的另一列第二子像素电路位于同一列。
例如，在本公开的实施例中，所述第一显示区还包括相邻设置第五发光单元列和第六发光单元列，所述第一发光单元列、所述第二发光单元列、第五发光单元列和第六发光单元列沿所述第一方向重复排列，所述第三发光单元列和所述第四发光单元列沿所述第一方向交替排列，所述显示基板还包括沿所述第二方向延伸的多条第五子数据线和多条第六子数据线，各第五子数据线与各第五发光单元列连接，各第六子数据线与各第六发光单元列连接，与所述第五发光单元列连接的一列第一子像素电路和与所述第四发光单元列连接的一列第二子像素电路位于同一列，与所述第六发光单元列连接的一列第一子像素电路和与所述第四发光单元列连接的另一列第二子像素电路位于同一列，所述第六子数据线或所述第五子数据线与所述第四子数据线之间设置有间隔。
例如，在本公开的实施例中，所述第一显示区包括沿所述第一方向和所述第二方向交替排列的多个第一子发光单元组和多个第二子发光单元组，所述第一子发光单元组包括所述第一发光单元列和所述第二发光单元列中的发光单元，所述第二子发光单元组包括所述第五发光单元列和所述第六发光单元列中的发光单元，所述第二显示区包括多个第三子发光单元组，各所述子发光单元组包括一个第一颜色发光单元、一个第二颜色发光单元对以及一个第三颜色发光单元，所述第一颜色发光单元和所述第三颜色发光单元沿所述第二方向排列，所述第二颜色发光单元对包括沿所述第二方向排列的两个第二颜色发光单 元，所述第一颜色发光单元和所述第二颜色发光单元对沿所述第一方向排列，且所述第一子发光单元组中所述第一颜色发光单元和所述第三颜色发光单元的排列方向与所述第二子发光单元组中所述第一颜色发光单元和所述第三颜色发光单元的排列方向相反，所述第一子发光单元组中各发光单元的相对位置分布与所述第三子发光单元组中各发光单元的相对位置分布相同。
例如，在本公开的实施例中，所述衬底基板还包括第三显示区，所述第二显示区还包括多个第三子像素电路，所述第三显示区包括多个第三发光单元，所述多个第三发光单元包括相邻设置的第七发光单元列和第八发光单元列，所述第一发光单元列和所述第二发光单元列的排列方向与所述第七发光单元列和所述第八发光单元列的排列方向相同，所述第三显示区中的各发光单元列与一列第二子像素电路对连接，各列第二子像素电路对包括相邻两列第三子像素电路；所述显示基板还包括沿所述第二方向延伸的多条第七子数据线和多条第八子数据线，各第七子数据线与各第七发光单元列连接，各第八子数据线与各第八发光单元列连接，所述第七子数据线和所述第八子数据线的至少之一设置在所述第三子数据线和所述第四子数据线之间。
例如，在本公开的实施例中，所述第七子数据线和所述第八子数据线均设置在所述第三子数据线和所述第四子数据线之间，且所述第八子数据线与所述第五子数据线之间设置有间隔以设置所述子数据线连接部。
例如，在本公开的实施例中，所述多个第三子像素电路别配置为分别与多个第四子发光单元组连接，各所述第四子发光单元组中各发光单元的相对位置分布与所述第三子发光单元组中各发光单元的相对位置分布相同，与所述第三子发光单元组连接的所述第一子像素电路对和与所述第四发光单元组连接的所述第二子像素电路对沿所述第一方向和所述第二方向交替排列。
例如，在本公开的实施例中，所述第三显示区包括中心区以及围绕所述中心区的边缘区，所述边缘区包括沿所述第一方向和所述第二方向排列的多个虚设像素电路以形成多个虚设像素电路列和多个虚设像素电路行。
例如，在本公开的实施例中，所述第三显示区内的所述多个虚设像素电路列包括相邻四列组成的虚设像素电路列组，每个虚设像素电路列组包括沿所述第一方向依次排列的第一虚设像素电路列、第二虚设像素电路列、第三虚设像素电路列和第四虚设像素电路列，所述显示基板还包括第一虚设数据线、第二虚设数据线、第三虚设数据线和第四虚设数据线，所述第一虚设数据线与所述 第一虚设像素电路列连接，所述第二虚设数据线与所述第二虚设像素电路列连接，所述第三虚设数据线与所述第三虚设像素电路列连接，且所述第四虚设数据线与所述第四虚设像素电路列连接，与所述第一发光单元列连接的一列第一子像素电路和所述第一虚设像素电路列位于同一列，与所述第二发光单元列连接的一列第一子像素电路和所述第二虚设像素电路列位于同一列，与所述第五发光单元列连接的一列第一子像素电路与所述第三虚设像素电路列位于同一列，与所述第六发光单元列连接的一列第一子像素电路与所述第四虚设像素电路列位于同一列，与所述第一发光单元组连接的两条子数据线与相应的两条虚设数据线为连续的两条子数据线，或者与所述第二发光单元组连接的两条子数据线与相应的两条虚设数据线为连续的两条数据线。
例如，在本公开的实施例中，所述显示基板还包括位于所述第三显示区远离所述第一显示区一侧的周边区，与所述第一发光单元组或所述第二发光单元组连接的所述两条虚设数据线绕过所述中心区以在所述周边区分别连接所述第七子数据线和所述第八子数据线。
例如，在本公开的实施例中，所述第一虚设数据线和所述第一子数据线为一条连续的数据线，所述第二虚设数据线和所述第二子数据线为一条连续的子数据线，所述第三虚设数据线和所述第五子数据线之间设置有间隔，所述第四虚设数据线和所述第六子数据线之间设置有间隔。
例如，在本公开的实施例中，所述第一虚设数据线绕过所述中心区以在所述周边区连接所述第七子数据线，所述第二虚设数据线绕过所述中心区以在所述周边区连接所述第八子数据线。
本公开另一实施例提供一种显示装置，包括上述显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为根据本公开实施例提供的一种显示基板的局部平面结构示意图；
图2为图1所示的第二像素电路组和第三像素电路组至少之一的像素电路等效图；
图3A为根据本公开实施例提供的第二显示区内的像素电路的有源半导体 层的局部平面结构示意图；
图3B为根据本公开实施例提供的第二显示区内的有源半导体层和第一导电层叠示意图；
图3C为根据本公开实施例提供的第二显示区内的第二导电层的局部平面结构示意图；
图3D为根据本公开实施例提供的第二显示区内的有源半导体层、第一导电层以及第二导电层的叠示意图；
图3E为根据本公开实施例提供的第二显示区的源漏金属层的局部平面结构示意图；
图3F为根据本公开实施例提供的第二显示区内的有源半导体层、第一导电层、第二导电层以及源漏金属层的叠示意图；
图4A为根据本公开实施例提供的第二显示区的第二发光单元组与第二像素电路组的连接关系示意图；
图4B为图4A中一个发光单元的示意性层结构图；
图4C为图4A所示第二显示区的第二发光单元组和过孔位置关系示意图；
图5A为根据本公开实施例提供的第一显示区和第二显示区交界处的部分像素电路结构示意图；
图5B为图5A所示位置的数据线连接部所在膜层结构示意图；
图5C为图5A所示位置的数据线所在膜层结构示意图；
图5D为图1所示的显示基板中的第一显示区和第二显示区的部分平面图；
图5E为根据本公开实施例的另一示例提供的显示基板中的第一显示区和第二显示区的部分平面图；
图6为根据本公开实施例提供的第一显示区和第三显示区的边缘区交界处的部分像素电路结构示意图；
图7为根据本公开实施例提供的位于第一显示区的发光单元组的第二电极的示意图；
图8为根据本公开实施例提供的位于第二显示区非边缘的发光单元组的第二电极的示意图；
图9为根据本公开实施例提供的位于第三显示区的发光单元组的第二电极的示意图；
图10为根据本公开实施例提供的第二显示区的与第一显示区交界的两行 发光单元组中的各发光单元的第二电极的示意图；以及
图11为根据本公开实施例提供的第二显示区的与第一显示区交界的两列发光单元组中的各发光单元的第二电极的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
在研究中，本申请的发明人发现：目前，采用屏下摄像头设计的有机发光二极管显示装置中，低密度显示区(L区)的显示亮度和电流比高密度显示区(H区)低至少一倍，会影响显示效果。
本公开的实施例提供一种显示基板以及显示装置。显示基板包括衬底基板，包括第一显示区和第二显示区，第一显示区包括多个第一发光单元和多个第一子像素电路，多个第一发光单元包括相邻设置的第一发光单元列和第二发光单元列，各发光单元列与相应的一列第一子像素电路连接，第二显示区包括多个第二发光单元和多个第二子像素电路，多个第二发光单元包括相邻设置的第三发光单元列和第四发光单元列，第二显示区中的各发光单元列与一列第一子像素电路对连接，各列第一子像素电路对包括相邻两列第二子像素电路；沿第二方向延伸的多条第一子数据线、多条第二子数据线、多条第三子数据线以及多条第四子数据线，各第一子数据线与各第一发光单元列连接，各第二子数据线与各第二发光单元列连接，各第三子数据线与各第三发光单元列连接，各第四子数据线与各第四发光单元列连接，第二方向与第一方向相交。第一发光单元列和第二发光单元列的排列方向与第三发光单元列和第四发光单元列的 排列方向相同，与第一发光单元列连接的一列第一子像素电路和与第三发光单元列连接的一列第二子像素电路位于同一列，第一子数据线和第三子数据线为沿第二方向延伸且连续的一条数据线；与第四发光单元列连接的两列第二子像素电路和与第二发光单元列连接的一列第一子像素电路均位于不同列，第二子数据线与第四子数据线通过数据线连接部连接，且数据线连接部的延伸方向与第二方向相交。本公开实施例提供的显示基板中，在第一显示区的像素电路和第二显示区的像素电路交界的位置，第二子数据线与第四子数据线不连接，并通过数据线连接部连接第二子数据线与第四子数据线，从而可以保证从数据线传输至第一显示区中发光单元的数据信号与从数据线传输至第二显示区中发光单元的数据信号的匹配。
下面结合附图对本公开实施例提供的显示基板以及显示装置进行描述。
图1为根据本公开实施例提供的一种显示基板的局部平面结构示意图。如图1所示，显示基板包括衬底基板10。显示基板包括第一显示区100和第二显示区200。例如，显示基板还包括第三显示区300。例如，第二显示区200位于第三显示区300的周围，例如位于第三显示区300的沿X方向的两侧，第一显示区100位于第二显示区200和第三显示区300的周围。例如，第二显示区200和第三显示区300位于显示区的边缘，即显示基板包括显示区以及围绕显示区的周边区，第二显示区200和第三显示区300远离第一显示区100的边缘与周边区相接。也就是，第一显示区100仅位于第三显示区300沿Y方向的一侧。例如，第三显示区300的形状可以为矩形，该矩形沿Y方向延伸的两个边缘分别与位于其两侧的第二显示区200相接，该矩形沿X方向延伸的一个边缘与周边区相接，另一个边缘与第一显示区100相接。例如，第二显示区200位于沿X方向排列的第一显示区100和第三显示区300之间，且第二显示区200的沿X方向延伸的两个边缘之一与周边区相接，另一个边缘与第一显示区100相接。
如图1所示，第一显示区100包括多个第一发光单元组110和与多个第一发光单元组110分别连接的多个第一像素电路组120。例如，一个第一发光单元组110可以与一个第一像素电路组120连接以驱动第一发光单元组110发光，第一发光单元组110以及驱动第一发光单元组110发光的第一像素电路组120均位于第一显示区100。
如图1所示，第二显示区200包括多个第二发光单元组210和多个第二像 素电路组220，多个第二发光单元组210分别与多个第二像素电路组220连接。例如，第二显示区200还包括多个第三像素电路组230。例如，一个第二发光单元组210可以与一个第二像素电路组220连接以驱动第二发光单元组210发光，第二发光单元组210以及驱动第二发光单元组210发光的第二像素电路组220均位于第二显示区200。例如，第三显示区300包括多个第三发光单元组310，多个第三发光单元组310分别与多个第三像素电路组230连接，也就是，位于第三显示区300的第三发光单元组310和位于第二显示区200的第三像素电路组230连接，第三发光单元组310与驱动第三发光单元组310发光的第三像素电路组230位于不同的显示区。例如，如图1所示，第三显示区300的中心区301仅设置透明的第三发光单元组310，而没有设置非透明的像素电路组，该中心区301可以作为屏下摄像区，既可以具有较高的光透过率以实现摄像功能，又可以通过与其他区域的像素电路组连接而实现发光，不影响屏幕的显示功能。
如图1所示，多个第二发光单元组210的密度小于多个第一发光单元组110的密度。例如，多个第三发光单元组310的密度小于多个第一发光单元组110的密度。屏下摄像区(第三显示区的中心区)的发光单元组的密度(即像素密度)低于正常显示区(第一显示区)的发光单元组的密度，则摄像头可以设置在能够允许更多光透过的低像素密度区域的下方。上述“多个第二发光单元组210的密度和多个第三发光单元组310的密度均小于多个第一发光单元组110的密度”指相同面积下第二发光单元组的数量小于第一发光单元组的数量。
例如，第一显示区100为主要的显示区域，具有较高的分辨率(PPI，Pixel Per Inch)，即第一显示区100内排布有密度较高的用于显示的子像素。每个子像素包括发光单元以及驱动发光单元的像素电路。第三显示区300可以允许从显示基板显示侧射入的光透过显示基板而到达显示基板的背侧，从而使位于显示基板背侧的传感器等部件的正常工作。本公开实施例不限于此，例如，第三显示区300也可以允许从显示基板的背侧发出的光通过显示基板而到达显示基板的显示侧。第三显示区300和第二显示区200也包括多个子像素，以用于显示。但是，由于子像素的像素电路通常不透光，为了提高第三显示区300的中心区301的透光性，可以将第三显示区300的子像素的发光单元与驱动该发光单元的像素电路从物理位置上分离。例如，与第三显示区300中的发光单元组(例如图1中第三显示区300内的方框所示)连接的像素电路可以设置在第二 显示区200，因此占据了第二显示区200的部分空间；而第二显示区200的剩余空间用于设置第二显示区200的像素(包括第二像素电路组220和第二发光单元组210)，例如第二显示区200中的每一个点填充方框代表一个像素。此时，第二显示区200中的像素以及与第三显示区300中的第三发光单元组310连接的第三像素电路组230在第二显示区200中阵列排布。由此，第三显示区300和第二显示区200的分辨率低于第一显示区100的分辨率，即第三显示区300和第二显示区200内排布的用于显示的像素的密度小于第一显示区100的像素密度。
图2为图1所示的第二像素电路组和第三像素电路组中的像素电路对的等效图。如图2所示，各像素电路组包括多个像素电路600。第二像素电路组220包括多个第一像素电路单元610，第一像素电路单元610至少包括第一像素电路611和第二像素电路612。例如，第一像素电路单元610可以包括两个像素电路，则第一像素电路单元610可以称为像素电路对610。本公开实施例示意性的示出第一像素电路单元包括两个像素电路，但不限于此，还可以包括三个像素电路或更多个像素电路。例如，各发光单元组包括多个发光单元，第一像素电路组210包括多个像素电路，各像素电路被配置为与一个发光单元连接以驱动该发光单元发光；第二像素电路组220包括多个像素电路对610，第二像素电路组220的各像素电路对610被配置为与一个发光单元连接以驱动该发光单元发光。
例如，第三像素电路组230多个第二像素电路单元，各第二像素电路单元至少包括第三像素电路和第四像素电路，且第二像素电路单元中的至少两个像素电路被配置为与同一个发光单元连接以驱动该发光单元发光。例如，第二像素电路单元可以包括两个像素电路，则第二像素电路单元也可以称为像素电路对610。本公开实施例示意性的示出第二像素电路单元包括两个像素电路，但不限于此，还可以包括三个像素电路或更多个像素电路。
例如，显示基板还包括位于衬底基板上的复位电源信号线、数据线、扫描信号线、电源信号线、复位控制信号线以及发光控制信号线。如图2所示，各像素电路600包括数据写入晶体管T4、驱动晶体管T3、阈值补偿晶体管T2以及第一复位控制晶体管T7，阈值补偿晶体管T2的第一极与驱动晶体管T3的第一极连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的栅极连接，第一复位控制晶体管T7的第一极与复位电源信号线连接以接收复位信号Vinit， 第一复位控制晶体管T7的第二极与发光单元连接，数据写入晶体管T4的第一极与驱动晶体管T3的第二极连接。例如，如图2所示，各子像素的像素电路还包括存储电容C、第一发光控制晶体管T6、第二发光控制晶体管T5和第二复位晶体管T1。数据写入晶体管T4的栅极与扫描信号线电连接以接收扫描信号Gate；存储电容C的第一极与电源信号线电连接，存储电容C的第二极与驱动晶体管T3的栅极电连接；阈值补偿晶体管T2的栅极与扫描信号线电连接以接收补偿控制信号；第一复位晶体管T7的栅极与复位控制信号线电连接以接收复位控制信号Reset；第二复位晶体管T1的第一极与复位电源信号线电连接以接收复位信号Vinit，第二复位晶体管T1的第二极与驱动晶体管T3的栅极电连接，第二复位晶体管T1的栅极与复位控制信号线电连接以接收复位控制信号Reset；第一发光控制晶体管T6的栅极与发光控制信号线电连接以接收发光控制信号EM；第二发光控制晶体管T5的第一极与电源信号线电连接，第二发光控制晶体管T5的第二极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T5的栅极与发光控制信号线电连接以接收发光控制信号EM。上述电源信号线指输出电压信号VDD的信号线，可以与电压源连接以输出恒定的电压信号，例如正电压信号。
例如，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T3的栅极和阈值补偿晶体管T2的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，数据写入晶体管T3的栅极和阈值补偿晶体管T2的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T3的栅极电连接到第一扫描信号线，阈值补偿晶体管T2的栅极电连接到第二扫描信号线，而第一扫描信号线和第二扫描信号线传输的信号可以相同，也可以不同，从而使得数据写入晶体管T3的栅极和阈值补偿晶体管T2可以被分开单独控制，增加控制像素电路的灵活性。
例如，第一发光控制晶体管T6和第二发光控制晶体管T5被输入的发光控制信号可以相同，即，第一发光控制晶体管T6的栅极和第二发光控制晶体管T5的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，第一发光控制晶体管T6的栅极和第二发光控制晶体管T5的栅极也可以分别电连接至不同的发光控制信号线，而不同的发光控制信号线传输的信号可以相同，也可以不同。
例如，第一复位晶体管T7和第二复位晶体管T1被输入的复位控制信号可 以相同，即，第一复位晶体管T7的栅极和第二复位晶体管T1的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，第一复位晶体管T7的栅极和第二复位晶体管T1的栅极也可以分别电连接至不同的复位控制信号线，此时，不同复位控制信号线上的信号可以相同也可以不相同。
例如，如图2所示，显示基板工作时，画面显示的第一阶段，第二复位晶体管T1打开，使N1节点的电压初始化；第二阶段，同一个数据信号Data通过两个相连的数据写入晶体管T4，以及与两个相连的数据写入晶体管T4分别连接的两个驱动晶体管T3以及两个阈值补偿晶体管T2存储在两个像素电路600的两个N1节点；在第三发光阶段，两个像素电路600(即第一像素电路611和第二像素电路612组成的像素电路对610)中的第二发光控制晶体管T5、驱动晶体管T3以及第一发光控制晶体管T6均打开，以将同样的数据信号传输到两个N4节点，此时，两个像素电路600的N4节点相连，共同驱动同一个发光单元20发光，可以达到增加电流和亮度的目的。
需要说明的是，在本公开实施例中，子像素的像素电路除了可以为图2所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。只要将两个像素电路的数据写入晶体管T4相连，并将两个像素电路的N4节点相连以实现共同驱动同一个发光单元发光即可。
图3A为根据本公开实施例提供的第二显示区内的像素电路的有源半导体层的局部平面结构示意图。如图3A所示，有源半导体层3100可采用半导体材料图案化形成。有源半导体层3100可用于制作上述的第二复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6和第一复位控制晶体管T7的有源层。有源半导体层3100包括各子像素的各晶体管的有源层图案(沟道区)和掺杂区图案(源漏掺杂区)，且同一像素电路中的各晶体管的有源层图案和掺杂区图案一体设置。
需要说明的是，有源层可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个子像素的各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素电路中的各晶体管包括掺杂区图案(即源极区域和漏极区域)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
例如，有源半导体层3100可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
图3B为根据本公开实施例提供的第二显示区内的有源半导体层和第一导电层叠示意图。显示基板包括位于有源半导体层远离衬底基板一侧的栅极绝缘层，用于将上述的有源半导体层3100与后续形成的第一导电层3200(即栅极金属层)绝缘。图3B示出了该显示基板包括的第一导电层3200，第一导电层3200设置在栅极绝缘层上，从而与有源半导体层3100绝缘。第一导电层320可以包括电容C的第二极CC2、沿第一方向(图中的X方向)延伸的多条扫描信号线430、多条复位控制信号线440、多条发光控制信号线450以及第二复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6和第一复位控制晶体管T7的栅极。
例如，如图3B所示，数据写入晶体管T3的栅极可以为扫描信号线430与有源半导体层3100交叠的部分；第一发光控制晶体管T6的栅极可以为发光控制信号线450与有源半导体层3100交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制信号线450与有源半导体层3100交叠的第二部分。第二复位晶体管T1的栅极为复位控制信号线440与有源半导体层3100交叠的第一部分，第一复位控制晶体管T7的栅极为复位控制信号线440与有源半导体层3100交叠的第二部分。阈值补偿晶体管T2可为双栅结构的薄膜晶体管，阈值补偿晶体管T2的第一个栅极可为扫描信号线430与有源半导体层3100交叠的部分，阈值补偿晶体管T2的第二个栅极可为从扫描信号线430突出的突出结构P与有源半导体层3100交叠的部分。如图3B所示，驱动晶体管T1的栅极可为电容C的第二极CC2。
需要说明的是，图3B中的各虚线矩形框示出了第一导电层3200与有源半导体层3100交叠的各个部分。作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体层通过离子掺杂等工艺导体化作为各个晶体管的第一极和第二极。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
例如，如图3B所示，扫描信号线430、复位控制信号线440和发光控制信号线450沿第二方向(Y方向)排布。扫描信号线430位于复位控制信号线440和发光控制信号线450之间。本公开实施例中的第一方向和第二方向为彼此相交的方向，例如第一方向与第二方向垂直。本公开实施例中的第一方向和第二方向可以互换。
例如，在第二方向上，电容C的第二极CC2(即驱动晶体管T1的栅极)位于扫描信号线430和发光控制信号线450之间。从扫描信号线430突出的突出结构P位于扫描信号线430的远离发光控制信号线450的一侧。
例如，在上述的第一导电层3200上形成有第一绝缘层，用于将上述的第一导电层3200与后续形成的第二导电层3300绝缘。
图3C为根据本公开实施例提供的第二显示区内的第二导电层的局部平面结构示意图，图3D为根据本公开实施例提供的第二显示区内的有源半导体层、第一导电层以及第二导电层的叠示意图。如图3C至图3D所示，第二导电层330包括电容C的第一极CC1以及沿第一方向延伸多条复位电源信号线410。电容C的第一极CC1与电容C的第二极CC2至少部分重叠以形成电容C。
如图3C至图3D所示，本公开实施例提供的显示基板还包括多个第一连接部510，至少部分第一连接部510的第一端与第一像素电路单元中的第一像素电路611的数据写入晶体管T4的第二极连接，第一连接部510的第二端与第一像素电路单元中的第二像素电路612的数据写入晶体管T4的第二极连接以使第一像素电路单元的至少两个数据写入晶体管T4与同一条数据线连接，且沿第二方向，第一连接部510位于第一像素电路611中的数据写入晶体管T2的第二极与第一复位控制晶体管T7的第一极之间。
本公开实施例中，第二显示区内的至少两个像素电路的数据写入晶体管的第二极通过第一连接部连接以驱动一个发光单元发光，可以增加第二显示区的发光单元的电流和亮度，例如可使第二显示区的发光单元的电流和亮度增加到采用一个像素电路驱动情况下的1.8到2倍，解决了第二显示区中电流和亮度偏小的问题，实现更加均匀的全面屏的视觉显示效果。
例如，部分第一连接部510的第一端与第二像素电路单元中的第三像素电路的数据写入晶体管T4的第二极连接，第一连接部510的第二端与第二像素电路单元中的第四像素电路的数据写入晶体管T4的第二极连接以使第二像素电路单元的至少两个数据写入晶体管T4与同一条数据线连接，且沿第二方向， 第一连接部510位于第三像素电路中的数据写入晶体管T2的第二极与第一复位控制晶体管T7的第一极之间。为了方便后续描述，本公开说明书中的第一像素电路单元和第二像素电路单元同一称为像素电路对，则各像素电路单元包括的两个像素电路均称为第一像素电路和第二像素电路，即第二像素电路单元中的第三像素电路可以称为第一像素电路，第二像素电路单元中的第四像素电路可以称为第二像素电路。
例如，沿第二方向，第一连接部510位于第一像素电路611中的阈值补偿晶体管T3的第二极与第一复位控制晶体管T7的第一极之间。
例如，第一连接部510与复位电源信号线410同层设置。
例如，在上述的第二导电层3300上形成有第二绝缘层，用于将上述的第二导电层3300与后续形成的源漏极金属层3400绝缘。
例如，图3E为根据本公开实施例提供的第二显示区的源漏金属层的局部平面结构示意图，图3F为根据本公开实施例提供的第二显示区内的有源半导体层、第一导电层、第二导电层以及源漏金属层的叠示意图。如图3E至图3F所示，源漏金属层3400包括沿第二方向延伸的数据线420以及电源信号线460。数据线420通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层的过孔与数据写入晶体管T2的第二极电连接。电源信号线460通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层的过孔与第二发光控制晶体管T5的第一极电连接。电源信号线460和数据线420沿第一方向交替设置。电源信号线460通过贯穿第二绝缘层的过孔与电容C的第一极CC1电连接。
例如，在上述的源漏极金属层3400远离衬底基板的一侧可以设置钝化层以及平坦层用于保护上述的源漏极金属层3400。
例如，图3D至图3F示意性的示出第二像素电路组220中的部分像素电路以及第三像素电路组230中的部分像素电路。本公开实施例示意性的示出第二像素电路组220和第三像素电路组230均包括像素电路对，像素电路对包括沿第一方向排列的第一像素电路611和第二像素电路612，且各像素电路对中的两个像素电路的数据写入晶体管T4的第二极均通过第一连接部510连接以驱动同一个发光单元发光。本公开实施例不限于此，例如，还可以仅第二像素电路组包括上述像素电路对，或者仅第三像素电路组包括上述像素电路对。
例如，如图3D至图3F所示，第二像素电路组220和第三像素电路组230可以包括排列为两行的八个像素电路，即二维阵列排布的四个像素电路对。而 第一像素电路组不包括上述像素电路对(未示出)，仅包括二维阵列排布的四个像素电路，第一像素电路组中沿第一方向排列的相邻的两个像素电路各驱动一个发光单元发光，且该相邻的两个像素电路中的两个数据写入晶体管彼此独立，且分别连接不同的数据线。本公开实施例中的第一像素电路组与第二像素电路组的版图区别主要在于是否设置了第一连接部，以及与第一连接部连接的数据写入晶体管的第二极的位置的设置。
例如，如图3D至图3F所示，在本公开实施例提供的显示基板可以采用四分之一全高屏分辨率(Quarter High Definition,QHD)，但是由于以该分辨率设计的各个像素电路的阈值补偿晶体管的第二极与第一复位控制晶体管的第一极之间沿第二方向的距离很小，例如小于2微米，例如为1.4～1.8微米，由此，阈值补偿晶体管的第二极与第一复位控制晶体管的第一极之间很难设置连接像素电路对的两个数据写入晶体管的第二极(data输入节点)的第一连接部。由于QHD分辨率产品中像素的大小一般小于全屏分辨率(Full High Definition,FHD)产品中像素的大小，本公开实施例中，将具有QHD分辨率的像素电路设计到具有FHD分辨率的像素间距(pixel pitch)里，从而增加各像素电路中阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第一极之间在沿第二方向上的距离，以保证像素电路对的两个像素电路的data输入节点通过第一连接部实现打孔连接。
例如，如图3D至图3F所示，相对于一种显示基板，其第二显示区中包括多个发光单元以及与多个发光单元一一对应连接的多个像素电路，相邻像素电路之间设置不与任何发光单元连接的虚设像素电路的情况，本公开实施例中，采用第一连接部连接虚设像素电路与连接第二显示区中的发光单元的像素电路，可以在尽量少改变像素电路整体结构的基础上，有效利用虚设像素电路，从而可以增加第二显示区(和第三显示区至少之一)的发光单元的电流和亮度，实现更加均匀的全面屏的视觉显示效果。
例如，阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第一极之间在沿第二方向上的距离为7～12微米以在阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第一极之间设置第一连接部510。
例如，如图3A至图3F所示，各像素电路还包括：与数据线420同层设置的第二连接部520和第三连接部530，第二连接部520被配置为连接阈值补偿晶体管T2的第二极和驱动晶体管T3的栅极，第三连接部530被配置为连接第 一复位控制晶体管T7的第一极和复位电源信号线410。例如，第二连接部520的一端通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层中的过孔与阈值补偿晶体管T2的第二极电连接，第二连接部520的另一端通过贯穿第一绝缘层和第二绝缘层中的过孔与驱动晶体管T3的栅极(即电容C的第二极CC2)电连接。第三连接部530的一端通过贯穿第二绝缘层中的过孔与复位电源信号线410电连接，第三连接部530的另一端通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层中的过孔与第一复位控制晶体管T7的第一极电连接。
例如，如图3A至图3F所示，第一像素电路611中，第二连接部520与第三连接部530的彼此靠近的边缘之间的在第二方向的距离为7～12微米以在第二连接部520与第三连接部530之间设置第一连接部510。例如，第一像素电路611中，第二连接部520与第三连接部530的彼此靠近的边缘之间的在第二方向的距离可以为8～11微米。
例如，如图3A至图3F所示，第一连接部510与数据线420位于不同层，且沿垂直于衬底基板的第三方向，各第一连接部510与数据线420和电源信号线460有交叠。例如，像素电路对610包括的两个数据写入晶体管T4之间设置有一条数据线410和一条电源信号线460，连接上述两个数据写入晶体管T4的第一连接部510与数据线410和电源信号线460均有交叠。
例如，如图3A至图3F所示，各像素电路还包括与数据线420同层设置的第四连接部540，第四连接部540被配置为连接第一连接部510和数据写入晶体管T4的第二极，像素电路对610之一(例如第二像素电路612)的第四连接部540与紧邻的数据线420之间具有间隔，像素电路对610的另一个(例如第一像素电路611)的第四连接部540与数据线420为一体结构以实现像素电路对610仅与一条数据线420连接。上述“第四连接部540与紧邻的数据线420之间具有间隔”中“紧邻的数据线”指第四连接部540和该数据线420之间没有其他数据线。
例如，如图1、图3A至图3F所示，多个第一像素电路组210沿第一方向和第二方向呈阵列排布。沿第一方向，多个第二像素电路组220和多个第三像素电路组230交替设置，沿第二方向，多个第二像素电路组220和多个第三像素电路组230交替设置，且第二像素电路组220和第三像素电路组230与不同的数据线420连接。
例如，沿第一方向延伸的直线经过像素电路对中的两个数据写入晶体管的 第二极，第一连接部的整体沿第一方向延伸。例如，不同像素电路组连接不同的数据线，因此不同像素电路组中的第一连接部沿第一方向的长度可以不同。例如，同一像素电路组中，不同像素电路对中的第一连接部沿第一方向的长度也可以不同。
例如，如图3E所示，以与数据线420为一体的第四连接部540为第一子部541，与紧邻数据线420具有间隔的第四连接部540为第二子部542，以第二像素电路组包括八个阵列排布的像素电路(沿行方向排列四个像素电路，沿列方向排列的两个像素电路)为例，则第二像素电路组中，两个第一子部541沿第二方向排列(例如位于一列)，两个第二子部542沿第二方向排列(例如位于一列)，且第一子部541与第二子部542在第一方向(例如在行方向)上交替排列。同理，第三像素电路组中的第一子部和第二子部的排列方式与第二像素电路组中的第一子部和第二子部的排列方式相同。对于沿第二方向交替排列的第二像素电路组和第三像素电路组，第二像素电路组中的第一子部和第三像素电路组中的第二子部位于不同列以使第二像素电路组与第三像素电路组连接至不同的数据线。
由于第一像素电路组中没有像素电路对的设计，所以第一像素电路组中沿第一方向或第二方向排列的相邻两个像素电路中的第四连接部均与数据线为一体结构以实现各像素电路与相应数据线的电连接。
例如，如图3A至图3F所示，显示基板还包括与第一连接部510同层设置的多个覆盖部S，各阈值补偿晶体管T2包括两个栅极T2-g1和T2-g2以及位于两个栅极之间的有源半导体层3100。沿第三方向，覆盖部S与两个栅极之间的有源半导体层3100、数据线420以及电源信号线460均有交叠。
例如，双栅型阈值补偿晶体管T2的两段沟道之间的有源半导体层在阈值补偿晶体管T2关闭时处于浮置(floating)状态，易受周围线路电压的影响而跳变，从而会影响阈值补偿晶体管T2的漏电流，进而影响发光亮度。为了保持阈值补偿晶体管T2的两段沟道之间的有源半导体层电压稳定，设计覆盖部S与阈值补偿晶体管T2的两段沟道之间的有源半导体层形成电容，覆盖部S可以连接至电源信号线460以获得恒定电压，因此处于浮置状态的有源半导体层的电压可以保持稳定。覆盖部S与双栅型阈值补偿晶体管T2的两段沟道之间的有源半导体层交叠，还可以防止两个栅极之间的有源半导体层被光照而改变特性，例如防止该部分有源半导体层的电压发生变化，以防止产生串扰。例 如，电源信号线460可以通过贯穿第二绝缘层的过孔与覆盖部S电连接以为覆盖部S提供恒定电压。
例如，与有源半导体层交叠的覆盖部S在沿第一方向延伸的第一直线上的正投影与第一连接部510在第一直线上的正投影有交叠，第四连接部540在沿第二方向延伸的第二直线上的正投影与覆盖部S在第二直线上的正投影有交叠，由此，为了与同层设置的覆盖部S保持距离，第一连接部510的整体设置为非直线型，例如折线形。
例如，如图3A至图3F所示，第一连接部510包括沿第一方向延伸的主体连接部511和位于主体连接部511两端的且沿第二方向延伸的两个端部512，两个端部512分别与像素电路对610的两个第四连接部540连接，两个端部512在第二直线上的正投影与覆盖部S在第二直线上的正投影有交叠。由此，主体连接部和两个端部形成了折线形以与覆盖部保持距离。
例如，在第二方向上，覆盖部S与阈值补偿晶体管T2的第二极之间的距离小于覆盖部S与第一复位控制晶体管T7的第一极之间的距离，即覆盖部S更靠近阈值补偿晶体管T2。由此，为了方便设计，且使得第一连接部510与覆盖部S之间保持一定间隔，第一连接部510设置为更靠近第一复位晶体管T7的第一极，即，在Y方向上，主体连接部511与第一像素电路611中的阈值补偿晶体管T2的第二极之间的距离大于主体连接部511与第一像素电路611中的第一复位控制晶体管T7的第一极之间的距离。
例如，图4A为根据本公开实施例提供的第二显示区的第二发光单元组与第二像素电路组的连接关系示意图，图4B为图4A中一个发光单元的示意性层结构图。如图1至图4B所示，各发光单元组包括多个发光单元20。例如，各发光单元组包括一个第一颜色发光单元201、一个第二颜色发光单元对202以及一个第三颜色发光单元203，第一颜色发光单元201和第三颜色发光单元203沿第二方向排列，第二颜色发光单元对202包括沿第二方向排列的两个第二颜色发光单元，第一发光单元块202-1和第二发光单元块202-2，第一颜色发光单元201和第二颜色发光单元对202沿第一方向排列。例如，第一颜色发光单元201的第二电极在沿Y方向延伸的直线上的正投影与第一发光单元块202-1的第二电极在该直线上的正投影有交叠；第三颜色发光单元203的第二电极在该方向延伸的直线上的正投影与两个第二颜色发光单元的第二电极之间的间隔在该直线上的正投影交叠。例如，第三颜色发光单元203的主体电极 (后续描述)在该方向延伸的直线上的正投影与两个第二颜色发光单元的主体电极在该直线上的正投影没有交叠。
例如，各发光单元20包括沿垂直于衬底基板10的方向依次设置的第一电极21、发光层23以及第二电极22，第二电极12位于发光层13面向衬底基板10的一侧。显示基板还包括像素限定层24，像素限定层24包括用于限定子像素的发光区的开口，该开口暴露发光单元20的第二电极22，当后续的发光单元20的发光层23形成在上述像素限定层24的开口中时，发光层23与第二电极22接触，从而这部分能够驱动发光层23进行发光以形成有效发光区。这里的“有效发光区”可以指二维的平面区域，该平面区域平行于衬底基板。需要说明的是，像素限定层的开口由于工艺原因，远离衬底基板的部分尺寸略大于靠近衬底基板部分的尺寸，或者从靠近衬底基板一侧到远离衬底基板一侧的方向上呈现尺寸逐渐增加的形态，因此有效发光区的尺寸与像素限定层开口的不同位置的尺寸可能略有不同，但整体区域形状和尺寸基本相当。例如，有效发光区在衬底基板上的正投影与对应的像素限定层的开口在衬底基板上的正投影大致重合。例如，有效发光区在衬底基板上的正投影完全落在对应的像素限定层的开口在衬底基板上的正投影内，且二者形状相似，有效发光区在衬底基板上的投影面积相比对应的像素限定层的开口在衬底基板上的投影面积略小。
例如，第一颜色发光单元可以为红色发光单元和蓝色发光单元之一，第三颜色发光单元为红色发光单元和蓝色发光单元的另一个，第二颜色发光单元对为绿色发光单元对。本公开示意性的示出第一颜色发光单元为红色发光单元，第二颜色发光单元为绿色发光单元。
例如，如图1至图4B所示，各像素电路还包括与数据线420同层设置的第五连接部550，位于第一显示区100和第二显示区200的发光单元20的第二电极22可以直接通过第五连接部550与第一发光控制晶体管T6的第二极电连接。例如，第一显示区100中，第一发光单元组110中的各发光单元20的第二极可以直接通过第一像素电路组120中相应的像素电路600的第五连接部550与第一发光控制晶体管T6的第二极电连接。第二显示区200中，第二发光单元组210中的各发光单元20的第二极可以直接通过第二像素电路组220中相应的像素电路600的第五连接部550与第一发光控制晶体管T6的第二极电连接。例如，第二显示区200中，第二发光单元组210中的各发光单元20的第二极可以通过钝化层以及平坦层中的第一过孔561与第五连接部550连 接。
例如，如图1至图4B所示，第二像素电路组220包括多个像素电路对610，第二发光单元组210的各发光单元20的第二电极22包括主体电极以及连接电极，主体电极的形状与各发光单元20的有效发光区的形状基本相同，连接电极被配置为直接与第五连接部550电连接以与像素电路对610的两个第一发光控制晶体管T6的第二极电连接。
例如，如图1至图4B所示，显示基板还包括位于第二电极22与数据线420所在膜层之间多条透明走线700，各透明走线700沿第一方向延伸。例如，第三像素电路组230包括多个像素电路对610，透明走线700被配置为连接第三发光单元组310中的发光单元20的第二电极22以及第五连接部550以使第三发光单元组310的各发光单元20的第二电极22与第三像素电路组230的像素电路对610的两个第一发光控制晶体管T6的第二极电连接。
例如，第二显示区200中，透明走线700通过钝化层以及平坦层中的第二过孔562与第三像素电路组310中的第五连接部550电连接；第三显示区300中，发光单元20的第二电极22通过位于透明走线700与第二电极22之间的第三绝缘层与透明走线700连接，进而实现与第二显示区200中的像素电路600的连接。
例如，图4C为图4A所示第二显示区的第二发光单元组和过孔位置关系示意图。如图4A和图4C所示，连接一个第二发光单元组210和一个第二像素电路组220的多个第一过孔561组成的一个第一过孔组5610，连接一个第三发光单元组310和一个第三像素电路组230的多个第二过孔562组成一个第二过孔组5620。沿第一方向，多个第一过孔组5610和多个第二过孔组5620交替排列；沿第二方向，多个第一过孔组5610和多个第二过孔组5620交替排列。相对于第二发光单元组和第三发光单元组均通过透明走线所在膜层与第五连接部连接的情况，本公开实施例中，第二发光单元组的发光单元的第二电极直接与第五连接部连接，而第三发光单元组的发光单元的第二电极通过透明走线与第五连接部连接，可以将更多空间留给透明走线，防止信号发生串扰。
例如，图5D为图1所示的显示基板中的第一显示区和第二显示区的部分平面图。如图1和图5D所示，本公开一实施例中，显示基板中的第一显示区100和第二显示区200包括沿第一方向和第二方向排列的多个像素电路030以形成多个像素电路列32和多个像素电路行31。位于第一显示区100的多个像 素电路030包括多个第一子像素电路031，位于第二显示区200的多个像素电路030包括多个第二子像素电路032，第一显示区100的多个第一发光单元(即第一发光单元组110中包括的三种颜色的发光单元，例如图中所示的R、G1、G2、B)与多个第一子像素电路031一一对应连接，第二显示区200的各第二发光单元(即第二发光单元组210中包括的三种颜色的发光单元，例如图中所示的R、G1、G2、B)与至少两个第二子像素电路032连接。
例如，如图1所示，第一显示区100和第二显示区200在Y方向(即数据线的延伸方向)上相接。第三显示区300包括中心区301以及围绕中心区301的边缘区302，且第三显示区300的边缘区302与第一显示区100在Y方向上相接。例如，图1示意性的示出第三显示区300的形状为矩形，第三显示区300的中心区301的形状为圆形，则边缘区302为位于矩形中除圆形中心区以外的区域。本公开实施例不限于此，第三显示区的中心区和边缘区的形状可以根据实际产品需求进行设置。
例如，如图1所示，第三显示区300的中心区301和边缘区302均设置有第三发光单元组310，且位于第三显示区300的多个第三发光单元组310通过透明走线700分别与第二显示区200中的多个第三像素电路组230电连接以驱动第三发光单元组310发光。第三显示区300的中心区301仅设置发光单元组，不设置像素电路组从而可以减少金属覆盖面积，以实现较高的透光率，而第三显示区300的边缘区302除设置发光单元组外还设置有挡光结构以使得第三显示区300形成具有预设形状的透光区(即中心区301)。例如，本公开实施例中设置在第三显示区300的周边区302的挡光结构可以为多个虚设像素电路组320，多个虚设像素电路组320包括位于第三发光单元组310与衬底基板之间的部分，以及位于相邻第三发光单元组310之间的间隔的部分，各虚设像素电路组320不与任何发光单元组连接，仅为悬空的像素电路。例如，边缘区302为环形走线区。例如，连接第三像素电路组的数据线、扫描信号线、电源信号线、复位控制线、发光控制信号线、复位电源信号线等走线均位于环形走线区。
例如，如图1所示，第三显示区300中的第三发光单元组310可以采用左右对半控制的方式，有关于第三显示区300的沿Y方向延伸的中心线轴对称的两个第二显示区200中的第三像素电路组230分别进行控制。例如，位于上述中心线左侧的第三发光单元组310由位于中心线左侧的第二显示区200内的第三像素电路组230控制，位于上述中心线右侧的第三发光单元组310由位于中 心线右侧的第二显示区200内的第三像素电路组230控制。用于驱动圆形中心区301中的发光单元的走线以密集排布的方式布置在边缘区302中，可以使作为屏下显示区的圆形中心区301具有尽量大的面积。
例如，如图1所示，第一显示区100和第二显示区200包括沿第一方向和第二方向排列的多个像素电路以形成多个像素电路列32和多个像素电路行31。例如，第三显示区300的边缘区302包括沿第一方向和第二方向排列的多个虚设像素电路034以形成多个虚设像素电路列和多个虚设像素电路行。这里将第三显示区300中的虚设像素电路也称为像素电路，虽然虚设像素电路不与任何发光单元连接，但是其结构可以与其他区域的像素电路结构大致相同，例如，均包括7T1C(即七个晶体管和一个电容)结构。例如，多条沿Y方向延伸的数据线420分别与多个像素电路列32相连。
例如，如图1至图4A所示，各像素电路列32包括相邻四列组成的像素电路列组，每个像素电路列组包括沿X方向(即与数据线420的延伸方向相交的方向)依次排列的第一像素电路列321、第二像素电路列322、第三像素电路列323和第四像素电路列324。第一显示区100内的第一像素电路列321、第二像素电路列322、第三像素电路列323以及第四像素电路列324分别与沿第X方向依次排列的第一数据线421、第二数据线422、第三数据线423和第四数据线424相连。第二显示区200内的第一像素电路列321中的至少部分像素电路、第二像素电路列322中的至少部分像素电路、第三像素电路列323中的至少部分像素电路以及第四像素电路列324中的至少部分像素电路分别与沿第X方向依次排列的第一数据线421、第二数据线422、第三数据线423和第四数据线424相连。
例如，如图1至图4A所示，在第二显示区200内，在至少一个像素电路列组中，位于同一像素电路行31且位于第一像素电路列321和第二像素电路列322的两个像素电路的数据输出端(即第四连接部540)电连接以形成第一像素电路对601，位于同一像素电路行31且位于第三像素电路列323和第四像素电路列324的两个像素电路600的数据输出端(即第四连接部540)电连接以形成第二像素电路对602。本公开实施例示意性的示出第二显示区内的各像素电路列组均包括第一像素电路对和第二像素电路对为例进行描述，但不限于此，可以根据实际产品需求进行设置。
例如，如图1至图4A，第一显示区100、第二显示区200和第三显示区 300均包括多个发光单元20，第一显示区100内的多个发光单元20分别与第一显示区100的多个像素电路600连接。第二显示区200的多个发光单元20分别与第二显示区200的一部分像素电路600连接，第三显示区300的多个发光单元20分别与第二显示区200的另一部分像素电路600连接。即，第二显示区200中，第二发光单元组210中的发光单元20与第二像素电路组220中的像素电路600连接；第三显示区300中的第三发光单元组310中的发光单元20与第二显示区200中的第三像素电路组230中的像素电路600连接。本公开实施例示意性的示出第二显示区仅包括第二像素电路组和第三像素电路组，但不限于此，根据产品中空间设计需求等因素，第二显示区还可以包括其他像素电路组，例如虚设像素电路组(不与发光单元连接的)等。
例如，如图1至图4A所示，第二显示区200内的第二像素电路组220和第三像素电路组230均包括第一像素电路对601和第二像素电路对602，则第二显示区200和第三显示区300中，多个发光单元20分别与第二显示区200内的多个第一像素电路对601和多个第二像素电路对602连接。
例如，本公开实施例中第一显示区设置的发光单元可以称为第一发光单元，第二显示区设置的发光单元可以称为第二发光单元，第三显示区设置的发光单元可以称为第三发光单元。
由于第二像素电路组220和第三像素电路组230在X方向和Y方向均交替排列，且沿Y方向排列的同一列第二像素电路组220和第三像素电路组230与不同的数据线420连接。因此，位于第二显示区200内的第一像素电路列321中的部分像素电路与第一数据线421相连，例如位于第一像素电路列321中的第二像素电路组220中的像素电路与第一数据线421相连，而位于第一像素电路列321中的第三像素电路组230中的像素电路与第一数据线421不相连。同理，位于第二显示区200内的第二像素电路列322中的部分像素电路与第二数据线422相连，例如位于第二像素电路列322中的第三像素电路组230中的像素电路与第二数据线422相连，而位于第二像素电路列322中的第二像素电路组220中的像素电路与第二数据线422不相连。位于第二显示区200内的第三像素电路列323中的部分像素电路与第三数据线423相连，例如位于第三像素电路列323中的第三像素电路组230中的像素电路与第三数据线423相连，而位于第三像素电路列323中的第二像素电路组220中的像素电路与第三数据线423不相连。位于第二显示区200内的第四像素电路列324中的部分像素电路 与第四数据线424相连，例如位于第四像素电路列324中的第二像素电路组220中的像素电路与第四数据线422相连，而位于第四像素电路列324中的第三像素电路组230中的像素电路与第四数据线424不相连。
例如，如图1至图4A所示，与第二显示区200的多个发光单元20连接的多个第一像素电路对601与第一数据线421相连，与第二显示区200的多个发光单元20连接的多个第二像素电路对602与第四数据线424相连，与第三显示区300的多个发光单元20连接的多个第一像素电路对601与第二数据线422相连，与第三显示区300的多个发光单元20连接的多个第二像素电路对601与第三数据线423相连。
例如，第二像素电路组220中，第一像素电路对601中的两个像素电路与第一数据线421相连，第二像素电路对602中的两个像素电路与第四数据线424相连。第三像素电路组230中，第一像素电路对601中的两个像素电路与第二数据线422相连，第二像素电路对602中的两个像素电路与第三数据线423相连。
例如，如图1至图4A所示，与第二发光单元组210中的第一颜色发光单元201和第三颜色发光单元203连接的第一像素电路对601与第一数据线421相连，与第二发光单元组210中的第二颜色发光单元对202连接的第二像素电路对602与第四数据线424相连。
图5A为根据本公开实施例提供的第一显示区和第二显示区交界处的部分像素电路结构示意图，图5B为图5A所示位置的数据线连接部所在膜层结构示意图，图5C为图5A所示位置的数据线所在膜层结构示意图。如图1至图5D所示，在第一显示区100和第二显示区200的交界处，即第一子像素电路031和第二子像素电路032之间的间隔处，与至少一个像素电路列组连接的第二数据线422、第三数据线423以及第四数据线424断开以形成第一断口4201，第一数据线421保持连续，没有断口。也就是，第二数据线422中位于第二显示区200的部分与位于第一显示区100的部分在第一显示区100和第二显示区200交界处不连接。同理，第三数据线423中位于第二显示区200的部分与位于第一显示区100的部分在第一显示区100和第二显示区200交界处不连接；第四数据线424中位于第二显示区200的部分与位于第一显示区100的部分在第一显示区100和第二显示区200交界处不连接。第二数据线422位于第一显示区100的部分靠近第二显示区200的端点4220通过数据线连接部560连接 到第四数据线424位于第二显示区200靠近第一显示区100的端点4240，数据线连接部560穿过第三数据线423的第一断口4201。这里的第一数据线421、第二数据线422、第三数据线423和第四数据线424可以指一条连续的数据线，如第一数据线421为连续的数据线；也可以指与同一列像素电路连接且不连续的数据线，如第二数据线422、第三数据线423以及第四数据线424，由此，与第一子像素电路连接的第二数据线422和与第二子像素电路连接的第二数据线422被配置为传输不同的信号；与第一子像素电路连接的第三数据线423和与第二子像素电路连接的第三数据线423被配置为传输不同的信号；与第一子像素电路连接的第四数据线424和与第二子像素电路连接的第四数据线424被配置为传输不同的信号。
例如，与第一子像素电路031连接的第二数据线422和与第二子像素电路032连接的第二数据线422被配置为传输不同的信号；与第一子像素电路031连接的第三数据线423和与第二子像素电路032连接的第三数据线423被配置为传输不同的信号；与第一子像素电路031连接的第四数据线424和与第二子像素电路032连接的第四数据线424被配置为传输不同的信号。本申请中虽然将位于第一显示区和第二显示区中位于同一直线的数据线均称为第二数据线、第三数据线或第四数据线，但是位于不同显示区的第二数据线(第三数据线或第四数据线)被配置为传输不同的信号。
例如，本公开实施例示意性的示出第一显示区中的第二数据线靠近第二显示区的端点通过数据线连接部与第二显示区中的第四数据线靠近第一显示区的端点连接，但不限于此，第一显示区中的第二数据线靠近第二显示区的端点还可以通过数据线连接部与第二显示区中的第三数据线靠近第一显示区的端点连接。
本公开实施例中，位于第一显示区中的像素电路称为第一子像素电路，与位于第二显示区中的发光单元连接的像素电路称为第二子像素电路，与位于第三显示区中的发光单元连接的像素电路称为第三子像素电路。
例如，如图5A所示，本公开实施例以与第一显示区100中的第一像素电路列321连接的多个发光单元20包括第一颜色发光单元和第三颜色发光单元，与第一显示区100中的第二像素电路列322连接的多个发光单元20包括第二颜色发光单元对，与第一显示区100中的第三像素电路列323连接的多个发光单元20包括第一颜色发光单元和第三颜色发光单元，与第一显示区100中的 第四像素电路列324连接的多个发光单元20包括第二颜色发光单元对为例。
本公开实施例中，数据信号从位于第一显示区远离第二显示区一侧的源极驱动集成电路经数据线传输给第一显示区和第二显示区中的像素电路，传输给与第二显示区中一种颜色发光单元连接的像素电路的数据信号应与传输给与第一显示区中的上述相同颜色发光单元连接的像素电路的数据信号相同。由此，第一显示区中同一像素电路列连接至同一数据线，而第二显示区中的像素电路对连接至同一数据线时，容易出现传输至与第一显示区中第一颜色发光单元连接的像素电路的数据信号与传输至与第二显示区中第二颜色发光单元对连接的像素电路对的数据信号相同的问题，导致第一显示区和第二显示区的数据信号不匹配。
例如，第一显示区100中，各第一发光单元组110包括一个第一颜色发光单元、一个第二颜色发光单元对以及一个第三颜色发光单元，各第二颜色发光单元对包括第一发光单元块和第二发光单元块。第一颜色发光单元和第三颜色发光单元沿平行于数据线延伸方向的方向(Y方向)排列，第一发光单元块和第二发光单元块沿Y方向排列，第一颜色发光单元和第二颜色发光单元对沿与Y方向相交的X方向排列，相邻两个第一发光单元组中第一颜色发光单元指向第三颜色发光单元的方向相反。也就是，与第一显示区中靠近第二显示区的一行像素电路且位于像素电路列组中的四个像素电路连接的发光单元依次为第一颜色发光单元、第一发光单元块、第三颜色发光单元以及第二发光单元块。而与上述像素电路列组中的且位于第一显示区靠近第二显示区的第二行像素电路连接的四个发光单元依次为第三颜色发光单元、第二发光单元块、第一颜色发光单元以及第一发光单元块。由此，与第一像素电路列和与第三像素电路列的像素电路连接的第一颜色发光单元和第三颜色发光单元的排列方式不同，与第二像素电路列和与第四像素电路列的像素电路连接的第一发光单元块和第二发光单元块的排列方式不同。数据线传输的数据信号与相应颜色发光单元的排列相关，且第一显示区和第二显示区均应按照上述发光单元排列方式传输匹配的数据信号。
例如，如图1至图5A所示，与第二显示区200中第一像素电路列321连接的多个发光单元20包括交替排列的第一颜色发光单元201和第三颜色发光单元203，与位于第二显示区200靠近第一显示区100的一行且为第一像素电路列321的像素电路连接的发光单元例如为第三颜色发光单元203。第一显示 区100中与第一像素电路列321连接的多个发光单元20包括交替排列的第一颜色发光单元和第三颜色发光单元，与位于第一显示区100靠近第二显示区200的一行且为第一像素电路列321的像素电路连接的发光单元为第一颜色发光单元。由此，第一显示区的靠近第二显示区的一行像素电路行中且与第一数据线连接的像素电路与第一颜色发光单元连接，第二显示区的靠近第一显示区的一行像素电路行中且与同一条第一数据线连接的像素电路与第三颜色发光单元连接，该发光单元的排列方式与第一数据线传输的数据信号相匹配，则第一数据线可以在第一显示区和第二显示区的交界处保持连接，无需在两个显示区交界处断开。
例如，如图1至图5A所示，与第二显示区200中第四像素电路列324连接的多个第二颜色发光单元对202包括交替排列的第一发光单元块202-1和第二发光单元块202-2，与位于第二显示区200靠近第一显示区100的一行且为第四像素电路列324的像素电路连接的发光单元例如为第二发光单元块202-2。第一显示区100中与第四像素电路列324连接的多个第二颜色发光单元对包括交替排列的第一发光单元块和第二发光单元块，与位于第一显示区100靠近第二显示区200的一行且为第四像素电路列324的像素电路连接的发光单元也为第二发光单元块。由此，与第一显示区靠近第二显示区的一行像素电路行且为第四像素电路列的像素电路连接的发光单元和与第二显示区靠近第一显示区的一行像素电路行且为第四像素电路列的像素电路连接的发光单元为同一种发光单元，则与第一显示区的第四像素电路列连接的第四数据线的数据信号和与第二显示区的第四像素电路列连接的第四数据线的数据信号不匹配，因此，第四数据线在第一显示区和第二显示区的交界处应断开连接。
例如，如图1至图5A所示，第一显示区100中与第二像素电路列322连接的多个第二颜色发光单元对包括交替排列的第一发光单元块和第二发光单元块，且与位于第一显示区100靠近第二显示区200的一行且为第二像素电路列322的像素电路连接的发光单元为第一发光单元块。由此，与第二显示区的第四像素电路列连接的第四数据线的数据信号和与第一显示区的第二像素电路列连接的第二数据线的数据信号相匹配，则第二数据线中位于第一显示区的部分与位于第二显示区的部分在两个显示区交界位置处断开连接，且位于第一显示区的第二数据线通过数据线连接部与位于第二显示区的第四数据线连接，以满足集成电路(IC)在第一显示区和第二显示区统一的算法处理。
本公开实施例中，在第一显示区和第二显示区交界的位置，断开第二数据线、第三数据线以及第四数据线，并通过数据线连接部连接第二数据线位于第一显示区的部分靠近第二显示区的端点与第四数据线位于第二显示区靠近第一显示区的端点，从而可以保证从数据线传输至第一显示区中发光单元的数据信号与从数据线传输至第二显示区中发光单元的数据信号的匹配。
例如，如图5A至图5C所示，数据线连接部560与多条数据线420位于不同层。例如，沿垂直于衬底基板的方向，数据线连接部560与电源信号线460有交叠。由于，数据线连接部需要穿过第三数据线的第一断口以及两条电源信号线实现连接第二数据线的端点和第四数据线的端点，由此，数据线连接部需要与数据线设置在不同层。
例如，如图5A至图5C所示，数据线连接部560与复位电源信号线410位于同层以方便设计。
例如，如图5A至图5C所示，第一显示区100中与第二显示区200相邻的一行第一像素电路行31中的且位于第三像素电路列323和第四像素电路列324的两个像素电路中的阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第一极之间设置有数据线连接部560。
本公开实施例中，第一显示区100和第二显示区200交界处指与第一显示区100靠近第二显示区200的一行像素电路行31中像素电路的第一复位晶体管的第一极与数据写入晶体管的第二极之间的间隔。
例如，第一显示区100中与第二显示区200相邻的一行像素电路行31中，阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第二极之间的在第二方向的距离为7～12微米以在阈值补偿晶体管T2的第二极与第一复位控制晶体管T7的第一极之间设置数据线连接部560。
例如，第一显示区100中的像素电路中，第二连接部520与第三连接部530的彼此靠近的边缘之间的在第二方向的距离为7～12微米以在第二连接部520与第三连接部530之间设置数据线连接部560。本公开实施例中，第一连接部与数据线连接部虽然分别设置在第二显示区以及第一显示区和第二显示区的交界，但是通过调整像素电路的阈值补偿晶体管的第二极与第一复位控制晶体管的第一极之间的空间的距离，可以将第一连接部和数据线连接部均设置在像素电路的阈值补偿晶体管的第二极与第一复位控制晶体管的第一极之间的预留出的较大的空间，以防止对其他信号产生干扰。
例如，图6为根据本公开实施例提供的第一显示区和第三显示区的边缘区交界处的部分像素电路结构示意图。例如，如图6所示，第三显示区内的多个虚设像素电路列包括相邻四列组成的虚设像素电路列组，每个虚设像素电路列组包括沿第二方向依次排列的第一虚设像素电路列0341、第二虚设像素电路列0342、第三虚设像素电路列0343和第四虚设像素电路列0344，第一虚设像素电路列0341的至少部分虚设像素电路034、第二虚设像素电路列0342的至少部分虚设像素电路034、第三虚设像素电路列0343的至少部分虚设像素电路034以及第四虚设像素电路列0344的至少部分虚设像素电路034分别与沿第二方向依次排列的第一数据线421、第二数据线422、第三数据线423和第四数据线424相连，虚设像素电路034和第一像素电路031的间隔处(例如第三显示区300的边缘区302和第一显示区100的交界处)，第三数据线423和第四数据线424断开以形成第二断口4202。
例如，上述的第一虚设像素电路列0341、第二虚设像素电路列0342、第三虚设像素电路列0343和第四虚设像素电路列0344也可以分别称为第一像素电路列、第二像素电路列、第三像素电路列和第四像素电路列。
例如，如图1至图6所示，与第三发光单元组310中的第一颜色发光单元和第三颜色发光单元连接的像素电路对可以为第一像素电路对601和第二像素电路对602之一，与第三发光单元组310中的第二颜色发光单元对连接的像素电路对可以为第一像素电路对601和第二像素电路对602的另一个。
例如，与第三发光单元组310的第一颜色发光单元和第三颜色发光单元连接的像素电路对可以与第二数据线422和第三数据线423之一连接，与第三发光单元组310的第一发光单元块和第二发光单元块连接的像素电路对可以与第二数据线422和第三数据线423的另一个连接。例如，与第三发光单元组310的第一颜色发光单元和第三颜色发光单元连接的像素电路对可以与第三数据线423连接，与第三发光单元组310的第一发光单元块和第二发光单元块连接的像素电路对可以与第二数据线422连接。由于在第一显示区和第二显示区的交界，第二数据线和第三数据线均断开，与第三发光单元组连接的像素电路不能被与第二显示区相接的第一显示区中的数据线输入匹配的数据信号。因此，本公开实施例中采用第三显示区的边缘区和第一显示区的交界处连续的第一数据线和第二数据线分别连接与第三发光单元组310的第一发光单元块和第二发光单元块连接的像素电路对以及与第三发光单元组310的第一颜色发光单元 和第三发光单元连接的像素电路对，以实现对与第三发光单元组连接的像素电路输入匹配的数据信号，满足集成电路在第一显示区和第三显示区统一的算法处理。
例如，第三显示区300中与第二显示区200的第三像素电路列323连接的多个发光单元包括交替排列的第一颜色发光单元和第三颜色发光单元，且与位于第二显示区200远离第一显示区100的第一行以及第三像素电路列323的像素电路连接的发光单元为第三颜色发光单元。第一显示区100中与第一像素电路列321连接的多个发光单元20包括交替排列的第一颜色发光单元和第三颜色发光单元，与位于第一显示区100靠近的第三显示区300一行且连接第一颜色发光单元的像素电路连接的数据线为第一数据线。
例如，第三显示区300中与第二显示区200的第二像素电路列322连接的多个发光单元包括交替排列的第一发光单元块和第二发光单元块，且与位于第二显示区200远离第一显示区100的第一行以及第二像素电路列322中的像素电路连接的发光单元为第二发光单元块。第一显示区100中与第二像素电路列322连接的多个发光单元20包括交替排列的第一发光单元块和第二发光单元块，与位于第一显示区100靠近的第三显示区300一行且连接第一发光单元块的像素电路连接的数据线为第二数据线。由此，第一显示区与第三显示区的边缘区相接的区域中的第一数据线和第二数据线上的数据信号分别与第二显示区中的第三数据线和第二数据线上的数据信号匹配，而第一显示区与第三显示区的边缘区相接的区域中的第三数据线和第四数据线传输的数据信号与第二显示区中的第三数据线和第二数据线上的数据信号不匹配，则第三显示区的边缘区和第一显示区的交界处，第一数据线和第二数据线保持连接，而第三数据线和第四数据线断开连接。
例如，如图1至图6所示，显示基板还包括位于第三显示区300远离第一显示区100一侧的周边区303，位于第三显示区300的边缘区302的第一数据线421绕过中心区301以在周边区303连接到第二显示区200的第二数据线422和第三数据线423之一，位于第三显示区300的边缘区302的第二数据线422绕过中心区301以在周边区303连接到第二显示区200的第二数据线422和第三数据线423的另一个。
例如，本公开实施例示意性的示出，位于第三显示区300的边缘区302的第一数据线421绕过中心区301以在周边区303连接到第二显示区200的第三 数据线423，位于第三显示区300的边缘区302的第二数据线422绕过中心区301以在周边区303连接到第二显示区200的第二数据线422，从而方便第三显示区和第二显示区中数据线的走线。
例如，如图1-图6所示，本公开另一实施例提供一种显示基板包括第一显示区100和第二显示区200。第一显示区100包括多个第一发光单元110-1和多个第一子像素电路031，多个第一发光单元110-1包括相邻设置的第一发光单元列110-11和第二发光单元列110-12，各发光单元列与相应的一列第一子像素电路031连接，第二显示区120包括多个第二发光单元120-1和多个第二子像素电路032，多个第二发光单元120-1包括相邻设置的第三发光单元列120-11和第四发光单元列120-12，第二显示区200中的各发光单元列与一列第一子像素电路对032-1连接，各列第一子像素电路对032-1包括相邻两列第二子像素电路032。
例如，如图1-图6所示，显示基板还包括沿第二方向延伸的多条第一子数据线4210、多条第二子数据线4220、多条第三子数据线4230以及多条第四子数据线4240，各第一子数据线4210与各第一发光单元列110-11连接，各第二子数据线4220与各第二发光单元列110-12连接，各第三子数据线4230与各第三发光单元列120-11连接，各第四子数据线4240与各第四发光单元列120-12连接，第二方向与第一方向相交。
例如，如图1-图6所示，第一发光单元列110-11和第二发光单元列110-12的排列方向与第三发光单元列120-11和第四发光单元列120-12的排列方向相同，与第一发光单元列110-11连接的一列第一子像素电路031和与第三发光单元列120-11连接的一列第二子像素电路032位于同一列，第一子数据线4210和第三子数据线4230为沿第二方向延伸且连续的一条数据线；与第四发光单元列120-12连接的两列第二子像素电路032和与第二发光单元列110-12连接的一列第一子像素电路031均位于不同列，第二子数据线4220与第四子数据线4240通过数据线连接部560连接，且数据线连接部560的延伸方向与第二方向相交。
这里的第一子数据线4210、第二子数据线4220、第三子数据线4230和第四子数据线4240与上述实施例中的第一数据线421、第二数据线422、第三数据线423和第四数据线424指代的含义不同，这里的第一子数据线4210仅指上述实施例中的第一数据线421中连接第一显示区中像素电路的数据线，这里 的第二子数据线4220指上述实施例中的第二数据线422中连接第一显示区中像素电路的数据线，这里的第三子数据线4230仅指上述实施例中的第一数据线421中连接第二显示区中像素电路的数据线，这里的第四子数据线4240仅指上述实施例中的第四数据线424中连接第二显示区中像素电路的数据线。
在第一显示区的像素电路和第二显示区的像素电路交界的位置，断开第二子数据线与第四子数据线，并通过数据线连接部连接第二子数据线与第四子数据线，从而可以保证从数据线传输至第一显示区中发光单元的数据信号与从数据线传输至第二显示区中发光单元的数据信号的匹配。
例如，如图1-图6所示，与第二发光单元列110-12连接的一列第一子像素电路031和与第三发光单元列120-11连接的另一列第二子像素电路032位于同一列。
例如，如图1-图6所示，第一显示区100还包括相邻设置第五发光单元列110-13和第六发光单元列110-14，第一发光单元列110-11、第二发光单元列110-12、第五发光单元列110-13和第六发光单元列110-14沿第一方向重复排列，第三发光单元列120-11和第四发光单元列120-12沿第一方向交替排列。
例如，如图1-图6所示，显示基板还包括沿第二方向延伸的多条第五子数据线4250和多条第六子数据线4260，各第五子数据线4250与各第五发光单元列110-13连接，各第六子数据线4260与各第六发光单元列110-14连接。
例如，如图1-图6所示，与第五发光单元列110-13连接的一列第一子像素电路031和与第四发光单元列120-12连接的一列第二子像素电路032位于同一列，与第六发光单元列110-14连接的一列第一子像素电路031和与第四发光单元列120-12连接的另一列第二子像素电路032位于同一列，第六子数据线4260或第五子数据线4250与第四子数据线4240之间设置有间隔。图5D示意性的示出与第六子数据线4260连接的像素电路和与第四子数据线4240连接的像素电路位于同一列，则第六子数据线4260和第四子数据线4240之间设置有间隔，但不限于此，在第四子数据线连接的像素电路与第五子数据线连接的像素电路位于同一列使，第四子数据线与第五子数据线之间设置有间隔。这里的第五子数据线4250仅指上述实施例中的第三数据线423中连接第一显示区中像素电路的数据线，这里的第六子数据线4260指上述实施例中的第四数据线424中连接第一显示区中像素电路的数据线。
例如，图5E为根据本公开实施例的另一示例提供的显示基板中的第一显 示区和第二显示区的部分平面图。图5E所示示例与图5D所示示例不同之处在于像素的排列，图5D所示示例中像素排列为GGRB排列，图5E所示示例中像素排列为realRGB排列。如图5E所示，位于第一显示区100中的每六个RGB发光单元为一个重复周期。与第一显示区100的第一列R发光单元连接的数据线420和与第二显示区100的第一列R发光单元连接的数据线420为同一条连续的数据线；与第一显示区100第二列G发光单元连接的数据线420和与第二显示区100的第二列R发光单元连接的数据线420之间具有间隔，且与第一显示区100第二列G发光单元连接的数据线420通过数据线连接部560和与第二显示区100的第三列G(或第四列G)发光单元连接的数据线420连接；与第一显示区100第三列B发光单元连接的数据线420和与第二显示区100的第三列G发光单元连接的数据线420之间具有间隔，且与第一显示区100第三列B发光单元连接的数据线420通过数据线连接部560和与第二显示区100的第五列B(或第六列B)发光单元连接的数据线420连接；与第一显示区100第四列G发光单元连接的数据线420和与第二显示区100的第四列G发光单元连接的数据线420之间具有间隔；与第一显示区100第五列R发光单元连接的数据线420和与第二显示区100的第五列B发光单元连接的数据线420之间具有间隔；与第一显示区100第六列G发光单元连接的数据线420和与第二显示区100的第六列B发光单元连接的数据线420之间具有间隔。本公开实施例不限于上述连接，只要第一显示区中的一个R发光单元与第二显示区中的一个R发光单元连接至同一数据线，第一显示区中的一个B发光单元与第二显示区中的一个B发光单元连接至同一数据线，第一显示区中的一个G发光单元与第二显示区中的一个G发光单元连接至同一数据线即可。
例如，如图1-图6所示，第一显示区100包括沿第一方向和第二方向交替排列的多个第一子发光单元组1-1和多个第二子发光单元组1-2，第一子发光单元组1-1包括第一发光单元列110-11和第二发光单元列110-12中的发光单元，第二子发光单元组1-2包括第五发光单元列110-13和第六发光单元列110-14中的发光单元，第二显示区200包括多个第三子发光单元组1-3。
例如，如图1-图6所示，各子发光单元组包括一个第一颜色发光单元R、一个第二颜色发光单元对G1和G2以及一个第三颜色发光单元B，第一颜色发光单元R和第三颜色发光单元B沿第二方向排列，第二颜色发光单元对G1和G2包括沿第二方向排列的两个第二颜色发光单元，第一颜色发光单元R和 第二颜色发光单元对G1和G2沿第一方向排列，且第一子发光单元组1-1中第一颜色发光单元R和第三颜色发光单元B的排列方向与第二子发光单元组1-2中第一颜色发光单元R和第三颜色发光单元B的排列方向相反，第一子发光单元组1-1中各发光单元的相对位置分布与第三子发光单元组1-3中各发光单元的相对位置分布相同。本公开实施例示意性的以第一颜色发光单元为红色发光单元，第二颜色发光单元对为绿色发光单元对且第三颜色发光单元为蓝色发光单元为例，但不限于此。例如，第一颜色发光单元可以为蓝色发光单元，第二颜色发光单元对为绿色发光单元对且第三颜色发光单元可以为红色发光单元。例如，第一颜色发光单元为绿色发光单元，第二颜色发光单元对为红色发光单元对且第三颜色发光单元为蓝色发光单元。
例如，如图1-图6所示，衬底基板还包括第三显示区300，第二显示区200还包括多个第三子像素电路033，第三显示区300包括多个第三发光单元130-1，多个第三发光单元130-1包括相邻设置的第七发光单元列130-11和第八发光单元列130-12，第一发光单元列110-11和第二发光单元列110-12的排列方向与第七发光单元列130-11和第八发光单元列130-12的排列方向相同，第三显示区300中的各发光单元列与一列第二子像素电路对033-1连接，各列第二子像素电路对033-1包括相邻两列第三子像素电路033。
例如，如图1-图6所示，显示基板还包括沿第二方向延伸的多条第七子数据线4270和多条第八子数据线4280，各第七子数据线4270与各第七发光单元列130-11连接，各第八子数据线4280与各第八发光单元列130-12连接。
例如，如图1-图6所示，第七子数据线4270和第八子数据线4280的至少之一设置在第三子数据线4230和第四子数据线4240之间。这里的第七子数据线4270仅指上述实施例中的第二数据线422中连接第二显示区中像素电路的数据线，这里的第八子数据线4280指上述实施例中的第三数据线423中连接第二显示区中像素电路的数据线。
例如，如图1-图6所示，第七子数据线4270和第八子数据线4280均设置在第三子数据线4230和第四子数据线4240之间，且第八子数据线4280与第五子数据线4250之间设置有间隔以设置数据线连接部560。
例如，第八子数据线4280与第五子数据线4250数据线在第一显示区像素电路和第二显示区像素电路之间间隔位置处有断口，连接部560设置在断口处。
例如，如图1-图6所示，多个第三子像素电路033被配置为与多个第四子 发光单元组1-4，各第四子发光单元组1-4中各发光单元的相对位置分布与第三子发光单元组1-3中各发光单元的相对位置分布相同，与第三子发光单元组1-3连接的第一子像素电路对032-1和与第四发光单元组1-4连接的第二子像素电路对033-1沿第一方向和第二方向交替排列。
例如，如图1-图6所示，第三显示区300包括中心区301以及围绕中心区301的边缘区302，边缘区302包括沿第一方向和第二方向排列的多个虚设像素电路以形成多个虚设像素电路列320-1和多个虚设像素电路行320-2。
例如，如图1-图6所示，第三显示区300内的多个虚设像素电路列320-1包括相邻四列组成的虚设像素电路列组3201，每个虚设像素电路列组3201包括沿第一方向依次排列的第一虚设像素电路列0341、第二虚设像素电路列0342、第三虚设像素电路列0343和第四虚设像素电路列0343。
例如，如图1-图6所示，显示基板还包括第一虚设数据线431、第二虚设数据线432、第三虚设数据线433和第四虚设数据线434，第一虚设数据线431与第一虚设像素电路列0341连接，第二虚设数据线432与第二虚设像素电路列0342连接，第三虚设数据线433与第三虚设像素电路列0343连接，且第四虚设数据线434与第四虚设像素电路列0344连接。
例如，如图1-图6所示，与第一发光单元列110-11连接的一列第一子像素电路031和第一虚设像素电路列0341位于同一列，与第二发光单元列110-12连接的一列第一子像素电路031和第二虚设像素电路列0342位于同一列，与第五发光单元列110-13连接的一列第一子像素电路031与第三虚设像素电路列0343位于同一列，与第六发光单元列110-14连接的一列第一子像素电路031与第四虚设像素电路列0344位于同一列。与第一发光单元组1-1连接的两条数据线与相应的两条虚设数据线为连续的两条数据线，或者与第二发光单元组1-2连接的两条数据线与相应的两条虚设数据线为连续的两条数据线。图6示意性的示出与与第一发光单元组1-1连接的两条数据线与相应的两条虚设数据线为连续的两条数据线。
例如，如图1-图6所示，显示基板还包括位于第三显示区300远离第一显示区100一侧的周边区400，与第一发光单元组1-1或第二发光单元组1-2连接的两条虚设数据线绕过中心区301以在周边区400分别连接第七子数据线4270和第八子数据线4280。
例如，如图1-图6所示，第一虚设数据线431和第一子数据线4210为一 条连续的数据线，第二虚设数据线432和第二子数据线4220为一条连续的数据线，第三虚设数据线433和第五子数据线4250之间设置有间隔，第四虚设数据线434和第六子数据线4260之间设置有间隔。
例如，如图1-图6所示，第一虚设数据线431绕过中心区301以在周边区400连接第七子数据线4270，第二虚设数据线绕过中心区以在周边区连接第八数据线。
例如，图7为根据本公开实施例提供的位于第一显示区的发光单元组的第二电极的示意图，图8为根据本公开实施例提供的位于第二显示区非边缘的发光单元组的第二电极的示意图，图9为根据本公开实施例提供的位于第三显示区的发光单元组的第二电极的示意图。如图1至图9所示，各发光单元20的第二电极22包括主体电极22-1以及连接电极22-2，主体电极22-1的形状与各发光单元20的有效发光区的形状基本相同，连接电极22-2被配置为通过与第五连接部550以与像素电路的第一发光控制晶体管T6的第二极电连接。位于显示区的各发光单元组包括多个不同颜色发光单元，例如，各发光单元组包括一个第一颜色发光单元201、第二颜色发光单元对202以及第三颜色发光单元203。
例如，如图1至图9所示，位于第二显示区200的非边缘区域和第三显示区300的至少之一中的一种颜色发光单元的主体电极22-1的面积大于位于第一显示区100的且与上述一种颜色发光单元颜色相同的发光单元20的主体电极22-1的面积。各颜色发光单元的主体电极的面积与其有效发光区的面积相关，本公开实施例中，通过将位于第二显示区的非边缘区域和第三显示区的至少之一中的一种颜色发光单元的主体电极的面积设置为大于位于第一显示区的且与上述一种颜色发光单元颜色相同的发光单元的主体电极的面积，可以使得位于第二显示区的非边缘区域和第三显示区的至少之一中的一种颜色发光单元的有效发光区的面积设计为大于位于第一显示区的且与上述一种颜色发光单元颜色相同的发光单元的有效发光区的面积。
本公开实施例中，由于第二显示区和第三显示区的发光单元组的密度均小于第一显示区的发光单元组的密度，通过将第二显示区和第三显示区的至少之一的发光单元中主体电极的面积设置为大于第一显示区的发光单元中主体电极的面积以使位于第二显示区的非边缘区域和第三显示区的至少之一中的一种颜色发光单元的有效发光区的面积设计为大于位于第一显示区的且与上述 一种颜色发光单元颜色相同的发光单元的有效发光区的面积，可以在保证发光单元发光材料寿命的基础上增加第二显示区和第三显示区至少之一的亮度，实现更加均匀的全面屏视觉显示效果。
例如，本公开实施例示意性的示出位于第二显示区200的非边缘区域和第三显示区300中，一种颜色发光单元的主体电极22-1的面积大于位于第一显示区100的且与上述一种颜色发光单元颜色相同的发光单元20的主体电极22-1的面积以使位于第二显示区的非边缘区域和第三显示区的一种颜色发光单元的有效发光区的面积设计为大于位于第一显示区的且与上述一种颜色发光单元颜色相同的发光单元的有效发光区的面积，由此，可以在保证发光单元发光材料寿命的基础上增加第二显示区和第三显示区的亮度，实现更加均匀的全面屏视觉显示效果。
例如，在本公开实施例的一示例中，第一显示区、第二显示区和第三显示区中的各发光单元均与一个像素电路连接，即第二显示区和第三显示区中各发光单元可以不与像素电路对连接，而仅是与一个像素电路连接。此时，第二显示区和第三显示区的发光单元组的密度均小于第一显示区的发光单元组的密度，通过将第二显示区和第三显示区的至少之一的发光单元中主体电极的面积设置为大于第一显示区的发光单元中主体电极的面积以使位于第二显示区的非边缘区域和第三显示区的至少之一中的一种颜色发光单元的有效发光区的面积设计为大于位于第一显示区的且与上述一种颜色发光单元颜色相同的发光单元的有效发光区的面积，可以尽量均匀各显示区的显示效果。
例如，在本公开实施例的另一示例中，各像素电路组包括多个像素电路，第二显示区中的第二像素电路组和第三像素电路组至少之一包括多个像素电路对，各像素电路对包括的两个像素电路被配置为与同一个发光单元的第二电极电连接。例如，第二显示区中的第二像素电路组和第三像素电路组均包括多个像素电路对，第二像素电路组中的各像素电路对与第二发光单元组中的各发光单元连接，第三像素电路组中的各像素电路对与第三发光单元组中的各发光单元连接。第二显示区和第三显示区的发光单元组的密度均小于第一显示区的发光单元组的密度，将与第二显示区和第三显示区的发光单元连接的像素电路设计为像素电路对的方案与将第二显示区和第三显示区的发光单元中主体电极的面积设置为大于第一显示区的发光单元中主体电极的面积的方案结合，可以在保证发光单元的发光材料寿命的基础上，将使第二显示区和第三显示区的 发光单元的电流和亮度增加到一个像素电路驱动情况下的1.8到2倍，解决了第二显示区和第三显示区中电流和亮度偏小的问题，实现更加均匀的全面屏的视觉显示效果。
例如，如图1至图9所示，各发光单元组包括第一颜色发光单元201，位于第二显示区200的非边缘区域和第三显示区300的至少之一中的各第一颜色发光单元201的主体电极2011的面积与位于第一显示区100的各第一颜色发光单元201的主体电极2011的面积比为1.5～2.5，例如为1.9～2.1。
例如，位于第二显示区200的非边缘区域和第三显示区300的至少之一中的各第一颜色发光单元201的有效发光区的面积与位于第一显示区100的各第一颜色发光单元201的有效发光区的面积比为2。
例如，如图1至图9所示，位于各显示区的第一颜色发光单元201的主体电极2011和有效发光区的形状均为六边形，位于第二显示区200的非边缘的第一颜色发光单元201的连接电极2012的面积可以大于位于第一显示区100的第一颜色发光单元201的连接电极2012的面积以实现与像素电路对的连接。
例如，如图1至图9所示，位于第二显示区200的非边缘区域和第三显示区300的至少之一中的各第二颜色发光单元对202的主体电极2021的面积与位于第一显示区100的各第二颜色发光单元对202的主体电极2021的面积比为1.5～2.5，例如为1.9～2.1。
例如，位于第二显示区200的非边缘区域和第三显示区300的各第二颜色发光单元对202的有效发光区的面积与位于第一显示区100的各第二颜色发光单元对202的有效发光区的面积比为2。
例如，如图1至图9所示，位于第二显示区200的非边缘区域和第三显示区300的至少之一中的各第一发光单元块202-1的主体电极2021-1的面积与位于第一显示区100的各第一发光单元块202-1的主体电极2021-1的面积比为1.5～2.5，例如为1.9～2.1。例如，位于第二显示区200的非边缘区域和第三显示区300的至少之一中的各第二发光单元块202-2的主体电极2021-2的面积与位于第一显示区100的各第二发光单元块202-2的主体电极2021-2的面积比为1.5～2.5，例如为1.9～2.1。
例如，位于第二显示区200的非边缘区域的各第一发光单元块202-1的连接电极2022-1的面积大于位于第一显示区100的各第一发光单元块202-1的连接电极2022-1的面积。例如，位于第二显示区200的非边缘区域的各第二发 光单元块202-2的连接电极2022-2的面积大于位于第一显示区100的各第二发光单元块202-2的连接电极2022-2的面积以方便与像素电路对连接。
例如，位于第二显示区200的非边缘区域和第三显示区300的至少之一中的各第三颜色发光单元203的主体电极2031的面积与位于第一显示区100的各第三颜色发光单元203的主体电极2031的面积比为1.5～2.5，例如为1.9～2.1。
例如，位于第二显示区200的非边缘区域和第三显示区300的各第三颜色发光单元203的主体电极2031的面积与位于第一显示区100的各第三颜色发光单元203的主体电极2031的面积比为2。例如，位于第二显示区200的非边缘区域和第三显示区300的各第三颜色发光单元203的有效发光区的面积与位于第一显示区100的各第三颜色发光单元203的有效发光区的面积比为2。
例如，位于第二显示区200的非边缘区域的各第三颜色发光单元203的连接电极2032的面积大于位于第一显示区100的各第三颜色发光单元203的连接电极2032的面积以实现与像素电路对的连接。
例如，各显示区的第三颜色发光单元的主体电极和有效发光区的形状均为六边形。
例如，如图8和图9所示，第二显示区的发光单元组的发光单元的第二电极直接与像素电路对连接，则第二显示区的发光单元的连接电极的面积较大，而第三显示区的发光单元组的发光单元的第二电极通过透明走线与第二显示区的像素电路对连接，则第三显示区的发光单元的连接电极的面积可以设置的较小。
例如，图10为根据本公开实施例提供的第二显示区的与第一显示区交界的两行发光单元组中的各发光单元的第二电极的示意图。如图1至图10所示，第二显示区200的与第一显示区100在Y方向上相邻的一行发光单元组中的各第一颜色发光单元201的主体电极2011的形状和面积与位于第一显示区100的各第一颜色发光单元201的主体电极的2011形状和面积均大致相同。本公开实施例将第二显示区的与第一显示区在Y方向上彼此相邻的两行发光单元组中的各第一颜色发光单元的主体电极的形状和面积设置为均大致相同，即位于第二显示区边缘的第一颜色发光单元的主体电极的面积与位于第二显示区非边缘区域的第一颜色发光单元的主体电极的面积设计为不同，可以在将第二显示区大部分第一颜色发光单元的亮度增加以均匀全面屏显示效果的同时，防止两行发光单元的主体电极在空间上出现冲突。
例如，如图1至图10所示，第二显示区200的与第一显示区100在第一方向上相邻的一行发光单元组中的各第二颜色发光单元对202的主体电极2021的面积与位于第一显示区100的各第二颜色发光单元对202的主体电极2021的面积比为0.9～1.1。本公开实施例将第二显示区的与第一显示区在Y方向上彼此相邻的两行发光单元组中的各第二颜色发光单元的主体电极的面积设置为大致相同，即位于第二显示区边缘的第二颜色发光单元的主体电极的面积与位于第二显示区非边缘区域的第二颜色发光单元的主体电极的面积设计为不同，可以在将第二显示区大部分第二颜色发光单元的亮度增加以均匀全面屏显示效果的同时，防止两行发光单元的主体电极在空间上出现冲突。
例如，如图1至图10所示，第一显示区100内的第二颜色子像素对202包括的两个第二颜色子像素的主体电极2021的形状与第二显示区200的与第一显示区100在第一方向上相邻的一行发光单元组的各第二颜色发光单元对202的两个主体电极2021的形状不同。
本公开实施例中，位于第二显示区非边缘区域中的相邻两个发光单元之间的像素限定层的间隙(PDL gap)的尺寸与位于第二显示区边缘区域中的相邻两个发光单元之间的PDL gap的尺寸大致相同，以使得第二显示区显示图像光的均一性。
例如，如图1至图10所示，第一显示区100内的第二颜色子像素对202包括的两个第二颜色子像素的主体电极2021的形状均为五边形，且各五边形包括沿X方向延伸的一条第一边1、沿Y方向延伸的两条第二边2以及与两条第二边2连接的两条第三边3，两条第三边3交叉形成尖角，两个第二颜色子像素的主体电极2021的两个尖角彼此靠近。第二显示区200的与第一显示区100在Y方向上相邻的一行发光单元组的各第二颜色发光单元对202的各主体电极2021包括沿X方向延伸的一条第四边4、沿Y方向延伸的两条第五边5、与两条第五边5连接的两条第六边6以及连接两条第六边6的第七边7，两个第二颜色子像素的主体电极2021的两条第七边7彼此靠近。
例如，如图7至图10所示，第一显示区100的第二颜色发光单元的主体电极2021的第二边2的长度小于第二显示区200边缘的第二颜色发光单元的主体电极2021的第五边5的长度以保证第一显示区的第二颜色发光单元的主体电极的面积与第二显示区边缘的第二颜色发光单元的主体电极的面积大致相等。
例如，如图7至图10所示，在第二显示区200的边缘的第二颜色发光单元的主体电极2021的面积设置为与第一显示区100的第二颜色发光单元的主体电极2021的面积相同时，为了保证第二显示区200边缘的第二颜色发光单元与第一颜色发光单元(或第三颜色发光单元)之间的PDL gap与第二显示区200非边缘区域的第二颜色发光单元与第一颜色发光单元(或第三颜色发光单元)之间的PDL gap，第二显示区200的与第一显示区100在第一方向上相邻的一行发光单元组中的各第二颜色发光单元对的两个主体电极的中心连线与第一显示区的各第二颜色发光单元对的两个主体电极的中心连线不平行。
在第二显示区200的边缘的第二颜色发光单元的主体电极2021的面积设置为与第一显示区100的第二颜色发光单元的主体电极2021的面积相同时，为了保证第二显示区200边缘的第二颜色发光单元与第一颜色发光单元(或第三颜色发光单元)之间的PDL gap与第二显示区200非边缘区域的第二颜色发光单元与第一颜色发光单元(或第三颜色发光单元)之间的PDL gap位于第二显示区200边缘的第二颜色发光单元的主体电极的形状如果为包括尖角的五边形，则会与第一颜色发光单元(或第三颜色发光单元)的连接电极在空间上存在冲突。因此第二显示区边缘的第二颜色发光单元的主体电极的形状不再包括尖角。此时，为了保证第二显示区边缘的第二颜色发光单元的主体电极的面积与第一显示区的第二颜色发光单元的主体电极的面积大致相同，则需要对第二显示区边缘的第二颜色发光单元的主体电极形状进行补偿，即增加两条第六边6以及连接两条第六边6的第七边7，从而在保证第二显示区边缘的第二颜色发光单元的主体电极在空间上没有冲突的情况下，实现其面积与第一显示区的第二颜色发光单元的面积相等。
例如，如图1至图10所示，第二显示区200的与第一显示区100在Y方向上的相邻的一行发光单元组中的各第三颜色发光单元203的主体电极2031的形状和面积与位于第一显示区100的各第三颜色发光单元203的主体电极2031的形状和面积均大致相同。本公开实施例将第二显示区的与第一显示区在Y方向上彼此相邻的两行发光单元组中的各第三颜色发光单元的主体电极的形状和面积设置为均大致相同，即位于第二显示区边缘的第三颜色发光单元的主体电极的面积与位于第二显示区非边缘区域的第三颜色发光单元的主体电极的面积设计为不同，可以在将第二显示区大部分第三颜色发光单元的亮度增加以均匀全面屏显示效果的同时，防止两行发光单元的主体电极在空间上出现 冲突。
例如，图11为根据本公开实施例提供的第二显示区的与第一显示区交界的两列发光单元组中的各发光单元的第二电极的示意图。如图11所示，第二显示区200的与第一显示区100在X方向上相邻的一列发光单元组中，第二颜色发光单元对202位于第一颜色发光单元201和第三颜色发光单元203靠近第一显示区100的一侧，该列发光单元组中的各第二颜色发光单元对202的主体电极2021的面积和形状与位于第一显示区100的各第二颜色发光单元对202的主体电极2021的面积和形状均大致相同。本公开实施例将第二显示区的与第一显示区在X方向上彼此相邻的两列发光单元组中的各第二颜色发光单元对的主体电极的形状和面积设置为均大致相同，即位于第二显示区边缘的第二颜色发光单元对的主体电极的面积与位于第二显示区非边缘区域的第二颜色发光单元对的主体电极的面积设计为不同，可以在将第二显示区大部分第二颜色发光单元对的亮度增加以均匀全面屏显示效果的同时，防止两列发光单元的主体电极在空间上出现冲突。
例如，沿Y方向排列的相邻两个第二发光单元组之间设置有第三像素电路组，由此，沿Y方向排列的相邻的两个第二发光单元组之间的间隔处不设置发光单元组。第一显示区100在X方向靠近第二显示区200的一列多个第一发光单元组中的相邻两个第一发光单元组之间设置有间隔，该间隔区域包括不与发光单元组连接的一个第一像素电路组，且沿X方向，该第一像素电路组和与第一显示区100紧邻的一列第二发光单元组中的发光单元组位于同一直线上，由此，可以平衡在X方向上第一显示区与第二显示区的亮度分布。
例如，如图11所示，第二显示区200的与第一显示区100在X方向上相邻的一列发光单元组中，各第一颜色发光单元201的主体电极2011的面积与位于第一显示区100的各第一颜色发光单元201的主体电极2011的面积比为1.5～2.5，例如为1.9～2.1。例如，第二显示区200的与第一显示区100在X方向上相邻的一列发光单元组中，各第一颜色发光单元201的有效发光区的面积与位于第一显示区100的各第一颜色发光单元201的有效发光区的面积比为2。本公开实施例中，在保证第二显示区的与第一显示区在X方向上相邻的一列发光单元组中的发光单元的主体电极在空间上不发生冲突的情况下，位于第二显示区边缘的第一颜色发光单元的主体电极的形状和面积与位于第二显示区非边缘区域的第一颜色发光单元的主体电极的形状和面积均大致相同，可以在将 第二显示区大部分第一颜色发光单元的亮度增加以均匀全面屏显示效果的同时，防止两列发光单元的主体电极在空间上出现冲突。
例如，如图11所示，第二显示区200的与第一显示区100在X方向上相邻的一列发光单元组中，各第三颜色发光单元203的主体电极2031的面积与位于第一显示区100的各第三颜色发光单元203的主体电极2031的面积比为1.5～2.5，例如为1.9～2.1。例如，第二显示区200的与第一显示区100在X方向上相邻的一列发光单元组中，各第三颜色发光单元203的有效发光区的面积与位于第一显示区100的各第三颜色发光单元203的有效发光区的面积比为2。本公开实施例中，在保证第二显示区的与第一显示区在X方向上相邻的一列发光单元组中的发光单元的主体电极在空间上不发生冲突的情况下，位于第二显示区边缘的第三颜色发光单元的主体电极的形状和面积与位于第二显示区非边缘区域的第三颜色发光单元的主体电极的形状和面积均大致相同，可以在将第二显示区大部分第三颜色发光单元的亮度增加以均匀全面屏显示效果的同时，防止两列发光单元的主体电极在空间上出现冲突。
本公开另一实施例提供一种显示装置，包括上述任一种显示基板。
本公开实施例的一示例提供的显示装置中，第二显示区内的两个像素电路驱动一个发光单元发光，可以增加第二显示区和第三显示区至少之一的发光单元的电流和亮度，实现更加均匀的全面屏的视觉显示效果。
本公开实施例的一示例提供的显示装置中，通过将第二显示区和第三显示区的至少之一的发光单元中主体电极的面积设置为大于第一显示区的发光单元中主体电极的面积以使位于第二显示区的非边缘区域和第三显示区的至少之一中的一种颜色发光单元的有效发光区的面积设计为大于位于第一显示区的且与上述一种颜色发光单元颜色相同的发光单元的有效发光区的面积，可以在保证发光单元发光材料寿命的基础上增加第二显示区和第三显示区至少之一的亮度，实现更加均匀的全面屏视觉显示效果。
本公开实施例的一示例提供的显示装置中，通过对第一显示区和第二显示区以及第一显示区和第三显示区交界处数据线的设计，可以满足集成电路(IC)在第一显示区和第二显示区统一的算法处理。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (13)

  1. 一种显示基板，包括：
    衬底基板，包括第一显示区和第二显示区，所述第一显示区包括多个第一发光单元和多个第一子像素电路，所述多个第一发光单元包括相邻设置的第一发光单元列和第二发光单元列，各发光单元列与相应的一列第一子像素电路连接，所述第二显示区包括多个第二发光单元和多个第二子像素电路，所述多个第二发光单元包括相邻设置的第三发光单元列和第四发光单元列，所述第二显示区中的各发光单元列与一列第一子像素电路对连接，各列第一子像素电路对包括相邻两列第二子像素电路；
    沿第二方向延伸的多条第一子数据线、多条第二子数据线、多条第三子数据线以及多条第四子数据线，各第一子数据线与各第一发光单元列连接，各第二子数据线与各第二发光单元列连接，各第三子数据线与各第三发光单元列连接，各第四子数据线与各第四发光单元列连接，所述第二方向与所述第一方向相交；
    其中，所述第一发光单元列和所述第二发光单元列的排列方向与所述第三发光单元列和所述第四发光单元列的排列方向相同；
    与所述第一发光单元列连接的一列第一子像素电路和与所述第三发光单元列连接的一列第二子像素电路位于同一列，所述第一子数据线和所述第三子数据线为沿所述第二方向延伸且连续的一条数据线；
    与所述第四发光单元列连接的两列所述第二子像素电路和与所述第二发光单元列连接的一列第一子像素电路均位于不同列，所述第二子数据线与所述第四子数据线通过数据线连接部连接，且所述数据线连接部的延伸方向与所述第二方向相交。
  2. 根据权利要求1所述的显示基板，其中，与所述第二发光单元列连接的一列第一子像素电路和与所述第三发光单元列连接的另一列第二子像素电路位于同一列。
  3. 根据权利要求2所述的显示基板，其中，所述第一显示区还包括相邻设置第五发光单元列和第六发光单元列，所述第一发光单元列、所述第二发光单元列、第五发光单元列和第六发光单元列沿所述第一方向重复排列，所述第三发光单元列和所述第四发光单元列沿所述第一方向交替排列；
    所述显示基板还包括沿所述第二方向延伸的多条第五子数据线和多条第六子数据线，各第五子数据线与各第五发光单元列连接，各第六子数据线与各第六发光单元列连接；
    与所述第五发光单元列连接的一列第一子像素电路和与所述第四发光单元列连接的一列第二子像素电路位于同一列，与所述第六发光单元列连接的一列第一子像素电路和与所述第四发光单元列连接的另一列第二子像素电路位于同一列，所述第六子数据线或所述第五子数据线与所述第四子数据线之间设置有间隔。
  4. 根据权利要求3所述的显示基板，其中，所述第一显示区包括沿所述第一方向和所述第二方向交替排列的多个第一子发光单元组和多个第二子发光单元组，所述第一子发光单元组包括所述第一发光单元列和所述第二发光单元列中的发光单元，所述第二子发光单元组包括所述第五发光单元列和所述第六发光单元列中的发光单元，所述第二显示区包括多个第三子发光单元组；
    各所述子发光单元组包括一个第一颜色发光单元、一个第二颜色发光单元对以及一个第三颜色发光单元，所述第一颜色发光单元和所述第三颜色发光单元沿所述第二方向排列，所述第二颜色发光单元对包括沿所述第二方向排列的两个第二颜色发光单元，所述第一颜色发光单元和所述第二颜色发光单元对沿所述第一方向排列，且所述第一子发光单元组中所述第一颜色发光单元和所述第三颜色发光单元的排列方向与所述第二子发光单元组中所述第一颜色发光单元和所述第三颜色发光单元的排列方向相反，所述第一子发光单元组中各发光单元的相对位置分布与所述第三子发光单元组中各发光单元的相对位置分布相同。
  5. 根据权利要求4所述的显示基板，其中，所述衬底基板还包括第三显示区，所述第二显示区还包括多个第三子像素电路，所述第三显示区包括多个第三发光单元，所述多个第三发光单元包括相邻设置的第七发光单元列和第八发光单元列，所述第一发光单元列和所述第二发光单元列的排列方向与所述第七发光单元列和所述第八发光单元列的排列方向相同，所述第三显示区中的各发光单元列与一列第二子像素电路对连接，各列第二子像素电路对包括相邻两列第三子像素电路；
    所述显示基板还包括沿所述第二方向延伸的多条第七子数据线和多条第八子数据线，各第七子数据线与各第七发光单元列连接，各第八子数据线与各 第八发光单元列连接；
    所述第七子数据线和所述第八子数据线的至少之一设置在所述第三子数据线和所述第四子数据线之间。
  6. 根据权利要求5所述的显示基板，其中，所述第七子数据线和所述第八子数据线均设置在所述第三子数据线和所述第四子数据线之间，且所述第八子数据线与所述第五子数据线之间设置有间隔以设置所述子数据线连接部。
  7. 根据权利要求5或6所述的显示基板，其中，所述多个第三子像素电路被配置为分别与多个第四子发光单元组连接，各所述第四子发光单元组中各发光单元的相对位置分布与所述第三子发光单元组中各发光单元的相对位置分布相同；
    与所述第三子发光单元组连接的所述第一子像素电路对和与所述第四发光单元组连接的所述第二子像素电路对沿所述第一方向和所述第二方向交替排列。
  8. 根据权利要求5-7任一项所述的显示基板，其中，所述第三显示区包括中心区以及围绕所述中心区的边缘区，所述边缘区包括沿所述第一方向和所述第二方向排列的多个虚设像素电路以形成多个虚设像素电路列和多个虚设像素电路行。
  9. 根据权利要求8所述的显示基板，其中，所述第三显示区内的所述多个虚设像素电路列包括相邻四列组成的虚设像素电路列组，每个虚设像素电路列组包括沿所述第一方向依次排列的第一虚设像素电路列、第二虚设像素电路列、第三虚设像素电路列和第四虚设像素电路列；
    所述显示基板还包括第一虚设数据线、第二虚设数据线、第三虚设数据线和第四虚设数据线，所述第一虚设数据线与所述第一虚设像素电路列连接，所述第二虚设数据线与所述第二虚设像素电路列连接，所述第三虚设数据线与所述第三虚设像素电路列连接，且所述第四虚设数据线与所述第四虚设像素电路列连接；
    与所述第一发光单元列连接的一列第一子像素电路和所述第一虚设像素电路列位于同一列，与所述第二发光单元列连接的一列第一子像素电路和所述第二虚设像素电路列位于同一列，与所述第五发光单元列连接的一列第一子像素电路与所述第三虚设像素电路列位于同一列，与所述第六发光单元列连接的一列第一子像素电路与所述第四虚设像素电路列位于同一列；
    与所述第一发光单元组连接的两条子数据线与相应的两条虚设数据线为连续的两条子数据线，或者与所述第二发光单元组连接的两条子数据线与相应的两条虚设数据线为连续的两条数据线。
  10. 根据权利要求9所述的显示基板，其中，所述显示基板还包括位于所述第三显示区远离所述第一显示区一侧的周边区，与所述第一发光单元组或所述第二发光单元组连接的所述两条虚设数据线绕过所述中心区以在所述周边区分别连接所述第七子数据线和所述第八子数据线。
  11. 根据权利要求10所述的显示基板，其中，所述第一虚设数据线和所述第一子数据线为一条连续的数据线，所述第二虚设数据线和所述第二子数据线为一条连续的子数据线，所述第三虚设数据线和所述第五子数据线之间设置有间隔，所述第四虚设数据线和所述第六子数据线之间设置有间隔。
  12. 根据权利要求10或11所述的显示基板，其中，所述第一虚设数据线绕过所述中心区以在所述周边区连接所述第七子数据线，所述第二虚设数据线绕过所述中心区以在所述周边区连接所述第八子数据线。
  13. 一种显示装置，包括权利要求1-12任一项所述的显示基板。
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