WO2022110307A1 - 液晶显示器 - Google Patents

液晶显示器 Download PDF

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Publication number
WO2022110307A1
WO2022110307A1 PCT/CN2020/134851 CN2020134851W WO2022110307A1 WO 2022110307 A1 WO2022110307 A1 WO 2022110307A1 CN 2020134851 W CN2020134851 W CN 2020134851W WO 2022110307 A1 WO2022110307 A1 WO 2022110307A1
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WO
WIPO (PCT)
Prior art keywords
pixel
sub
scan line
line
data
Prior art date
Application number
PCT/CN2020/134851
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English (en)
French (fr)
Inventor
许森
金一坤
肖邦清
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2022110307A1 publication Critical patent/WO2022110307A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • the present invention relates to a liquid crystal display and a method for eliminating crosstalk thereof. Specifically, the present invention eliminates vertical crosstalk by connecting each sub-pixel in a pixel unit in a liquid crystal display to two data lines, and transmitting data signals with opposite polarities in the two data lines.
  • ultra-high-definition liquid crystal displays such as Super Narrow Bezel with a seam less than 5.5mm and Ultra Narrow Bezel with a seam less than 1mm (Zero Bezel) application, inject new vitality and vitality into the panel industry.
  • the gate driver is thin-film on-chip (chip On film; COF) packaging design, the drive signals of the scan line and the data line are designed on the same side, reducing the width of the left and right sides of the liquid crystal display, and achieving the effect of ultra-narrow borders.
  • each pixel is only connected to one data line, and the distance between the pixel display area and its left and right data lines is the same, and the coupling voltages of the pixel voltages are made positive and one by the opposite way of driving the data lines on the left and right sides of the pixel.
  • the interference to the pixels is balanced to solve the problem of vertical crosstalk.
  • the distance between the data line and the pixel electrode on the left and right sides of the pixel is different, resulting in parasitic capacitance between the data line and the pixel electrode.
  • the common way of opposing the data line signals on the left and right sides cannot completely cancel out the interference to the pixels.
  • the purpose of the present invention is to provide a liquid crystal display, which changes the arrangement of three sub-pixels in a pixel unit, so that each sub-pixel is connected to two data lines, and transmits data signals with opposite polarities in the two data lines , so as to improve the coupling effect of parasitic capacitance on each sub-pixel and further reduce the risk of vertical crosstalk.
  • the present invention discloses a liquid crystal display including a gate driver, a source driver and a pixel unit.
  • the gate driver is electrically connected to the first scan line and the second scan line.
  • the source driver is electrically connected to the first data line, the second data line, the third data line and the fourth data line.
  • the pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel.
  • the first sub-pixel is electrically connected to the first scan line, the first data line, and the second data line.
  • the first data signal of the first data line and the first data signal of the second data line The polarities of the two data signals are opposite.
  • the second sub-pixel is electrically connected to the second scan line, the second data line and the third data line.
  • the polarity of the second data signal of the second data line is opposite to that of the third data signal of the third data line.
  • the third sub-pixel is electrically connected to the first scan line, the third data line and the fourth data line, and the third data signal and the fourth data of the third data line The polarity of the fourth data signal of the line is reversed.
  • the first scan line includes a first vertical scan line and a first horizontal scan line.
  • the first vertical scan line is electrically connected to the gate driver for receiving a first scan signal from the gate driver.
  • the first horizontal scan line is electrically connected to the first vertical scan line for receiving the first scan signal from the first vertical scan line and providing the first scan signal to the first a sub-pixel and the third sub-pixel.
  • the first vertical scan line and the lower plate common electrode are arranged on a first metal layer, and the first horizontal scan line is arranged on a second metal layer, the first metal layer and the first metal layer are An insulating layer is arranged between the two metal layers.
  • the first horizontal scan line is electrically connected to the first vertical scan line through a first via hole of the insulating layer.
  • the second scan line includes a second vertical scan line and a second horizontal scan line.
  • the second vertical scan line is electrically connected to the gate driver for receiving a second scan signal from the gate driver.
  • the second horizontal scan line is electrically connected to the second vertical scan line for receiving the second scan signal from the second vertical scan line and providing the second scan signal to the second subpixel.
  • the second vertical scan line and the lower plate common electrode are disposed on the first metal layer, and the second horizontal scan line is disposed on the second metal layer, the first metal layer and the first metal layer are An insulating layer is arranged between the two metal layers.
  • the second horizontal scan line is electrically connected to the second vertical scan line through a second via hole of the insulating layer.
  • the first sub-pixel, the second sub-pixel and the third sub-pixel correspond to red, blue and green, respectively.
  • the first aperture ratio of the first subpixel, the second aperture ratio of the second subpixel, and the third aperture ratio of the third subpixel are the same.
  • a first parasitic capacitance and a second parasitic capacitance exist in the first sub-pixel
  • a third parasitic capacitance and a fourth parasitic capacitance exist in the second sub-pixel
  • the third sub-pixel There is a fifth parasitic capacitance and a sixth parasitic capacitance.
  • the present invention changes the arrangement between the sub-pixels in the pixel unit, makes each sub-pixel connect to two data lines, and transmits opposite signals in the two data lines connected to each sub-pixel, In order to reduce the coupling effect of parasitic capacitance on each sub-pixel.
  • FIG. 1 depicts a schematic diagram of a liquid crystal display of the present invention.
  • FIG. 2 depicts a schematic diagram of an equivalent circuit of the pixel unit of the present invention.
  • FIG. 3 is a schematic diagram of the layout of the pixel unit of the present invention.
  • FIG. 4 depicts a cross-sectional view of a first horizontal scan line.
  • FIG. 5 depicts a cross-sectional view of a second horizontal scan line.
  • FIG. 6 is a clock diagram of the traced signal of the present invention.
  • FIG. 7 depicts a schematic diagram of the arrangement of sub-pixels in the pixel unit of the present invention.
  • FIG. 8 depicts a schematic diagram of the arrangement of sub-pixels in the pixel unit of the present invention.
  • FIG. 9 is a clock diagram of a data signal of the present invention.
  • FIG. 10 is a clock diagram of the data signal of the present invention.
  • FIG. 1 depicts a schematic diagram of a liquid crystal display of the present invention.
  • the liquid crystal display 1 includes a gate driver 2 , a source driver 3 and a pixel unit PXU.
  • the gate driver 1 is electrically connected to the first scan line and the second scan line.
  • the source driver 2 is electrically connected to the first data line D1 , the second data line D2 , the third data line D3 and the fourth data line D4 .
  • the pixel unit PXU includes a first sub-pixel PX1, a second sub-pixel PX2 and a third sub-pixel PX3, which correspond to different colors respectively.
  • the first sub-pixel PX1 is red
  • the second sub-pixel PX2 is blue
  • the third sub-pixel PX3 is green.
  • the colors corresponding to the first sub-pixel PX1 , the second sub-pixel PX2 and the third sub-pixel PX3 are interchangeable.
  • the first sub-pixel PX1 can also be blue or green
  • the second sub-pixel PX2 can also be green or red
  • the third sub-pixel PX3 can also be red or blue.
  • each scan line includes a vertical scan line and a Horizontal scan lines.
  • Each vertical scan line is electrically connected to the gate driver 2 for receiving the scan signal from the gate driver 2, and then transmits the scan signal to the corresponding horizontal scan line, and then the horizontal scan line transmits the scan signal to the connected sub-pixels to turn on the thin film transistors in the sub-pixels.
  • FIG. 2 depicts a schematic diagram of an equivalent circuit of the pixel unit of the present invention.
  • FIG. 3 is a schematic diagram of the layout of the pixel unit of the present invention.
  • the vertical scan lines for example: the first vertical scan line VG1, the second vertical scan line VG2, the third vertical scan line VG3 and the n-th vertical scan line VGn shown in FIG. 1
  • horizontal scan lines for example, the first horizontal scan line HG1, the second horizontal scan line HG2, the third horizontal scan line HG3, and the nth horizontal scan line HGn shown in FIG.
  • An insulating layer is disposed between the second metal layer M2 , the first metal layer M1 and the second metal layer M2 , and the preparation sequence of the two layers of metal can be interchanged.
  • the horizontal scan lines can be fabricated on the first metal layer, and the vertical scan lines can be fabricated on the second metal layer.
  • the vertical scan line transmits signals to the horizontal scan line electrically connected to it through the via hole
  • the lower plate common electrode CE is used as a bridge metal through the second layer
  • the lower plate common electrode CE forms a mesh structure in the panel display area, which improves the common Electrode CE signal stability.
  • the data line is the third layer of metal.
  • One pixel unit PXU includes a total of four data lines, of which two data lines pass through the display area of each sub-pixel, and the other two data lines pass through the non-display area of the pixel.
  • the first scan line includes a first vertical scan line VG1 and a first horizontal scan line HG1.
  • the first vertical scan line VG1 passes through the non-display area on the left side of the first sub-pixel PX1 and is electrically connected to the gate driver 2 for receiving the first scan signal from the gate driver 2 .
  • the first horizontal scan line HG1 is electrically connected to the first vertical scan line VG1 through the first via hole 11 for receiving the first scan signal from the first vertical scan line VG1 and providing the first scan signal to the first sub-pixel PX1 and the third subpixel PX3 to turn on the thin film transistor T1 in the first subpixel PX1 and the thin film transistor T3 in the third subpixel PX3.
  • FIG. 4 depicts a cross-sectional view of the first horizontal scan line. From the bottom, the glass substrate GLS, the first metal layer M1, the first insulating layer IL1, the second metal layer M2, the second insulating layer IL2, the third metal layer M3, the third insulating layer IL3, the first color resist CF1, the third color resist CF3, the fourth insulating layer IL4 and the conductive film CL. It can be seen from FIG. 4 that the first vertical scan line VG1, the second vertical scan line VG2, the third vertical scan line VG3 and the lower plate common electrode CE located between the adjacent vertical scan lines are all disposed on the first metal. Layer M1.
  • the second metal layer M2 After covering the first insulating layer IL1 on the first metal layer M1, the second metal layer M2 is formed.
  • the second metal layer M2 is the first horizontal scan line HG1, and then the second insulating layer IL2 is covered on the second metal layer M2, and then the third metal layer M3 is formed.
  • the third metal layer M3 includes a first data line D1, a second data line D2, a third data line D3 and a fourth data line D4.
  • a first color resist CF1 corresponding to the color of the first sub-pixel PX1 and a third color resist CF3 corresponding to the color of the third sub-pixel PX3 are formed.
  • the conductive film CL is then covered.
  • the conductive film CL is disposed on the same layer as the pixel electrode, and can be used to shield the electric field signal of the horizontal scanning line.
  • the second scan line includes a second vertical scan line VG2 and a second horizontal scan line HG2.
  • the second vertical scan line VG2 passes between the first sub-pixel PX1 and the third sub-pixel PX3 and is electrically connected to the gate driver 2 for receiving the second scan signal from the gate driver 2 .
  • the second vertical scan line VG2 also passes through the middle of the second sub-pixel PX2 to divide the second sub-pixel PX2 into left and right display areas, and the size and ratio of the left and right display areas of the second sub-pixel PX2 are the same.
  • the second horizontal scan line HG2 is electrically connected to the second vertical scan line VG2 through the second via hole 22 for receiving the second scan signal from the second vertical scan line VG2 and providing the second scan signal to the second sub-pixel PX2 , to turn on the thin film transistor T2 in the second sub-pixel PX2.
  • FIG. 5 depicts a cross-sectional view of the second horizontal scan line.
  • the difference from the cross-sectional view of the first horizontal scanning line HG1 is that after the third insulating layer IL3 is covered on the third metal layer M3, a second color resist CF2 corresponding to the color of the second sub-pixel PX2 is fabricated, and is After the second color resist CF2 is covered with the fourth insulating layer IL4, it is then covered with the conductive film CL.
  • the conductive film CL is disposed on the same layer as the pixel electrode, and can be used to shield the electric field signal of the horizontal scanning line.
  • the third scan line includes a third vertical scan line VG3 and a third horizontal scan line HG3.
  • the third vertical scan line VG3 is electrically connected to the gate driver 2 for receiving a third scan signal from the gate driver 2 .
  • the third horizontal scan line HG3 is electrically connected to the third vertical scan line VG3 through the third via hole 33 for receiving the third scan signal from the third vertical scan line VG3.
  • the clock diagram of the first vertical scan line VG1, the first horizontal scan line HG1, the second vertical scan line VG2, the second horizontal scan line HG2, the third vertical scan line VG3 and the third horizontal scan line HG3 is shown in FIG. 6 .
  • the first horizontal scan line HG1 is electrically connected to the first vertical scan line VG1 through the first via 11
  • the clock HGCLK1 of the first horizontal scan line HG1 is synchronized with the clock VGCLK1 of the first vertical scan line VG1.
  • the second horizontal scan line HG2 is electrically connected to the second vertical scan line VG2 through the second via hole 22
  • the clock HGCLK2 of the second horizontal scan line HG2 is synchronized with the clock VGCLK2 of the second vertical scan line VG2.
  • the third horizontal scan line HG3 is electrically connected to the third vertical scan line VG3 through the third via 33
  • the clock HGCLK3 of the third horizontal scan line HG3 is synchronized with the clock VGCLK3 of the third vertical scan line
  • the first sub-pixel PX1 is further connected to the first data line D1 and the second data line D2.
  • the second sub-pixel PX2 is further connected to the second data line D2 and the third data line D3.
  • the third sub-pixel PX3 is further connected to the third data line D3 and the fourth data line D4. Therefore, in the pixel unit PXU, the arrangement of the first sub-pixel PX1 , the second sub-pixel PX2 and the third sub-pixel PX3 can be as shown in FIG. 7 .
  • the positions of the first sub-pixels PX1 and the second sub-pixels PX2 and the positions of the third sub-pixels PX3 can also be aligned up and down to form an arrangement as shown in FIG. 8 .
  • the first aperture ratio of the first sub-pixel PX1 and the second aperture ratio of the second sub-pixel PX2 and the third aperture ratio of the third sub-pixel PX3 is the same.
  • the second sub-pixel PX2 is divided into left and right display areas by the second vertical scanning line VG2, and the ratio of the left and right display areas is usually 1:1.
  • the aperture ratio of the second sub-pixel PX2 is mainly affected by the size of the total display area. Therefore, in the case where the total display area of the second sub-pixel PX2 is the same as that of the first sub-pixel PX1 and the third sub-pixel PX3, the second aperture ratio of the second sub-pixel PX2 is the same as that of the first sub-pixel PX1.
  • the aperture ratio and the third aperture ratio of the third sub-pixel PX3 are the same.
  • the first sub-pixel PX1 at least includes a thin film transistor T1 , a liquid crystal capacitor C LC1 , a storage capacitor C ST1 , and has a first parasitic capacitor C P1D1 and a second parasitic capacitor C P1D2 .
  • the second sub-pixel PX2 at least includes a thin film transistor T2, a liquid crystal capacitor C LC2 , a storage capacitor C ST2 , and has a third parasitic capacitor C P2D2 and a fourth parasitic capacitor C P2D3 .
  • the third sub-pixel PX3 at least includes a thin film transistor T3, a liquid crystal capacitor C LC3 , a storage capacitor C ST3 , and has a fifth parasitic capacitor C P3D3 and a sixth parasitic capacitor C P3D4 .
  • a parasitic capacitance C VG1D1 exists between the first data line D1 and the first vertical scan line VG1 .
  • the parasitic capacitance C VG2D3 exists between the second data line D3 and the second vertical scan line VG2.
  • the parasitic capacitance C VG3D4 exists between the fourth data line D4 and the third vertical scan line VG3.
  • the first parasitic capacitance C P1D1 exists between the first data line D1 and the first sub-pixel PX1
  • the second parasitic capacitance C P1D2 exists between the second data line D2 and the first sub-pixel PX1, so the first data line Changes of the first data signal transmitted by D1 and the second data signal transmitted by the second data line D2 may interfere with the stability of the signal of the first sub-pixel PX1, resulting in vertical crosstalk.
  • the third parasitic capacitance C P2D2 exists between the second data line D2 and the second sub-pixel PX2, and the fourth parasitic capacitance C P2D3 exists between the third data line D3 and the second sub-pixel PX2, so the second data line Changes of the second data signal transmitted by D2 and the third data signal transmitted by the third data line D3 may interfere with the stability of the signal of the second sub-pixel PX2, resulting in vertical crosstalk.
  • the fifth parasitic capacitance C P3D3 exists between the third data line D3 and the third sub-pixel PX3, and the sixth parasitic capacitance C P3D4 exists between the fourth data line D4 and the third sub-pixel PX3, so the third data line
  • the variation of the third data signal transmitted by D3 and the fourth data signal transmitted by the fourth data line D4 may interfere with the stability of the signal of the third sub-pixel PX3, resulting in vertical crosstalk.
  • the polarities of the first data signal transmitted on the first data line D1 and the second data signal transmitted on the second data line D2 in the present invention are opposite, and the second data signal transmitted on the second data line D2
  • the polarity of the third data signal transmitted on the third data line D3 is opposite to that of the third data signal transmitted on the third data line D3 and the polarity of the fourth data signal transmitted on the fourth data line D4 is opposite.
  • the polarities of the clock DCLK1 of the first data signal and the clock DCLK2 of the second data signal are opposite, representing the clock DCLK1 of the first data signal and the clock of the second data signal.
  • the phase and polarity of pulse DCLK2 are opposite.
  • the clock DCLK1 of the first data signal is of positive polarity
  • the clock DCLK2 of the second data signal is of negative polarity
  • the clock DCLK1 of the first data signal is of negative polarity
  • the clock DCLK2 of the second data signal is positive polarity.
  • the clock DCLK2 of the second data signal and the clock DCLK3 of the third data signal have opposite polarities, and the clock DCLK2 of the second data signal and the clock DCLK3 of the third data signal have opposite phases and polarities.
  • the clock DCLK2 of the second data signal is of positive polarity
  • the clock DCLK3 of the third data signal is of negative polarity
  • the clock DCLK3 of the third data signal is positive polarity.
  • the clock DCLK3 of the third data signal and the clock DCLK4 of the fourth data signal have opposite polarities, and the clock DCLK3 of the third data signal and the clock DCLK4 of the fourth data signal have opposite phases and polarities.
  • the clock DCLK3 of the third data signal is of positive polarity
  • the clock DCLK4 of the fourth data signal is of negative polarity
  • the clock DCLK4 of the fourth data signal is positive polarity.
  • the reference voltage for flipping the liquid crystal molecules in the liquid crystal capacitor C LC1 , the liquid crystal capacitor C LC2 , and the liquid crystal capacitor C LC3 is 7 volts (Volt; V), higher than 7V is positive, and lower than 7V is negative.
  • the clock DCLK1 of the first data signal is 14V
  • the clock DCLK2 of the second data signal is 0V
  • the clock DCLK3 of the third data signal is 14V.
  • the clock DCLK4 of the fourth data signal is 0V.
  • the clock diagram shown in FIG. 9 is in the form of dot inversion with opposite polarity.
  • the clock diagram shown in FIG. 10 is in the form of column inversion, the polarity is reversed, and the positive and negative polarity of the signal changes in units of one frame.
  • the problem of vertical crosstalk caused by the parasitic capacitance existing between the sub-pixel and the data line can be eliminated only by transmitting data signals with opposite polarities between the two data lines connected to the same sub-pixel, and the The data signal can be transmitted in dot inversion form, or only in sharp inversion form. In other words, as long as two data lines connected to the same sub-pixel transmit data signals with opposite polarities, they all belong to the scope of the present invention.
  • parasitic capacitance C VG1P1 there is a parasitic capacitance C VG1P1 between the first sub-pixel PX1 and the first vertical scanning line VG1 , and the parasitic capacitance C VG1P1 also affects the stability of the signal of the first sub-pixel PX1, and the second sub-pixel PX2 and the second vertical scanning
  • parasitic capacitance C VG2P2 between the lines VG2
  • the parasitic capacitance C VG2P2 also affects the stability of the signal of the second sub-pixel PX2
  • parasitic capacitance C VG3P3 between the third sub-pixel PX3 and the third vertical scanning line VG3
  • the parasitic capacitance C VG3P3 also affects the stability of the signal of the third sub-pixel PX3. Since the problem of vertical crosstalk is mainly caused by the signal change of the data line, the present invention mainly adjusts the signal change of the data line to offset the coupling effect on each sub-pixel and reduce the risk of vertical cross
  • the first sub-pixel PX1, the second sub-pixel PX2 and the third sub-pixel PX3 further include other parasitic capacitances, such as the parasitic capacitance between the gate and the source of the thin film transistor and the gate The parasitic capacitance between the pole and the drain, because these parasitic capacitances are compared with the aforementioned first parasitic capacitance C P1D1 , second parasitic capacitance C P1D2 , third parasitic capacitance C P2D2 , fourth parasitic capacitance C P2D3 , and fifth parasitic capacitance C P3D3 and the sixth parasitic capacitance C P3D4 have little influence on the signal stability of the first sub-pixel PX1 , the second sub-pixel PX2 and the third sub-pixel PX3 , so the present invention does not specifically aim to have little influence on each sub-pixel of parasitic capacitance.
  • the present invention changes the arrangement between the sub-pixels in the pixel unit, makes each sub-pixel connect to two data lines, and transmits opposite signals in the two data lines connected to each sub-pixel, In order to reduce the coupling effect of parasitic capacitance on each sub-pixel.

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Abstract

一种液晶显示器（1），包括栅极驱动器（2）、源极驱动器（3）以及像素单元（PXU）。像素单元（PXU）包括第一子像素（PX1）、第二子像素（PX2）以及第三子像素（PX3）。栅极驱动器（2）电性连接至第一扫描线及第二扫描线。源极驱动器（3）电性连接至第一数据线（D1）、第二数据线（D2）、第三数据线（D3）以及第四数据线（D4）。第一子像素（PX1）电性连接至第一扫描线、第一数据线（D1）及第二数据线（D2）。第一数据线（D1）的第一数据信号与第二数据线（D2）的第二数据信号的极性相反。第二子像素（PX2）电性连接至第二扫描线、第二数据线（D2）及第三数据线（D3）。第二数据线（D2）的第二数据信号与第三数据线（D3）的第三数据信号的极性相反。第三子像素（PX3）电性连接至第一扫描线、第三数据线（D3）及第四数据线（D4）。第三数据线（D3）的第三数据信号与第四数据线（D4）的第四数据信号的极性相反。

Description

液晶显示器 技术领域
本发明是关于一种液晶显示器及其串扰消除方法。具体而言，本发明通过将液晶显示器中像素单元内的各子像素连接至两条数据线，并在两条数据线中传送极性相反的数据信号，以消除垂直串扰。
 背景技术
随着现在面板产品逐渐往窄边框化以及高分辨率的方向发展，拼缝小于5.5mm的超窄边框（Super Narrow Bezel）以及拼缝小于1mm的超窄边框（Zero Bezel）等超高清液晶显示器的应用，为面板行业注入新的活力和生机。采用将栅极驱动器以薄膜覆晶（chip on film；COF）封装方式的设计，将扫描线和数据线的驱动信号设计在同一侧，减小液晶显示器左右两边的宽度，实现超窄边框的效果。
然而，由于数据线与像素之间存在寄生电容，数据线信号变化会干扰像素信号的稳定性，随着超窄边框设计的分辨率增加，像素尺寸减小，数据线与像素之间的寄生电容对像素的耦合效应更加明显，使面板产生垂直串扰，影响面板的产品质量。
在传统的像素设计中，每一像素仅连接至一条数据线，且像素显示区与其左右两边数据线距离相同，通过像素左右两侧数据线驱动信号相反的方式使像素电压的耦合电压一正一反，平衡对像素的干扰，来解决垂直串扰的问题。
但是在栅极驱动器以薄膜覆晶封装方式的设计中，由于像素内存在扫描线垂直方向的走线，使得像素左右两侧数据线与像素电极的距离不同，导致数据线与像素电极的寄生电容也存在差异，采用普通的左右两侧数据线信号相反的方式不能完全抵消对像素的干扰。
有鉴于此，本领域亟需一种串扰消除机制，以解决栅极驱动器以薄膜覆晶封装方式的设计中，寄生电容对象素产生垂直串扰的问题。
 技术问题
本发明的目的在于提供一种液晶显示器，其通过改变像素单元内三个子像素的排列方式，使每个子像素皆连接至两条数据线，并在两条数据线中传送极性相反的数据信号，以改善寄生电容对各子像素的耦合效应，并进一步降低垂直串扰的风险。
 技术解决方案
为达上述目的，本发明揭露一种液晶显示器，其包括栅极驱动器、源极驱动器以及像素单元。所述栅极驱动器电性连接至第一扫描线及第二扫描线。所述源极驱动器电性连接至第一数据线、第二数据线、第三数据线以及第四数据线。所述像素单元包括第一子像素、第二子像素以及第三子像素。所述第一子像素电性连接至所述第一扫描线、所述第一数据线以及所述第二数据线所述第一数据线的第一数据信号与所述第二数据线的第二数据信号的极性相反。所述第二子像素电性连接至所述第二扫描线、所述第二数据线以及所述第三数据线。所述第二数据线的所述第二数据信号与所述第三数据线的第三数据信号的极性相反。所述第三子像素电性连接至所述第一扫描线、所述第三数据线以及所述第四数据线，所述第三数据线的所述第三数据信号与所述第四数据线的第四数据信号的极性相反。
于一实施例中，所述第一扫描线包括第一垂直扫描线以及第一水平扫描线。所述第一垂直扫描线电性连接至所述栅极驱动器，用以自所述栅极驱动器接收第一扫描信号。所述第一水平扫描线电性连接至所述第一垂直扫描线，用以自所述第一垂直扫描线接收所述第一扫描信号，并提供所述第一扫描信号至所述第一子像素及所述第三子像素。
于一实施例中，所述第一垂直扫描线与下板共电极设置于第一金属层，以及所述第一水平扫描线设置于第二金属层，所述第一金属层及所述第二金属层之间设置绝缘层。
于一实施例中，所述第一水平扫描线穿过所述绝缘层的第一过孔电性连接至所述第一垂直扫描线。
于一实施例中，所述第二扫描线包括第二垂直扫描线以及第二水平扫描线。所述第二垂直扫描线电性连接至所述栅极驱动器，用以自所述栅极驱动器接收第二扫描信号。所述第二水平扫描线电性连接至所述第二垂直扫描线，用以自所述第二垂直扫描线接收所述第二扫描信号，并提供所述第二扫描信号至所述第二子像素。
于一实施例中，所述第二垂直扫描线与下板共电极设置于第一金属层，以及所述第二水平扫描线设置于第二金属层，所述第一金属层及所述第二金属层之间设置绝缘层。
于一实施例中，所述第二水平扫描线穿过所述绝缘层的过第二过孔电性连接至所述第二垂直扫描线。
于一实施例中，所述第一子像素、所述第二子像素以及所述第三子像素分别对应至红色、蓝色以及绿色。
于一实施例中，所述第一子像素的第一开口率、所述第二子像素的第二开口率以及所述第三子像素的第三开口率相同。
于一实施例中，所述第一子像素中存在第一寄生电容以及第二寄生电容，所述第二子像素中存在第三寄生电容以及第四寄生电容，以及所述第三子像素中存在第五寄生电容以及第六寄生电容。
 有益效果
相较于现有技术，本发明通过改变像素单元内子像素之间的排列方式，并使每个子像素连接到两条数据线，通过在每个子像素连接的两条数据线中传送相反的信号，以减低寄生电容对各子像素的耦合效应。
为让本发明的上述内容能更明显易懂，下文特举较佳实施例，并配合所附图式，作详细说明如下：
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1描绘本发明液晶显示器的示意图。
图2描绘本发明像素单元的等效电路示意图。
图3是本发明像素单元的布局示意图。
图4描绘第一水平扫描线的截面图。
图5描绘第二水平扫描线的截面图。
图6为本发明描线信号的时脉图。
图7描绘本发明像素单元中子像素排列的示意图。
图8描绘本发明像素单元中子像素排列的示意图。
图9为本发明数据信号的时脉图。
图10为本发明数据信号的时脉图。
 本发明的实施方式
以下将透过实施例来解释本发明内容，本发明的实施例并非用以限制本发明须在如实施例所述的任何特定的环境、应用或特殊方式方能实施。因此，关于实施例的说明仅为阐释本发明的目的，而非用以限制本发明。需说明者，以下实施例及附图中，与本发明非直接相关的元件已省略而未绘示，且附图中各元件间的尺寸关系仅为求容易了解，并非用以限制实际比例。
请参考图1-10。图1描绘本发明液晶显示器的示意图。液晶显示器1包括栅极驱动器2、源极驱动器3以及像素单元PXU。栅极驱动器1电性连接至第一扫描线及第二扫描线。源极驱动器2电性连接至第一数据线D1、第二数据线D2、第三数据线D3以及第四数据线D4。
像素单元PXU包括第一子像素PX1、第二子像素PX2以及第三子像素PX3，其分别对应至不同色彩。举例而言，第一子像素PX1为红色、第二子像素PX2为蓝色以及第三子像素PX3为绿色。需说明者，于本发明的子像素排列结构中，第一子像素PX1、第二子像素PX2以及第三子像素PX3对应的色彩可互换。换言之，第一子像素PX1亦可为蓝色或绿色，第二子像素PX2亦可为绿色或红色，以及第三子像素PX3亦可为红色或蓝色。
于本发明中，栅极驱动器2以及源极驱动器3是以薄膜覆晶（chip on film；COF）的方式封装，因此在液晶显示器1的走线中，每一条扫描线皆包括垂直扫描线及水平扫描线。各垂直扫描线接电性连接至栅极驱动器2，用以自栅极驱动器2接收扫描信号，再将扫描信号传送至对应的水平扫描线，再由水平扫描线将扫描信号传送至与其连接的子像素，以导通子像素内的薄膜晶体管。
请同时参考图2至图5，图2描绘本发明像素单元的等效电路示意图。图3是本发明像素单元的布局示意图。在制备过程中，垂直扫描线（例如：图1所示的第一垂直扫描线VG1、第二垂直扫描线VG2、第三垂直扫描线VG3以及第n条垂直扫描线VGn）与下板共电极CE设置于第一金属层M1，水平扫描线（例如：图1所示的第一水平扫描线HG1、第二水平扫描线HG2、第三水平扫描线HG3以及第n条水平扫描线HGn）设置于第二金属层M2，第一金属层M1及第二金属层M2之间设置绝缘层，且两层金属制备先后顺序可互换。换言之，于制备过程中，可将水平扫描线制作在第一金属层，以及将垂直扫描线制作在第二金属层。
垂直扫描线通过过孔将信号传输给与其电性连接的水平扫描线，下板共电极CE通过第二层做桥接金属，在面板显示区下板共电极CE形成网状结构，提升下板共电极CE信号的稳定性。数据线为第三层金属。一个像素单元PXU共包括四条数据线，其中每个子像素显示区内经过两条数据线，另外两条数据线从像素非显示区经过。
具体而言，第一扫描线包括第一垂直扫描线VG1以及第一水平扫描线HG1。第一垂直扫描线VG1从第一子像素PX1左侧的非显示区通过，且电性连接至栅极驱动器2，用以自栅极驱动器2接收第一扫描信号。第一水平扫描线HG1通过第一过孔11电性连接至第一垂直扫描线VG1，用以自第一垂直扫描线VG1接收第一扫描信号，并提供第一扫描信号至第一子像素PX1及第三子像素PX3，以导通第一子像素PX1中的薄膜晶体管T1以及第三子像素PX3中的薄膜晶体管T3。
请参考图4，其描绘第一水平扫描线的截面图。由底部开始依序为玻璃基板GLS、第一金属层M1、第一绝缘层IL1、第二金属层M2、第二绝缘层IL2、第三金属层M3、第三绝缘层IL3、第一色阻CF1、第三色阻CF3、第四绝缘层IL4以及导电膜CL。由图4中可看出，第一垂直扫描线VG1、第二垂直扫描线VG2、第三垂直扫描线VG3以及位于相邻的垂直扫描线之间的下板共电极CE皆设置在第一金属层M1。
于第一金属层M1上覆盖第一绝缘层IL1后再制作第二金属层M2。第二金属层M2为第一水平扫描线HG1，接着于第二金属层M2上覆盖第二绝缘层IL2后再制作第三金属层M3。第三金属层M3包括第一数据线D1、第二数据线D2、第三数据线D3以及第四数据线D4。接着，于第三金属层M3上覆盖第三绝缘层IL3后再制作对应第一子像素PX1的颜色的第一色阻CF1以及对应第三子像素PX3的颜色的第三色阻CF3，并在第一色阻CF1及第三色阻CF3上覆盖第四绝缘层IL4后，再覆盖导电膜CL。导电膜CL与像素电极设置于同一层，可用于屏蔽水平扫描线的电场信号。
第二扫描线包括第二垂直扫描线VG2以及第二水平扫描线HG2。第二垂直扫描线VG2从第一子像素PX1与第三子像素PX3中间通过，且电性连接至栅极驱动器2，用以自栅极驱动器2接收第二扫描信号。此外，第二垂直扫描线VG2还从第二子像素PX2中间通过，将第二子像素PX2分为左右两个显示区，且第二子像素PX2左右两个显示区的大小及比例皆相同。第二水平扫描线HG2通过第二过孔22电性连接至第二垂直扫描线VG2，用以自第二垂直扫描线VG2接收第二扫描信号，并提供第二扫描信号至第二子像素PX2，以导通第二子像素PX2中的薄膜晶体管T2。
请参考图5，其描绘第二水平扫描线的截面图。与第一水平扫描线HG1的截面图不同之处在于，在第三金属层M3上覆盖第三绝缘层IL3后，制作的是对应第二子像素PX2的颜色的第二色阻CF2，并在第二色阻CF2上覆盖第四绝缘层IL4后，再覆盖导电膜CL。导电膜CL与像素电极设置于同一层，可用于屏蔽水平扫描线的电场信号。
第三扫描线包括第三垂直扫描线VG3以及第三水平扫描线HG3。第三垂直扫描线VG3电性连接至栅极驱动器2，用以自栅极驱动器2接收第三扫描信号。第三水平扫描线HG3通过第三过孔33电性连接至第三垂直扫描线VG3，用以自第三垂直扫描线VG3接收第三扫描信号。
第一垂直扫描线VG1、第一水平扫描线HG1、第二垂直扫描线VG2、第二水平扫描线HG2、第三垂直扫描线VG3以及第三水平扫描线HG3的时脉图如图6所示。由于第一水平扫描线HG1通过第一过孔11电性连接至第一垂直扫描线VG1，因此第一水平扫描线HG1的时脉HGCLK1与第一垂直扫描线VG1的时脉VGCLK1同步。由于第二水平扫描线HG2通过第二过孔22电性连接至第二垂直扫描线VG2，因此第二水平扫描线HG2的时脉HGCLK2与第二垂直扫描线VG2的时脉VGCLK2同步。由于第三水平扫描线HG3通过第三过孔33电性连接至第三垂直扫描线VG3，因此第三水平扫描线HG3的时脉HGCLK3与第三垂直扫描线VG3的时脉VGCLK3同步。
第一子像素PX1除了电性连接至第一水平扫描线HG1以外，更连接至第一数据线D1以及第二数据线D2。第二子像素PX2除了电性连接至第二水平扫描线HG2以外，更连接至第二数据线D2以及第三数据线D3。第三子像素PX3除了电性连接至第一水平扫描线HG1以外，更连接至第三数据线D3以及第四数据线D4。因此，于像素单元PXU中，第一子像素PX1、第二子像素PX2以及第三子像素PX3的排列方式可如图7所示。
于其他实施例中，亦可将第一子像素PX1及第二子像素PX2的位置与第三子像素PX3的位置上下对掉，形成如图8所示的排列方式。不论第一子像素PX1、第二子像素PX2以及第三子像素PX3是以图7或图8的结构排列，第一子像素PX1的第一开口率、第二子像素PX2的第二开口率以及第三子像素PX3的第三开口率皆相同。
此外，第二子像素PX2被第二垂直扫描线VG2分为左右两个显示区，其左右两个显示区比例通常为1:1，然而第二子像素PX2的开口率主要受总显示区大小的影响，因此在第二子像素PX2的总显示区与第一子像素PX1及第三子像素PX3相同的情况下，第二子像素PX2的第二开口率与第一子像素PX1的第一开口率以及第三子像素PX3的第三开口率相同。
于图2中可看出，第一子像素PX1中至少包括薄膜晶体管T1、液晶电容C LC1、存储电容C ST1，且存在第一寄生电容C P1D1以及第二寄生电容C P1D2。第二子像素PX2中至少包括薄膜晶体管T2、液晶电容C LC2、存储电容C ST2，且存在第三寄生电容C P2D2以及第四寄生电容C P2D3。第三子像素PX3中至少包括薄膜晶体管T3、液晶电容C LC3、存储电容C ST3，且存在第五寄生电容C P3D3以及第六寄生电容C P3D4。此外，寄生电容C VG1D1存在于第一数据线D1和第一垂直扫描线VG1之间。寄生电容C VG2D3存在于第二数据线D3和第二垂直扫描线VG2之间。寄生电容C VG3D4存在于第四数据线D4和第三垂直扫描线VG3之间。
第一寄生电容C P1D1存在于第一数据线D1与第一子像素PX1之间，以及第二寄生电容C P1D2存在于第二数据线D2与第一子像素PX1之间，因此第一数据线D1传送的第一数据信号及第二数据线D2传送的第二数据信号变化会干扰第一子像素PX1信号的稳定性，产生垂直串扰。
第三寄生电容C P2D2存在于第二数据线D2与第二子像素PX2之间，以及第四寄生电容C P2D3存在于第三数据线D3与第二子像素PX2之间，因此第二数据线D2传送的第二数据信号及第三数据线D3传送的第三数据信号变化会干扰第二子像素PX2信号的稳定性，产生垂直串扰。
第五寄生电容C P3D3存在于第三数据线D3与第三子像素PX3之间，以及第六寄生电容C P3D4存在于第四数据线D4与第三子像素PX3之间，因此第三数据线D3传送的第三数据信号极第四数据线D4传送的第四数据信号变化会干扰第三子像素PX3信号的稳定性，产生垂直串扰。
为了解决垂直串扰的问题，本发明于第一数据线D1传送的第一数据信号与第二数据线D2传送的第二数据信号的极性相反，于第二数据线D2传送的第二数据信号与第三数据线D3传送的第三数据信号的极性相反，以及于第三数据线D3传送的第三数据信号与第四数据线D4传送的第四数据信号的极性相反。
详言之，请参考图9及图10，第一数据信号的时脉DCLK1与第二数据信号的时脉DCLK2的极性相反，代表第一数据信号的时脉DCLK1与第二数据信号的时脉DCLK2相位及极性皆相反。当第一数据信号的时脉DCLK1为正极性时，第二数据信号的时脉DCLK2为负极性，以及当第一数据信号的时脉DCLK1为负极性时，第二数据信号的时脉DCLK2为正极性。
第二数据信号的时脉DCLK2与第三数据信号的时脉DCLK3的极性相反，代表第二数据信号的时脉DCLK2与第三数据信号的时脉DCLK3相位及极性皆相反。当第二数据信号的时脉DCLK2为正极性时，第三数据信号的时脉DCLK3为负极性，以及当第二数据信号的时脉DCLK2为负极性时，第三数据信号的时脉DCLK3为正极性。
第三数据信号的时脉DCLK3与第四数据信号的时脉DCLK4的极性相反，代表第三数据信号的时脉DCLK3与第四数据信号的时脉DCLK4相位及极性皆相反。当第三数据信号的时脉DCLK3为正极性时，第四数据信号的时脉DCLK4为负极性，以及当第三数据信号的时脉DCLK3为负极性时，第四数据信号的时脉DCLK4为正极性。
举例而言，假设使液晶电容C LC1、液晶电容C LC2以及液晶电容C LC3内液晶分子翻转的参考电压为7伏特（Volt；V），高于7V为正极性，低于7V为负极性。当第一数据信号的时脉DCLK1为14V时，第二数据信号的时脉DCLK2为0V。当第二数据信号的时脉DCLK2为0V时，第三数据信号的时脉DCLK3为14V。当第三数据信号的时脉DCLK3为14V时，第四数据信号的时脉DCLK4为0V。
图9所示之时脉图为点反转形式的极性相反。图10所示之时脉图为列反转形式的极性相反，信号的正负极性以一帧为单位产生变化。于本发明中，仅需于同一个子像素所连接的两条数据线传送极性相反的数据信号，即可消除子像素与数据线间所存在的寄生电容造成垂直串扰的问题，并不限制仅能以点反转形式传送数据信号，或仅能以烈反转形式传送数据信号。换言之，只要于同一个子像素所连接的两条数据线传送极性相反的数据信号皆属于本发明的范畴。
此外，第一子像素PX1与第一垂直扫描线VG1之间还存在寄生电容C VG1P1，寄生电容C VG1P1也会影响第一子像素PX1信号的稳定性，第二子像素PX2与第二垂直扫描线VG2之间还存在寄生电容C VG2P2，寄生电容C VG2P2也会影响第二子像素PX2信号的稳定性，以及第三子像素PX3与第三垂直扫描线VG3之间还存在寄生电容C VG3P3，寄生电容C VG3P3也会影响第三子像素PX3信号的稳定性。由于主要是因为数据线信号变化造成垂直串扰的问题，因此于本发明中主要针对数据线的信号变化作调整，来抵消对各子像素的耦合效应，降低垂直串扰的风险。
需说明者，本领域技术人员可了解第一子像素PX1、第二子像素PX2以及第三子像素PX3中更包括其他寄生电容，例如：薄膜晶体管内部栅极与源极间的寄生电容以及栅极与漏极间的寄生电容，由于该些寄生电容相较于前述第一寄生电容C P1D1、第二寄生电容C P1D2、第三寄生电容C P2D2、第四寄生电容C P2D3、第五寄生电容C P3D3以及第六寄生电容C P3D4对第一子像素PX1、第二子像素PX2以及第三子像素PX3信号稳定性的影响较小，故于本发明中不特别针对对各个子像素影响较小的寄生电容作说明。
工业实用性
相较于现有技术，本发明通过改变像素单元内子像素之间的排列方式，并使每个子像素连接到两条数据线，通过在每个子像素连接的两条数据线中传送相反的信号，以减低寄生电容对各子像素的耦合效应。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

  1.    一种液晶显示器，其包括：
    栅极驱动器，电性连接至第一扫描线及第二扫描线；
    源极驱动器，电性连接至第一数据线、第二数据线、第三数据线以及第四数据线；以及
    像素单元，包括：
    第一子像素，电性连接至所述第一扫描线、所述第一数据线以及所述第二数据线，所述第一数据线的第一数据信号与所述第二数据线的第二数据信号的极性相反；
    第二子像素，电性连接至所述第二扫描线、所述第二数据线以及所述第三数据线，所述第二数据线的所述第二数据信号与所述第三数据线的第三数据信号的极性相反；以及
    第三子像素，电性连接至所述第一扫描线、所述第三数据线以及所述第四数据线，所述第三数据线的所述第三数据信号与所述第四数据线的第四数据信号的极性相反。
  2. 如权利要求1所述的液晶显示器，其中所述第一扫描线包括：
    第一垂直扫描线，电性连接至所述栅极驱动器，用以自所述栅极驱动器接收第一扫描信号；以及
    第一水平扫描线，电性连接至所述第一垂直扫描线，用以自所述第一垂直扫描线接收所述第一扫描信号，并提供所述第一扫描信号至所述第一子像素及所述第三子像素。
  3. 如权利要求2所述的液晶显示器，其中所述第一垂直扫描线与下板共电极设置于第一金属层，以及所述第一水平扫描线设置于第二金属层，所述第一金属层及所述第二金属层之间设置绝缘层。
  4. 如权利要求3所述的液晶显示器，其中所述第一水平扫描线穿过所述绝缘层的第一过孔电性连接至所述第一垂直扫描线。
  5. 如权利要求2所述的液晶显示器，其中所述第二扫描线包括：
    第二垂直扫描线，电性连接至所述栅极驱动器，用以自所述栅极驱动器接收第二扫描信号；以及
    第二水平扫描线，电性连接至所述第二垂直扫描线，用以自所述第二垂直扫描线接收所述第二扫描信号，并提供所述第二扫描信号至所述第二子像素。
  6. 如权利要求5所述的液晶显示器，其中所述第二垂直扫描线与下板共电极设置于第一金属层，以及所述第二水平扫描线设置于第二金属层，所述第一金属层及所述第二金属层之间设置绝缘层。
  7. 如权利要求6所述的液晶显示器，其中所述第二水平扫描线穿过所述绝缘层的过第二过孔电性连接至所述第二垂直扫描线。
  8. 如权利要求1所述的液晶显示器，其中所述第一子像素、所述第二子像素以及所述第三子像素分别对应至红色、蓝色以及绿色。
  9. 如权利要求1所述的液晶显示器，其中所述第一子像素的第一开口率、所述第二子像素的第二开口率以及所述第三子像素的第三开口率相同。
  10. 如权利要求1所述的液晶显示器，其中所述第一子像素中存在第一寄生电容以及第二寄生电容，所述第二子像素中存在第三寄生电容以及第四寄生电容，以及所述第三子像素中存在第五寄生电容以及第六寄生电容。
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