WO2022106955A1 - トランジスタ、及び半導体装置 - Google Patents
トランジスタ、及び半導体装置 Download PDFInfo
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- WO2022106955A1 WO2022106955A1 PCT/IB2021/060337 IB2021060337W WO2022106955A1 WO 2022106955 A1 WO2022106955 A1 WO 2022106955A1 IB 2021060337 W IB2021060337 W IB 2021060337W WO 2022106955 A1 WO2022106955 A1 WO 2022106955A1
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Definitions
- One aspect of the present invention relates to transistors, semiconductor devices, and electronic devices.
- the technical field of the invention disclosed in the present specification and the like relates to a product, a driving method, or a manufacturing method.
- one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in the present specification includes a semiconductor device, a display device, a liquid crystal display device, a light emitting device, a power storage device, an image pickup device, a storage device, a signal processing device, and a processor.
- a CPU is an aggregate of semiconductor elements having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes as connection terminals formed therein.
- IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as one of various electronic device components.
- transistors are widely applied to integrated circuits (ICs) and electronic devices such as image display devices (also simply referred to as display devices).
- ICs integrated circuits
- image display devices also simply referred to as display devices.
- Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
- a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state.
- a low power consumption CPU that applies the characteristic that the leakage current of a transistor using an oxide semiconductor is low is disclosed (see Patent Document 1).
- a storage device capable of retaining a storage content for a long period of time by applying the characteristic that a transistor using an oxide semiconductor has a low leakage current is disclosed (see Patent Document 2).
- AI artificial intelligence
- the mechanism of the brain is incorporated as an electronic circuit, and it has a circuit corresponding to "neurons” and "synapses" of the human brain. Therefore, such integrated circuits are sometimes called “neuromorphic”, “brainmorphic”, “brain-inspired” and the like.
- the integrated circuit has a non-Von Neumann architecture, and is expected to be able to perform parallel processing with extremely low power consumption as compared with the Von Neumann architecture in which the power consumption increases as the processing speed increases.
- a model of information processing that imitates a neural network having "neurons” and “synapses” is called an artificial neural network (ANN).
- ANN artificial neural network
- the operation of the weighted sum of the neuron outputs, that is, the product-sum operation is the main operation.
- Non-Patent Document 1 proposes a product-sum calculation circuit using a non-volatile memory element.
- the product-sum calculation circuit in each memory element, the operation in the sub-threshold region of the transistor having silicon in the channel formation region is used, and the data corresponding to the multiplier and the input data corresponding to the multiplicand stored in each memory element are used. Outputs the current corresponding to the multiplication with. That is, it enables calculation with analog values.
- the data corresponding to the product-sum operation is acquired by the sum of the currents output by the memory elements in each column. Since the product-sum calculation circuit has a memory element inside, it is possible to eliminate reading and writing of data from an external memory in multiplication or addition. Therefore, it is expected that the number of times of data transfer due to reading and writing can be reduced, and the power consumption can be reduced.
- transistors are developed aiming at good characteristics.
- good characteristics include high reliability and a steep change from the off state to the on state, that is, having a small S value.
- semiconductors, insulating films, etc. used for transistors that have many defects and / or impurities, it is possible to realize transistors with poor characteristics, that is, large S values, but such transistors are common. It is also unreliable and unrealistic to use in circuits. Further, it is not common to develop a transistor having good reliability, good characteristics, and a large S value.
- the subthreshold region is not so wide because the current in the off state flows at a constant level.
- One aspect of the present invention is to provide a transistor having high reliability and a large S value.
- one aspect of the present invention is to provide a semiconductor device that performs calculations by utilizing the operation of the subthreshold region of a transistor.
- one aspect of the present invention is to provide a semiconductor device having a wide subthreshold region.
- one aspect of the present invention is to provide a new transistor or a new semiconductor device.
- the problem of one aspect of the present invention is not limited to the problems listed above.
- the issues listed above do not preclude the existence of other issues.
- Other issues are issues not mentioned in this item, which are described below. Issues not mentioned in this item can be derived from the description of the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
- one aspect of the present invention solves at least one of the above-listed problems and other problems. It should be noted that one aspect of the present invention does not need to solve all of the above-listed problems and other problems.
- One aspect of the present invention is an oxide semiconductor layer having a channel forming region, a gate electrode having a region overlapping the oxide semiconductor layer via an insulating layer, and a region overlapping the oxide semiconductor layer via a strong dielectric layer. It is a transistor having a first conductive layer having the above, and the strong dielectric layer has a crystal, and the crystal has a crystal structure exhibiting strong dielectric property.
- a region overlapping the first oxide semiconductor layer having a channel forming region, the first insulating layer, the first oxide semiconductor layer, and the first gate insulating layer is provided.
- the dielectric layer has a crystal, and the crystal has a crystal structure exhibiting strong dielectric property.
- one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance, and a second capacitance.
- the gate of the first transistor and the gate of the second transistor are electrically connected to the first wiring, and one of the source or drain of the first transistor and one of the source or drain of the third transistor are Electrically connected to the second wiring, the other of the source or drain of the first transistor is electrically connected to the gate of the third transistor, and one of the source or drain of the second transistor and the fourth.
- One of the source or drain of the transistor is electrically connected to the third wiring, the other of the source or drain of the second transistor is electrically connected to the gate of the fourth transistor, and the third transistor.
- the gate of the fourth transistor is connected to the first wiring through the first capacitance, the gate of the fourth transistor is connected to the first wiring through the second capacitance, and the third transistor and the fourth transistor are connected to the first wiring.
- the transistor has a first oxide semiconductor layer having a channel forming region, a first gate electrode having a region overlapping the first oxide semiconductor layer via the first gate insulating layer, and a first gate electrode, respectively.
- a second oxide semiconductor layer having an oxide semiconductor layer and a conductive layer having an overlapping region via a strong dielectric layer, and the first transistor and the second transistor each having a channel forming region.
- a second gate electrode having a region overlapping with the second oxide semiconductor layer and a second gate insulating layer, and a strong dielectric layer, and the strong dielectric layer has crystals.
- the crystal is a crystal structure that exhibits strong dielectric property.
- the ferroelectric layer has one or both of hafnium and zirconium as a material having ferroelectricity.
- the ferroelectric layer is configured to generate polarization by applying an electric field between the first conductive layer and the oxide semiconductor layer.
- one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance, and a second capacitance.
- the gate of the first transistor and the gate of the second transistor are electrically connected to the first wiring, and one of the source or drain of the first transistor and one of the source or drain of the third transistor are Electrically connected to the second wiring, the other of the source or drain of the first transistor is electrically connected to the gate of the third transistor, and one of the source or drain of the second transistor and the fourth.
- One of the source or drain of the transistor is electrically connected to the third wiring, the other of the source or drain of the second transistor is electrically connected to the gate of the fourth transistor, and the third transistor.
- the gate of the fourth transistor is connected to the first wiring through the first capacitance, the gate of the fourth transistor is connected to the first wiring through the second capacitance, and the S value of the third transistor is used.
- the S value of the fourth transistor is larger than the S value of the first transistor.
- the semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics.
- a semiconductor element transistor, diode, photodiode, etc.
- the storage device, the display device, the light emitting device, the lighting device, the electronic device, and the like may be a semiconductor device itself, and may have a semiconductor device.
- an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display
- an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display
- One or more devices, light emitting devices, loads, etc. can be connected between X and Y.
- a circuit that enables functional connection between X and Y for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion) Circuits (digital-analog conversion circuit, analog-to-digital conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes the signal potential level, etc.), voltage source, current source , Switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, storage circuit, control circuit, etc.) It is possible to connect one or more to and from. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. do.
- X and Y are electrically connected, it means that X and Y are electrically connected (that is, another element between X and Y). Or when they are connected by sandwiching another circuit) and when X and Y are directly connected (that is, they are connected without sandwiching another element or another circuit between X and Y). If there is) and.
- X and Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and the X, the source (or the second terminal, etc.) of the transistor are connected to each other. (1 terminal, etc.), the drain of the transistor (or the 2nd terminal, etc.), and Y are electrically connected in this order.
- the source of the transistor (or the first terminal, etc.) is electrically connected to X
- the drain of the transistor (or the second terminal, etc.) is electrically connected to Y
- the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.
- X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor.
- the terminals, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.
- the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be separated. Separately, the technical scope can be determined. It should be noted that these expression methods are examples, and are not limited to these expression methods.
- X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
- the circuit diagram shows that the independent components are electrically connected to each other, the case where one component has the functions of a plurality of components together.
- one conductive film has both the function of the wiring and the function of the component of the function of the electrode. Therefore, the electrical connection in the present specification also includes the case where one conductive film has the functions of a plurality of components in combination.
- the “resistance element” may be, for example, a circuit element having a resistance value higher than 0 ⁇ , wiring having a resistance value higher than 0 ⁇ , or the like. Therefore, in the present specification and the like, the “resistance element” includes wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, a coil, and the like. Therefore, the term “resistance element” may be paraphrased into terms such as “resistance”, “load”, and “region having a resistance value”. On the contrary, the terms “resistance”, “load”, and “region having a resistance value” may be paraphrased into terms such as “resistance element”.
- the resistance value can be, for example, preferably 1 m ⁇ or more and 10 ⁇ or less, more preferably 5 m ⁇ or more and 5 ⁇ or less, and further preferably 10 m ⁇ or more and 1 ⁇ or less. Further, for example, it may be 1 ⁇ or more and 1 ⁇ 10 9 ⁇ or less.
- the “capacitance element” means, for example, a circuit element having a capacitance value higher than 0F, a wiring region having a capacitance value higher than 0F, a parasitic capacitance, and a transistor. It can be the gate capacitance of. Therefore, in the present specification and the like, the “capacitive element” includes a pair of electrodes and a circuit element including a dielectric contained between the electrodes. In addition, terms such as “capacitive element”, “parasitic capacitance”, and “gate capacitance” may be paraphrased into terms such as "capacity”.
- the term “capacity” may be paraphrased into terms such as “capacitive element”, “parasitic capacitance”, and “gate capacitance”.
- the term “pair of electrodes” of “capacity” can be paraphrased as “pair of conductors", “pair of conductive regions", “pair of regions” and the like.
- the value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. Further, for example, it may be 1 pF or more and 10 ⁇ F or less.
- the transistor has three terminals called a gate, a source, and a drain.
- the gate is a control terminal that controls the conduction state of the transistor.
- the two terminals that function as sources or drains are the input and output terminals of the transistor.
- One of the two input / output terminals becomes a source and the other becomes a drain depending on the high and low potentials given to the conductive type (n-channel type and p-channel type) of the transistor and the three terminals of the transistor. Therefore, in the present specification and the like, the terms source and drain may be paraphrased.
- the transistor when explaining the connection relationship of transistors, "one of the source or drain” (or the first electrode or the first terminal), “the other of the source or drain” (or the second electrode, or the second electrode, or The notation (second terminal) is used.
- it may have a back gate in addition to the above-mentioned three terminals.
- one of the gate or the back gate of the transistor may be referred to as a first gate
- the other of the gate or the back gate of the transistor may be referred to as a second gate.
- the terms “gate” and “backgate” may be interchangeable.
- the respective gates When the transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, and the like in the present specification and the like.
- the S value is a gate voltage required for the current (subthreshold current) between the source electrode and the drain electrode to increase by an order of magnitude. Normally, the smaller the S value, the more the subthreshold current with respect to the gate voltage. The slope is large, the switching characteristics are excellent, and the characteristics are good.
- a transistor having a multi-gate structure having two or more gate electrodes can be used as an example of a transistor.
- the channel forming regions are connected in series, so that the structure is such that a plurality of transistors are connected in series. Therefore, the multi-gate structure can reduce the off-current and improve the withstand voltage of the transistor (improve the reliability).
- the multi-gate structure due to the multi-gate structure, even if the voltage between the drain and the source changes when operating in the saturated region, the current between the drain and the source does not change much, and the slope is flat. The characteristics can be obtained. By utilizing the voltage / current characteristics with a flat slope, it is possible to realize an ideal current source circuit or an active load having a very high resistance value. As a result, it is possible to realize a differential circuit or a current mirror circuit having good characteristics.
- the circuit element may have a plurality of circuit elements.
- one resistance is described on the circuit diagram, it includes the case where two or more resistances are electrically connected in series.
- one capacity is described on the circuit diagram, it includes a case where two or more capacities are electrically connected in parallel.
- one transistor is described on the circuit diagram, two or more transistors are electrically connected in series, and the gates of the respective transistors are electrically connected to each other.
- Shall include.
- the switch has two or more transistors, and two or more transistors are electrically connected in series or in parallel. It is assumed that the gates of the respective transistors are electrically connected to each other.
- a node can be paraphrased as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on a circuit configuration, a device structure, and the like.
- terminals, wiring, etc. can be paraphrased as nodes.
- ground potential ground potential
- the potentials are relative, and when the reference potential changes, the potential given to the wiring, the potential applied to the circuit, the potential output from the circuit, and the like also change.
- high level potential and “low level potential” do not mean a specific potential.
- “High level potential” means a potential located on the positively larger side with respect to “low level potential”
- “low level potential” means more with respect to “high level potential”. It shall mean that the potential is located on the negative side.
- both of the two wirings “function as wirings that supply high level potentials” the high level potentials given by both wirings do not have to be equal to each other.
- both of the two wirings “function as wirings that supply low-level potentials” the low-level potentials provided by both wirings do not have to be equal to each other. ..
- the "current” is a charge transfer phenomenon (electrical conduction).
- the description “electrical conduction of a positively charged body is occurring” means “electrical conduction of a negatively charged body in the opposite direction”. Is happening. " Therefore, in the present specification and the like, “current” refers to a charge transfer phenomenon (electrical conduction) associated with carrier transfer, unless otherwise specified.
- the carrier here include electrons, holes, anions, cations, complex ions, and the like, and the carriers differ depending on the system in which the current flows (for example, semiconductor, metal, electrolytic solution, vacuum, etc.).
- the "current direction” in wiring or the like is the direction in which the carrier that becomes a positive charge moves, and is described as a positive current amount.
- the direction in which the carrier that becomes a negative charge moves is opposite to the direction of the current, and is expressed by the amount of negative current. Therefore, in the present specification and the like, if there is no disclaimer regarding the positive or negative current (or the direction of the current), the description such as “current flows from element A to element B” means “current flows from element B to element A”. Can be rephrased as. Further, the description such as “a current is input to the element A” can be rephrased as "a current is output from the element A” or the like.
- the ordinal numbers “1st”, “2nd”, and “3rd” are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. For example, the component referred to in “first” in one of the embodiments of the present specification and the like may be the other embodiment or the component referred to in “second” in the scope of claims. There can also be. Further, for example, the component referred to in “first” in one of the embodiments of the present specification and the like may be omitted in other embodiments or in the scope of claims.
- the terms “upper” and “lower” do not limit the positional relationship of the components to be directly above or directly below and to be in direct contact with each other.
- the electrode B does not have to be formed in direct contact with the insulating layer A, and another configuration is formed between the insulating layer A and the electrode B. Do not exclude those that contain elements.
- words such as “membrane” and “layer” can be interchanged with each other depending on the situation.
- the terms “insulating layer” and “insulating film” may be changed to the term "insulator”.
- Electrode may be used as part of a “wiring” and vice versa.
- the term “electrode” or “wiring” also includes a case where a plurality of “electrodes” or “wiring” are integrally formed.
- a “terminal” may be used as part of a “wiring” or “electrode” and vice versa.
- the term “terminal” includes a case where a plurality of "electrodes", “wiring”, “terminals” and the like are integrally formed.
- the "electrode” can be a part of “wiring” or “terminal”, and for example, “terminal” can be a part of “wiring” or “electrode”. Further, terms such as “electrode”, “wiring”, and “terminal” may be replaced with terms such as "area” in some cases.
- terms such as “wiring”, “signal line”, and “power line” can be interchanged with each other in some cases or depending on the situation.
- the reverse is also true, and it may be possible to change terms such as “signal line” and “power line” to the term “wiring”.
- a term such as “power line” may be changed to a term such as "signal line”.
- a term such as “signal line” may be changed to a term such as “power line”.
- the term “potential” applied to the wiring may be changed to a term such as “signal” in some cases or depending on the situation.
- the reverse is also true, and terms such as “signal” may be changed to the term “potential”.
- the semiconductor impurities refer to, for example, other than the main components constituting the semiconductor layer.
- an element having a concentration of less than 0.1 atomic% is an impurity.
- the inclusion of impurities may result in, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like.
- the impurities that change the characteristics of the semiconductor include, for example, group 1 element, group 2 element, group 13 element, group 14 element, group 15 element, and other than the main component.
- the impurities that change the characteristics of the semiconductor include, for example, Group 1 element, Group 2 element, Group 13 element, Group 15 element and the like (however, oxygen, Does not contain hydrogen).
- the switch means a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows.
- the switch means a switch having a function of selecting and switching a path through which a current flows. Therefore, the switch may have two or three or more terminals through which a current flows, in addition to the control terminals.
- an electric switch, a mechanical switch, or the like can be used. That is, the switch is not limited to a specific switch as long as it can control the current.
- Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, shotkey diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or logic circuits that combine these.
- transistors for example, bipolar transistors, MOS transistors, etc.
- diodes for example, PN diodes, PIN diodes, shotkey diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.
- the "conduction state" of the transistor is, for example, a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited, and a current is applied between the source electrode and the drain electrode. It means a state where it
- the "non-conducting state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically cut off.
- the polarity (conductive type) of the transistor is not particularly limited.
- An example of a mechanical switch is a switch that uses MEMS (Micro Electro Mechanical Systems) technology.
- the switch has an electrode that can be moved mechanically, and by moving the electrode, conduction and non-conduction are controlled and operated.
- parallel means a state in which two straight lines are arranged at an angle of -10 ° or more and 10 ° or less. Therefore, the case of ⁇ 5 ° or more and 5 ° or less is also included.
- substantially parallel or approximately parallel means a state in which two straight lines are arranged at an angle of -30 ° or more and 30 ° or less.
- vertical means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included.
- substantially vertical or “approximately vertical” means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
- a transistor having high reliability and a large S value it is possible to provide a semiconductor device that performs calculations by utilizing the operation of the subthreshold region of the transistor.
- a semiconductor device having a wide subthreshold region it is possible to provide a novel transistor or a novel semiconductor device.
- the effect of one aspect of the present invention is not limited to the effects listed above.
- the effects listed above do not preclude the existence of other effects.
- the other effects are the effects not mentioned in this item, which are described below. Effects not mentioned in this item can be derived from the description in the specification, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
- one aspect of the present invention has at least one of the above-listed effects and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.
- FIG. 1A and 1B are schematic cross-sectional views showing a configuration example of a transistor according to a semiconductor device.
- FIG. 2 is a circuit diagram showing a configuration example of a product-sum calculation circuit related to a semiconductor device.
- FIG. 3 is a timing chart showing an operation example of the semiconductor device.
- FIG. 4 is an explanatory diagram showing an operating state during the periods T1 to T2.
- FIG. 5 is an explanatory diagram showing an operating state during the periods T3 to T4.
- FIG. 6 is an explanatory diagram showing an operating state after the period T5.
- FIG. 7 is a timing chart showing an operation example of the semiconductor device.
- FIG. 8 is an explanatory diagram showing an operating state during the periods T6 to T7.
- FIG. 9 is an explanatory diagram showing an operating state during the periods T8 to T9.
- FIG. 10 is an explanatory diagram showing an operating state after the period T10.
- 11A and 11B are schematic cross-sectional views showing a configuration example of a transistor according to a semiconductor device.
- FIG. 12A is a diagram for explaining the classification of the crystal structure of IGZO
- FIG. 12B is a diagram for explaining the XRD spectrum of crystalline IGZO
- FIG. 12C is a diagram for explaining the microelectron diffraction pattern of crystalline IGZO.
- .. 13A to 13H are diagrams showing electronic devices.
- FIG. 14A is a diagram showing an Id-Vg curve by device simulation
- FIG. 14B is an enlarged view of a part of FIG. 14A.
- FIG. 14C is a diagram in which the S value in each Id is calculated with the Id in FIG. 14B as the horizontal axis.
- a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is contained in the channel forming region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel forming region of a transistor having at least one of an amplification action, a rectifying action, and a switching action, the metal oxide is referred to as a metal oxide semiconductor. be able to. Further, when the term "OS transistor" is used, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
- a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, the metal oxide having nitrogen may be referred to as a metal oxynitride.
- the configuration shown in each embodiment can be appropriately combined with the configuration shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.
- the content described in one embodiment (may be a part of the content) is different from the content described in the embodiment (may be a part of the content) and one or more different implementations. It is possible to apply, combine, or replace at least one content with the content described in the form of (may be a part of the content).
- figure (which may be a part) described in one embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more different figures.
- the figure (which may be a part) described in the embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more different figures.
- more figures can be formed.
- the code is used for identification such as "_1", “[n]”, “[m, n]”. May be added and described. Further, in the drawings and the like, when the reference numerals such as “_1”, “[n]” and “[m, n]” are added to the reference numerals, when it is not necessary to distinguish them in the present specification and the like, when it is not necessary to distinguish them.
- the identification code may not be described.
- the semiconductor device described in this embodiment is a transistor having a TGSA (Transistor self-align) structure as shown in FIG.
- the transistor also has a conductive layer 103 on the back channel side, and has an insulating film between the conductive layer 103 and the semiconductor layer 130.
- the insulating film contains a ferroelectric layer 120.
- the side closer to the gate electrode 160 is referred to as the front channel side, and the side far from the gate electrode is referred to as the back channel side.
- the structure of the transistor is not limited to the TGSA structure, and a so-called top gate type structure, bottom gate type structure, or the like may be adopted.
- the conductive layer 103 and the ferroelectric layer 120 may be provided on the back channel side.
- a material having a ferroelectricity may be used in a state where the ferroelectricity is exhibited.
- hafnium oxide is preferable.
- a metal oxide such as zirconium oxide or zirconium oxide hafnium (HfZrOX ( X may be described as a real number larger than 0)) may be used.
- hafnium oxide is added to the element J1 (the element J1 here is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y)).
- hafnium oxide is added to the element J1 (the element J1 here is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y)).
- lanthanum (La), strontium (Sr), etc.) can be added.
- the ratio of the number of atoms of the hafnium atom to the element J1 can be appropriately set, and for example, the number of atoms of the hafnium atom and the element J1 may be 1: 1 or close to it.
- element J2 is added to zirconium oxide (the element J2 here is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y)).
- the element J2 here is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y)
- lanthanum (La), strontium (Sr), etc.) and the like can be used.
- the ratio of the number of atoms of the zirconium atom to the element J2 can be appropriately set, and for example, the number of atoms of the zirconium atom to the element J2 may be 1: 1 or close to it.
- materials capable of having a piezoelectricity lead titanate (PbTiO X ), barium titanate strontium (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantanate (SBT), Piezoelectric ceramics having a perovskite structure such as bismuth ferrite (BFO) and barium titanate may be used.
- Al nitride scandium Al 1-a Sc a N b (a is a real number larger than 0 and smaller than 0.5, and b is a value of 1 or its vicinity).
- AlScN Al-Ga-Sc nitride
- Ga-Sc nitride and the like can be used.
- a metal nitride having an element Ma1, an element Ma2, and nitrogen can be used as a material capable of having ferroelectricity.
- the element Ma1 is one or a plurality selected from aluminum (Al), gallium (Ga), indium (In) and the like.
- the elements Ma2 are boron (B), scandium (Sc), yttrium (Y), lanthanoid (lantern (La), cerium (Ce), placeodim (Pr), neodym (Nd), promethium (Pm), and samarium (Pm).
- the metal oxide having the element Ma1 and nitrogen may have ferroelectricity even if it does not contain the element Ma2.
- a material capable of having ferroelectricity a material in which the element Ma3 is added to the metal nitride can be used.
- the element Ma3 is one or a plurality selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd) and the like.
- Mg magnesium
- Ca calcium
- Zn zinc
- Cd cadmium
- the ratio of the number of atoms of the element Ma1, the number of atoms of the element Ma2, and the number of atoms of the element Ma3 can be appropriately set.
- the metal nitride contains at least a Group 13 element and nitrogen which is a Group 15 element, the metal nitride is a strong dielectric of Group III-V and a strength of Group III nitride. It may be called a dielectric or the like.
- perovskite-type oxynitrides such as SrTaO 2 N and BaTaO 2 N, GaFeO 3 having a ⁇ -alumina type structure, and the like can be used.
- the material capable of having ferroelectricity can be, for example, a mixture or a compound composed of a plurality of materials selected from the materials listed above.
- the material capable of having ferroelectricity may be a laminated structure composed of a plurality of materials selected from the materials listed above.
- the crystal structure and electrical characteristics of the materials listed above may change depending not only on the film forming conditions but also on various processes, the above-mentioned materials are used as ferroelectrics in the present specification and the like. It is called a material that can have ferroelectricity as well as being called.
- the ferroelectric substance shall include a material that may have ferroelectricity. In the specification of the present application, even if a material may have ferroelectricity, if it is not explicitly used as a material capable of having ferroelectricity, it is treated as an insulator.
- hafnium oxide As a material capable of having ferroelectricity, hafnium oxide, or a material having hafnium oxide and zirconium oxide (typically HfZrOx) can have ferroelectricity even when processed into a thin film of several nm. Therefore, it is suitable.
- AlScN aluminum nitride scandium
- AlScN aluminum nitride scandium
- the film thickness of the layer of the material capable of having ferroelectricity can be 1 nm or more, preferably 2 nm or more, and more preferably 5 nm or more. Further, a film thickness to the extent that leakage current does not occur is more preferable. Further, the film thickness of the layer of the material capable of having ferroelectricity is preferably such that a sufficient electric field can be applied to generate polarization. For example, it can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, still more preferably 10 nm or less.
- the film thickness range of the layer of the material capable of having ferroelectricity may be 2 nm or more and 30 nm or less, more preferably 5 nm or more and 15 nm or less.
- a layered material capable of having ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film.
- such a device having a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in the present specification and the like.
- HfZrOX When used as a material capable of having ferroelectricity, it is preferable to form a film by using an atomic layer deposition (ALD) method, particularly a thermal ALD method. Further, when a material capable of having ferroelectricity is formed by using the thermal ALD method, it is preferable to use a material containing no hydrocarbon (also referred to as Hydro Carbon, HC) as a precursor. When one or both of hydrogen and carbon are contained in the material which may have a ferroelectricity, the crystallization of the material which may have a ferroelectricity may be hindered.
- ALD atomic layer deposition
- HC Hydro Carbon
- a precursor containing no hydrocarbon a chlorine-based material can be mentioned.
- HfZrO x hafnium oxide and zirconium oxide
- HfCl 4 and / or ZrCl 4 may be used as the precursor.
- a dopant typically silicon, carbon, etc.
- a forming method using a material containing a hydrocarbon in the precursor may be used.
- high-purity intrinsicity is achieved by thoroughly eliminating at least one of impurities, here hydrogen, hydrocarbon, and carbon in the film. It is possible to form a film having a strong ferroelectricity. It should be noted that the film having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later have very high consistency in the manufacturing process. Therefore, it is possible to provide a method for manufacturing a semiconductor device having high productivity.
- the impurity concentration of the material having ferroelectricity is low.
- the hydrogen concentration of the material capable of having ferroelectricity is preferably 5 ⁇ 10 20 atoms / cm 3 or less, and more preferably 1 ⁇ 10 20 atoms / cm 3 or less.
- the carbon concentration of the material capable of having ferroelectricity is preferably 5 ⁇ 10 19 atoms / cm 3 or less, and more preferably 1 ⁇ 10 19 atoms / cm 3 or less.
- HfZrOX is used as a material capable of having ferroelectricity
- the oxidizing agent of the thermal ALD method is not limited to this.
- the oxidizing agent in the thermal ALD method may contain one or more selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 .
- the crystal structure of the material capable of having ferroelectricity is not particularly limited as long as it is in a state where ferroelectricity is exhibited.
- the crystal structure of the material that may have strong dielectric property may be one or more selected from cubic, tetragonal, orthorhombic, and monoclinic.
- a material capable of having ferroelectricity it is preferable to have an orthorhombic crystal structure because ferroelectricity is exhibited.
- a layer that enhances crystallinity may be formed before forming a material that may have ferroelectricity.
- HfZrOx when used as a material having strong dielectric property, a metal oxide such as hafnium oxide or zirconium oxide, or hafnium or zirconium can be used as the layer for enhancing crystallinity.
- AlScN when used as a material having a ferroelectricity, it is preferable to use aluminum nitride, a metal nitride such as scandium nitride, or aluminum or scandium as the layer for enhancing crystallinity.
- a material capable of having ferroelectricity a composite structure having an amorphous structure and a crystal structure may be used.
- HfZrOX when used as a material capable of having ferroelectricity, ferroelectricity is exhibited by including an O phase as a crystal structure.
- the ferroelectric layer 120 may be a laminate of a layer 122 of a material capable of having ferroelectricity and an insulator.
- the ferroelectric layer 120 has a layer 122 of a material capable of having ferroelectricity between the conductive layer 103 and the semiconductor layer 130, and an insulating layer 124 which is a first insulating layer. And may be provided in order.
- the ferroelectric layer 120 has a structure in which a second insulating layer and a layer 122 of a material capable of having ferroelectricity are sequentially provided between the conductive layer 103 and the semiconductor layer 130. May be good.
- the ferroelectric layer 120 has a second insulating layer, a layer 122 of a material capable of having ferroelectricity, and a first insulating layer (insulating layer 124) between the conductive layer 103 and the semiconductor layer 130. ) And may be provided in order.
- the insulator material used for the first insulating layer (insulating layer 124) and the second insulating layer may be any ordinary dielectric material, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide. , Aluminum nitride, aluminum oxide and the like can be used. Further, the insulator can be formed into a film by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In particular, the sputtering method is preferable when an oxide semiconductor is used as the semiconductor layer 130 because the amount of hydrogen incorporated as impurities into the film formed is small.
- the ALD method includes a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactor is performed only by thermal energy, and a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactor.
- a thermal ALD Thermal ALD
- PEALD Plasma Enhanced ALD
- FIGS. 1A and 1B are cross-sectional views showing a configuration example of the transistor 100.
- FIG. 1 is an example in which a layer 122 of a material capable of having ferroelectricity and an insulating layer 124 are provided in order above the conductive layer 103.
- FIG. 1A is a cross-sectional view of the transistor 100 in the channel direction
- FIG. 1B is a cross-sectional view of the transistor 100 in the channel width direction.
- the transistor 100 is a transistor (OS transistor) having a metal oxide (oxide semiconductor) in the semiconductor layer 130.
- the transistor 100 has a characteristic that the off current is very small. Further, the transistor 100 has a wide subthreshold region in the gate-source voltage-drain current characteristic.
- the transistor 100 is placed on a conductive layer 103 arranged so as to be embedded in an insulator, a dielectric layer 120 arranged on the conductive layer 103, and a dielectric layer 120. It has an arranged semiconductor layer 130, a conductive layer 142a and a conductive layer 142b arranged in contact with the semiconductor layer 130 and separated from each other, and a gate electrode 160.
- the conductive layer 103 is arranged so as to be embedded in an insulator, and can be formed by a so-called damascene process.
- the ferroelectric layer 120 can be provided on a relatively flat surface.
- the stress applied to the material having the ferroelectricity can be made constant, and the crystal structure of the material having the ferroelectricity can be strengthened.
- a crystal structure exhibiting dielectric property it can be constantly contained in the ferroelectric layer 120.
- the conductive layer 103 is formed longer than the gate electrode 160 in the cross section in the channel length direction as shown in FIG. 1A. This is because such a configuration makes it easier to exert the influence of the spontaneous polarization expressed on the ferroelectric layer 120 on the transistor 100.
- the material capable of having ferroelectricity is an insulator, which has a property that polarization is generated inside by applying an electric field (electric field) from the outside, and polarization remains even if the electric field is set to zero (the present specification). In, it is assumed that the polarization in the same direction as the direction of the electric field (electric field) applied from the outside remains).
- an electric field (electric field) to the extent that polarization remains is applied to the ferroelectric layer 120 provided on the back channel side, and the characteristics of the transistor (S) are affected by the residual polarization of the ferroelectric layer 120. Value) can be changed.
- the S value is made larger than the characteristics immediately after the transistor is formed by setting the direction of the residual polarization from the conductive layer 103 to the semiconductor layer (OS) 130. be able to. This is because the residual polarization in the ferroelectric layer 120 induces a negative charge on the back channel side in the semiconductor layer (OS), so that the controllability due to the electric field from the gate electrode deteriorates.
- 0 V is applied to the gate electrode 160, the conductive layer 142a, and the conductive layer 142b, and a positive potential is applied to the conductive layer 103.
- a positive charge is induced in the conductive layer 103, and a negative charge is induced in the semiconductor layer (OS) 130.
- OS semiconductor layer
- a new transistor can be provided.
- the present invention it is possible to make the presence or absence of the conductive layer and the strong dielectric layer on the back channel side of the transistor separately, and the transistor whose S value can be changed after forming the semiconductor device is good. It is possible to provide a semiconductor device having transistors having various characteristics in one circuit.
- FIG. 2 is an example of a circuit (multiply-accumulate circuit) that can be used for the product-sum calculation.
- the circuit may be provided as one cell in a matrix of m (m is an integer of 2 or more) in the row direction and n (n is an integer of 2 or more) in the column direction to form a product-sum calculation circuit.
- m is an integer of 2 or more
- n is an integer of 2 or more
- FIG. 2 is an example of a circuit (multiply-accumulate circuit) that can be used for the product-sum calculation.
- the circuit may be provided as one cell in a matrix of m (m is an integer of 2 or more) in the row direction and n (n is an integer of 2 or more) in the column direction to form a product-sum calculation circuit.
- n is an integer of 2 or more
- FIG. 2 is an example of a circuit (multiply-accumulate circuit) that can be used for the product-sum calculation.
- the circuit may be provided as one cell in
- the transistor M1 and the transistor M2 a transistor capable of increasing the S value after manufacturing the transistor described in the first embodiment can be used.
- the S value of the transistor M1 and the transistor M2 it is possible to widen the range of the voltage for operating the product-sum calculation circuit.
- an OS transistor having a low off-current and a small S value for the transistor Tr1 and the transistor Tr2 it is possible to realize a product-sum calculation circuit capable of low power consumption and high-speed operation of the circuit.
- the transistor Tr1 and the transistor Tr2 may have a single gate structure or a dual gate structure. Any structure can be manufactured in the same process as the transistor M1 and the transistor M2.
- the drive circuit for driving the circuit of FIG. 2 may be built on the Si substrate. It is possible to reduce the occupied area of the circuit by stacking it with the cell. Further, the drive circuit may be formed of an OS transistor. Since the OS transistor has a low leakage current, the standby current is small and the circuit can be made into a low power consumption circuit. When formed by an OS transistor, the transistor M1 and the transistor M2 can be formed at the same time as the transistor Tr1 and the transistor Tr2, so that the process does not increase and the cost can be reduced.
- Transistors M1 and M2 are transistors having a ferroelectric layer and a conductive layer on the back channel side.
- each of the transistor M1 and the transistor M2 has a gate G1 and a gate G2.
- the conductive layer BG1 and the conductive layer BG2 are used as the conductive layers on the back channel side of each of the transistor M1 and the transistor M2.
- FIG. 3 shows timing charts (T1 to T5) of an operation example of the arithmetic circuit of FIG. Further, FIGS. 4 to 6 show the states at each timing.
- a positive electric field may be applied from the conductive layer BG1 and the conductive layer BG2 on the back channel side toward the semiconductor layer so as to be equal to or higher than the coercive electric field.
- a high level potential Vhi (> Vth> 0V) is applied to the conductive layer BG1, the conductive layer BG2, and the wiring g, and the wiring x and the wiring y are subjected to a high level potential Vhi (> Vth> 0V).
- Apply a ground potential GND ( ⁇ 0V).
- the conductive layer BG1 and the conductive layer BG2 are electrically connected to each other, so that the same potential can be applied. By doing so, the number of wirings of the circuit can be reduced, and the area occupied by the circuit can be reduced. Further, the potentials of the conductive layer BG1 and the conductive layer BG2 may be individually controlled. By controlling individually, it is possible to give an optimum potential according to each transistor, and fine control is possible with respect to a change in the S value.
- the reference current value I x0 and the current value w ⁇ I x0 are set as the amount of current flowing when operating in the subthreshold region of the transistor M1 and the transistor M2. Since the wiring g has a high level potential Vhi, the transistor Tr1 and the transistor Tr2 are turned on, and with the passage of time, the transistor M1 and the gate G1 and the gate G2 of the transistor M2 have a reference current value I x 0 and a current, respectively.
- the potential corresponds to the value w ⁇ I ⁇ 0, and this potential is equal to the potential applied to the wiring x and the wiring y, respectively.
- these potentials are Vg1 and Vg2.
- the potential of the wiring g is returned to the ground potential.
- the transistor Tr1 and the transistor Tr2 are turned off, and the potentials Vg1 and Vg2 of the gate G1 and the gate G2 of the transistor M1 and the transistor M2 are held.
- the current value xxI x0 which is x times the reference current value, is passed through the input side wiring x while keeping the potential of the wiring g at the ground potential. Since the potential of the wiring g is the ground potential, the transistor Tr1 is in the off state and no current flows through the transistor Tr1, but the potential of the gate G1 of the transistor M1 has a current value xxI due to the capacitance coupling by the capacitance C1. It changes to the potential according to x0 . Let ⁇ be the amount of change in potential. At this time, assuming that the capacitive coupling coefficient around the capacitance C1 is 1, the potentials of the wiring x and the gate G1 of the transistor M1 are Vg1 + ⁇ .
- the potential of the gate G2 of the transistor M2 also changes by ⁇ due to the capacitive coupling between the wiring x and the capacitance C2, and becomes Vg2 + ⁇ .
- a current of x ⁇ w ⁇ I x 0 flows through the output side wiring y. This is xxw times the reference current value, and the result of multiplying x and w is output.
- the current value xxI x0 and the current value xxwxI x0 are also set as the amount of current flowing when operating in the subthreshold region of the transistor M1 and the transistor M2.
- the current value x ⁇ w ⁇ I x 0 flowing through the output side wiring y may be detected by a current detector provided on the GND side of the transistor M2. Further, the product-sum calculation can be performed by providing the circuit as one cell in a matrix and detecting the current with the wiring y in the column direction in common.
- the threshold voltage Vth When the threshold voltage Vth is positive, a positive potential is applied to the wiring x and the wiring y, and when the conductive layer BG1 of the transistor M1 and the conductive layer BG2 of the transistor M2 are set to GND, the transistors M1 and M2 An electric field opposite to that of writing is applied to each strong dielectric layer, but the potential applied to the wiring x and the wiring y is the sub-threshold region of the transistor M1 and the transistor M2. It is a potential to operate at, the electric field is small, and by driving at high speed, it is possible to finish the calculation before the polarization (residual polarization) written in the strong dielectric layer is inverted or decreased. be.
- FIG. 7 shows a timing chart of an operation example when the threshold voltage Vth is negative. Further, FIGS. 8 to 10 show the states at each timing.
- the threshold voltage Vth is positive is that even if the ground potential GND is applied to the wiring g, the gates of the transistors M1 and M2 are turned on, so that the high level potential Vhi is not applied to the wiring g. good. Further, at the timing (T7) of returning the potentials of the conductive layer BG1 and the conductive layer BG2 to the ground potential, the potential of the wiring g is set to the low level potential Vlo. In addition, Vlo has a potential lower than the ground potential GND.
- ⁇ Initial state> As an initial state (FIG. 7: T8 to T9, FIG. 9), a ground potential GND (note that the ground potential GND is higher than Vth) is applied to the wiring g, and a reference current value I x0 is applied to the input side wiring x.
- the current value w ⁇ I ⁇ 0, which is w times the reference current value, is passed through the output side wiring y.
- the reference current value I x0 and the current value w ⁇ I x0 are set as the amount of current flowing when operating in the sub-threshold region of the transistors M1 and M2, but since Vth is negative, the input side wiring x and the output side are set.
- a potential lower than the ground potential GND is applied to the wiring y.
- the potential of the wiring g is returned to the low level potential Vlo.
- the transistor Tr1 and the transistor Tr2 are turned off, and the potentials Vg1 and Vg2 of the gate G1 and the gate G2 of the transistor M1 and the transistor M2 are held.
- the current value xxI x0 which is x times the reference current value, is passed through the input side wiring x while the potential of the wiring g remains the low level potential Vlo. Since the potential of the wiring g is a low level potential Vlo, the transistor Tr1 is in the off state and no current flows through the transistor Tr1, but the potential of the gate G1 of the transistor M1 has a current value x due to capacitive coupling by the capacitance C1. It changes to the potential according to ⁇ I ⁇ 0 . At this time, assuming that the capacitive coupling coefficient around the capacitance C1 is 1, the potentials of the wiring x and the gate G1 of the transistor M1 are Vg1 + ⁇ .
- the potential of the gate G2 of the transistor M2 also changes by ⁇ due to the capacitive coupling between the wiring x and the capacitance C2, and becomes Vg2 + ⁇ .
- a current of x ⁇ w ⁇ I x 0 flows through the output side wiring y. This is xxw times the reference current value, and the result of multiplying x and w is output.
- the current value xxI x0 and the current xxwxI x0 are also set as the amount of current flowing when operating in the subthreshold region of the transistor M1 and the transistor M2.
- Writing to the ferroelectric layer may be performed once after the transistor is formed. If an electric field in the opposite direction to that at the time of writing is not applied, the polarization remains as it is, so that the writing operation is unnecessary every time the product-sum operation is performed. Further, once the writing is performed on the strong dielectric layer, the S values of the transistor M1 and the transistor M2 are kept increased due to the influence of the residual polarization, so that the conductive layer BG1 and the conductive layer BG2 are maintained during the arithmetic processing.
- the ground potential may be set to GND or the like, and since it is not necessary to apply and control the potential to the conductive layer BG1 and the conductive layer BG2, it is possible to perform arithmetic processing with low power consumption. That is, it may be performed continuously between T2 and T3, and between T7 and T8, but it is not necessary to perform it continuously.
- the transistor M1 and the transistor M2 have a characteristic that the S value is increasing, the potential to be applied to the current to be applied to the wiring x and the wiring y can be finely (accurately) adjusted, so that the wiring x and the wiring It is possible to perform a product-sum operation in y with a wide range of voltages for driving. Further, even if the characteristics of the transistor M1 and the transistor M2 in the subthreshold region are not clearly understood, if the potential rise of each wiring can be stopped by detecting the current value flowing through the wiring x and the wiring y. It is possible to calculate correctly.
- FIG. 11A is a cross-sectional view of the transistor 500 in the channel direction
- FIG. 11B is a cross-sectional view of the transistor 500 in the channel width direction.
- the transistor 500 shown in FIGS. 11A and 11B has the same configuration as the transistor 100 described in the first embodiment.
- the transistor 500 shows a configuration in which a layer 522 of a material capable of having a ferroelectricity and a conductor 503 are provided, but the layer 522 or a conductor 503 of a material capable of having a ferroelectricity, or having a ferroelectricity. It is possible to simultaneously make a transistor having a structure in which both the layer 522 of the material and the conductor 503 are not provided.
- the transistor and the transistor 500 may extend the layer 522 of the material capable of having ferroelectricity and share the layer.
- the layer 522 of the material which may have ferroelectricity may be provided separately.
- the transistor 500 is provided above the insulator 512.
- the transistor 500 is insulated from the insulator 514 and the insulator 516 arranged on the insulator 512 and the conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516.
- the insulator layer 520 arranged on the body 516 and the conductor 503, the oxide 530 arranged on the insulator layer 520, and the conductor 542a and the conductor arranged apart from each other on the oxide 530.
- Insulator 580 arranged on the body 542b, the conductor 542a and the conductor 542b, and having an opening superimposed between the conductor 542a and the conductor 542b, and an insulator arranged on the bottom surface and the side surface of the opening. It has a 550 and a conductor 560 arranged on the forming surface of the insulator 550.
- the conductor 503 is arranged so as to be embedded in the insulator 514 and the insulator 516, and can be formed by a so-called damascene process.
- the ferroelectric layer 520 can be provided on a relatively flat surface.
- the stress applied to the material having the ferroelectricity can be made constant, and the crystal structure of the material having the ferroelectricity can be strengthened.
- a crystal structure exhibiting dielectric property it can be constantly contained in the ferroelectric layer 520.
- the transistor 500 shows a configuration in which two layers of oxide 530a and oxide 530b are laminated in a region where a channel is formed and in the vicinity thereof, but one aspect of the present invention is not limited to this. do not have.
- a single layer of the oxide 530b, a three-layer structure in which the oxide 530c is provided on the upper layer of the oxide 530b, or a laminated structure of four or more layers may be provided.
- the conductor 560 is shown as a two-layer laminated structure, but one aspect of the present invention is not limited to this.
- the conductor 560 may have a single-layer structure or a laminated structure of three or more layers.
- the transistor 500 is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration, driving method, and the like.
- the oxide 530a and the oxide 530b may be collectively referred to as an oxide 530.
- the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b function as a source electrode or a drain electrode, respectively.
- the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
- the arrangement of the conductor 560, the conductor 542a and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing the alignment margin, the occupied area of the transistor 500 can be reduced. As a result, the semiconductor device can be miniaturized and highly integrated.
- the conductor 560 is formed in a region between the conductor 542a and the conductor 542b in a self-aligned manner, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Therefore, the switching speed of the transistor 500 can be improved and high frequency characteristics can be provided.
- the conductor 560 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode.
- the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 without interlocking with the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be made larger than 0V, and the off-current can be reduced. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when it is not applied.
- the conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to cover the channel forming region formed in the oxide 530. Can be done.
- the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate electrode and the second gate electrode is called a slurried channel (S-channel) structure.
- the conductor 503 functions as an electrode for generating residual polarization by applying an electric field (electric field) to the layer 522 of the material capable of having ferroelectricity.
- an electric field electric field
- the conductor 503 may be able to adjust the potential independently of the conductor 560, and a constant potential may be applied during the circuit drive.
- the conductor 503a is formed in contact with the inner wall of the opening of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside.
- the transistor 500 shows a configuration in which the conductor 503a and the conductor 503b are laminated, one aspect of the present invention is not limited to this.
- the conductor 503 may be provided as a single layer or a laminated structure having three or more layers.
- the conductor 503a it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate).
- a conductive material having a function of suppressing the diffusion of oxygen for example, at least one oxygen atom, oxygen molecule, etc.
- the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.
- a metal nitride film such as TiN X or TaN X.
- the conductor 503a since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 503b from being oxidized and the conductivity from being lowered.
- the conductor 503 also has a wiring function
- the conductor 503b is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride and the above-mentioned conductive material may be laminated.
- the layer 522 of a material capable of having ferroelectricity can be formed by using the material shown in the first embodiment.
- Materials that can have ferroelectricity are used under conditions that exhibit ferroelectricity.
- the conditions for exhibiting ferroelectricity differ depending on the material used, and specifically, the crystal structure of crystals contained in the film and the like.
- the thickness range of the layer of the material having a ferroelectricity is 2 nm or more and 30 nm or less, more preferably 5 nm or more and 15 nm or less.
- Ferroelectricity is often exhibited by the inclusion of the O phase as the crystal structure of the crystals contained in the film.
- the ferroelectric layer 520 may be a laminate of a layer 522 of a material capable of having ferroelectricity and an insulator.
- a layer 522 of a material capable of having ferroelectricity is provided on the insulator 516 and the conductor 503, and the first insulator is formed on the layer 522 of the material capable of having ferroelectricity.
- a certain insulator 524 is provided.
- a second insulator may be provided on the insulator 516 and the conductor 503, and a layer 522 of a material capable of having ferroelectricity may be provided on the second insulator.
- an insulator 524 is provided on the side close to the oxide 530, a second insulator is provided on the side close to the conductor 503, and a second insulator and a strong insulator are provided on the insulator 516 and on the conductor 503.
- a layer 522 of a material capable of having a dielectric property and a first insulator (insulator 524) may be provided in order.
- the first insulator (insulator 524) or the second insulator, or the first insulator (insulator 524) is provided.
- the second insulator has a function as a second gate insulating film.
- a material applicable to the first insulator (insulator 524) can be used.
- the insulator 524 in contact with the oxide 530 it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition. That is, it is preferable that the insulator 524 has an excess oxygen region formed therein. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen deficiency in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.
- an oxide material in which a part of oxygen is desorbed by heating is those whose oxygen desorption amount in terms of oxygen atoms is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis.
- the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
- the insulator having the excess oxygen region and the oxide 530 may be brought into contact with each other to perform one or more of heat treatment, microwave treatment, or RF treatment. By performing this treatment, water or hydrogen in the oxide 530 can be removed.
- a reaction in which the bond of VOH is cleaved occurs, in other words, a reaction of “ VOH ⁇ VO + H ” occurs, and dehydrogenation can be performed.
- a part of the hydrogen generated at this time may be combined with oxygen to form H2O and may be removed from the oxide 530 or the insulator in the vicinity of the oxide 530. Further, a part of hydrogen may be diffused or captured (also referred to as gettering) in the conductor 542a and the conductor 542b.
- the microwave processing for example, it is preferable to use a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side.
- a device having a power source for generating high-density plasma for example, by using a gas containing oxygen and using a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be generated.
- the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
- oxygen and argon are used as the gas to be introduced into the apparatus for performing microwave treatment, and the oxygen flow rate ratio (O 2 / (O 2 + Ar)) is 50% or less, preferably 10% or more and 30. It is better to do it at% or less.
- the heat treatment may be performed, for example, at 100 ° C. or higher and 450 ° C. or lower, more preferably 350 ° C. or higher and 400 ° C. or lower.
- the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more.
- the heat treatment is preferably performed in an oxygen atmosphere.
- oxygen can be supplied to the oxide 530 to reduce oxygen deficiency (VO).
- the heat treatment may be performed in a reduced pressure state.
- the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas. good.
- the heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more, and then continuously heat-treated in an atmosphere of nitrogen gas or an inert gas.
- the oxygen deficiency in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "VO + O ⁇ null" can be promoted. .. Further, the oxygen supplied to the hydrogen remaining in the oxide 530 reacts with the hydrogen, so that the hydrogen can be removed (dehydrated) as H2O . As a result, it is possible to suppress the hydrogen remaining in the oxide 530 from being recombined with the oxygen deficiency to form VOH.
- the second insulator is thermally stable.
- silicon oxide and silicon nitride nitride are suitable because they are thermally stable.
- a second insulator having a laminated structure that is thermally stable and has a high relative permittivity can be obtained.
- the ferroelectric layer 520 having a laminated structure of two layers, a layer 522 of a material capable of having ferroelectricity and an insulator 524 are shown.
- the ferroelectric layer 520 may have a single layer, two layers, or a laminated structure of four or more layers.
- the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
- the transistor 500 it is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel forming region.
- the metal oxide that functions as an oxide semiconductor will be described in detail in the fourth embodiment.
- the oxide 530 can suppress the diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b. Further, by having the oxide 530c on the oxide 530b, it is possible to suppress the diffusion of impurities from the structure formed above the oxide 530c to the oxide 530b.
- the oxide 530 has a structure of a plurality of oxide layers having different atomic number ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic number ratio of the element Ma in the constituent elements is larger than the atomic number ratio of the element Ma in the constituent elements in the metal oxide used for the oxide 530b. Is preferable. Further, in the metal oxide used for the oxide 530a, the atomic number ratio of the element Ma to In is preferably larger than the atomic number ratio of the element Ma to In in the metal oxide used for the oxide 530b.
- the atomic number ratio of In to the element Ma is preferably larger than the atomic number ratio of In to the element Ma in the metal oxide used for the oxide 530a.
- the oxide 530c a metal oxide that can be used for the oxide 530a or the oxide 530b can be used.
- the atomic number ratio of In to the element Ma in the metal oxide used for the oxide 530a is smaller than the atomic number ratio of In to the element Ma in the metal oxide used for the oxide 530b, In is used as the oxide 530b.
- In-Ga-Zn oxide having a composition of 3 or its vicinity can be used.
- a metal oxide having a composition in the vicinity of any one can be used.
- oxides 530a, oxides 530b, and oxides 530c so as to satisfy the above-mentioned atomic number ratio relationship.
- the above composition indicates the atomic number ratio in the oxide formed on the substrate or the atomic number ratio in the sputter target. Further, as the composition of the oxide 530b, by increasing the ratio of In, the on-current of the transistor, the mobility of the field effect, and the like can be increased, which is preferable.
- the energy at the lower end of the conduction band of the oxide 530a and the oxide 530c is higher than the energy at the lower end of the conduction band of the oxide 530b.
- the electron affinity of the oxide 530a and the oxide 530c is smaller than the electron affinity of the oxide 530b.
- the energy level at the lower end of the conduction band changes gently.
- the energy level at the lower end of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c is continuously changed or continuously bonded.
- the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, thereby forming a mixed layer having a low defect level density.
- the oxide 530b is an In-Ga-Zn oxide
- In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like may be used as the oxide 530a and the oxide 530c.
- the main path of the carrier is oxide 530b.
- the oxide 530a and the oxide 530c have the above-mentioned constitution, the defect level density at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.
- a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided on the oxide 530b.
- the conductors 542a and 542b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium.
- Iridium, strontium, a metal element selected from lanthanum, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like is preferably used.
- tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable.
- tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
- a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.
- the conductor 542a and the conductor 542b are shown as a single-layer structure, but a laminated structure of two or more layers may be used.
- a tantalum nitride film and a tungsten film may be laminated.
- the titanium film and the aluminum film may be laminated.
- a two-layer structure in which an aluminum film is laminated on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a tungsten film. It may have a two-layer structure in which copper films are laminated.
- a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed on the aluminum film or a copper film.
- a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.
- the oxygen in the oxide 530 is removed by the contact between the conductor 542a and the conductor 542b and the oxide 530. It may diffuse to the conductor 542a and the conductor 542b, and the conductor 542a and the conductor 542b may be oxidized. It is highly probable that the conductivity of the conductor 542a and the conductor 542b will decrease due to the oxidation of the conductor 542a and the conductor 542b.
- the diffusion of oxygen in the oxide 530 to the conductor 542a and the conductor 542b can be rephrased as the conductor 542a and the conductor 542b absorbing the oxygen in the oxide 530.
- a region 543a and a region 543b may be formed as a low resistance region at the interface of the oxide 530 with the conductor 542a (conductor 542b) and its vicinity thereof.
- the region 543a functions as one of the source region or the drain region
- the region 543b functions as the other of the source region or the drain region.
- a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.
- the oxygen concentration in the region 543a (region 543b) may be reduced. Further, in the region 543a (region 543b), a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the component of the oxide 530 may be formed. In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.
- the insulator 544 is provided so as to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and come into contact with the insulator 524.
- the insulator 544 as an insulator containing one or more selected from hafnium, aluminum, gallium, ittrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lantern, magnesium and the like. Metal oxides can be used. Further, as the insulator 544, silicon nitride oxide, silicon nitride or the like can also be used.
- the insulator 544 it is preferable to use aluminum or an oxide containing one or both oxides of hafnium, such as aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate). ..
- hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent step.
- the conductors 542a and 542b are materials having oxidation resistance or materials whose conductivity does not significantly decrease even if oxygen is absorbed, the insulator 544 is not an essential configuration. It may be appropriately designed according to the desired transistor characteristics.
- the insulator 544 By having the insulator 544, it is possible to prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b via the oxide 530c and the insulator 550. Further, it is possible to suppress the oxidation of the conductor 542 due to the excess oxygen contained in the insulator 580.
- the insulator 550 functions as a first gate insulating film. Similar to the above-mentioned insulator 524, the insulator 550 is preferably formed by using an insulator that contains excessive oxygen and releases oxygen by heating.
- silicon oxide having excess oxygen silicon oxide, silicon nitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon, and silicon oxide with nitrogen added, vacancies Silicon oxide having can be used.
- silicon oxide and silicon nitride are preferable because they are stable against heat.
- the insulator that releases oxygen by heating can effectively supply oxygen from the insulator 550 to the channel forming region of the oxide 530b. Further, as with the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced.
- the film thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.
- a metal oxide may be provided between the insulator 550 and the conductor 560.
- the metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560.
- the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 530.
- oxidation of the conductor 560 due to excess oxygen can be suppressed.
- a material that can be used for the insulator 544 may be used.
- the insulator 550 may have a laminated structure. As transistors become finer and more integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, an insulator that functions as a gate insulating film is heat-k material and heat. By forming a laminated structure with a material that is stable, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a laminated structure that is thermally stable and has a high relative permittivity can be obtained.
- the conductor 560 functioning as the gate electrode or the first gate electrode is shown as a two-layer structure in FIGS. 11A and 11B, but may have a single-layer structure or a laminated structure of three or more layers. ..
- the conductor 560a has a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ( N2O, NO, NO2 , etc.) and copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 550 and the conductivity from being lowered.
- impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ( N2O, NO, NO2 , etc.) and copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing
- the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
- an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b into a film by a sputtering method, the electric resistance value of the conductor 560a can be lowered to form a conductor. This can be called an OC (Oxide Conductor) electrode.
- the conductor 560b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 560b may have a laminated structure, for example, titanium or a laminated structure of titanium nitride and the conductive material.
- the insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544.
- the insulator 580 preferably has an excess oxygen region.
- silicon, resin, or the like silicon oxide and silicon nitride nitride are preferable because they are thermally stable.
- silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later step.
- the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 in which oxygen is released by heating, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.
- the opening of the insulator 580 is formed so as to overlap the region between the conductor 542a and the conductor 542b.
- the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
- the conductor 560 may have a shape having a high aspect ratio.
- the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape having a high aspect ratio, the conductor 560 is formed without collapsing during the process. Can be done.
- the insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550.
- an excess oxygen region can be provided in the insulator 550 and the insulator 580. Thereby, oxygen can be supplied into the oxide 530 from the excess oxygen region.
- metal oxidation as an insulator containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like. Things can be used.
- aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, the aluminum oxide formed by the sputtering method can have a function as a barrier film for impurities such as hydrogen as well as an oxygen supply source.
- an insulator 581 that functions as an interlayer film on the insulator 574. It is preferable that the insulator 581 has a reduced concentration of impurities such as water or hydrogen in the membrane, similarly to the insulator 524 and the like.
- the conductor 540a and the conductor 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544.
- the conductor 540a and the conductor 540b are provided so as to face each other with the conductor 560 interposed therebetween.
- a new transistor can be provided.
- the presence or absence of the conductive layer and / or the strong dielectric layer on the back channel side of the transistor can be made separately, and the S value can be changed after forming the semiconductor device. It is possible to provide a semiconductor device having a transistor having good characteristics in one circuit.
- the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like. ..
- FIG. 12A is a diagram illustrating the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).
- IGZO a metal oxide containing In, Ga, and Zn
- oxide semiconductors are roughly classified into “Amorphous”, “Crystalline”, and “Crystal”.
- Amorphous includes completely amorphous.
- “Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned crystal) (exclusion single crystal).
- single crystal, poly crystal, and single crystal atomous are excluded from the classification of "Crystalline”.
- “Crystal” includes single crystal and poly crystal.
- the structure in the thick frame shown in FIG. 12A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystalline phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
- the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum.
- XRD X-ray diffraction
- FIG. 12B the XRD spectrum obtained by GIXD (Grazing-Intensity XRD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in FIG. 12B (the vertical axis is the intensity (Intensity) as an arbitrary unit (a.u.)). (Represented by).
- the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
- the XRD spectrum obtained by the GIXD measurement shown in FIG. 12B is simply referred to as an XRD spectrum.
- a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
- the crystal structure of the film or the substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
- the diffraction pattern of the CAAC-IGZO film is shown in FIG. 12C.
- FIG. 12C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
- electron beam diffraction is performed with the probe diameter set to 1 nm.
- oxide semiconductors may be classified differently from FIG. 12A.
- oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
- the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
- the non-single crystal oxide semiconductor includes a polycrystal oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: atomous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
- CAAC-OS CAAC-OS
- nc-OS nc-OS
- a-like OS the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.
- CAAC-OS is an oxide semiconductor having a plurality of crystal regions, the plurality of crystal regions having the c-axis oriented in a specific direction.
- the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
- the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
- the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
- Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
- the maximum diameter of the crystal region is less than 10 nm.
- the size of the crystal region may be about several tens of nm.
- CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements Ma, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and the element Ma can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element Ma. The In layer may contain Zn.
- the layered structure is observed as a grid image, for example, in a high-resolution TEM image.
- the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.
- a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam transmitted through the sample (also referred to as a direct spot) as the center of symmetry.
- the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
- a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction, the bond distance between atoms changes due to the replacement of metal atoms, and the like. It is thought that this is the reason.
- CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
- a configuration having Zn is preferable.
- In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
- CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be deteriorated due to the mixing of impurities and the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures (so-called thermal budgets) in the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
- nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
- nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
- nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
- the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method. For example, when structural analysis is performed on an nc-OS film using an XRD device, a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan. Further, when electron beam diffraction (also referred to as limited field electron diffraction) using an electron beam having a probe diameter larger than that of nanocrystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is performed. Is observed.
- electron beam diffraction also referred to as limited field electron diffraction
- nanocrystals for example, 50 nm or more
- electron diffraction also referred to as nanobeam electron diffraction
- an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
- An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
- the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
- the a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. In addition, a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
- CAC-OS relates to the material composition.
- CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
- the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
- the mixed state is also called a mosaic shape or a patch shape.
- the CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic, and the first region is distributed in the film (hereinafter, also referred to as a cloud shape). It is said.). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
- the atomic number ratios of In, Ga, and Zn with respect to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn].
- the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
- the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
- the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
- the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
- the first region is a region in which indium oxide, indium zinc oxide, or the like is the main component.
- the second region is a region containing gallium oxide, gallium zinc oxide, or the like as a main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
- a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1) and the region containing Ga as a main component (second region) have a structure in which they are unevenly distributed and mixed.
- CAC-OS does not include a laminated structure of two or more types of films having different compositions. Further, the first region and the second region do not take out a part of the layered crystal structure and treat it as a region. That is, when crystals are contained in the first region and the second region, those crystals have different crystals.
- the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function).
- the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS for the transistor, high on -current (Ion), high field effect mobility ( ⁇ ), and good switching operation can be realized.
- Oxide semiconductors have various structures, and each has different characteristics.
- the oxide semiconductor of one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
- the oxide semiconductor as a transistor, a transistor with high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.
- the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm -3 or less, preferably 1 ⁇ 10 15 cm -3 or less, more preferably 1 ⁇ 10 13 cm -3 or less, and more preferably 1 ⁇ 10 11 cm ⁇ . It is 3 or less, more preferably less than 1 ⁇ 10 10 cm -3 , and more preferably 1 ⁇ 10 -9 cm -3 or more.
- the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
- a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
- An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
- the trap level density may also be low.
- the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel forming region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
- impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
- the concentration of silicon and / or carbon in the oxide semiconductor and the concentration of silicon and / or carbon in the vicinity of the interface with the oxide semiconductor Is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
- the oxide semiconductor contains an alkali metal or an alkaline earth metal
- defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
- the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, and more preferably 1 ⁇ 10 18 atoms / cm 3 or less. , More preferably 5 ⁇ 10 17 atoms / cm 3 or less.
- hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen deficiency in the oxide semiconductor.
- the oxygen deficiency and hydrogen may be combined to form VOH.
- VOH acts as a donor and may generate electrons as carriers.
- a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.
- VOH in the oxide 530 it is preferred to reduce VOH in the oxide 530 as much as possible to achieve high purity or substantially high purity.
- impurities such as water and hydrogen in the oxide semiconductor must be removed (may be described as dehydration or dehydrogenation treatment). It is important to supply oxygen to the oxide semiconductor to compensate for the oxygen deficiency (sometimes referred to as dehydrogenation treatment).
- Defects containing hydrogen in oxygen deficiencies can function as donors for oxide semiconductors. However, it is difficult to quantitatively evaluate the defect. Therefore, in oxide semiconductors, the carrier concentration may be used for evaluation instead of the donor concentration. Therefore, in the present specification and the like, as a parameter of the oxide semiconductor, a carrier concentration assuming a state in which an electric field is not applied may be used instead of the donor concentration. That is, the "carrier concentration" described in the present specification and the like may be paraphrased as a "donor concentration".
- the hydrogen in the oxide semiconductor is reduced as much as possible.
- the hydrogen concentration obtained by secondary ion mass spectrometry is less than 1 ⁇ 10 20 atoms / cm 3 , preferably 1 ⁇ 10 19 atoms / cm. It is less than 3 , more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
- the oxide semiconductor is a semiconductor having a high band gap and is intrinsic (also referred to as type I) or substantially intrinsic, and has a channel forming region.
- the carrier concentration of the oxide semiconductor is preferably less than 1 ⁇ 10 18 cm -3 , more preferably less than 1 ⁇ 10 17 cm -3 , and further preferably less than 1 ⁇ 10 16 cm -3 . It is preferably less than 1 ⁇ 10 13 cm -3 , even more preferably less than 1 ⁇ 10 12 cm -3 .
- the lower limit of the carrier concentration of the oxide semiconductor in the channel formation region is not particularly limited, but may be, for example, 1 ⁇ 10 -9 cm -3 .
- the semiconductor device according to one aspect of the present invention can be used for a processor such as a CPU or GPU, or a chip.
- a processor such as a CPU or GPU, or a chip
- these can be miniaturized and further reduced in power consumption.
- 13A to 13H show specific examples of electronic devices including a processor such as a CPU, GPU, or a chip according to one aspect of the present invention.
- Chips such as CPUs and GPUs according to one aspect of the present invention can be mounted on various electronic devices.
- electronic devices include electronic devices with relatively large screens, such as television devices, monitors for desktop or notebook information terminals, digital signage (electronic signs), large game consoles such as pachinko machines, and the like.
- digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like can be mentioned.
- artificial intelligence can be mounted on the electronic device.
- the electronic device of one aspect of the present invention may have an antenna.
- the display unit can display images, information, and the like.
- the antenna may be used for non-contact power transmission.
- the electronic device of one aspect of the present invention includes sensors (force, displacement, position, speed, acceleration, angular speed, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to measure voltage, power, radiation, current flow, humidity, gradient, vibration, odor or infrared rays).
- the electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function to display a date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like. 13A to 13H show examples of electronic devices.
- FIG. 13A illustrates a mobile phone (smartphone) which is a kind of information terminal.
- the information terminal 5100 has a housing 5101 and a display unit 5102, and a touch panel is provided in the display unit 5102 and a button is provided in the housing 5101 as an input interface.
- the information terminal 5100 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
- Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5102.
- Examples include an application displayed on the display unit 5102, an application for performing biometric authentication such as a fingerprint and a voice print, and the like.
- FIG. 13B illustrates a notebook-type information terminal 5200.
- the notebook type information terminal 5200 has a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.
- the note-type information terminal 5200 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
- applications using artificial intelligence include design support software, text correction software, menu automatic generation software, and the like. Further, by using the notebook type information terminal 5200, it is possible to develop a new artificial intelligence.
- a smartphone and a notebook-type information terminal are taken as examples as electronic devices, and although they are shown in FIGS. 13A and 13B, respectively, information terminals other than the smartphone and the notebook-type information terminal can be applied.
- Examples of information terminals other than smartphones and notebook-type information terminals include PDAs (Personal Digital Assistants), desktop-type information terminals, workstations, and the like.
- FIG. 13C shows a portable game machine 5300, which is an example of a game machine.
- the portable game machine 5300 has a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like.
- the housing 5302 and the housing 5303 can be removed from the housing 5301.
- the connection unit 5305 provided in the housing 5301 to another housing (not shown)
- the video output to the display unit 5304 can be output to another video device (not shown). can.
- the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play the game at the same time.
- the chips shown in the previous embodiment can be incorporated into the chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.
- FIG. 13D shows a stationary game machine 5400, which is an example of a game machine.
- a controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.
- a low power consumption game machine By applying a chip such as a CPU or GPU of one aspect of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400, a low power consumption game machine can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
- the portable game machine 5300 having artificial intelligence can be realized.
- expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the program that the game has, but by applying artificial intelligence to the portable game machine 5300.
- Expressions that are not limited to game programs are possible. For example, it is possible to express what the player asks, the progress of the game, the time, and the behavior of the characters appearing in the game.
- the game player can be constructed by artificial intelligence in an anthropomorphic manner. Therefore, by setting the opponent as a game player by artificial intelligence, even one person can play the game. You can play the game.
- 13C and 13D show a portable game machine and a stationary game machine as an example of the game machine, but the game machine to which a chip such as a CPU or GPU according to one aspect of the present invention is applied is not limited thereto. ..
- a game machine to which a chip such as a CPU or GPU according to one aspect of the present invention is applied for example, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), or a batting practice machine installed in a sports facility. A throwing machine and the like can be mentioned.
- Chips such as CPUs and GPUs can be applied to large computers.
- FIG. 13E is a diagram showing a supercomputer 5500, which is an example of a large computer.
- FIG. 13F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.
- the supercomputer 5500 has a rack 5501 and a plurality of rack mount type computers 5502.
- the plurality of computers 5502 are stored in the rack 5501. Further, the computer 5502 is provided with a plurality of substrates 5504, and the GPU or the chip described in the above embodiment can be mounted on the substrate.
- the supercomputer 5500 is a large computer mainly used for scientific and technological calculations. In scientific and technological calculations, it is necessary to process a huge amount of calculations at high speed, so power consumption is high and the heat generated by the chip is large.
- a chip such as a CPU or GPU according to one aspect of the present invention to the supercomputer 5500, a supercomputer having low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
- 13E and 13F show a supercomputer as an example of a large computer, but the large computer to which a chip such as a CPU or GPU according to one aspect of the present invention is applied is not limited to this.
- Examples of a large-scale computer to which a chip such as a CPU or GPU according to one aspect of the present invention is applied include a computer (server) for providing a service, a large-scale general-purpose computer (mainframe), and the like.
- [Mobile] Chips such as CPUs and GPUs according to one aspect of the present invention can be applied to a moving vehicle and the vicinity of the driver's seat of the vehicle.
- FIG. 13G is a diagram showing the periphery of the windshield in the interior of an automobile, which is an example of a moving body.
- the display panel 5701 attached to the dashboard, the display panel 5702, the display panel 5703, and the display panel 5704 attached to the pillar are illustrated.
- the display panel 5701 to the display panel 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, an air conditioner setting, and the like.
- the display items, layout, and the like displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved.
- the display panel 5701 to 5703 can also be used as a lighting device.
- the display panel 5704 can supplement the field of view (blind spot) blocked by the pillars by projecting an image from an image pickup device (not shown) provided in the automobile. That is, by displaying the image from the image pickup device provided on the outside of the automobile, the blind spot can be supplemented and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, it is possible to confirm safety more naturally and without discomfort.
- the display panel 5704 can also be used as a lighting device.
- the chip can be used, for example, in an automatic driving system of an automobile.
- the chip can be used in a system for performing road guidance, danger prediction, and the like.
- the display panel 5701 to the display panel 5704 may be configured to display information such as road guidance and danger prediction.
- moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the chip of one aspect of the present invention is applied to these moving objects. Therefore, it is possible to provide a system using artificial intelligence.
- FIG. 13H shows an electric freezer / refrigerator 5800 which is an example of an electric appliance.
- the electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
- the electric refrigerator-freezer 5800 has a function to automatically generate foods based on the foodstuffs stored in the electric refrigerator-freezer 5800, the expiration date of the foodstuffs, etc., and the foodstuffs stored in the electric food-freezer refrigerator 5800. It can have a function of automatically adjusting the temperature according to the above.
- electric refrigerator / freezer has been described as an example of electric appliances
- other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner including an air conditioner.
- air conditioner including an air conditioner. Examples include washing machines, dryers, and audiovisual equipment.
- the electronic device described in this embodiment the function of the electronic device, the application example of artificial intelligence, its effect, etc. can be appropriately combined with the description of other electronic devices.
- FIGS. 14A to 14C show the results of the device simulation.
- FIG. 14A shows an Id-Vg curve
- FIG. 14B shows an enlarged region of Id from 1 ⁇ 10 -15 A to 1 ⁇ 10 -12 A
- FIG. 14C shows the horizontal axis as the range of the previous Id.
- the S value in Id is calculated.
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Abstract
Description
図2は、半導体装置に係る積和演算回路の構成例を示す回路図である。
図3は、半導体装置の動作例を示すタイミングチャートである。
図4は、期間T1~T2における動作状態を示す説明図である。
図5は、期間T3~T4における動作状態を示す説明図である。
図6は、期間T5以降における動作状態を示す説明図である。
図7は、半導体装置の動作例を示すタイミングチャートである。
図8は、期間T6~T7における動作状態を示す説明図である。
図9は、期間T8~T9における動作状態を示す説明図である。
図10は、期間T10以降における動作状態を示す説明図である。
図11A、及び図11Bは、半導体装置に係るトランジスタの構成例を示す断面模式図である。
図12AはIGZOの結晶構造の分類を説明する図であり、図12Bは結晶性IGZOのXRDスペクトルを説明する図であり、図12Cは結晶性IGZOの極微電子線回折パターンを説明する図である。
図13A乃至図13Hは電子機器を示す図である。
図14Aは、デバイスシミュレーションによるId−Vgカーブを示す図であり、図14Bは、図14Aの一部を拡大した図である。図14Cは、図14BのIdを横軸として各IdにおけるS値を算出した図である。
本実施の形態では、本発明の一態様の半導体装置について説明する。
本実施の形態で説明する半導体装置は、一例として、図1に示すようにTGSA(Trench gate self align)構造を有するトランジスタである。当該トランジスタは、バックチャネル側にも導電層103を有し、導電層103と、半導体層130との間の絶縁膜を有する。当該絶縁膜には、強誘電体層120が含まれている。ここで、半導体層130において、ゲート電極160に近い側をフロントチャネル側とし、ゲート電極から遠い側をバックチャネル側と称する。トランジスタの構造としては、TGSA構造に限定されず、いわゆるトップゲート型構造、ボトムゲート型構造などを採用してよい。それらの構造において、バックチャネル側に、導電層103と強誘電体層120を設ければよい。強誘電体層120には、強誘電性を有しうる材料を強誘電性が発現する状態で用いればよい。
本実施の形態では、上記実施の形態で説明したトランジスタを備えた積和演算回路について説明する。
図2は、積和演算に用いることが可能な回路(積和演算回路)の一例である。当該回路を一つのセルとして行方向にm個(mは2以上の整数)、列方向にn個(nは2以上の整数)のマトリクス状に設けて積和演算回路としてもよい。以降では、簡略化のため、図2に示すように一つのセルの演算回路で説明をすることとする。当該回路は、トランジスタTr1、トランジスタTr2、トランジスタM1、トランジスタM2、容量C1、及び容量C2を有する。ここで、トランジスタM1、トランジスタM2は、実施の形態1で説明したトランジスタ作製後にS値を大きくすることが出来るトランジスタを用いることができる。このトランジスタM1、及びトランジスタM2のS値を大きくすることで、積和演算回路を動作させるための電圧の範囲を広くすることが可能となる。また、トランジスタTr1、及びトランジスタTr2には、低いオフ電流で且つ小さなS値を有するOSトランジスタを用いることで、低消費電力で且つ回路の高速動作が可能な積和演算回路を実現できる。また、トランジスタTr1、及びトランジスタTr2は、シングルゲート構造としてもよいし、デュアルゲート構造としてもよい。いずれの構造でも、トランジスタM1、及びトランジスタM2と同時の工程で作製することが可能である。
次に、図2の演算回路の動作例について説明する。
はじめに、トランジスタTr1、トランジスタTr2、トランジスタM1、及びトランジスタM2を作製後において、トランジスタTr1、トランジスタTr2、トランジスタM1、及びトランジスタM2のトランジスタにおける、しきい電圧Vthが正の場合について説明する。また、トランジスタTr1、トランジスタTr2、トランジスタM1、及びトランジスタM2のしきい電圧Vthはそれぞれ同一であると仮定する。また、トランジスタTr1、トランジスタTr2、トランジスタM1、及びトランジスタM2のそれぞれのS値は、初期値においてS1であるとする。
次に、強誘電体層への書き込みが終わったトランジスタM1、及びトランジスタM2での演算処理について述べる。なお、配線x及び配線yに流れる電流をそれぞれId1、Id2とする。初期状態(図3:T3~T4、図5)として、配線gに高レベル電位Vhiを印加して、入力側配線xに、基準電流値Ix0を流し、出力側配線yに基準電流値のw倍である電流値w×Ix0を流す。基準電流値Ix0及び電流値w×Ix0は、トランジスタM1、及びトランジスタM2のサブスレッショルド領域で動作するときに流れる電流量として設定される。配線gが高レベル電位Vhiであるため、トランジスタTr1、及びトランジスタTr2はオン状態となり、時間の経過と共に、トランジスタM1、及びトランジスタM2のゲートG1、及びゲートG2は、それぞれ基準電流値Ix0及び電流値w×Ix0に応じた電位となるが、この電位はそれぞれ、配線x、配線yに印加される電位に等しい。ここでは、それらの電位をVg1、Vg2とする。
次に(図3:T5~、図6)、配線gの電位は接地電位のまま、入力側配線xに基準電流値のx倍である電流値x×Ix0を流す。配線gの電位が接地電位のため、トランジスタTr1はオフ状態であり、トランジスタTr1を介して電流は流れないが、トランジスタM1のゲートG1の電位は、容量C1による容量結合によって、電流値x×Ix0に応じた電位に変化する。電位の変化量をΔとする。このとき、容量C1の周辺における容量結合係数を1とした場合、配線x及びトランジスタM1のゲートG1の電位は、Vg1+Δとなる。
次に、トランジスタTr1、トランジスタTr2、トランジスタM1、及びトランジスタM2を作製後において、トランジスタTr1、トランジスタTr2、トランジスタM1、及びトランジスタM2のトランジスタにおける、しきい電圧Vthが負の場合について説明する。
初期状態(図7:T8~T9、図9)として、配線gに接地電位GND(なお、接地電位GNDはVthよりも高い)を印加して、入力側配線xに、基準電流値Ix0を流し、出力側配線yに基準電流値のw倍である電流値w×Ix0を流す。基準電流値Ix0及び電流値w×Ix0は、トランジスタM1、M2のサブスレッショルド領域で動作するときに流れる電流量として設定されるが、Vthが負であるため、入力側配線x及び出力側配線yには、接地電位GNDよりも低レベルの電位を印加することとなる。
次に(図7:T10~、図10)、配線gの電位は低レベル電位Vloのまま、入力側配線xに基準電流値のx倍である電流値x×Ix0を流す。配線gの電位が低レベル電位Vloのため、トランジスタTr1はオフ状態であり、トランジスタTr1を介して電流は流れないが、トランジスタM1のゲートG1の電位は、容量C1による容量結合によって、電流値x×Ix0に応じた電位に変化する。このとき、容量C1の周辺における容量結合係数を1とした場合、配線x及びトランジスタM1のゲートG1の電位は、Vg1+Δとなる。
本実施の形態では、上記実施の形態で説明した半導体装置の構成例、及び半導体装置に適用できるトランジスタの構成例について説明する。
本実施の形態では、上記の実施の形態で説明したOSトランジスタに用いることができる金属酸化物(以下、酸化物半導体ともいう。)について説明する。
まず、酸化物半導体における、結晶構造の分類について、図12Aを用いて説明を行う。図12Aは、酸化物半導体、代表的にはIGZO(Inと、Gaと、Znと、を含む金属酸化物)の結晶構造の分類を説明する図である。
なお、酸化物半導体は、結晶構造に着目した場合、図12Aとは異なる分類となる場合がある。例えば、酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、上述のCAAC−OS、及びnc−OSがある。また、非単結晶酸化物半導体には、多結晶酸化物半導体、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)、非晶質酸化物半導体、などが含まれる。
CAAC−OSは、複数の結晶領域を有し、当該複数の結晶領域はc軸が特定の方向に配向している酸化物半導体である。なお、特定の方向とは、CAAC−OS膜の厚さ方向、CAAC−OS膜の被形成面の法線方向、またはCAAC−OS膜の表面の法線方向である。また、結晶領域とは、原子配列に周期性を有する領域である。なお、原子配列を格子配列とみなすと、結晶領域とは、格子配列の揃った領域でもある。さらに、CAAC−OSは、a−b面方向において複数の結晶領域が連結する領域を有し、当該領域は歪みを有する場合がある。なお、歪みとは、複数の結晶領域が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。つまり、CAAC−OSは、c軸配向し、a−b面方向には明らかな配向をしていない酸化物半導体である。
nc−OSは、微小な領域(例えば、1nm以上10nm以下の領域、特に1nm以上3nm以下の領域)において原子配列に周期性を有する。別言すると、nc−OSは、微小な結晶を有する。なお、当該微小な結晶の大きさは、例えば、1nm以上10nm以下、特に1nm以上3nm以下であることから、当該微小な結晶をナノ結晶ともいう。また、nc−OSは、異なるナノ結晶間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、nc−OSは、分析方法によっては、a−like OS、及び非晶質酸化物半導体と区別が付かない場合がある。例えば、nc−OS膜に対し、XRD装置を用いて構造解析を行うと、θ/2θスキャンを用いたOut−of−plane XRD測定では、結晶性を示すピークが検出されない。また、nc−OS膜に対し、ナノ結晶よりも大きいプローブ径(例えば50nm以上)の電子線を用いる電子線回折(制限視野電子線回折ともいう。)を行うと、ハローパターンのような回折パターンが観測される。一方、nc−OS膜に対し、ナノ結晶の大きさと近いかナノ結晶より小さいプローブ径(例えば1nm以上30nm以下)の電子線を用いる電子線回折(ナノビーム電子線回折ともいう。)を行うと、ダイレクトスポットを中心とするリング状の領域内に複数のスポットが観測される電子線回折パターンが取得される場合がある。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。a−like OSは、鬆又は低密度領域を有する。即ち、a−like OSは、nc−OS及びCAAC−OSと比べて、結晶性が低い。また、a−like OSは、nc−OS及びCAAC−OSと比べて、膜中の水素濃度が高い。
次に、上述のCAC−OSの詳細について、説明を行う。なお、CAC−OSは材料構成に関する。
CAC−OSとは、例えば、金属酸化物を構成する元素が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つまたは複数の金属元素が偏在し、該金属元素を有する領域が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで混合した状態をモザイク状、またはパッチ状ともいう。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
本発明の一態様に係る半導体装置は、CPU、GPUなどのプロセッサ、またはチップに用いることができる。上記実施の形態に示す半導体装置を、CPU、GPUなどのプロセッサ、またはチップに用いることで、これらを小型化し、さらに低消費電力化できる。図13A乃至図13Hに、本発明の一態様に係るCPU、GPUなどのプロセッサ、またはチップを備えた電子機器の具体例を示す。
本発明の一態様に係るCPU、GPUなどのチップは、様々な電子機器に搭載することができる。電子機器の例としては、例えば、テレビジョン装置、デスクトップ型またはノート型の情報端末用などのモニタ、デジタルサイネージ(電子看板)、パチンコ機などの大型ゲーム機、などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、電子ブックリーダー、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。また、本発明の一態様に係るGPUまたはチップを電子機器に設けることにより、電子機器に人工知能を搭載することができる。
図13Aには、情報端末の一種である携帯電話(スマートフォン)が図示されている。情報端末5100は、筐体5101と、表示部5102と、を有しており、入力用インターフェースとして、タッチパネルが表示部5102に備えられ、ボタンが筐体5101に備えられている。
図13Cは、ゲーム機の一例である携帯ゲーム機5300を示している。携帯ゲーム機5300は、筐体5301、筐体5302、筐体5303、表示部5304、接続部5305、操作キー5306等を有する。筐体5302、および筐体5303は、筐体5301から取り外すことが可能である。筐体5301に設けられている接続部5305を別の筐体(図示せず)に取り付けることで、表示部5304に出力される映像を、別の映像機器(図示せず)に出力することができる。このとき、筐体5302、および筐体5303は、それぞれ操作部として機能することができる。これにより、複数のプレイヤーが同時にゲームを行うことができる。筐体5301、筐体5302、および筐体5303の基板に設けられているチップなどに先の実施の形態に示すチップを組み込むことができる。
本発明の一態様のCPU、GPUなどのチップは、大型コンピュータに適用することができる。
本発明の一態様のCPU、GPUなどのチップは、移動体である自動車、および自動車の運転席周辺に適用することができる。
図13Hは、電化製品の一例である電気冷凍冷蔵庫5800を示している。電気冷凍冷蔵庫5800は、筐体5801、冷蔵室用扉5802、冷凍室用扉5803等を有する。
Claims (6)
- チャネル形成領域を有する酸化物半導体層と、前記酸化物半導体層と絶縁層を介して重なる領域を有するゲート電極と、前記酸化物半導体層と強誘電体層を介して重なる領域を有する第1の導電層と、を有するトランジスタであって、
前記強誘電体層は、結晶を有し、
前記結晶は、強誘電性を発現する結晶構造であるトランジスタ。 - チャネル形成領域を有する第1の酸化物半導体層と、第1の絶縁層と、前記第1の酸化物半導体層と前記第1の絶縁層を介して重なる領域を有する第1のゲート電極と、前記第1の酸化物半導体層と強誘電体層を介して重なる領域を有する第1の導電層と、を有する第1のトランジスタと、
チャネル形成領域を有する第2の酸化物半導体層と、第2の絶縁層と、前記第2の酸化物半導体層と前記第2の絶縁層を介して重なる領域を有する第2のゲート電極と、前記強誘電体層と、を有する第2のトランジスタと、を有し、
前記第2のトランジスタは、前記強誘電体層を介して前記第2の酸化物半導体層と重なる領域に、前記強誘電体層に接する導電層を有さず、
前記強誘電体層は、結晶を有し、
前記結晶は、強誘電性を発現する結晶構造である半導体装置。 - 第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、第4のトランジスタと、第1の容量と、第2の容量と、を有し、
前記第1のトランジスタのゲートと、前記第2のトランジスタのゲートは、第1の配線に電気的に接続され、
前記第1のトランジスタのソースまたはドレインの一方と、前記第3のトランジスタのソースまたはドレインの一方は、第2の配線に電気的に接続され、
前記第1のトランジスタのソースまたはドレインの他方は、前記第3のトランジスタのゲートと電気的に接続され、
前記第2のトランジスタのソースまたはドレインの一方と、前記第4のトランジスタのソースまたはドレインの一方は、第3の配線に電気的に接続され、
前記第2のトランジスタのソースまたはドレインの他方は、前記第4のトランジスタのゲートと電気的に接続され、
前記第3のトランジスタのゲートは、第1の容量を介して前記第2の配線に接続され、
前記第4のトランジスタのゲートは、第2の容量を介して前記第2の配線に接続され、
前記第3のトランジスタ及び前記第4のトランジスタは、それぞれ、
チャネル形成領域を有する第1の酸化物半導体層と、前記第1の酸化物半導体層と第1の絶縁層を介して重なる領域を有する第1のゲート電極と、前記第1の酸化物半導体層と強誘電体層を介して重なる領域を有する第1の導電層と、を有し、
前記第1のトランジスタ及び前記第2のトランジスタは、それぞれ、
チャネル形成領域を有する第2の酸化物半導体層と、前記第2の酸化物半導体層と第2の絶縁層を介して重なる領域を有する第2のゲート電極と、前記強誘電体層と、を有し、
前記強誘電体層は、結晶を有し、
前記結晶は、強誘電性を発現する結晶構造である半導体装置。 - 請求項1乃至請求項3のいずれか一において、
前記強誘電体層は、強誘電性を有する材料としてハフニウム及びジルコニウムの一方、又は双方を含む酸化物を有する半導体装置。 - 請求項1乃至請求項4のいずれか一において、
前記第1の導電層と前記酸化物半導体層との間に電界を印加することにより、前記強誘電体層に分極を発生させる半導体装置。 - 第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、第4のトランジスタと、第1の容量と、第2の容量と、を有し、
前記第1のトランジスタのゲートと、前記第2のトランジスタのゲートは、第1の配線に電気的に接続され、
前記第1のトランジスタのソースまたはドレインの一方と、前記第3のトランジスタのソースまたはドレインの一方は、第2の配線に電気的に接続され、
前記第1のトランジスタのソースまたはドレインの他方は、前記第3のトランジスタのゲートと電気的に接続され、
前記第2のトランジスタのソースまたはドレインの一方と、前記第4のトランジスタのソースまたはドレインの一方は、第3の配線に電気的に接続され、
前記第2のトランジスタのソースまたはドレインの他方は、前記第4のトランジスタのゲートと電気的に接続され、
前記第3のトランジスタのゲートは、第1の容量を介して前記第2の配線に接続され、
前記第4のトランジスタのゲートは、第2の容量を介して前記第2の配線に接続され、
前記第3のトランジスタのS値と前記第4のトランジスタのS値は、前記第1のトランジスタのS値よりも大きい半導体装置。
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JP2011049537A (ja) * | 2009-08-25 | 2011-03-10 | Korea Electronics Telecommun | 不揮発性メモリセル及びその製造方法 |
WO2017090559A1 (ja) * | 2015-11-25 | 2017-06-01 | 東レ株式会社 | 強誘電体記憶素子、その製造方法、ならびにそれを用いたメモリセルおよびそれを用いた無線通信装置 |
WO2018234919A1 (ja) * | 2017-06-21 | 2018-12-27 | 株式会社半導体エネルギー研究所 | ニューラルネットワークを有する半導体装置 |
JP2019023853A (ja) * | 2017-05-03 | 2019-02-14 | 株式会社半導体エネルギー研究所 | ニューラルネットワーク、蓄電システム、車両、及び電子機器 |
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JP2011049537A (ja) * | 2009-08-25 | 2011-03-10 | Korea Electronics Telecommun | 不揮発性メモリセル及びその製造方法 |
WO2017090559A1 (ja) * | 2015-11-25 | 2017-06-01 | 東レ株式会社 | 強誘電体記憶素子、その製造方法、ならびにそれを用いたメモリセルおよびそれを用いた無線通信装置 |
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