WO2022104856A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022104856A1
WO2022104856A1 PCT/CN2020/131416 CN2020131416W WO2022104856A1 WO 2022104856 A1 WO2022104856 A1 WO 2022104856A1 CN 2020131416 W CN2020131416 W CN 2020131416W WO 2022104856 A1 WO2022104856 A1 WO 2022104856A1
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Prior art keywords
layer
sub
common electrode
insulating layer
disposed
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PCT/CN2020/131416
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English (en)
French (fr)
Inventor
许森
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Priority to US16/973,479 priority Critical patent/US11977304B2/en
Publication of WO2022104856A1 publication Critical patent/WO2022104856A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • the present invention relates to the field of display technology, and in particular, to a display panel and a display device with an ultra-narrow frame.
  • the storage capacitor can use the scanning line of the upper row of the pixel as the potential reference electrode, and this technical scheme is generally referred to as Cst On gate, that is, the pixel electrode and the scan line coincide.
  • the common electrode trace adopts a ring-shaped seal design, which will reduce the pixel density.
  • the aperture ratio of the electrodes if the single-sided Acom wiring design is used, if the single-sided Acom wiring is disconnected, it will affect the alignment of the liquid crystal; if the Acom-free wiring design is used, the problem of dark spots in the subsequent process will be affected, which will affect the display effect of the panel. .
  • An object of the present invention is to provide a display panel, in which the first common electrode wiring is arranged below the electrode trunk, which can reduce a shadow and increase the penetration rate.
  • the present invention provides a display panel, which includes a plurality of sub-pixels, and the sub-pixels are arranged in an array; wherein, the sub-pixels include: a first common electrode wiring; Two electrode trunks; wherein, the first common electrode wiring is arranged below the first electrode trunk.
  • the sub-pixel further includes: a second common electrode wiring, which is arranged at a corner of the sub-pixel, and is connected to the first common electrode wiring through a first connecting line.
  • the sub-pixel further includes: a second connection line, one end of which is connected to the second common electrode line, and the other end extends to adjacent sub-pixels along the boundary of the sub-pixel.
  • the sub-pixels further include: thin film transistors, which are disposed at opposite corners of the corners of the sub-pixels.
  • the sub-pixel further includes: a scan line disposed below the pixel electrode and connected to the thin film transistor.
  • the cross-sectional structure of the sub-pixel includes: a first metal layer, and the second common electrode wiring is formed in the first metal layer; a first insulating layer , set on the first metal layer; the active layer, set on the first insulating layer; the second metal layer, set on the active layer; the second insulating layer, set on the active layer layer and the first insulating layer, the second insulating layer is provided with a first slot, the first slot is recessed to the upper surface of the second metal layer; the color resist layer is arranged on the On the second insulating layer, the color resist layer has a second slot, and the second slot is recessed to the upper surface of the second insulating layer; the third insulating layer is disposed on the color resist layer, The third insulating layer has a third slot corresponding to the first slot, the first slot is connected to the third slot; and a transparent electrode layer is provided between the second slot and the third slot. in the first slot.
  • first common electrode wiring, the first connecting line and the second common electrode wiring are prepared on the same metal layer.
  • first common electrode wiring, the first connecting line, the second common electrode wiring and the second connecting line are prepared on the same metal layer.
  • first common electrode wiring and the scanning line are prepared in the same layer.
  • the layered structure of the sub-pixel includes: a gate layer; a first insulating layer, disposed on the gate layer; and an active layer, disposed on the first insulating layer a second metal layer, arranged on the active layer; a second insulating layer, arranged on the active layer, the second metal layer and the first insulating layer; a color resist layer, arranged on the on the second insulating layer; and a third insulating layer on the color resist layer.
  • the present invention provides a display panel, using a new common electrode wiring design, since the position of the electrode trunk in the pixel electrode itself is a dark area, the first common electrode wiring is arranged on the electrode Below the trunk, in order to achieve the purpose of reducing a shadow and increasing the penetration rate.
  • the pattern of the pixel electrode of the second common electrode line is an ITO pattern that shields the electric field to prevent light leakage, which can prevent light leakage from the second common electrode line.
  • FIG. 1 is a schematic diagram of a sub-pixel structure in the prior art.
  • FIG. 2 is a schematic diagram of a sub-pixel structure provided by the present invention.
  • FIG. 3 is a cross-sectional view of the second common electrode wiring in FIG. 2 of the present invention.
  • FIG. 4 is a cross-sectional view of the thin film transistor shown in FIG. 2 of the present invention.
  • Sub-pixel 110 first common electrode wiring 101; second common electrode wiring 102;
  • the third insulating layer 118 the transparent electrode layer 119 .
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, “plurality” means two or more. Additionally, the term “comprising” and any variations thereof are intended to cover non-exclusive inclusion.
  • the present invention provides a display panel 100 , which includes a plurality of sub-pixels 110 , and the sub-pixels 110 are arranged in an array.
  • the sub-pixel 110 includes: a first common electrode line 101 , a second common electrode line 102 , a first connection line 104 , a second connection line 105 and a pixel electrode 103 .
  • the pixel electrode 103 includes a first electrode trunk 1031 and a second electrode trunk 1032 arranged perpendicular to each other.
  • the first electrode trunk 1031 bisects the second electrode trunk 1032 vertically.
  • the material of the pixel electrode 103 includes indium tin oxide.
  • the pixel electrode 103 further includes electrode branches 1033 which are respectively connected obliquely to the first electrode trunk 1031 and the second electrode trunk 1032 .
  • the pixel electrode 103 has four domains, and the electrode branches 1033 in different domain regions are symmetrical with respect to the first electrode trunk 1031 and the second electrode trunk 1032 .
  • the first common electrode trace 101 is disposed below the first electrode trunk 1031 .
  • the second common electrode traces 102 are disposed at the corners of the sub-pixels 110 , and are connected to the first common electrode traces 101 through the first connection wires 104 .
  • a transparent electrode layer is provided on the second common electrode wiring 102 , and the pattern of the pixel electrode 103 is an ITO pattern that shields the electric field to prevent light leakage, which can prevent the second common electrode wiring 102 from leaking light.
  • the transparent electrode layer can be divided into two types of electrical signals, namely pixel electrodes and data shading (data BM less, DBS)
  • the first electrode trunk 1031/second electrode trunk 1032/electrode branch 1033 can be collectively referred to as pixel electrodes, so the pixel electrodes are used to control the deflection of the liquid crystal to control the amount of light transmission, so that the panel presents different brightness.
  • the DBS is completely separated from the pixel electrodes and is a special electrode pattern.
  • the DBS is used for shading, but the DBS and the pixel electrode are also electrode patterns, and the assigned electrical signals are different. If they are connected together, a short circuit will occur, so a gap will appear at the position of the second common electrode trace 102. The gap is where the light leaks.
  • the second common electrode wiring 102 is used to pass through this gap. Because the second common electrode wiring 102 is made of metal material, it is opaque to light, so it can be Shielding the light of the light source has achieved the purpose of shielding light leakage.
  • the design of the new common electrode wiring is used. Since the position of the electrode trunk in the pixel electrode 103 itself is a dark area, the first common electrode wiring 101 is arranged under the electrode trunk to reduce a shadow. The purpose of increasing the penetration rate.
  • connection line 105 One end of the second connection line 105 is connected to the second common electrode trace 102 , and the other end extends to the adjacent sub-pixels 110 along the boundary of the sub-pixels 110 .
  • the first common electrode wiring 101 , the second common electrode wiring 102 , the scanning line 106 , the first connecting line 104 and the second connecting line 105 are formed in the first metal layer 112 .
  • the sub-pixel 110 further includes: a thin film transistor 120 and a scan line 106 .
  • the thin film transistors 120 are disposed at opposite corners of the corners.
  • the scan line 106 is disposed below the pixel electrode 103 and connected to the thin film transistor 120 .
  • the cross-sectional structure of the sub-pixel 110 includes: the first metal layer 112 , the first insulating layer 113 , the active layer 114 , and the second metal layer layer 115 , the second insulating layer 116 , the color resist layer 117 , the third insulating layer 118 and the transparent electrode layer 119 .
  • the first metal layer 112 and the second common electrode traces 102 are formed in the first metal layer 112 .
  • the first insulating layer 113 is disposed on the first metal layer 112 .
  • the active layer 114 is disposed on the first insulating layer 113 .
  • the second metal layer 115 is disposed on the active layer 114 .
  • the second insulating layer 116 On the active layer 114 and the first insulating layer 113 , the second insulating layer 116 has a first slot 1161 , and the first slot 1161 is recessed to the second metal layer 115 the upper surface.
  • the color resist layer 117 is disposed on the second insulating layer 116 , and the color resist layer 117 has a second slot 1171 , and the second slot 1171 is recessed to the upper surface of the second insulating layer 116 .
  • the color resist layer 117 is R/G/B color resist.
  • the positions of the first slot 1161 and the second slot 1171 are overlapped, that is, during preparation, the second slot 1171 is first opened, and then the bottom of the second slot 1171 is opened. The first slot 1161 is opened.
  • the third insulating layer 118 is disposed on the color resist layer 117, the third insulating layer 118 has a third slot 1181 corresponding to the first slot 1161, and the first slot 1161 is connected The third slot 1181.
  • the transparent electrode layer 119 is disposed in the second slot 1171 and the first slot 1161 .
  • the pattern of the transparent electrode layer 119 here is an ITO pattern that shields the electric field to prevent light leakage, which can prevent the second common electrode trace 102 from leaking light.
  • the transparent electrode layer 119 is used to connect the pixel electrode 103 and the second metal layer 115 .
  • the patterned transparent electrode layer 119 is the pixel electrode 103 .
  • the first common electrode traces 101 , the first connection wires 104 and the second common electrode traces 102 are fabricated on the same metal layer.
  • the first common electrode trace 101 , the first connection wire 104 , the second common electrode trace 102 and the second connection wire 105 are fabricated on the same metal layer.
  • the first common electrode traces 101 and the scan lines 106 are fabricated in the same layer.
  • the layered structure of the sub-pixel 110 includes: a gate layer 121 , a first insulating layer 113 , an active layer 114 , a second metal layer 115 , and a second insulating layer layer 116 , color resist layer 117 and third insulating layer 118 .
  • the first insulating layer 113 is disposed on the gate layer 121 .
  • the active layer 114 is disposed on the first insulating layer 113 .
  • the second metal layer 115 is disposed on the active layer 114 .
  • the second insulating layer 116 is disposed on the active layer 114 , the second metal layer 115 and the first insulating layer 113 .
  • the color resist layer 117 is disposed on the second insulating layer 116 ; the third insulating layer 118 is disposed on the color resist layer 117 .
  • the present invention also provides a display device, wherein the display device includes the display panel of the present invention.

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  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
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Abstract

一种显示面板（100）及显示装置，显示面板（100）包括若干子像素（110），子像素（110）包括：第一公共电极走线（101）、第二公共电极走线（102）、第一连接线（104）、第二连接线（105）以及像素电极（103）。子像素结构使用新的公共电极走线的设计，由于像素电极（103）内电极主干的位置本身是暗区，从而将第一公共电极走线（101）设置在电极主干的下方，以达到减少一道暗影，增加穿透率的目的。

Description

显示面板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种超窄边框的显示面板及显示装置。
 背景技术
现有液晶显示器的像素设计方案中，存储电容可以使用像素上一行的扫描线作为电位参考电极，该技术方案一般被称为Cst on gate，即像素电极和扫描线重合。
 技术问题
如图1所示，如果下板共电极也同传统的Cst on COM(下板共电极作为电位参考电极)设计方法一样，公共电极走线（Acom走线）采用环形四周封口设计，会降低像素电极的开口率。而如果使用单侧Acom走线设计，如果单侧的Acom走线断线，会影响液晶配向；使用无Acom走线设计，会使后续制程中无法暗点化的问题，会影响面板的显示效果。
因此，有必要提供一种显示面板，采用新的Acom走线设计，可以降低像素电极的开口率。
 技术解决方案
本发明一目的提供一种显示面板，将第一公共电极走线设置在电极主干的下方，能够减少一道暗影，增加穿透率。
本发明提供一种显示面板，包括多个子像素，所述子像素阵列设置；其中，所述子像素中包括：第一公共电极走线；像素电极，包括相互垂直设置的第一电极主干以及第二电极主干；其中，所述第一公共电极走线设于所述第一电极主干的下方。
进一步地，所述子像素还包括：第二公共电极走线，设于所述子像素的边角处，通过一第一连接线连接所述第一公共电极走线。
进一步地，所述子像素还包括：第二连接线，一端连接所述第二公共电极走线，另一端沿着所述子像素的边界延伸至相邻的子像素。
进一步地，所述子像素还包括：薄膜晶体管，设于所述子像素的边角的对角处。
进一步地，所述子像素还包括：扫描线，设于所述像素电极的下方且连接所述薄膜晶体管。
进一步地，在所述第二公共电极走线处，所述子像素的剖面结构包括：第一金属层，所述第二公共电极走线形成于所述第一金属层中；第一绝缘层，设于所述第一金属层上；有源层，设于所述第一绝缘层上；第二金属层，设于所述有源层上；第二绝缘层，设于所述有源层以及所述第一绝缘层上，所述第二绝缘层设有一第一开槽，所述第一开槽下凹至所述第二金属层的上表面；色阻层，设于所述第二绝缘层上，所述色阻层具有第二开槽，所述第二开槽下凹至所述第二绝缘层的上表面；第三绝缘层，设于所述色阻层上，所述第三绝缘层具有与所述第一开槽相对应的第三开槽 ，所述第一开槽连接所述第三开槽；以及透明电极层，设于所述第二开槽与所述第一开槽中。
进一步地，所述第一公共电极走线、所述第一连接线以及所述第二公共电极走线制备于同一金属层。
进一步地，所述第一公共电极走线、所述第一连接线、所述第二公共电极走线以及所述第二连接线制备于同一金属层。
进一步地，所述第一公共电极走线与所述扫描线制备于同一层。
进一步地，在所述薄膜晶体管处，所述子像素的层状结构包括：栅极层；第一绝缘层，设于所述栅极层上；有源层，设于所述第一绝缘层上；第二金属层，设于所述有源层上；第二绝缘层，设于所述有源层、所述第二金属层以及所述第一绝缘层上；色阻层，设于所述第二绝缘层上；第三绝缘层，设于所述色阻层上。
 有益效果
本申请的有益效果为：本发明中提供一种显示面板，使用新的公共电极走线的设计，由于像素电极内电极主干的位置本身是暗区，从而将第一公共电极走线设置在电极主干的下方，以达到减少一道暗影，增加穿透率的目的。并且所述第二公共电极走线的像素电极的图案为遮蔽电场防止漏光的ITO图案，可以防止第二公共电极走线漏光。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有技术子像素结构的示意图。
图2为本发明提供的子像素结构的示意图。
图3为本发明图2中所述第二公共电极走线的剖面图。
图4为本发明图2中所述薄膜晶体管处的剖面图。
显示面板100；
子像素110；第一公共电极走线101；第二公共电极走线102；
第一连接线104；第二连接线105；像素电极103；
薄膜晶体管120；扫描线106；第一电极主干1031；
第二电极主干1032；电极分支1033；栅极层121；
第一金属层112；第一绝缘层113；有源层114；
第二金属层115；第二绝缘层116；色阻层117；
第三绝缘层118；透明电极层119。
 本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
如图2所示，本发明提供一种显示面板100，包括多个子像素110，所述子像素110阵列设置。
其中，所述子像素110包括：第一公共电极走线101、第二公共电极走线102、第一连接线104、第二连接线105以及像素电极103。
所述像素电极103包括相互垂直设置的第一电极主干1031以及第二电极主干1032。所述第一电极主干1031垂直平分所述第二电极主干1032。
所述像素电极103的材料包括氧化铟锡。
所述像素电极103还包括电极分支1033，分别倾斜连接所述第一电极主干1031以及所述第二电极主干1032。
所述像素电极103具有四个畴，不同畴区域内的电极分支1033关于第一电极主干1031以及所述第二电极主干1032对称。
所述第一公共电极走线101设于所述第一电极主干1031的下方。
所述第二公共电极走线102设于所述子像素110的边角处，通过所述第一连接线104连接所述第一公共电极走线101。
所述第二公共电极走线102的上设有透明电极层，像素电极103的图案为遮蔽电场防止漏光的ITO图案，可以防止第二公共电极走线102漏光。
在本实施例中，透明电极层可分为两种电信号，分别是像素电极以及数据遮光（data BM less，DBS）
第一电极主干1031/第二电极主干1032/电极分支1033是可以统称为像素电极，所以像素电极是用来控制液晶偏转的，以控制光透过量，使面板呈现出不同的亮度。
DBS与像素电极是完全分开的，是一种特殊的电极图案。DBS是用来遮光的，但DBS与像素电极同样是电极图案，所赋予的电信号不同，若连在一起则会发生短路，所以在第二公共电极走线102的位置会出现一道缝隙，这道缝隙正是漏光的位置，本发明中使用第二公共电极走线102走线穿过这道缝隙，因第二公共电极走线102是金属材质，其本身是不透光的，所以可以是遮蔽光源的光，已达到遮蔽漏光的目的。
在本发明中使用新的公共电极走线的设计，由于像素电极103内电极主干的位置本身是暗区，从而将第一公共电极走线101设置在电极主干的下方，以达到减少一道暗影，增加穿透率的目的。
所述第二连接线105一端连接所述第二公共电极走线102，另一端沿着所述子像素110的边界延伸至相邻的子像素110。
所述第一公共电极走线101、所述第二公共电极走线102、扫描线106、所述第一连接线104以及所述第二连接线105形成于第一金属层112中。
在一实施例中，所述子像素110还包括：薄膜晶体管120以及扫描线106。
所述薄膜晶体管120设于所述边角的对角处。
所述扫描线106设于所述像素电极103的下方且连接所述薄膜晶体管120。
如图3所示，在所述第二公共电极走线102处，所述子像素110的剖面结构包括：所述第一金属层112、第一绝缘层113、有源层114、第二金属层115、第二绝缘层116、色阻层117、第三绝缘层118以及透明电极层119。
所述第一金属层112所述第二公共电极走线102形成于所述第一金属层112中。所述第一绝缘层113设于所述第一金属层112上。所述有源层114设于所述第一绝缘层113上。
所述第二金属层115设于所述有源层114上。所述第二绝缘层116。设于所述有源层114以及所述第一绝缘层113上，所述第二绝缘层116设有一第一开槽1161，所述第一开槽下1161凹至所述第二金属层115的上表面。
所述色阻层117设于所述第二绝缘层116上，所述色阻层117具有第二开槽1171，所述第二开槽1171下凹至所述第二绝缘层116的上表面。所述色阻层117为R/G/B色阻。所述第一开槽1161和所述第二开槽1171的位置是重叠设置的，即在制备的时候，先开设所述第二开槽1171，然后在所述第二开槽1171的槽底开设所述第一开槽1161。
所述第三绝缘层118设于所述色阻层117上，所述第三绝缘层118具有与所述第一开槽1161相对应的第三开槽1181 ，所述第一开槽1161连接所述第三开槽1181。
所述透明电极层119设于所述第二开槽1171与所述第一开槽1161中。在此处的透明电极层119的图案为遮蔽电场防止漏光的ITO图案，可以防止第二公共电极走线102漏光。在实施例中，所述透明电极层119用以将像素电极103和第二金属层115连接。
所述透明电极层119图案化即为所述像素电极103。
在一实施例中，所述第一公共电极走线101、所述第一连接线104以及所述第二公共电极走线102制备于同一金属层。
在一实施例中，所述第一公共电极走线101、所述第一连接线104、所述第二公共电极走线102以及所述第二连接线105制备于同一金属层。
在一实施例中，所述第一公共电极走线101与所述扫描线106制备于同一层。
如图4所示，在所述薄膜晶体管120处，所述子像素110的层状结构包括：栅极层121、第一绝缘层113、有源层114、第二金属层115、第二绝缘层116、色阻层117以及第三绝缘层118。
所述第一绝缘层113设于所述栅极层121上。所述有源层114设于所述第一绝缘层113上。
所述第二金属层115设于所述有源层114上。所述第二绝缘层116设于所述有源层114、所述第二金属层115以及所述第一绝缘层113上。
所述色阻层117设于所述第二绝缘层116上；所述第三绝缘层118设于所述色阻层117上。
本发明还提供一种显示装置，其中，所述显示装置包括本发明所述的显示面板。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，包括多个子像素，所述子像素阵列设置；
    其中，所述子像素包括：
    第一公共电极走线；以及
    像素电极，包括相互垂直设置的第一电极主干以及第二电极主干；
    其中，所述第一公共电极走线设于所述第一电极主干的下方。
  2. 如权利要求1所述的显示面板，其中，
    所述子像素还包括：
    第二公共电极走线，设于所述子像素的边角处，通过一第一连接线连接所述第一公共电极走线。
  3. 如权利要求2所述的显示面板，其中，
    所述子像素还包括：
    第二连接线，一端连接所述第二公共电极走线，另一端沿着所述子像素的边界延伸至相邻的子像素。
  4. 如权利要求1所述的显示面板，其中，
    所述子像素还包括：
    薄膜晶体管，设于所述子像素的边角的对角处。
  5. 如权利要求1所述的显示面板，其中，
    所述子像素还包括：
    扫描线，设于所述像素电极的下方且连接薄膜晶体管。
  6. 如权利要求2所述的显示面板，其中，
    在所述第二公共电极走线处，所述子像素的剖面结构包括：
    第一金属层，所述第二公共电极走线形成于所述第一金属层中；
    第一绝缘层，设于所述第一金属层上；
    有源层，设于所述第一绝缘层上；
    第二金属层，设于所述有源层上；
    第二绝缘层，设于所述有源层以及所述第一绝缘层上，所述第二绝缘层设有一第一开槽，所述第一开槽下凹至所述第二金属层的上表面；
    色阻层，设于所述第二绝缘层上，所述色阻层具有第二开槽，所述第二开槽下凹至所述第二绝缘层的上表面；
    第三绝缘层，设于所述色阻层上，所述第三绝缘层具有与所述第一开槽相对应的第三开槽，所述第一开槽连接所述第三开槽；以及
    透明电极层，设于所述第二开槽与所述第一开槽中。
  7. 如权利要求2所述的显示面板，其中，
    所述第一公共电极走线、所述第一连接线以及所述第二公共电极走线制备于同一金属层。
  8. 如权利要求3所述的显示面板，其中，
    所述第一公共电极走线、所述第一连接线、所述第二公共电极走线以及所述第二连接线制备于同一金属层。
  9. 如权利要求5所述的显示面板，其中，
    所述第一公共电极走线与所述扫描线制备于同一层。
  10. 如权利要求4所述的显示面板，其中，
    在所述薄膜晶体管处，所述子像素的层状结构包括：
    栅极层；
    第一绝缘层，设于所述栅极层上；
    有源层，设于所述第一绝缘层上；
    第二金属层，设于所述有源层上；
    第二绝缘层，设于所述有源层、所述第二金属层以及所述第一绝缘层上；
    色阻层，设于所述第二绝缘层上；
    第三绝缘层，设于所述色阻层上。
  11. 一种显示装置，包括一显示面板，其中，所述显示面板包括多个子像素，所述子像素阵列设置；
    其中，所述子像素包括：
    第一公共电极走线；以及
    像素电极，包括相互垂直设置的第一电极主干以及第二电极主干；
    其中，所述第一公共电极走线设于所述第一电极主干的下方。
  12. 如权利要求11所述的显示装置，其中，
    所述子像素还包括：
    第二公共电极走线，设于所述子像素的边角处，通过一第一连接线连接所述第一公共电极走线。
  13. 如权利要求12所述的显示装置，其中，
    所述子像素还包括：
    第二连接线，一端连接所述第二公共电极走线，另一端沿着所述子像素的边界延伸至相邻的子像素。
  14. 如权利要求11所述的显示装置，其中，
    所述子像素还包括：
    薄膜晶体管，设于所述子像素的边角的对角处。
  15. 如权利要求11所述的显示装置，其中，
    所述子像素还包括：
    扫描线，设于所述像素电极的下方且连接薄膜晶体管。
  16. 如权利要求12所述的显示装置，其中，
    在所述第二公共电极走线处，所述子像素的剖面结构包括：
    第一金属层，所述第二公共电极走线形成于所述第一金属层中；
    第一绝缘层，设于所述第一金属层上；
    有源层，设于所述第一绝缘层上；
    第二金属层，设于所述有源层上；
    第二绝缘层，设于所述有源层以及所述第一绝缘层上，所述第二绝缘层设有一第一开槽，所述第一开槽下凹至所述第二金属层的上表面；
    色阻层，设于所述第二绝缘层上，所述色阻层具有第二开槽，所述第二开槽下凹至所述第二绝缘层的上表面；
    第三绝缘层，设于所述色阻层上，所述第三绝缘层具有与所述第一开槽相对应的第三开槽，所述第一开槽连接所述第三开槽；以及
    透明电极层，设于所述第二开槽与所述第一开槽中。
  17. 如权利要求12所述的显示装置，其中，
    所述第一公共电极走线、所述第一连接线以及所述第二公共电极走线制备于同一金属层。
  18. 如权利要求13所述的显示装置，其中，
    所述第一公共电极走线、所述第一连接线、所述第二公共电极走线以及所述第二连接线制备于同一金属层。
  19. 如权利要求15所述的显示装置，其中，
    所述第一公共电极走线与所述扫描线制备于同一层。
  20. 如权利要求14所述的显示装置，其中，
    在所述薄膜晶体管处，所述子像素的层状结构包括：
    栅极层；
    第一绝缘层，设于所述栅极层上；
    有源层，设于所述第一绝缘层上；
    第二金属层，设于所述有源层上；
    第二绝缘层，设于所述有源层、所述第二金属层以及所述第一绝缘层上；
    色阻层，设于所述第二绝缘层上；
    第三绝缘层，设于所述色阻层上。
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