WO2022226982A1 - 一种显示基板及显示装置 - Google Patents

一种显示基板及显示装置 Download PDF

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Publication number
WO2022226982A1
WO2022226982A1 PCT/CN2021/091406 CN2021091406W WO2022226982A1 WO 2022226982 A1 WO2022226982 A1 WO 2022226982A1 CN 2021091406 W CN2021091406 W CN 2021091406W WO 2022226982 A1 WO2022226982 A1 WO 2022226982A1
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WIPO (PCT)
Prior art keywords
sub
pixel
display area
gate line
pixels
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Application number
PCT/CN2021/091406
Other languages
English (en)
French (fr)
Inventor
姜晶晶
刘晓那
马禹
陈维涛
邵喜斌
闫岩
曹薇
李晓颖
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/091406 priority Critical patent/WO2022226982A1/zh
Priority to CN202180001036.XA priority patent/CN115552624A/zh
Priority to US17/753,365 priority patent/US20240038776A1/en
Publication of WO2022226982A1 publication Critical patent/WO2022226982A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • the frame of the backlight module will block some pixels around the display panel.
  • the sub-pixel RGB loss of different pixels is inconsistent, resulting in a rainbow pattern on the edge of the screen, and the colors displayed on the left and right sides are also different.
  • Embodiments of the present disclosure provide a display substrate and a display device, which can improve the problem of iridescent patterns on the edge of narrow-frame products and improve product quality.
  • An embodiment of the present disclosure provides a display substrate, including a middle display area, and a first peripheral display area and a second peripheral display area located on opposite sides of the middle display area, the display area includes an array of pixel units, each The pixel unit includes at least two sub-pixels that emit light of different colors, and the opening shape of the sub-pixels is a rectangle, and the rectangle includes a long side and a short side; wherein,
  • the sub-pixels in each pixel unit are sequentially arranged along the extension direction of the short side of the sub-pixels, and all The extension direction of the first peripheral display area and the second peripheral display area is perpendicular to the extension direction of the short side of the sub-pixels in the intermediate display area, and at least one of the first peripheral display area and the second peripheral display area
  • the extension direction of the short side of the sub-pixels in the area is perpendicular to the extension direction of the short side of the sub-pixels in the middle display area.
  • the pixel unit includes at least a first sub-pixel, a second sub-pixel and a third sub-pixel;
  • the pixel opening area of the first sub-pixel in the middle display area is the same as that of the first peripheral display area and the first sub-pixel in the second peripheral display area;
  • the pixel opening area of the second sub-pixel in the middle display area is the same as that of the first peripheral display area and the second sub-pixel in the second peripheral display area;
  • the pixel opening area of the third sub-pixel in the middle display area is the same as that of the first peripheral display area and the third sub-pixel in the second peripheral display area.
  • the display substrate further includes crossed and insulated data lines and gate lines, each of the sub-pixels is provided with a thin film transistor and a pixel electrode, the gate of the thin film transistor is connected to the gate line, and the source is connected to the data.
  • the line is connected, the drain is connected with the pixel electrode;
  • the sources of the thin film transistors of the sub-pixels with different colors of light are respectively connected to different data lines;
  • the gates of the thin film transistors of each sub-pixel are connected to the same gate line adjacent to the pixel unit of the row, or to at least two gate lines adjacent to the pixel unit of the row. , and the gates of the thin film transistors of the sub-pixels of the same color are connected to the same gate line.
  • At least one grid line branch is further provided on the grid line, and the grid line branch is connected to the grid line.
  • the lines are cross-connected; the source of the thin film transistor of at least one color sub-pixel in the pixel unit is connected to the gate line branch.
  • the gate line branch is cross-connected with the gate line, and the gate of the thin film transistor of a sub-pixel closest to the gate line in the pixel unit
  • the electrode is connected to the gate line, and the gate electrode of the thin film transistor of the sub-pixel on the side away from the gate line in the pixel unit is connected to the gate line branch.
  • the display is displayed in the first peripheral display area and the second peripheral display area.
  • one of the at least two grid lines adjacent to the row of pixel units is the first grid line, and the other grid line is the second grid line;
  • At least one first grid line branch is provided on the first grid line, and the first grid line branch is cross-connected with the first grid line, or at least one first grid line branch is provided on the second grid line.
  • Two gate line branches, the second gate line branch is cross-connected with the second gate line;
  • the gate of the thin film transistor of a sub-pixel closest to the first gate line in the pixel unit is connected to the first gate line, and the thin film transistor of a sub-pixel closest to the second gate line in the pixel unit has a gate.
  • the gate is connected to the second gate line, and the gate of the thin film transistor of the sub-pixel far from the first gate line and the second gate line in the pixel unit is branched from the first gate line or the second gate line Gate line branch connections.
  • sub-pixels of the same color in the pixel units in the same column are connected to the same data line, and each of the data lines is connected to the same data line.
  • the grid lines are vertically intersected or arranged in a winding shape in a manner of bypassing the sub-pixels.
  • Embodiments of the present disclosure further provide a display device including the display substrate provided by the embodiments of the present disclosure.
  • the display device is a spliced screen, including a plurality of single screens spliced with each other, each of the single screens includes the display substrate and a protective cover plate, wherein the protective cover plate is provided with a light-shielding layer, The light shielding layer is extended along the side of the protective cover plate, and a part of the peripheral display area is shielded by the light shielding layer, and another part is not shielded by the light shielding layer.
  • the pixel unit array on each single screen is aligned with the pixel unit array in another single screen disposed adjacent to the single screen.
  • the pixel arrangement structure is improved, and each sub-pixel of the pixel unit in the middle display area located in the middle position in the display area is sequentially arranged along the extension direction of the short side, and the sub-pixels located in the peripheral
  • Each sub-pixel of the pixel unit in at least one of the two peripheral display areas that is, the first peripheral display area and the second peripheral display area
  • the directions are arranged in sequence, and the short sides of the sub-pixels in at least one of the first peripheral display area and the second peripheral display area are perpendicular to the short sides of the sub-pixels in the middle display area.
  • Fig. 1 represents the cross-sectional structure schematic diagram of a kind of splicing screen product structure in the prior art
  • Fig. 2 is a schematic diagram showing the occlusion of the surrounding pixels by the frame of the splicing screen in the top view of Fig. 1, and only a corner area of the splicing screen is shown in the figure;
  • FIG. 3 shows a schematic diagram of a pixel arrangement structure in a display substrate provided by an embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of a wiring diagram of part C in FIG. 3 in the display substrate provided by the present disclosure
  • FIG. 5 shows another schematic diagram of wiring in part C of FIG. 3 in the display substrate provided by the present disclosure
  • FIG. 6 shows another schematic diagram of wiring in part C of FIG. 3 in the display substrate provided by the present disclosure
  • FIG. 7 shows another schematic diagram of wiring in part C of FIG. 3 in the display substrate provided by the present disclosure
  • FIG. 8 shows another schematic diagram of wiring in part C in FIG. 3 in the display substrate provided by the present disclosure.
  • FIG. 1 is a schematic cross-sectional structure diagram of the product structure of the splicing screen
  • FIG. 2 is a schematic diagram of the occlusion of the surrounding pixels by the frame of the splicing screen in the top view of FIG. 1 , only a corner of the splicing screen is shown in the figure.
  • the frame 20 will block the peripheral part of the pixels of the display substrate 10. Due to the difference in the straightness of the edge of the frame, the degree of shading will be different, and the degree of opening loss of the RGB sub-pixels 30 in different pixel units will be different. As a result, rainbow patterns appear on the edge of the screen, and the colors on the opposite sides are different.
  • embodiments of the present disclosure provide a display substrate and a display device.
  • the phenomenon of rainbow patterns in display products can be improved to improve product quality.
  • FIG. 3 is a schematic diagram illustrating an arrangement structure of pixels in a display substrate according to an embodiment of the present disclosure.
  • the display substrate provided by the embodiment of the present disclosure includes an intermediate display area A, and a first peripheral display area B1 and a second peripheral display area B2 located on opposite sides of the intermediate display area A.
  • the display The area includes a pixel unit array, the pixel unit array includes a plurality of pixel units 300 distributed in an array, each pixel unit 300 includes at least two sub-pixels emitting light of different colors, the opening shape of the sub-pixels is a rectangle, the The rectangle includes a long side 300b and a short side 300a; wherein,
  • each sub-pixel in each pixel unit 300 extends along the short side of the sub-pixel Arranged in sequence; and the extension direction of the first peripheral display area B1 and the second peripheral display area B2 is perpendicular to the extension direction of the short side of the sub-pixels in the intermediate display area A, and the first peripheral display area B1 and the The short-side extension direction of the sub-pixels in at least one of the second peripheral display areas B2 is perpendicular to the short-side extension direction of the sub-pixels in the intermediate display area A.
  • the short side extending direction of each sub-pixel in the middle display area A is the row direction X of the pixel unit array
  • the long side extending direction is the column direction Y of the pixel unit array.
  • a peripheral display area B1 is the peripheral display area located on the left side of the intermediate display area A; the second peripheral display area B2 is the peripheral display area located on the right side of the intermediate display area A, and the pixel units 300 in the intermediate display area A
  • the sub-pixels are arranged in sequence along the short-side extension direction, that is, in the X-direction; the short-side extension direction of each sub-pixel of the pixel unit 300 in the first peripheral display area B1 and the second peripheral display area B2 and the middle display area
  • the short side extending direction of the inner sub-pixels is vertical, that is, they are arranged in the Y direction, and the sub-pixels in the pixel unit are arranged in sequence along the short side extending direction, that is, they are sequentially arranged in the Y direction.
  • the first peripheral display area B1 and the second peripheral display area B2 are respectively covered by four corresponding four peripheral display areas on the frame. Partially occluded by the side frame.
  • the sub-pixels of the pixel unit 300 in the middle display area A located in the middle position in the display area are arranged in sequence along the extension direction of the short side, and are located in the peripheral position.
  • Each sub-pixel design of the pixel unit 300 in at least one of the two peripheral display areas ie, the first peripheral display area B1 and the second peripheral display area B2 perpendicular to the short-side extension direction of the sub-pixels in the middle display area
  • the short sides of the sub-pixels in at least one of the first peripheral display area B1 and the second peripheral display area B2 are arranged perpendicular to the short sides of the sub-pixels in the middle display area A.
  • the extending directions of the edges of the frames located on the first side 110 and the second side 120 will be aligned with the pixel units 300 in the first peripheral display area B1 and the second peripheral display area B2.
  • the pixels are arranged in the same direction, so that when the frame blocks the pixel units 300 in the first peripheral display area B1 and/or the second peripheral display area B2, part of the pixel units 300 in the first peripheral display area B1 and the second peripheral display area B2 are covered by the frame.
  • the other part is not blocked by the frame, and the sub-pixel openings in each blocked pixel unit 300 in the peripheral display area will be lost in the same proportion, thereby improving the problem of rainbow patterns and improving product quality.
  • the first peripheral display area B1 may include only one row of pixel units 300 , or may include at least two rows of pixel units 300 ; similarly, the second peripheral display area B2 may One column of pixel units 300 may also include at least two columns of pixel units 300 .
  • the pixel unit 300 includes at least a first sub-pixel 310, a second sub-pixel 320 and a third sub-pixel 330.
  • the first sub-pixel 310 is a red sub-pixel
  • the second sub-pixel 310 is a red sub-pixel
  • the sub-pixel 320 is a green sub-pixel
  • the third sub-pixel 330 is a blue sub-pixel.
  • the pixel opening area of the first sub-pixel 310 in the middle display area A is the same as that of the first sub-pixel 310 in the first peripheral display area B1 and the second peripheral display area B2 ;
  • the pixel opening area of the second sub-pixel 320 in the intermediate display area A is the same as that of the first peripheral display area B1 and the second sub-pixel 320 in the second peripheral display area B2;
  • the third sub-pixel 330 in A has the same pixel opening area as the third sub-pixel 330 in the first peripheral display area B1 and the second peripheral display area B2.
  • the opening areas of the sub-pixels located in the first peripheral display area B1 and the second peripheral display area B2 are the same as the opening areas of the sub-pixels located in the middle display area A.
  • the corresponding display driving circuit wiring manners in the display substrate in the embodiment of the present disclosure may be various.
  • the base substrate 100 is provided with crossed and insulated data lines 500 and gate lines 600, and each of the sub-pixels is provided with a thin film transistor and a pixel electrode, and the thin film transistor
  • the gate is connected to the gate line 600, the source is connected to the data line 500, and the drain is connected to the pixel electrode.
  • the sources of the thin film transistors of sub-pixels with different colors of light are respectively connected to different data lines 500; and in the plurality of pixel units 300 in the same row, the thin film transistors of the sub-pixels
  • the gates are all connected to the same gate line 600 adjacent to the row of pixel units 300, or to at least two gate lines 600 adjacent to the row of pixel units 300, and to the gates of the thin film transistors of the same color sub-pixels connected to the same gate line 600 .
  • the wiring patterns of the signal lines in the first peripheral display area B1 and the second peripheral display area B2 are different from the wiring patterns of the signal lines in the middle display area A.
  • the middle display area A since the sub-pixels of each pixel unit 300 are arranged in sequence along the extension direction of the short side of the sub-pixels, that is, the X direction, and the gate lines 600 extend along the X direction, the thin film transistors in each sub-pixel and the The distance between the gate lines 600 is the same, and the source of the thin film transistor can be directly connected to the gate line 600; and in the pixel units 300 in the first peripheral display area B1 and the second peripheral display area B2, since each sub-pixel is along the same
  • the sub-pixels in the middle display area are arranged in order in the direction perpendicular to the short sides, that is, the Y direction.
  • the distances from the sub-pixels in the same pixel unit 300 to the gate line 600 are different, so that the sub-pixels in the same pixel unit 300 are connected to each other.
  • the same or at least two gate lines 600 adjacent to the pixel unit 300 in at least one of the first peripheral display area B1 and the second peripheral display area B2, on the gate line 600
  • the gate line branch 600' is cross-connected with the gate line 600
  • the extension direction of the gate line branch 600' is the extension direction of the long side of the sub-pixels in the middle display area, That is, the Y direction can be formed by extending the gate line 600 ;
  • the source of the thin film transistor of at least one color sub-pixel in the pixel unit 300 is connected to the gate line 600 through the gate line branch 600 ′.
  • the gate line 600 is further provided with at least one gate line branch 600 ′, and the gate line branch 600 ′ intersects the gate line 600 connected, and the gate of the thin film transistor of a sub-pixel closest to the gate line 600 in the pixel unit 300 is connected to the gate line 600, and the sub-pixel on the side of the pixel unit 300 away from the gate line 600 is connected to the gate line 600.
  • the gate of the thin film transistor is connected to the gate line branch 600'.
  • the pixel unit 300 includes a first sub-pixel 310, a second sub-pixel 320 and a third sub-pixel 330, and the thin film transistors of the pixel units 300 in the same row are connected to the On the same gate line 600 on the side of the row pixel unit 300 close to the fourth side 140 (ie, the same gate line 600 located below the pixel unit 300 as shown in the figure).
  • the first peripheral display area B1 and the second peripheral display area B2 the first sub-pixel 310 of the pixel unit 300 is located on the side closest to the fourth side 140, and the third sub-pixel 310 is located on the side closest to the fourth side 140.
  • the pixel 330 is located on the side closest to the third side 130 , the gate line 600 is provided with two gate line branches 600 ′, and the thin film transistor in the first sub-pixel 310 is directly connected to the gate line 600 connection, the thin film transistor of the second sub-pixel 320 is connected to the gate line 600 through one gate line branch 600 ′ of the two gate line branches 600 ′, and the thin film transistor of the third sub-pixel 330 is connected to the gate line 600 through two gate line branches 600 ′.
  • Another gate line branch 600 ′ of the line branches 600 ′ is connected to the gate line 600 .
  • one gate line 600 on the at least two gate lines 600 adjacent to the row of pixel units 300 is the first gate line 610,
  • the other gate line 600 is the second gate line 620;
  • the first gate line 610 is provided with at least one first gate line branch 610 ′, and the first gate line branch 610 ′ is cross-connected with the first gate line 610 , or the second gate line 620 at least one second gate line branch 620 ′ is provided on it, and the second gate line branch 620 ′ is cross-connected with the second gate line 620 ;
  • the gate of the thin film transistor of a sub-pixel of the pixel unit 300 closest to the first gate line 610 is connected to the first gate line 610
  • the sub-pixel of the pixel unit 300 closest to the second gate line 620 The gate of the thin film transistor of the pixel is connected to the second gate line 620
  • the gate of the thin film transistor of the sub-pixel in the pixel unit 300 far from the first gate line 610 and the second gate line 620 is connected to the first gate line 610 and the second gate line 620.
  • a gate line branch 610' or the second gate line branch 620' is connected.
  • the pixel unit 300 includes a first sub-pixel 310, a second sub-pixel 320 and a third sub-pixel 330, and the thin film transistors of the pixel units 300 in the same row are connected to the same On the adjacent first gate line 610 and the second gate line 620 of the row pixel unit 300 (ie, the two gate lines 600 located above and below the pixel unit 300 shown in the figure).
  • the first sub-pixel 310 of the pixel unit 300 is located on the side closest to the fourth side 140
  • the third sub-pixel 310 is located on the side closest to the fourth side 140.
  • the pixel 330 is located on the side closest to the third side 130, wherein the first sub-pixel 310 can be directly connected to the first gate line 610 or connected to the first gate line 610 through a first gate line branch 610' , the third sub-pixel 330 can be directly connected to the second gate line 620 or connected to the second gate line 620 through the second gate line branch 620 ′, and the second sub-pixel 320 can be connected to the first gate line 610 Another first gate line branch 610 ′ on or connected to another second gate line branch 620 ′ on the second gate line 620 .
  • sub-pixels of different colors are respectively connected to different data lines 500
  • sub-pixels of the same color in the same column of pixel units 300 are connected to to the same data line 500.
  • first peripheral display area B1 and the second peripheral display area B2 sub-pixels of the same color in the pixel units 300 in the same row are connected to the same data line 500, and each of the data lines 500 is connected to the same data line 500.
  • the gate lines 600 are vertically intersected or arranged in a winding shape in a manner of bypassing the sub-pixels.
  • the first sub-pixel 310 in the pixel unit 300 is connected to the first peripheral display area B1 and the second peripheral display area B2.
  • a data line 500 and a third data line 500 to which the third sub-pixel 330 is connected are located on opposite sides of the pixel unit 300, namely the side close to the middle display area A and the side far from the middle display area A, the The second data line 500 connected to the second sub-pixel 320 is located in the middle of the pixel unit 300, and the pixel electrode of each sub-pixel is divided into a first part 300A and a second part 300B, and the first part 300A and the second part 300B are connected by The bridge 300C is connected, and the orthographic projections of the first portion and the second portion on the base substrate 100 do not coincide with the orthographic projection of the second data line 500 on the base substrate 100 to reduce parasitic capacitance and the like.
  • the first sub-pixel 310 in the pixel unit 300 is connected to the The first data line 500 and the third data line 500 connected to the third sub-pixel 330 are located on opposite sides of the pixel unit 300 respectively, that is, the side close to the middle display area A and the side far from the middle display area A, so The second data line 500 connected to the second sub-pixel 320 may be located on the side of the pixel unit 300 close to the middle display area A or on the side away from the middle display area A.
  • the first sub-pixels 310 in the pixel unit 300 are connected to
  • the first data line 500 and the third data line 500 connected to the third sub-pixel 330 are respectively located on opposite sides of the pixel unit 300 and are arranged perpendicular to the gate line 600, and the second data line connected to the second sub-pixel 320 500 is set in winding mode;
  • the second sub-pixels 320 in the pixel unit 300 are connected to
  • the third data line 500 to which the second data line 500 and the third sub-pixel 330 are connected is located on the same side of the pixel unit 300 or on opposite sides of the pixel unit 300, and is arranged perpendicular to the gate line 600.
  • the connected second data lines 500 are arranged in a winding manner.
  • an embodiment of the present disclosure further provides a display device including the display substrate provided by the embodiment of the present disclosure.
  • the display device may be various display devices such as a computer, a mobile phone, and a TV.
  • the display device is a spliced screen, including a plurality of single screens spliced with each other, a pixel unit array on each of the single screens and another of the single screens arranged adjacent to the single screen.
  • the pixel unit arrays in the screen are aligned, and each single screen includes the display substrate and a protective cover plate, wherein the protective cover plate is provided with a light-shielding layer, and the light-shielding layer is along the side of the protective cover plate It is extended and arranged, and a part of the peripheral display area is shielded by the light shielding layer, and another part of the area is not shielded by the light shielding layer.
  • the pixel unit array on each single screen is aligned with the pixel unit array in another single screen adjacent to the single screen, that is, in the X direction (ie, the middle display area
  • the Nth row of pixel units of each single screen is located on the same straight line.
  • the pixel units of the Nth column of each single screen are located on the same straight line.

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Abstract

本公开提供一种显示基板及显示装置，该显示基板包括中间显示区域、及位于中间显示区域相对两侧的第一周边显示区域和第二周边显示区域，显示区域中每一像素单元包括发出不同颜色光的至少两个子像素，子像素的开口形状为矩形，包括长边和短边；在第一周边显示区域和第二周边显示区域中至少一个区域及中间显示区域，每个像素单元中各子像素均沿子像素的短边延伸方向依次排列；第一周边显示区域和第二周边显示区域的延伸方向与中间显示区域内子像素的短边延伸方向垂直，且子像素的短边延伸方向与中间显示区域内子像素的短边延伸方向垂直。本公开的显示基板及显示装置能够改善窄边框产品边缘彩虹纹的问题，提高产品品质。

Description

一种显示基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
在相关技术中，对于窄边框设计的显示产品，以拼接屏产品为例，背光模组的边框会遮挡住显示面板周边部分像素，由于边框边缘的直线度差异，会造成对像素遮挡程度不同，从而不同像素的子像素RGB损失程度不一致，而导致屏幕边缘出现彩虹纹问题，且左右两侧呈现的颜色也不一样。
发明内容
本公开实施例提供了一种显示基板及显示装置，能够改善窄边框产品边缘彩虹纹的问题，提高产品品质。
本公开实施例所提供的技术方案如下：
本公开实施例提供了一种显示基板，包括中间显示区域、及位于所述中间显示区域相对两侧的第一周边显示区域和第二周边显示区域，所述显示区域包括像素单元阵列，每一像素单元包括发出不同颜色光的至少两个子像素，所述子像素的开口形状为矩形，所述矩形包括长边和短边；其中，
在所述第一周边显示区域和所述第二周边显示区域中至少一个区域、及所述中间显示区域，每个像素单元中各子像素均沿子像素的短边延伸方向依次排列，且所述第一周边显示区域和所述第二周边显示区域的延伸方向与所述中间显示区域内子像素的短边延伸方向垂直，所述第一周边显示区域和所述第二周边显示区域中至少一个区域内的子像素的短边延伸方向与所述中间显示区域内子像素的短边延伸方向垂直。
示例性的，所述像素单元至少包括第一子像素、第二子像素和第三子像素；
所述中间显示区域内的第一子像素与所述第一周边显示区域、所述第二 周边显示区域内的第一子像素的像素开口面积相同；
所述中间显示区域内的第二子像素与所述第一周边显示区域、所述第二周边显示区域内的第二子像素的像素开口面积相同；
所述中间显示区域内的第三子像素与所述第一周边显示区域、所述第二周边显示区域内的第三子像素的像素开口面积相同。
示例性的，所述显示基板还包括交叉且绝缘设置的数据线和栅线，每一所述子像素内均设置薄膜晶体管和像素电极，薄膜晶体管的栅极与栅线连接、源极与数据线连接、漏极与像素电极连接；其中，
同一行的多个像素单元中，不同颜色光的子像素的薄膜晶体管的源极分别连接至不同数据线；
同一行的多个像素单元中，各子像素的薄膜晶体管的栅极均连接至与该行像素单元相邻的同一根栅线上，或者与该行像素单元相邻的至少两根栅线上、且同一颜色子像素的薄膜晶体管的栅极连接至同一根栅线上。
示例性的，在所述第一周边显示区域和所述第二周边显示区域中至少一个区域内，所述栅线上还设有至少一根栅线分支，所述栅线分支与所述栅线交叉连接；所述像素单元内至少一个颜色的子像素的薄膜晶体管的源极连接至所述栅线分支。
示例性的，同一行所述像素单元内各子像素的栅极连接至与该行像素单元相邻的同一根栅线上时，在所述第一周边显示区域和所述第二周边显示区域内，所述栅线上还设有至少一根栅线分支，所述栅线分支与所述栅线交叉连接，且所述像素单元中最靠近该栅线的一个子像素的薄膜晶体管的栅极与该栅线连接，所述像素单元中远离该栅线的一侧的子像素的薄膜晶体管的栅极与所述栅线分支连接。
示例性的，同一行所述像素单元内各子像素的栅极连接至与该行像素单元相邻的至少两根栅线上时，在所述第一周边显示区域和所述第二周边显示区域内，所述与该行像素单元相邻的至少两根栅线上中一个栅线为第一栅线，另一个栅线为第二栅线；
所述第一栅线上设有至少一根第一栅线分支，所述第一栅线分支与所述 第一栅线交叉连接，或者，所述第二栅线上设有至少一根第二栅线分支，所述第二栅线分支与所述第二栅线交叉连接；
所述像素单元中最靠近该第一栅线的一个子像素的薄膜晶体管的栅极与该第一栅线连接，所述像素单元中最靠近该第二栅线的一个子像素的薄膜晶体管的栅极与该第二栅线连接，所述像素单元中远离该第一栅线和所述第二栅线的子像素的薄膜晶体管的栅极与所述第一栅线分支或所述第二栅线分支连接。
示例性的，在所述第一周边显示区域和所述第二周边显示区域内，同一列所述像素单元内相同颜色的子像素连接至同一根数据线，且各所述数据线与所述栅线垂直交叉设置或以绕开子像素的方式呈绕线状设置。
本公开实施例还提供了一种显示装置，包括本公开实施例提供的显示基板。
示例性的，所述显示装置为拼接屏，包括相互拼接的多个单屏，每一所述单屏包括所述显示基板、及保护盖板，其中所述保护盖板上设有遮光层，所述遮光层沿所述保护盖板的侧边延伸设置，且所述周边显示区域的一部分区域被所述遮光层遮挡，另一部分区域未被所述遮光层遮挡。
示例性的，每一所述单屏上的像素单元阵列和与该单屏相邻设置的另一所述单屏中的像素单元阵列对齐。
本公开实施例所带来的有益效果如下：
本公开实施例所提供的显示基板及显示装置，对像素排列结构进行了改进，将显示区域中位于中间位置的中间显示区域中像素单元的各子像素沿短边延伸方向依次排列，而位于周边位置中与中间显示区域中子像素的短边延伸方向垂直的两个周边显示区域(即第一周边显示区域和第二周边显示区域)中至少一个区域内像素单元的各子像素沿短边延伸方向依次排列，而第一周边显示区域和第二周边显示区域中至少一个区域内的子像素短边与中间显示区域内的子像素短边方向垂直设置，这样，当显示基板应用于窄边框结构中时，边框遮挡第一周边显示区域和/或第二周边显示区域的像素单元时，第一周边显示区域和第二周边显示区域的像素单元一部分被边框遮挡，另一部分 未被边框遮挡，各子像素开口同比例损失，这样可改善彩虹纹的问题，提升产品品质。
附图说明
图1表示现有技术中一种拼接屏产品结构的断面结构示意图；
图2表示图1俯视图中拼接屏的边框对周边部分像素的遮挡情况示意图，图中仅示意出了拼接屏的一角区域；
图3表示本公开实施例所提供的显示基板中一种像素排列结构示意图；
图4表示本公开提供的显示基板中在图3中C局部的一种布线示意图；
图5表示本公开提供的显示基板中在图3中C局部的另一种布线示意图；
图6表示本公开提供的显示基板中在图3中C局部的另一种布线示意图；
图7表示本公开提供的显示基板中在图3中C局部的另一种布线示意图；
图8表示本公开提供的显示基板中在图3中C局部的另一种布线示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接 的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在对本公开实施例所提供的显示基板及显示装置进行详细说明之前，有必要对相关技术进行以下说明：
在相关技术中，对于窄边框显示产品，以拼接屏为例，图1所示为拼接屏产品结构的断面结构示意图，图2为图1俯视图中拼接屏的边框对周边部分像素的遮挡情况示意图，图中仅示意出了拼接屏的一角区域。如图1和图2所示，边框20会遮挡显示基板10的周边部分像素，由于边框边缘的直线度差异，会造成遮挡程度不同，不同像素单元内的RGB子像素30开口损失程度不一样，从而导致屏幕边缘出现彩虹纹问题，且相对两侧边所呈现的颜色也不一样。
为了改善上述显示产品产生彩虹纹的问题，本公开实施例提供了一种显示基板及显示装置，通过对像素排列结构进行改进，能够改善显示产品彩虹纹的现象，以提升产品品质。
图3所示为本公开实施例所提供的显示基板内像素排列结构示意图。如图3所示，本公开实施例所提供的显示基板包括中间显示区域A、及位于所述中间显示区域A相对两侧的第一周边显示区域B1和第二周边显示区域B2，所述显示区域包括像素单元阵列，所述像素单元阵列包括呈阵列分布的多个像素单元300，每一像素单元300包括发出不同颜色光的至少两个子像素，所述子像素的开口形状为矩形，所述矩形包括长边300b和短边300a；其中，
在所述第一周边显示区域B1和所述第二周边显示区域B2中至少一个区域、及所述中间显示区域A中，每个像素单元300中各子像素均沿子像素的短边延伸方向依次排列；且所述第一周边显示区域B1和所述第二周边显示区域B2的延伸方向与所述中间显示区域A内子像素的短边延伸方向垂直，所述第一周边显示区域B1和所述第二周边显示区域B2中至少一个区域内的子像素的短边延伸方向与所述中间显示区域A内子像素的短边延伸方向垂直。
以图3中所示的图纸方向为例，中间显示区域A中各子像素的短边延伸方向为像素单元阵列的行方向X，长边延伸方向为像素单元阵列的列方向Y， 所述第一周边显示区域B1即为位于中间显示区域A左侧的周边显示区域；所述第二周边显示区域B2即为位于中间显示区域A右侧的周边显示区域，中间显示区域A中的像素单元300内各子像素均沿短边延伸方向依次排列，即沿X方向依次排列；第一周边显示区域B1和第二周边显示区域B2中的像素单元300各子像素的短边延伸方向与中间显示区域内子像素的短边延伸方向垂直，即沿Y方向设置，且像素单元中各子像素沿短边延伸方向依次排列，即沿Y方向依次排列。
本公开实施例提供的显示基板在应用于窄边框显示产品中，尤其是应用于拼接屏时，所述第一周边显示区域B1、所述第二周边显示区域B2会分别被边框上对应的四个侧边框部分遮挡。
采用上述方案，通过对显示基板上的像素排列结构进行了改进，将显示区域中位于中间位置的中间显示区域A中像素单元300的各子像素沿短边延伸方向依次排列，而位于周边位置中、与中间显示区域中子像素的短边延伸方向垂直的两个周边显示区域(即第一周边显示区域B1和第二周边显示区域B2)中的至少一个区域内像素单元300的各子像素设计为沿短边延伸方向依次排列，而第一周边显示区域B1和第二周边显示区域B2中至少一个区域内的子像素短边与中间显示区域A内的子像素短边方向垂直设置，这样，当显示基板应用于窄边框结构中时，位于第一侧边110和第二侧边120的边框的边缘延伸方向会与第一周边显示区域B1和第二周边显示区域B2内各像素单元300内子像素排列方向一致，从而，边框遮挡第一周边显示区域B1和/或第二周边显示区域B2的像素单元300时，第一周边显示区域B1和第二周边显示区域B2的像素单元300一部分被边框遮挡，而另一部分未被边框遮挡，周边显示区域内被遮挡的各像素单元300内子像素开口会同比例损失，从而可改善彩虹纹的问题，提升产品品质。
需要说明的是，如图3所示，所述第一周边显示区域B1中可仅一列像素单元300，也可以包括至少两列像素单元300；同样的，所述第二周边显示区域B2中可一列像素单元300，也可以包括至少两列像素单元300。
在一些实施例中，如图所示，所述像素单元300至少包括第一子像素310、 第二子像素320和第三子像素330，例如，第一子像素310为红色子像素，第二子像素320为绿色子像素，第三子像素330为蓝色子像素。
如图3所示，在所述中间显示区域A内的第一子像素310与所述第一周边显示区域B1、所述第二周边显示区域B2内的第一子像素310的像素开口面积相同；所述中间显示区域A内的第二子像素320与所述第一周边显示区域B1、所述第二周边显示区域B2内的第二子像素320的像素开口面积相同；所述中间显示区域A内的第三子像素330与所述第一周边显示区域B1、所述第二周边显示区域B2内的第三子像素330的像素开口面积相同。
上述方案中，针对相同颜色的子像素，位于第一周边显示区域B1和第二周边显示区域B2内的子像素开口面积、与位于中间显示区域A内的子像素开口面积相同。
为了实现本公开实施例提供的显示基板中的像素排列结构，本公开实施例中的显示基板中相应的显示驱动电路布线方式可以有多种。
在本公开实施例提供的显示基板中，所述衬底基板100上设有交叉且绝缘设置的数据线500和栅线600，每一所述子像素内均设置薄膜晶体管和像素电极，薄膜晶体管的栅极与栅线600连接、源极与数据线500连接、漏极与像素电极连接。其中，同一行的多个像素单元300中，不同颜色光的子像素的薄膜晶体管的源极分别连接至不同数据线500；且同一行的多个像素单元300中，各子像素的薄膜晶体管的栅极均连接至与该行像素单元300相邻的同一根栅线600上，或者与该行像素单元300相邻的至少两根栅线600上、且同一颜色子像素的薄膜晶体管的栅极连接至同一根栅线600上。
由于在第一周边显示区域B1和第二周边显示区域B2内的像素单元300的各子像素排列方向与中间显示区域A内像素单元300的各子像素排列方向不同，因此，对于处于同一行像素单元300来说，所述第一周边显示区域B1和第二周边显示区域B2内的信号线布线方式会有别于所述中间显示区域A内的信号线布线方式。
在所述中间显示区域A内，由于各像素单元300的子像素沿子像素的短边延伸方向即X方向依次排列，且栅线600沿X方向延伸，因此，各子像素 内的薄膜晶体管与栅线600的距离相同，薄膜晶体管的源极可直接连接至栅线600上；而所述第一周边显示区域B1和第二周边显示区域B2内的像素单元300中，由于各子像素沿与中间显示区域内的子像素短边垂直的方向即Y方向依次排列，因此，同一像素单元300内的各子像素至栅线600的距离不同，为了使得同一像素单元300内的各子像素均连接至与该像素单元300相邻的同一根或至少两根栅线600上，在所述第一周边显示区域B1和所述第二周边显示区域B2中至少一个区域内，所述栅线600上还设有至少一根栅线分支600’，所述栅线分支600’与所述栅线600交叉连接，所述栅线分支600’的延伸方向为中间显示区域内子像素的长边延伸方向，即Y方向，可由所述栅线600延伸而成；所述像素单元300内至少一个颜色的子像素的薄膜晶体管的源极通过所述栅线分支600’连接至所述栅线600上。
作为一种示例性的实施例，如图4所示，同一行所述像素单元300内各子像素的栅极连接至与该行像素单元300相邻的同一根栅线600上时，在所述第一周边显示区域B1和所述第二周边显示区域B2内，所述栅线600上还设有至少一根栅线分支600’，所述栅线分支600’与所述栅线600交叉连接，且所述像素单元300中最靠近该栅线600的一个子像素的薄膜晶体管的栅极与该栅线600连接，所述像素单元300中远离该栅线600的一侧的子像素的薄膜晶体管的栅极与所述栅线分支600’连接。
例如，以图4所示的显示基板为例，所述像素单元300包括第一子像素310、第二子像素320和第三子像素330，同一行像素单元300的薄膜晶体管均连接至位于该行像素单元300的靠近第四侧边140的一侧的同一根栅线600(即图中所示的位于像素单元300下方的同一根栅线600)上。在所述第一周边显示区域B1和所述第二周边显示区域B2内，所述像素单元300的第一子像素310位于最靠近所述第四侧边140的一侧，所述第三子像素330位于最靠近所述第三侧边130的一侧，所述栅线600上设有两个栅线分支600’，所述第一子像素310内的薄膜晶体管直接与所述栅线600连接，所述第二子像素320的薄膜晶体管通过两个栅线分支600’中的一个栅线分支600’连接至所述栅线600，所述第三子像素330的薄膜晶体管通过两个栅线分支600’中 的另一个栅线分支600’连接至所述栅线600。
作为另一种示例性的实施例，如图5所示，同一行所述像素单元300内各子像素的栅极连接至与该行像素单元300相邻的至少两根栅线600上时，在所述第一周边显示区域B1和所述第二周边显示区域B2内，所述与该行像素单元300相邻的至少两根栅线600上中一个栅线600为第一栅线610，另一个栅线600为第二栅线620；
所述第一栅线610上设有至少一根第一栅线分支610’，所述第一栅线分支610’与所述第一栅线610交叉连接，或者，所述第二栅线620上设有至少一根第二栅线分支620’，所述第二栅线分支620’与所述第二栅线620交叉连接；
所述像素单元300中最靠近该第一栅线610的一个子像素的薄膜晶体管的栅极与该第一栅线610连接，所述像素单元300中最靠近该第二栅线620的一个子像素的薄膜晶体管的栅极与该第二栅线620连接，所述像素单元300中远离该第一栅线610和所述第二栅线620的子像素的薄膜晶体管的栅极与所述第一栅线分支610’或所述第二栅线分支620’连接。
例如，以图5所示的显示基板为例，所述像素单元300包括第一子像素310、第二子像素320和第三子像素330，同一行像素单元300的薄膜晶体管均连接至与该行像素单元300的相邻的第一栅线610和第二栅线620上(即图中所示的位于像素单元300上方和下方的两根栅线600)上。在所述第一周边显示区域B1和所述第二周边显示区域B2内，所述像素单元300的第一子像素310位于最靠近所述第四侧边140的一侧，所述第三子像素330位于最靠近所述第三侧边130的一侧，其中第一子像素310可直接连接至第一栅线610上或者通过第一栅线分支610’连接至所述第一栅线610上，第三子像素330可直接连接至第二栅线620上或者通过第二栅线分支620’连接至所述第二栅线620上，第二子像素320可连接至第一栅线610上的另一第一栅线分支610’或连接在第二栅线620上的另一第二栅线分支620’上。
此外，作为一种示例性的实施例，如图4所示，在所述中间显示区域A，不同颜色的子像素分别连接至不同数据线500，同一列像素单元300中相同 颜色的子像素连接至同一根数据线500。
在所述第一周边显示区域B1和所述第二周边显示区域B2内，同一列所述像素单元300内相同颜色的子像素连接至同一根数据线500，且各所述数据线500与所述栅线600垂直交叉设置或以绕开子像素的方式呈绕线状设置。
以图4所示为例，在第一周边显示区域B1和所述第二周边显示区域B2内，同一像素单元300中不同颜色子像素连接至不同的数据线500，且数据线500均与所述栅线600垂直。其中数据线500的具体布线方式应保证不同数据线500之间不重合。
作为一种具体的实施例，例如图6所示，在所述第一周边显示区域B1和所述第二周边显示区域B2内，所述像素单元300内的第一子像素310所连接的第一数据线500和第三子像素330所连接的第三数据线500分别位于该像素单元300的相对两侧，即靠近中间显示区域A的一侧和远离中间显示区域A的一侧，所述第二子像素320所连接的第二数据线500位于该像素单元300的中间，且各子像素的像素电极分为第一部分300A和第二部分300B，第一部分300A和第二部分300B间通过连接桥300C连接，且第一部分和第二部分在衬底基板100上的正投影与所述第二数据线500在所述衬底基板100上的正投影不重合，以减少寄生电容等。
作为另一种具体的实施例，例如图5所示，在所述第一周边显示区域B1和所述第二周边显示区域B2内，所述像素单元300内的第一子像素310所连接的第一数据线500和第三子像素330所连接的第三数据线500分别位于该像素单元300的相对两侧，即靠近中间显示区域A的一侧和远离中间显示区域A的一侧，所述第二子像素320所连接的第二数据线500可位于该像素单元300的靠近中间显示区域A的一侧或远离中间显示区域A的一侧。
作为另一种具体的实施例，例如图7所示，在所述第一周边显示区域B1和所述第二周边显示区域B2内，所述像素单元300内的第一子像素310所连接的第一数据线500和第二子像素320所连接的第二数据线500分别位于该像素单元300的相对两侧或位于像素单元的同一侧，并垂直于栅线600设置，第三子像素330所连接的第三数据线500以绕线方式设置；
作为另一种具体的实施例，例如图8所示，在所述第一周边显示区域B1和所述第二周边显示区域B2内，所述像素单元300内的第一子像素310所连接的第一数据线500和第三子像素330所连接的第三数据线500分别位于该像素单元300的相对两侧，并垂直于栅线600设置，第二子像素320所连接的第二数据线500以绕线方式设置；
作为另一种具体的实施例，例如图8所示，在所述第一周边显示区域B1和所述第二周边显示区域B2内，所述像素单元300内的第二子像素320所连接的第二数据线500和第三子像素330所连接的第三数据线500位于像素单元300的同一侧或位于该像素单元300的相对两侧，并垂直于栅线600设置，第一子像素310所连接的第二数据线500以绕线方式设置。
应当理解的是，以上仅是对栅线600和数据线500的布线方式进行举例，在实际应用中，并不对此进行限定。
此外，本公开实施例还提供了一种显示装置，包括本公开实施例提供的显示基板。所述显示装置可以是电脑、手机、电视等各种显示设备。
作为一种示例性实施例，所述显示装置为拼接屏，包括相互拼接的多个单屏，每一所述单屏上的像素单元阵列和与该单屏相邻设置的另一所述单屏中的像素单元阵列对齐，每一所述单屏包括所述显示基板、及保护盖板，其中所述保护盖板上设有遮光层，所述遮光层沿所述保护盖板的侧边延伸设置，且所述周边显示区域的一部分区域被所述遮光层遮挡，另一部分区域未被所述遮光层遮挡。
需要说明的是，每一所述单屏上的像素单元阵列和与该单屏相邻设置的另一所述单屏中的像素单元阵列对齐，也就是说，在X方向(即中间显示区域内子像素的短边延伸方向)拼接的多个单屏，每一所述单屏的第N行像素单元均位于同一直线上，同样的，在Y方向(即中间显示区域内子像素的短边垂直方向)拼接的多个单屏，每一所述单屏的第N列像素单元均位于同一直线上。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结 构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种显示基板，其特征在于，包括中间显示区域、及位于所述中间显示区域相对两侧的第一周边显示区域和第二周边显示区域，所述显示区域包括像素单元阵列，每一像素单元包括发出不同颜色光的至少两个子像素，所述子像素的开口形状为矩形，所述矩形包括长边和短边；其中，
    在所述第一周边显示区域和所述第二周边显示区域中至少一个区域、及所述中间显示区域，每个像素单元中各子像素均沿子像素的短边延伸方向依次排列；且所述第一周边显示区域和所述第二周边显示区域的延伸方向与所述中间显示区域内子像素的短边延伸方向垂直，所述第一周边显示区域和所述第二周边显示区域中至少一个区域内的子像素的短边延伸方向与所述中间显示区域内子像素的短边延伸方向垂直。
  2. 根据权利要求1所述的显示基板，其特征在于，
    所述像素单元至少包括第一子像素、第二子像素和第三子像素；
    所述中间显示区域内的第一子像素与所述第一周边显示区域、所述第二周边显示区域内的第一子像素的像素开口面积相同；
    所述中间显示区域内的第二子像素与所述第一周边显示区域、所述第二周边显示区域内的第二子像素的像素开口面积相同；
    所述中间显示区域内的第三子像素与所述第一周边显示区域、所述第二周边显示区域内的第三子像素的像素开口面积相同。
  3. 根据权利要求1所述的显示基板，其特征在于，
    所述显示基板还包括交叉且绝缘设置的数据线和栅线，每一所述子像素内均设置薄膜晶体管和像素电极，薄膜晶体管的栅极与栅线连接、源极与数据线连接、漏极与像素电极连接；其中，
    同一行的多个像素单元中，不同颜色光的子像素的薄膜晶体管的源极分别连接至不同数据线；
    同一行的多个像素单元中，各子像素的薄膜晶体管的栅极均连接至与该行像素单元相邻的同一根栅线上，或者与该行像素单元相邻的至少两根栅线上、且同一颜色子像素的薄膜晶体管的栅极连接至同一根栅线上。
  4. 根据权利要求3所述的显示基板，其特征在于，
    在所述第一周边显示区域和所述第二周边显示区域中至少一个区域内，所述栅线上还设有至少一根栅线分支，所述栅线分支与所述栅线交叉连接；所述像素单元内至少一个颜色的子像素的薄膜晶体管的源极连接至所述栅线分支。
  5. 根据权利要求4所述的显示基板，其特征在于，
    同一行所述像素单元内各子像素的栅极连接至与该行像素单元相邻的同一根栅线上时，在所述第一周边显示区域和所述第二周边显示区域内，所述栅线上还设有至少一根栅线分支，所述栅线分支与所述栅线交叉连接，且所述像素单元中最靠近该栅线的一个子像素的薄膜晶体管的栅极与该栅线连接，所述像素单元中远离该栅线的一侧的子像素的薄膜晶体管的栅极与所述栅线分支连接。
  6. 根据权利要求5所述的显示基板，其特征在于，
    同一行所述像素单元内各子像素的栅极连接至与该行像素单元相邻的至少两根栅线上时，在所述第一周边显示区域和所述第二周边显示区域内，所述与该行像素单元相邻的至少两根栅线上中一个栅线为第一栅线，另一个栅线为第二栅线；
    所述第一栅线上设有至少一根第一栅线分支，所述第一栅线分支与所述第一栅线交叉连接，或者，所述第二栅线上设有至少一根第二栅线分支，所述第二栅线分支与所述第二栅线交叉连接；
    所述像素单元中最靠近该第一栅线的一个子像素的薄膜晶体管的栅极与该第一栅线连接，所述像素单元中最靠近该第二栅线的一个子像素的薄膜晶体管的栅极与该第二栅线连接，所述像素单元中远离该第一栅线和所述第二栅线的子像素的薄膜晶体管的栅极与所述第一栅线分支或所述第二栅线分支连接。
  7. 根据权利要求3所述的显示基板，其特征在于，
    在所述第一周边显示区域和所述第二周边显示区域内，同一列所述像素单元内相同颜色的子像素连接至同一根数据线，且各所述数据线与所述栅线垂直交叉设置或以绕开子像素的方式呈绕线状设置。
  8. 一种显示装置，其特征在于，包括如权利要求1至7任一项所述的显示基板。
  9. 根据权利要求8所述的显示装置，其特征在于，
    所述显示装置为拼接屏，包括相互拼接的多个单屏，每一所述单屏包括所述显示基板、及保护盖板，其中所述保护盖板上设有遮光层，所述遮光层沿所述保护盖板的侧边延伸设置，且所述周边显示区域的一部分区域被所述遮光层遮挡，另一部分区域未被所述遮光层遮挡。
  10. 根据权利要求9所述的显示装置，其特征在于，
    每一所述单屏上的像素单元阵列和与该单屏相邻设置的另一所述单屏中的像素单元阵列对齐。
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