WO2020082542A1 - 像素结构、阵列基板及显示装置 - Google Patents

像素结构、阵列基板及显示装置 Download PDF

Info

Publication number
WO2020082542A1
WO2020082542A1 PCT/CN2018/120985 CN2018120985W WO2020082542A1 WO 2020082542 A1 WO2020082542 A1 WO 2020082542A1 CN 2018120985 W CN2018120985 W CN 2018120985W WO 2020082542 A1 WO2020082542 A1 WO 2020082542A1
Authority
WO
WIPO (PCT)
Prior art keywords
film transistor
line
thin film
light
pixel
Prior art date
Application number
PCT/CN2018/120985
Other languages
English (en)
French (fr)
Inventor
叶成亮
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US16/319,464 priority Critical patent/US11552105B2/en
Publication of WO2020082542A1 publication Critical patent/WO2020082542A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • the present invention relates to the field of display technology, and in particular to a pixel structure, an array substrate, and a display device.
  • FIG. 1 it is a schematic diagram of an equivalent circuit of the existing 3T pixel structure.
  • Each sub-pixel can be divided into a main area (Main) and a sub-area (Sub), which mainly includes a thin film transistor T1 in the main area and a storage capacitor in the main area.
  • the rotation angles of the liquid crystal molecules of the 4 domains in the main region and the 4 domains in the secondary region in the same sub-pixel can be different, for example, it can be applied to the PSVA (polymer stable vertical) of 8 domains and 3 transistors Alignment) pixels.
  • the black matrix (BM) design is cancelled in the direction of the data line, and the indium tin oxide (ITO) light-shielding electrode line is used to cover the data line, and is connected to the common voltage, and the upper plate color filter
  • the common electrode potential of the indium tin oxide of the film (CF) is the same, thus playing the role of a black matrix.
  • the shading electrode line above the data line is usually connected to the left and right through the ITO shading electrode connection line in the middle of the pixel to achieve the effect of a mesh line and reduce resistance.
  • FIG. 2 is a schematic cross-sectional view of the ITO shading electrode connection line at the thin film transistor T3 in the existing 3T pixel structure
  • FIG. 3 is the ITO shading electrode connection line at the thin film transistor T3 in the existing 3T pixel structure.
  • Top view As shown in FIGS. 2 and 3, the thin-film transistor T3 includes a gate 1, a source / drain 2, and a semiconductor layer 40. Due to the limited space for wiring, and in order to increase the aperture ratio, the light-shielding electrode connection line 30 needs to be directly
  • the semiconductor layer 40 of the thin film transistor T3 passes through directly above the thin film transistor T3.
  • the light shielding electrode connecting line 30 has the same potential as the light shielding electrode line connected to a common voltage.
  • the common voltage is about 6V.
  • the color resister 50 is blocked, the light shielding electrode connecting line 30 is far from the thin film transistor T3 below, but there are still The role of the gate switch may affect the off-state current of the thin film transistor T3.
  • the thin film transistor T3 is not completely turned off due to the common voltage on the light shielding electrode connection line 30 on the upper surface, which affects the display effect.
  • an object of the present invention is to provide a pixel structure, an array substrate, and a display device to improve the influence of the light-shielding electrode connection line on the thin-film transistor when passing through the thin-film transistor.
  • the present invention provides a pixel structure, including:
  • the pixel electrode is provided in a pixel area defined by the scanning line and the data line crossing;
  • a light-shielding electrode line connected to a common voltage and provided above the data line to shield the data line;
  • a first thin film transistor located between the scan line and the pixel electrode, and connected to the pixel electrode;
  • the shading electrode connection line extends in the direction of the scanning line and electrically connects two adjacent shading electrode lines
  • the shading electrode connection wire is wound to form a mesh pattern, and the semiconductor layer of the first thin film transistor is disposed opposite to the hollowed-out area of the mesh pattern.
  • the light-shielding electrode connection line and the semiconductor layer at least partially overlap.
  • the light-shielding electrode connection line further includes a linear portion, and the connection point between the linear portion and the mesh pattern does not overlap with the semiconductor layer.
  • the pixel structure further includes a second thin film transistor
  • the light-shielding electrode connection line further includes a fold line pattern
  • the light-shielding electrode connection line bypasses the semiconductor layer of the second thin-film transistor via the fold line pattern.
  • the pixel structure further includes a third thin film transistor, and the light-shielding electrode connection line also bypasses the semiconductor layer of the third thin film transistor via the broken line pattern.
  • the first thin film transistor is a shared thin film transistor
  • the second thin film transistor and the third thin film transistor are a main area thin film transistor and a secondary area thin film transistor, respectively.
  • the shading electrode wire and the shading electrode connection wire are indium tin oxide traces.
  • the fold line pattern is a right-angle fold line pattern.
  • the present invention also provides an array substrate including any of the pixel structures described above.
  • the present invention also provides a display device, including any of the pixel structures described above.
  • the pixel structure, the array substrate, and the display device of the present invention are designed to avoid the semiconductor layer of the thin film transistor through the patterned structure by the light shielding electrode connection line, thereby improving the effect on the off state of the thin film transistor when passing through the thin film transistor, and improving the display quality To increase the pixel aperture ratio.
  • FIG. 1 is a schematic diagram of an equivalent circuit of a conventional 3T pixel structure
  • FIG. 2 is a schematic cross-sectional view of a connection line of a light-shielding electrode at a thin film transistor T3 in a conventional 3T pixel structure;
  • FIG. 3 is a schematic top view of a light-shielding electrode connecting line at a thin film transistor T3 in a conventional 3T pixel structure;
  • FIG. 4 is a schematic cross-sectional view of a light-shielding electrode connection line at a first thin film transistor in a preferred embodiment of the pixel structure of the present invention
  • FIG. 5 is a schematic top view of a connection line of a light-shielding electrode at a first thin film transistor in a preferred embodiment of a pixel structure of the present invention
  • FIG. 6 is a schematic top view of a preferred embodiment of the pixel structure of the present invention.
  • Figure 4 It is a schematic cross-sectional view of the light-shielding electrode connecting line at the first thin-film transistor in a preferred embodiment of the pixel structure of the present invention.
  • 5 It is a schematic top view of the shading electrode connecting wire of the preferred embodiment.
  • the shading electrode connecting line 32 Winding to form a mesh pattern 33 ,
  • the semiconductor layer of the first thin film transistor 40 With mesh pattern 33 The hollowed-out areas are relatively arranged; a specific example of the first thin film transistor can be shown 1 Thin film transistor T3 , Mainly including gate 1 ,source / Drain 2 And the semiconductor layer 40 And other structures; pixel structure also includes color resist 50 ,The protective layer 60 Wait.
  • Shading electrode cable 32 Also includes straight parts 34 , Straight part 34 Via connection point 35 With mesh pattern 33 Connection point 35 Semiconductor layer 40 Does not overlap.
  • Fig 6 It is a schematic top view of a preferred embodiment of the pixel structure of the present invention.
  • the following figure 4 To figure 6 To illustrate the overall pixel structure of the preferred embodiment of the present invention, the preferred embodiment may specifically be 3T Eight-domain pixel structure, mainly including horizontal scanning lines 10 And vertical data lines 20 ; By crossed horizontal scan lines 10 And vertical data lines 20 A pixel electrode is provided in the defined pixel area; in the data line 20 A light shielding electrode line (not shown) is provided above to shield the data line 20 , The shading electrode line is connected to a common voltage during operation to function like a black matrix; the scan line 10 At least one thin film transistor connected to and controlling the pixel electrode is provided between the pixel electrode, and in this embodiment specifically includes a first thin film transistor (that is, a shared thin film transistor T3 ), The second thin film transistor (that is, the main area thin film transistor T1 ) And the third thin film transistor (that is, the sub-region thin film transistor T2 ), The gate and scanning line of each thin film transistor 10 For
  • the positions of the three thin film transistors in the pixel structure are in accordance with 3T
  • the eight-domain pixel structure is arranged and connected to the pixel electrodes corresponding to the main and sub-regions respectively.
  • the pixel electrodes of the main and sub-regions correspond to four domains respectively, totaling eight domains; common structures in pixel structures such as color 50 ,The protective layer 60 Wait, I won't repeat them here.
  • the pixel structure of the present invention further includes a light-shielding electrode connecting line 32 Along the scan line 10 Directional extension connects two adjacent shading electrode wires to each other electrically; shading electrode connecting wires 32 Can be designed to pass through the semiconductor layer of each thin film transistor 40 Directly above or diagonally above; in this embodiment, the shading electrode connection line 32 After the second thin film transistor and the third thin film transistor (that is, the main area thin film transistor T1 Thin film transistor T2 ) Obliquely above, sharing the thin film transistor after the first thin film crystal strand T3 Directly above; shading electrode cable 32 Both the light-shielding electrode wire and the light-shielding electrode wire can be traces of indium tin oxide, and can be made in the same layer.
  • the shading electrode connecting wire of the present invention 32 With a patterned structure to avoid the semiconductor layer of the thin film transistor through the patterned structure 40 Extend above the thin film transistor.
  • Shading electrode cable 32 At least including the mesh formed by winding ( mesh )pattern 33 , The semiconductor layer of the first thin film transistor 40 With the mesh pattern 33 The hollowed-out area is relatively arranged; the shading electrode connection line 32 Via mesh pattern 33 The semiconductor layer of the first thin film transistor can be avoided from directly above 40 , And can increase the aperture ratio of pixels.
  • Shading electrode cable 32 Also includes line charts 31 Case, the shading electrode connecting line 32 Via the polyline pattern 31 Bypassing the second thin film transistor, the main area thin film transistor T1 Semiconductor layer 40 , Shading electrode connecting wire 32 Via the polyline pattern 31 Also bypasses the third thin film transistor, the sub-region thin film transistor T2 Semiconductor layer 40 .
  • Shading electrode connecting wire 32 The patterned structure of at least includes a rectangular mesh pattern 33 , Can also be hollow mesh patterns of other suitable shapes, mesh patterns 33 Shared thin film transistor T3 Directly above, so that the shading electrode connection line 32 By sharing thin film transistors in segments T3 Directly above, through the mesh pattern 33 Of the hollow region avoids the semiconductor layer 40 To reduce the sharing of thin film transistors T3 Semiconductor layer 40 Interference while increasing the pixel aperture ratio.
  • Shading electrode connecting wire 32 Use right angle polyline patterns 31 Bypassing the main area thin film transistor from above diagonally T1 Thin film transistor T2 Semiconductor layer 40 Of course, you can also choose to use another mesh pattern to cover the main area of the thin film transistor T1 Thin film transistor T2 Directly above.
  • the light shielding electrode connecting line is designed to avoid the semiconductor layer of the thin film transistor through the patterned structure, for example, through the mesh pattern and / Or the broken line pattern avoids the semiconductor layer of the thin film transistor, which can reduce the interference to the semiconductor layer of the thin film transistor and reduce the leakage effect of the thin film transistor.
  • the mesh pattern can also play a role in improving the pixel aperture ratio.
  • the pixel structure includes only a first thin-film transistor
  • the light-shielding electrode connection line includes a mesh pattern directly above the first thin-film transistor. Through the mesh pattern, the light-shielding electrode connection line avoids the semiconductor layer of the first thin-film transistor and extends through the first The thin film transistor is directly above.
  • the pixel structure may further include at least a second thin film transistor, the light-shielding electrode connection line further includes a fold line pattern diagonally above the second thin-film transistor, and the light-shielding electrode connection line bypasses the semiconductor layer of the second TFT through the fold line pattern.
  • the present invention also correspondingly provides an embodiment of the array substrate and the display device including the above pixel structure.
  • the present invention by designing the light-shielding electrode connecting line to avoid the semiconductor layer of the thin film transistor, the interference to the thin film transistor can be reduced, the display quality can be improved, and the pixel aperture ratio can be increased to a certain extent.
  • the pixel structure, the array substrate, and the display device of the present invention are designed to avoid the semiconductor layer of the thin film transistor through the patterned structure by the light shielding electrode connection line, thereby improving the effect on the off state of the thin film transistor when passing through the thin film transistor, and improving the display quality To increase the pixel aperture ratio.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种像素结构、阵列基板及显示装置。该像素结构包括：扫描线（10）及数据线（20）；像素电极，设于由交叉的扫描线（10）和数据线（20）所限定的像素区域中；遮光电极线，连接至公共电压并且设于数据线（20）上方以遮蔽数据线（20）；第一薄膜晶体管T1，位于扫描线（10）与像素电极之间，并连接像素电极；遮光电极连接线（32），沿扫描线（10）方向延伸，并电性连接相邻两遮光电极线；遮光电极连接线（32）绕设形成网眼图案（33），第一薄膜晶体管T1的半导体层（40）与网眼图案（33）的镂空区域相对设置。还提供了相应的阵列基板及显示装置。通过将遮光电极连接线（32）设计为避开薄膜晶体管的半导体层（40），能够提高显示品质，增加像素开口率。

Description

像素结构、阵列基板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种像素结构、阵列基板及显示装置。
 背景技术
目前改善LCD大视角显示品味的方法主要应用3T（TFT，薄膜晶体管）技术，将子像素（sub pixel）的电压释放到公共（COM）电极上，从而达到8畴（domain）的显示效果。如图1所示，其为现有的3T像素结构的等效电路示意图，每个子像素可分为主区（Main）和次区（Sub），主要包括主区薄膜晶体管T1，主区存储电容C A，次区薄膜晶体管T2，次区存储电容C B，以及共享薄膜晶体管T3，对应每一行子像素分别设置一条扫描线scan，对应每一列子像素分别设置一条数据线Data。利用图1所示电路，可使同一个子像素内主区的4个畴与次区的4个畴的液晶分子的转动角度不一样，例如可应用于8畴3晶体管的PSVA（聚合物稳定垂直配向）像素。
同时，现有技术中为了曲面显示的目的，数据线方向取消黑色矩阵（BM）设计，改用氧化铟锡（ITO）遮光电极线覆盖数据线，并且连接至公共电压，与上板彩色滤光片（CF）的氧化铟锡公共电极电位一样，从而起到黑色矩阵的作用。为了增加遮光电极线电位的均匀性，通常会将数据线上方的遮光电极线通过像素中间的ITO遮光电极连接线左右连接起来，达到网格线（mesh line）的效果，减小遮光电极线的电阻值。
参见图2及图3，图2为现有3T像素结构中薄膜晶体管T3处的ITO遮光电极连接线的剖面示意图，图3为现有3T像素结构中薄膜晶体管T3处的ITO遮光电极连接线的俯视示意图。如图2和图3所示，薄膜晶体管T3包括栅极1、源/漏极2以及半导体层40等结构，由于用于布线的空间有限，同时为了增加开口率，遮光电极连接线30需要直接从薄膜晶体管T3的正上方经过薄膜晶体管T3的半导体层40。遮光电极连接线30与连接至公共电压的遮光电极线电位相同，一般来说公共电压在6V左右，虽然有色阻50相阻隔，遮光电极连接线30距离下面的薄膜晶体管T3较远，但是还是有栅极开关的作用，可能会影响薄膜晶体管T3的关态电流大小。显示时，即使下面薄膜晶体管T3的栅极（gate）已经处于关态状态，由于上表面的遮光电极连接线30上的公共电压的作用，薄膜晶体管T3没有完全关闭，影响显示效果。
 技术问题
因此，本发明的目的在于提供一种像素结构、阵列基板及显示装置，改善遮光电极连接线通过薄膜晶体管上方时对薄膜晶体管的影响。
 技术解决方案
为实现上述目的，本发明提供了一种像素结构，包括：
扫描线及数据线；
像素电极，设于由交叉的所述扫描线和所述数据线所限定的像素区域中；
遮光电极线，连接至公共电压并且设于所述数据线上方以遮蔽所述数据线；
第一薄膜晶体管，位于所述扫描线与所述像素电极之间，并连接所述像素电极；
遮光电极连接线，沿所述扫描线方向延伸，并电性连接相邻两所述遮光电极线；
所述遮光电极连接线绕设形成网眼图案，所述第一薄膜晶体管的半导体层与所述网眼图案的镂空区域相对设置。
其中，所述遮光电极连接线与所述半导体层至少部分重叠。
其中，所述遮光电极连接线还包括直线部分，所述直线部分与网眼图案的连接点与半导体层不重叠。
其中，所述像素结构还包括第二薄膜晶体管，所述遮光电极连接线还包括折线图案，所述遮光电极连接线经由所述折线图案绕过所述第二薄膜晶体管的半导体层。
其中，所述像素结构还包括第三薄膜晶体管，所述遮光电极连接线经由所述折线图案还绕过所述第三薄膜晶体管的半导体层。
其中，所述第一薄膜晶体管为共享薄膜晶体管，所述第二薄膜晶体管和第三薄膜晶体管分别为主区薄膜晶体管和次区薄膜晶体管。
其中，所述遮光电极线和遮光电极连接线为氧化铟锡走线。
其中，所述折线图案为直角折线图案。
本发明还提供了一种阵列基板，包括上述任一所述的像素结构。
本发明还提供了一种显示装置，包括上述任一所述的像素结构。
 有益效果
综上，本发明像素结构、阵列基板及显示装置通过将遮光电极连接线设计为通过图案化结构避开薄膜晶体管的半导体层，改善通过薄膜晶体管时，对薄膜晶体管关态的影响，提高显示品质，增加像素开口率。
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有的3T像素结构的等效电路示意图；
图2为现有3T像素结构中薄膜晶体管T3处的遮光电极连接线的剖面示意图；
图3为现有3T像素结构中薄膜晶体管T3处的遮光电极连接线的俯视示意图；
图4为本发明像素结构一较佳实施例中第一薄膜晶体管处的遮光电极连接线的剖面示意图；
图5为本发明像素结构一较佳实施例中第一薄膜晶体管处的遮光电极连接线的俯视示意图；
图6为本发明像素结构一较佳实施例的俯视示意图。
 本发明的实施方式
参见图 4 及图 5 ，图 4 为本发明像素结构一较佳实施例中第一薄膜晶体管处的遮光电极连接线的剖面示意图，图 5 为该较佳实施例的遮光电极连接线的俯视示意图。不同于现有像素结构，本发明的像素结构中：遮光电极连接线 32 绕设形成网眼图案 33 ，第一薄膜晶体管的半导体层 40 与网眼图案 33 的镂空区域相对设置；第一薄膜晶体管的一个具体实例可以为图 1 中的薄膜晶体管 T3 ，主要包括栅极 1 、源 / 漏极 2 以及半导体层 40 等结构；像素结构中还包括色阻 50 、保护层 60 等。由于空间有限，在此实施例中，所述遮光电极连接线 32 与所述半导体层 40 至少部分重叠；为减少对第一薄膜晶体管关态的影响，遮光电极连接线 32 需要尽可能避开半导体层 40 。遮光电极连接线 32 还包括直线部分 34 ，直线部分 34 通过连接点 35 与网眼图案 33 连接，连接点 35 与半导体层 40 不重叠。
图 6 为本发明像素结构一较佳实施例的俯视示意图。下面结合图 4 至图 6 来说明本发明该较佳实施例的整体像素结构，该较佳实施例具体可以为 3T 八畴像素结构，主要包括横向的扫描线 10 和纵向的数据线 20 ；由交叉的横向的扫描线 10 和纵向的数据线 20 所限定的像素区域中设有像素电极；在数据线 20 上方设有遮光电极线（图未示）以遮蔽数据线 20 ，工作时遮光电极线连接至公共电压以起到类似于黑色矩阵作用；所述扫描线 10 与所述像素电极之间设有连接并控制像素电极的至少一薄膜晶体管，在此实施例中具体包括第一薄膜晶体管（即共享薄膜晶体管 T3 ）、第二薄膜晶体管（即主区薄膜晶体管 T1 ）及第三薄膜晶体管（即次区薄膜晶体管 T2 ），各薄膜晶体管的栅极与扫描线 10 为同层金属形成，源 / 漏极与数据线 20 为同层金属形成；各薄膜晶体管的栅极可以连接扫描线 10 以接收扫描信号，源极可以连接数据线 20 以接收数据信号，漏极可以连接像素电极，各薄膜晶体管具有对应的半导体层 40 。在此实施例中，像素结构中的三个薄膜晶体管位置按照 3T 八畴像素结构进行布置，分别连接对应主区和次区的像素电极，主区和次区的像素电极各自对应四畴，合计八畴；像素结构中常见的结构如色阻 50 ，保护层 60 等，在此不再赘述。
本发明像素结构还包括，遮光电极连接线 32 沿扫描线 10 方向延伸将相邻两遮光电极线互相电性连接；遮光电极连接线 32 可以设计为经过各薄膜晶体管的半导体层 40 的正上方或斜上方；在此实施例中，遮光电极连接线 32 经过第二薄膜晶体管和第三薄膜晶体管（即主区薄膜晶体管 T1 和次区薄膜晶体管 T2 ）斜上方，经过第一薄膜晶体股即共享薄膜晶体管 T3 正上方；遮光电极连接线 32 和遮光电极线具体都可以为氧化铟锡走线，并且可以同层制作。
针对各薄膜晶体管的半导体层 40 ，本发明的遮光电极连接线 32 设有图案化结构，以通过图案化结构避开薄膜晶体管的半导体层 40 延伸经过薄膜晶体管上方。遮光电极连接线 32 至少包括绕设形成的网眼（ mesh ）图案 33 ，第一薄膜晶体管的半导体层 40 与所述网眼图案 33 的镂空区域相对设置；遮光电极连接线 32 经由网眼图案 33 可以从正上方避开第一薄膜晶体管的半导体层 40 ，并且可以增加像素的开口率。遮光电极连接线 32 还包括折线图 31 案，所述遮光电极连接线 32 经由所述折线图案 31 绕过所述第二薄膜晶体管即主区薄膜晶体管 T1 的半导体层 40 ，遮光电极连接线 32 经由所述折线图案 31 还绕过第三薄膜晶体管即次区薄膜晶体管 T2 的半导体层 40 。
在此实施例中，针对共享薄膜晶体管 T3 的半导体层 40 ，遮光电极连接线 32 的图案化结构至少包括一矩形的网眼图案 33 ，也可以为其他适合形状的中空的网眼图案，网眼图案 33 位于共享薄膜晶体管 T3 正上方，使得遮光电极连接线 32 以分段的形式通过共享薄膜晶体管 T3 正上方，通过网眼图案 33 的中空区域避开半导体层 40 ，减少对共享薄膜晶体管 T3 的半导体层 40 的干扰，同时增加像素的开口率。对于主区薄膜晶体管 T1 和次区薄膜晶体管 T2 ，遮光电极连接线 32 利用直角的折线图案 31 从斜上方绕过主区薄膜晶体管 T1 和次区薄膜晶体管 T2 的半导体层 40 ，当然，也可以选择利用另外的网眼图案覆盖到主区薄膜晶体管 T1 和次区薄膜晶体管 T2 正上方。
本发明通过将遮光电极连接线设计为通过图案化结构避开薄膜晶体管的半导体层，例如通过网眼图案和 / 或折线图案避开薄膜晶体管的半导体层，可以减少对薄膜晶体管半导体层的干扰，减少薄膜晶体管漏电效应，同时，通过网眼图案还可以起到提高像素开口率的作用。
前述较佳实施例仅作为本发明的举例，本发明的像素结构所包含薄膜晶体管的数量和位置也可以为其他配置。例如，像素结构中仅包含一第一薄膜晶体管，遮光电极连接线包括位于第一薄膜晶体管正上方的网眼图案，经由网眼图案，遮光电极连接线避开第一薄膜晶体管的半导体层延伸经过第一薄膜晶体管正上方。进一步，像素结构至少还可以包括一第二薄膜晶体管，遮光电极连接线还包括位于第二薄膜晶体管斜上方的折线图案，遮光电极连接线经由折线图案绕过第二薄膜晶体管的半导体层。
基于上述实施例的像素结构，本发明还相应提供了包括上述像素结构的阵列基板及显示装置的实施例。本发明通过将遮光电极连接线设计为避开薄膜晶体管的半导体层，可减少对薄膜晶体管的干扰，提高显示品质，也一定程度上提高像素开口率。
综上，本发明像素结构、阵列基板及显示装置通过将遮光电极连接线设计为通过图案化结构避开薄膜晶体管的半导体层，改善通过薄膜晶体管时，对薄膜晶体管关态的影响，提高显示品质，增加像素开口率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (20)

  1. 一种像素结构，包括：
    扫描线及数据线；
    像素电极，设于由交叉的所述扫描线和所述数据线所限定的像素区域中；
    遮光电极线，连接至公共电压并且设于所述数据线上方以遮蔽所述数据线；
    第一薄膜晶体管，位于所述扫描线与所述像素电极之间，并连接所述像素电极；
    遮光电极连接线，沿所述扫描线方向延伸，并电性连接相邻两所述遮光电极线；
    所述遮光电极连接线绕设形成网眼图案，所述第一薄膜晶体管的半导体层与所述网眼图案的镂空区域相对设置。
  2. 如权利要求1所述的像素结构，其中，所述遮光电极连接线与所述半导体层至少部分重叠。
  3. 如权利要求1所述的像素结构，其中，所述遮光电极连接线还包括直线部分，所述直线部分与网眼图案的连接点与半导体层不重叠。
  4. 如权利要求1所述的像素结构，还包括第二薄膜晶体管，所述遮光电极连接线还包括折线图案，所述遮光电极连接线经由所述折线图案绕过所述第二薄膜晶体管的半导体层。
  5. 如权利要求4所述的像素结构，还包括第三薄膜晶体管，所述遮光电极连接线经由所述折线图案还绕过所述第三薄膜晶体管的半导体层。
  6. 如权利要求5所述的像素结构，其中，所述第一薄膜晶体管为共享薄膜晶体管，所述第二薄膜晶体管和第三薄膜晶体管分别为主区薄膜晶体管和次区薄膜晶体管。
  7. 如权利要求1所述的像素结构，其中，所述遮光电极线和遮光电极连接线为氧化铟锡走线。
  8. 如权利要求4所述的像素结构，其中，所述折线图案为直角折线图案。
  9. 一种阵列基板，包括像素结构，所述像素结构包括：
    扫描线及数据线；
    像素电极，设于由交叉的所述扫描线和所述数据线所限定的像素区域中；
    遮光电极线，连接至公共电压并且设于所述数据线上方以遮蔽所述数据线；
    第一薄膜晶体管，位于所述扫描线与所述像素电极之间，并连接所述像素电极；
    遮光电极连接线，沿所述扫描线方向延伸，并电性连接相邻两所述遮光电极线；
    所述遮光电极连接线绕设形成网眼图案，所述第一薄膜晶体管的半导体层与所述网眼图案的镂空区域相对设置。
  10. 如权利要求9所述的阵列基板，其中，所述遮光电极连接线与所述半导体层至少部分重叠。
  11. 如权利要求9 所述的阵列基板，其中，所述遮光电极连接线还包括直线部分，所述直线部分与网眼图案的连接点与半导体层不重叠。
  12. 如权利要求9 所述的阵列基板，其中，所述像素结构还包括第二薄膜晶体管，所述遮光电极连接线还包括折线图案，所述遮光电极连接线经由所述折线图案绕过所述第二薄膜晶体管的半导体层。
  13. 如权利要求12 所述的阵列基板，其中，所述像素结构还包括第三薄膜晶体管，所述遮光电极连接线经由所述折线图案还绕过所述第三薄膜晶体管的半导体层。
  14. 如权利要求13 所述的阵列基板，其中，所述第一薄膜晶体管为共享薄膜晶体管，所述第二薄膜晶体管和第三薄膜晶体管分别为主区薄膜晶体管和次区薄膜晶体管。
  15. 如权利要求9 所述的阵列基板，其中，所述遮光电极线和遮光电极连接线为氧化铟锡走线。
  16. 如权利要求12 所述的阵列基板，其中，所述折线图案为直角折线图案。
  17. 一种显示装置，包括像素结构，所述像素结构包括：
    扫描线及数据线；
    像素电极，设于由交叉的所述扫描线和所述数据线所限定的像素区域中；
    遮光电极线，连接至公共电压并且设于所述数据线上方以遮蔽所述数据线；
    第一薄膜晶体管，位于所述扫描线与所述像素电极之间，并连接所述像素电极；
    遮光电极连接线，沿所述扫描线方向延伸，并电性连接相邻两所述遮光电极线；
    所述遮光电极连接线绕设形成网眼图案，所述第一薄膜晶体管的半导体层与所述网眼图案的镂空区域相对设置。
  18. 如权利要求17 所述的显示装置，其中，所述遮光电极连接线与所述半导体层至少部分重叠。
  19. 如权利要求17 所述的显示装置，其中，所述遮光电极连接线还包括直线部分，所述直线部分与网眼图案的连接点与半导体层不重叠。
  20. 如权利要求17 所述的显示装置，其中，所述像素结构还包括第二薄膜晶体管，所述遮光电极连接线还包括折线图案，所述遮光电极连接线经由所述折线图案绕过所述第二薄膜晶体管的半导体层；所述像素结构还包括第三薄膜晶体管，所述遮光电极连接线经由所述折线图案还绕过所述第三薄膜晶体管的半导体层；所述第一薄膜晶体管为共享薄膜晶体管，所述第二薄膜晶体管和第三薄膜晶体管分别为主区薄膜晶体管和次区薄膜晶体管。
PCT/CN2018/120985 2018-10-22 2018-12-13 像素结构、阵列基板及显示装置 WO2020082542A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/319,464 US11552105B2 (en) 2018-10-22 2018-12-13 Pixel structure, array substrate, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811232570.8 2018-10-22
CN201811232570.8A CN109343284B (zh) 2018-10-22 2018-10-22 像素结构、阵列基板及显示装置

Publications (1)

Publication Number Publication Date
WO2020082542A1 true WO2020082542A1 (zh) 2020-04-30

Family

ID=65311464

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/120985 WO2020082542A1 (zh) 2018-10-22 2018-12-13 像素结构、阵列基板及显示装置

Country Status (3)

Country Link
US (1) US11552105B2 (zh)
CN (1) CN109343284B (zh)
WO (1) WO2020082542A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI696991B (zh) * 2019-05-21 2020-06-21 友達光電股份有限公司 顯示裝置及其驅動方法
CN111681546B (zh) * 2019-07-26 2022-02-08 友达光电股份有限公司 元件阵列基板以及显示装置
CN111081717B (zh) * 2019-12-06 2022-10-04 Tcl华星光电技术有限公司 共享薄膜晶体管及显示面板
CN113050335A (zh) * 2021-03-15 2021-06-29 武汉华星光电技术有限公司 一种阵列基板、显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030137615A1 (en) * 2002-01-22 2003-07-24 Yoshiaki Nakayoshi Liquid crystal display device
US20110090446A1 (en) * 2009-10-19 2011-04-21 Kim Ji-Sun Display device
CN103293797A (zh) * 2012-06-08 2013-09-11 上海中航光电子有限公司 一种薄膜晶体管液晶显示装置及其制作方法
CN107121864A (zh) * 2017-07-07 2017-09-01 深圳市华星光电技术有限公司 阵列基板及液晶显示面板
CN107479271A (zh) * 2017-08-30 2017-12-15 深圳市华星光电技术有限公司 显示面板、阵列基板及其暗点化方法
CN107490912A (zh) * 2017-09-06 2017-12-19 深圳市华星光电技术有限公司 一种阵列基板、显示面板及显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102367320B1 (ko) * 2015-01-21 2022-02-25 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
CN104865766B (zh) * 2015-06-17 2018-06-19 南京中电熊猫液晶显示科技有限公司 多域垂直配向型液晶的像素结构
CN105116659B (zh) * 2015-09-28 2021-01-15 重庆京东方光电科技有限公司 阵列基板及其显示驱动方法、显示装置
CN107958910B (zh) * 2017-12-21 2020-06-12 惠科股份有限公司 主动开关阵列基板及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030137615A1 (en) * 2002-01-22 2003-07-24 Yoshiaki Nakayoshi Liquid crystal display device
US20110090446A1 (en) * 2009-10-19 2011-04-21 Kim Ji-Sun Display device
CN103293797A (zh) * 2012-06-08 2013-09-11 上海中航光电子有限公司 一种薄膜晶体管液晶显示装置及其制作方法
CN107121864A (zh) * 2017-07-07 2017-09-01 深圳市华星光电技术有限公司 阵列基板及液晶显示面板
CN107479271A (zh) * 2017-08-30 2017-12-15 深圳市华星光电技术有限公司 显示面板、阵列基板及其暗点化方法
CN107490912A (zh) * 2017-09-06 2017-12-19 深圳市华星光电技术有限公司 一种阵列基板、显示面板及显示装置

Also Published As

Publication number Publication date
CN109343284B (zh) 2020-10-30
CN109343284A (zh) 2019-02-15
US11552105B2 (en) 2023-01-10
US20210358953A1 (en) 2021-11-18

Similar Documents

Publication Publication Date Title
US10969641B2 (en) Liquid crystal display device
US9804450B2 (en) Liquid crystal display
WO2020082542A1 (zh) 像素结构、阵列基板及显示装置
TWI589972B (zh) 主動元件陣列基板及應用其之液晶面板
US9785017B2 (en) Liquid crystal display
US9400408B2 (en) Liquid crystal display
CN100373246C (zh) 平面开关模式有源矩阵型液晶显示器件及其制造方法
US8455870B2 (en) Thin film transistor array panel and method of manufacturing the same
TWI400537B (zh) 垂直配向液晶顯示器與其畫素結構
CN108983518B (zh) 阵列基板及其制备方法
KR20010039261A (ko) 수직 배향형 액정 표시 장치
TWI649607B (zh) 畫素結構及曲面顯示裝置
US10620487B2 (en) Pixel structure, array substrate, display device and method for manufacturing the same
JP2017151702A (ja) 表示装置
CN110018600A (zh) 阵列基板及液晶显示面板
CN107203076A (zh) 显示面板
JP2005122173A (ja) 横電界型の液晶表示装置
US8804082B2 (en) Liquid crystal display
US20080266230A1 (en) Liquid crystal display device
US20160109765A1 (en) Curved display device
JP6918090B2 (ja) 液晶表示装置
KR20170033935A (ko) 보상용 박막 트랜지스터를 구비한 액정 표시장치
JPWO2021102769A5 (zh)
CN117518543A (zh) 显示面板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18938136

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18938136

Country of ref document: EP

Kind code of ref document: A1