CN109343284B - 像素结构、阵列基板及显示装置 - Google Patents

像素结构、阵列基板及显示装置 Download PDF

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CN109343284B
CN109343284B CN201811232570.8A CN201811232570A CN109343284B CN 109343284 B CN109343284 B CN 109343284B CN 201811232570 A CN201811232570 A CN 201811232570A CN 109343284 B CN109343284 B CN 109343284B
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CN109343284A (zh
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叶成亮
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TCL Huaxing Photoelectric Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Abstract

本发明涉及一种像素结构、阵列基板及显示装置。该像素结构包括：扫描线及数据线；像素电极，设于由交叉的所述扫描线和所述数据线所限定的像素区域中；遮光电极线，连接至公共电压并且设于所述数据线上方以遮蔽所述数据线；第一薄膜晶体管，位于所述扫描线与所述像素电极之间，并连接所述像素电极；遮光电极连接线，沿所述扫描线方向延伸，并电性连接相邻两所述遮光电极线；所述遮光电极连接线绕设形成网眼图案，所述第一薄膜晶体管的半导体层与所述网眼图案的镂空区域相对设置。本发明还提供了相应的阵列基板及显示装置。本发明通过将遮光电极连接线设计为避开薄膜晶体管的半导体层，提高显示品质，增加像素开口率。

Description

像素结构、阵列基板及显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种像素结构、阵列基板及显示装置。
背景技术
目前改善LCD大视角显示品味的方法主要应用3T(TFT，薄膜晶体管)技术，将子像素(sub pixel)的电压释放到公共(COM)电极上，从而达到8畴(domain)的显示效果。如图1所示，其为现有的3T像素结构的等效电路示意图，每个子像素可分为主区(Main)和次区(Sub)，主要包括主区薄膜晶体管T1，主区存储电容CA，次区薄膜晶体管T2，次区存储电容CB，以及共享薄膜晶体管T3，对应每一行子像素分别设置一条扫描线scan，对应每一列子像素分别设置一条数据线Data。利用图1所示电路，可使同一个子像素内主区的4个畴与次区的4个畴的液晶分子的转动角度不一样，例如可应用于8畴3晶体管的PSVA(聚合物稳定垂直配向)像素。
同时，现有技术中为了曲面显示的目的，数据线方向取消黑色矩阵 (BM)设计，改用氧化铟锡(ITO)遮光电极线覆盖数据线，并且连接至公共电压，与上板彩色滤光片(CF)的氧化铟锡公共电极电位一样，从而起到黑色矩阵的作用。为了增加遮光电极线电位的均匀性，通常会将数据线上方的遮光电极线通过像素中间的ITO遮光电极连接线左右连接起来，达到网格线(mesh line)的效果，减小遮光电极线的电阻值。
参见图2及图3，图2为现有3T像素结构中薄膜晶体管T3处的ITO遮光电极连接线的剖面示意图，图3为现有3T像素结构中薄膜晶体管T3处的 ITO遮光电极连接线的俯视示意图。如图2和图3所示，薄膜晶体管T3包括栅极1、源/漏极2以及半导体层40等结构，由于用于布线的空间有限，同时为了增加开口率，遮光电极连接线30需要直接从薄膜晶体管T3的正上方经过薄膜晶体管T3的半导体层40。遮光电极连接线30与连接至公共电压的遮光电极线电位相同，一般来说公共电压在6V左右，虽然有色阻50相阻隔，遮光电极连接线30距离下面的薄膜晶体管T3较远，但是还是有栅极开关的作用，可能会影响薄膜晶体管T3的关态电流大小。显示时，即使下面薄膜晶体管T3的栅极(gate)已经处于关态状态，由于上表面的遮光电极连接线30 上的公共电压的作用，薄膜晶体管T3没有完全关闭，影响显示效果。
发明内容
因此，本发明的目的在于提供一种像素结构、阵列基板及显示装置，改善遮光电极连接线通过薄膜晶体管上方时对薄膜晶体管的影响。
为实现上述目的，本发明提供了一种像素结构，包括：
扫描线及数据线；
像素电极，设于由交叉的所述扫描线和所述数据线所限定的像素区域中；
遮光电极线，连接至公共电压并且设于所述数据线上方以遮蔽所述数据线；
第一薄膜晶体管，位于所述扫描线与所述像素电极之间，并连接所述像素电极；
遮光电极连接线，沿所述扫描线方向延伸，并电性连接相邻两所述遮光电极线；
所述遮光电极连接线绕设形成网眼图案，所述第一薄膜晶体管的半导体层与所述网眼图案的镂空区域相对设置。
其中，所述遮光电极连接线与所述半导体层至少部分重叠。
其中，所述遮光电极连接线还包括直线部分，所述直线部分与网眼图案的连接点与半导体层不重叠。
其中，所述像素结构还包括第二薄膜晶体管，所述遮光电极连接线还包括折线图案，所述遮光电极连接线经由所述折线图案绕过所述第二薄膜晶体管的半导体层。
其中，所述像素结构还包括第三薄膜晶体管，所述遮光电极连接线经由所述折线图案还绕过所述第三薄膜晶体管的半导体层。
其中，所述第一薄膜晶体管为共享薄膜晶体管，所述第二薄膜晶体管和第三薄膜晶体管分别为主区薄膜晶体管和次区薄膜晶体管。
其中，所述遮光电极线和遮光电极连接线为氧化铟锡走线。
其中，所述折线图案为直角折线图案。
本发明还提供了一种阵列基板，包括上述任一所述的像素结构。
本发明还提供了一种显示装置，包括上述任一所述的像素结构。
综上，本发明像素结构、阵列基板及显示装置通过将遮光电极连接线设计为通过图案化结构避开薄膜晶体管的半导体层，改善通过薄膜晶体管时，对薄膜晶体管关态的影响，提高显示品质，增加像素开口率。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有的3T像素结构的等效电路示意图；
图2为现有3T像素结构中薄膜晶体管T3处的遮光电极连接线的剖面示意图；
图3为现有3T像素结构中薄膜晶体管T3处的遮光电极连接线的俯视示意图；
图4为本发明像素结构一较佳实施例中第一薄膜晶体管处的遮光电极连接线的剖面示意图；
图5为本发明像素结构一较佳实施例中第一薄膜晶体管处的遮光电极连接线的俯视示意图；
图6为本发明像素结构一较佳实施例的俯视示意图。
具体实施方式
参见图4及图5，图4为本发明像素结构一较佳实施例中第一薄膜晶体管处的遮光电极连接线的剖面示意图，图5为该较佳实施例的遮光电极连接线的俯视示意图。不同于现有像素结构，本发明的像素结构中：遮光电极连接线32绕设形成网眼图案33，第一薄膜晶体管的半导体层40与网眼图案33 的镂空区域相对设置；第一薄膜晶体管的一个具体实例可以为图1中的薄膜晶体管T3，主要包括栅极1、源/漏极2以及半导体层40等结构；像素结构中还包括色阻50、保护层60等。由于空间有限，在此实施例中，所述遮光电极连接线32与所述半导体层40至少部分重叠；为减少对第一薄膜晶体管关态的影响，遮光电极连接线32需要尽可能避开半导体层40。遮光电极连接线32还包括直线部分34，直线部分34通过连接点35与网眼图案33连接，连接点35与半导体层40不重叠。
图6为本发明像素结构一较佳实施例的俯视示意图。下面结合图4至图 6来说明本发明该较佳实施例的整体像素结构，该较佳实施例具体可以为3T 八畴像素结构，主要包括横向的扫描线10和纵向的数据线20；由交叉的横向的扫描线10和纵向的数据线20所限定的像素区域中设有像素电极；在数据线20上方设有遮光电极线(图未示)以遮蔽数据线20，工作时遮光电极线连接至公共电压以起到类似于黑色矩阵作用；所述扫描线10与所述像素电极之间设有连接并控制像素电极的至少一薄膜晶体管，在此实施例中具体包括第一薄膜晶体管(即共享薄膜晶体管T3)、第二薄膜晶体管(即主区薄膜晶体管T1)及第三薄膜晶体管(即次区薄膜晶体管T2)，各薄膜晶体管的栅极与扫描线10为同层金属形成，源/漏极与数据线20为同层金属形成；各薄膜晶体管的栅极可以连接扫描线10以接收扫描信号，源极可以连接数据线 20以接收数据信号，漏极可以连接像素电极，各薄膜晶体管具有对应的半导体层40。在此实施例中，像素结构中的三个薄膜晶体管位置按照3T八畴像素结构进行布置，分别连接对应主区和次区的像素电极，主区和次区的像素电极各自对应四畴，合计八畴；像素结构中常见的结构如色阻50，保护层60 等，在此不再赘述。
本发明像素结构还包括，遮光电极连接线32沿扫描线10方向延伸将相邻两遮光电极线互相电性连接；遮光电极连接线32可以设计为经过各薄膜晶体管的半导体层40的正上方或斜上方；在此实施例中，遮光电极连接线32 经过第二薄膜晶体管和第三薄膜晶体管(即主区薄膜晶体管T1和次区薄膜晶体管T2)斜上方，经过第一薄膜晶体股即共享薄膜晶体管T3正上方；遮光电极连接线32和遮光电极线具体都可以为氧化铟锡走线，并且可以同层制作。
针对各薄膜晶体管的半导体层40，本发明的遮光电极连接线32设有图案化结构，以通过图案化结构避开薄膜晶体管的半导体层40延伸经过薄膜晶体管上方。遮光电极连接线32至少包括绕设形成的网眼(mesh)图案33，第一薄膜晶体管的半导体层40与所述网眼图案33的镂空区域相对设置；遮光电极连接线32经由网眼图案33可以从正上方避开第一薄膜晶体管的半导体层40，并且可以增加像素的开口率。遮光电极连接线32还包括折线图案31，所述遮光电极连接线32经由所述折线图案31绕过所述第二薄膜晶体管即主区薄膜晶体管T1的半导体层40，遮光电极连接线32经由所述折线图案 31还绕过第三薄膜晶体管即次区薄膜晶体管T2的半导体层40。
在此实施例中，针对共享薄膜晶体管T3的半导体层40，遮光电极连接线32的图案化结构至少包括一矩形的网眼图案33，也可以为其他适合形状的中空的网眼图案，网眼图案33位于共享薄膜晶体管T3正上方，使得遮光电极连接线32以分段的形式通过共享薄膜晶体管T3正上方，通过网眼图案 33的中空区域避开半导体层40，减少对共享薄膜晶体管T3的半导体层40的干扰，同时增加像素的开口率。对于主区薄膜晶体管T1和次区薄膜晶体管T2，遮光电极连接线32利用直角的折线图案31从斜上方绕过主区薄膜晶体管T1和次区薄膜晶体管T2的半导体层40，当然，也可以选择利用另外的网眼图案覆盖到主区薄膜晶体管T1和次区薄膜晶体管T2正上方。
本发明通过将遮光电极连接线设计为通过图案化结构避开薄膜晶体管的半导体层，例如通过网眼图案和/或折线图案避开薄膜晶体管的半导体层，可以减少对薄膜晶体管半导体层的干扰，减少薄膜晶体管漏电效应，同时，通过网眼图案还可以起到提高像素开口率的作用。
前述较佳实施例仅作为本发明的举例，本发明的像素结构所包含薄膜晶体管的数量和位置也可以为其他配置。例如，像素结构中仅包含一第一薄膜晶体管，遮光电极连接线包括位于第一薄膜晶体管正上方的网眼图案，经由网眼图案，遮光电极连接线避开第一薄膜晶体管的半导体层延伸经过第一薄膜晶体管正上方。进一步，像素结构至少还可以包括一第二薄膜晶体管，遮光电极连接线还包括位于第二薄膜晶体管斜上方的折线图案，遮光电极连接线经由折线图案绕过第二薄膜晶体管的半导体层。
基于上述实施例的像素结构，本发明还相应提供了包括上述像素结构的阵列基板及显示装置的实施例。本发明通过将遮光电极连接线设计为避开薄膜晶体管的半导体层，可减少对薄膜晶体管的干扰，提高显示品质，也一定程度上提高像素开口率。
综上，本发明像素结构、阵列基板及显示装置通过将遮光电极连接线设计为通过图案化结构避开薄膜晶体管的半导体层，改善通过薄膜晶体管时，对薄膜晶体管关态的影响，提高显示品质，增加像素开口率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (9)

1.一种像素结构，其特征在于，包括：
扫描线及数据线；
像素电极，设于由交叉的所述扫描线和所述数据线所限定的像素区域中；
遮光电极线，连接至公共电压并且设于所述数据线上方以遮蔽所述数据线；
第一薄膜晶体管，位于所述扫描线与所述像素电极之间，并连接所述像素电极；
遮光电极连接线，沿所述扫描线方向延伸，并电性连接相邻两所述遮光电极线；
所述遮光电极连接线绕设形成网眼图案，所述第一薄膜晶体管的半导体层与所述网眼图案的镂空区域相对设置；
所述遮光电极连接线还包括直线部分，所述直线部分与网眼图案的连接点与半导体层不重叠。
2.如权利要求1所述的像素结构，其特征在于，所述遮光电极连接线与所述半导体层至少部分重叠。
3.如权利要求1所述的像素结构，其特征在于，所述像素结构还包括第二薄膜晶体管，所述遮光电极连接线还包括折线图案，所述遮光电极连接线经由所述折线图案绕过所述第二薄膜晶体管的半导体层。
4.如权利要求3所述的像素结构，其特征在于，所述像素结构还包括第三薄膜晶体管，所述遮光电极连接线经由所述折线图案还绕过所述第三薄膜晶体管的半导体层。
5.如权利要求4所述的像素结构，其特征在于，所述第一薄膜晶体管为共享薄膜晶体管，所述第二薄膜晶体管和第三薄膜晶体管分别为主区薄膜晶体管和次区薄膜晶体管。
6.如权利要求1所述的像素结构，其特征在于，所述遮光电极线和遮光电极连接线为氧化铟锡走线。
7.如权利要求3所述的像素结构，其特征在于，所述折线图案为直角折线图案。
8.一种阵列基板，其特征在于，包括如权利要求1～7任一所述的像素结构。
9.一种显示装置，其特征在于，包括如权利要求1～7任一所述的像素结构。
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