WO2022104801A1 - 半导体器件及其制作方法 - Google Patents

半导体器件及其制作方法 Download PDF

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Publication number
WO2022104801A1
WO2022104801A1 PCT/CN2020/130919 CN2020130919W WO2022104801A1 WO 2022104801 A1 WO2022104801 A1 WO 2022104801A1 CN 2020130919 W CN2020130919 W CN 2020130919W WO 2022104801 A1 WO2022104801 A1 WO 2022104801A1
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region
layer
support structure
semiconductor device
nanowire
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PCT/CN2020/130919
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to CN202080028944.3A priority Critical patent/CN116325092A/zh
Priority to PCT/CN2020/130919 priority patent/WO2022104801A1/zh
Publication of WO2022104801A1 publication Critical patent/WO2022104801A1/zh
Priority to US18/063,867 priority patent/US20230106052A1/en

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    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof.
  • Wide-bandgap semiconductor materials, group III nitrides, as a typical representative of the third-generation semiconductor materials, have the excellent characteristics of large band gap, high pressure resistance, high temperature resistance, high electron saturation speed and drift speed, and easy formation of high-quality heterostructures. Ideal for manufacturing high temperature, high frequency, high power electronic devices.
  • a high breakdown voltage means that the device operates in a wider voltage range, enabling higher power density and higher device reliability. Therefore, how to improve the breakdown voltage of the device is the focus of electronic device researchers.
  • the object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can improve the breakdown voltage.
  • a semiconductor device comprising:
  • the substrate includes a first region, and a second region and a third region respectively located on both sides of the first region;
  • a first support structure on at least the second area and the third area
  • a first nanowire heterojunction comprising a first gate segment corresponding to the first region, a first source segment corresponding to the second region, and a first source segment corresponding to the second region a first drain segment of the third region; the first source segment and the first drain segment are located on the first support structure;
  • the first support structure is located only on the second area and the third area.
  • the substrate further includes a fourth area located between the first area and the second area, and a fifth area located between the first area and the third area; the first area A support structure is located on the second area and the fourth area.
  • a gate insulating layer is provided between the first gate segment and the ring gate.
  • the first nanowire heterojunction has a plurality of strips.
  • each of the first nanowire heterojunctions shares the first source region and/or the first drain region.
  • annular gates covering each of the first nanowire heterojunctions are separated from each other, or the annular gates covering each of the first nanowire heterojunctions are connected to each other.
  • the semiconductor device further includes:
  • a second nanowire heterojunction comprising a second gate segment corresponding to the first region, a second source segment corresponding to the second region, and a second source segment corresponding to the second region a second drain section of the third region; the second source section and the second drain section are located on the second support structure.
  • the second nanowire heterojunction has a plurality of strips.
  • each of the second nanowire heterojunctions shares the second source section and/or the second drain section.
  • the ring-shaped gate is coated on one of the second nanowire heterojunctions and the first nanowire heterojunction directly below the one second nanowire heterojunction.
  • a substrate is provided, the substrate includes a first area, and a second area and a third area respectively located on both sides of the first area; at least a first support is formed on the second area and the third area structure; forming a first sacrificial layer on the substrate exposed by the first support structure;
  • a first nanowire heterojunction is grown on the first support structure and the first sacrificial layer, the first nanowire heterojunction includes a first gate segment corresponding to the first region, a corresponding a first source segment in the second region and a first drain segment corresponding to the third region; the first source segment and the first drain segment are located in the first On a support structure, at least the first gate segment is located on the first sacrificial layer;
  • a source is formed on the first source section, a drain is formed on the first drain section, and a ring gate is formed overlying the first gate section.
  • the first support structure is only located on the second region and the third region; after removing the first sacrificial layer, the suspended first nanowire heterojunction is formed from the first nanowire heterojunction.
  • a source segment extends to the first drain segment.
  • a gate insulating layer is covered on the first gate section; the ring gate covers the gate insulating layer.
  • the grown first nanowire heterojunction is multiple.
  • each of the first nanowire heterojunctions shares the first source region and/or the first drain region.
  • the forming the first support structure includes: growing a first epitaxial layer on the substrate; patterning the first epitaxial layer, at least retaining all the second region and the third region. the first epitaxial layer to form the first support structure;
  • first patterned mask layer on the substrate, the first patterned mask layer has a first opening, and the first opening exposes at least the second region and the third region ;
  • first patterned mask layer as a mask, epitaxially growing the first support structure on the substrate.
  • the forming the first sacrificial layer includes: growing a first sacrificial layer on the first supporting structure and the substrate exposed by the first supporting structure, and removing the first sacrificial layer on the first supporting structure. the first sacrificial layer;
  • the manufacturing method of the semiconductor device further includes:
  • a second nanowire heterojunction is grown on the second support structure and the second sacrificial layer, the second nanowire heterojunction including a second gate segment corresponding to the first region, a corresponding A second source segment in the second region and a second drain segment corresponding to the third region; the second source segment and the second drain segment are located in the first On two supporting structures, at least the second gate segment is located on the second sacrificial layer;
  • the second sacrificial layer is removed, and the second nanowire heterojunction is suspended.
  • the forming the second support structure includes: growing a second epitaxial layer on the first nanowire heterojunction; patterning the second epitaxial layer, at least retaining the first source section and the the second epitaxial layer on the first drain segment to form the second support structure;
  • the second patterned mask layer having a second opening, the second opening at least exposing the first source electrode section and the first drain section; using the second patterned mask layer as a mask, the second support structure is epitaxially grown on the first nanowire heterojunction.
  • the forming the second sacrificial layer includes: growing a second sacrificial layer on the second support structure and the first nanowire heterojunction exposed by the second support structure, and removing the first nanowire heterojunction. the second sacrificial layer on the two supporting structures;
  • the material of the first sacrificial layer and/or the second sacrificial layer is N-type GaN.
  • the removal of the first sacrificial layer and/or the removal of the second sacrificial layer is achieved by using a selective etching solution.
  • the two-dimensional electron gas carriers or two-dimensional hole gas carriers in the heterojunction exhibit approximately one-dimensional transport during the migration process. In this way, the carrier mobility can be improved.
  • the ability of the ring gate to control the carriers is also greatly improved, so the breakdown voltage of the device can be greatly improved, the leakage problem can be reduced, and the efficiency and linearity of the radio frequency device can be improved.
  • the first support structure is located only on the second area and the third area; or b) the substrate further includes a fourth area located between the first area and the second area, and is located on the first area. A fifth area between the area and the third area; the first support structure is located on the second area and the fourth area, and on the third area and the fifth area.
  • the advantage of the a) scheme is that the suspended section of the first nanowire heterojunction can be increased, thereby reducing the probability of annihilation between the carriers in the heterojunction and the contact layer.
  • a) the ring gate directly contacts the first gate segment; or b) there is a gate insulating layer between the ring gate and the first gate segment.
  • the advantage of the b) scheme is that the MIS gate can reduce the gate leakage current.
  • the first nanowire heterojunction has a plurality of first nanowire heterojunctions, and each of the first nanowire heterojunctions shares the first source segment and the first drain segment.
  • annular gates covering each of the first nanowire heterojunctions are separated from each other, or the annular gates covering each of the first nanowire heterojunctions are connected together.
  • FIG. 1 is a schematic three-dimensional structure diagram of a semiconductor device according to a first embodiment of the present invention
  • FIG. 2(a) and FIG. 2(b) are cross-sectional views along line AA in FIG. 1, wherein the structures of the first nanowire heterojunction are different;
  • Fig. 2(c) is a schematic diagram of coating a first anti-scattering layer around the first nanowire heterojunction of Fig. 2(a);
  • FIG. 3 is a schematic three-dimensional structural diagram of the semiconductor structure after removing the source electrode, the drain electrode and the annular gate in FIG. 1;
  • FIG. 4 is a flowchart of a method for fabricating the semiconductor device in FIG. 1 to FIG. 2( c );
  • 5 to 8(b) are schematic diagrams of intermediate structures corresponding to the process in FIG. 4;
  • FIG. 9 is a schematic three-dimensional structure diagram of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 11 is a schematic three-dimensional structure diagram of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 12 is a schematic three-dimensional structure diagram of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 13 is a schematic three-dimensional structure diagram of a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 14(a) and FIG. 14(b) are cross-sectional views along line BB in FIG. 13 , wherein the structures of the second nanowire heterojunction are different;
  • Fig. 14(c) is a schematic diagram of coating a second anti-scattering layer around the second nanowire heterojunction of Fig. 14(a);
  • FIG. 15 is a schematic three-dimensional structural diagram of the semiconductor structure after removing the source electrode, the drain electrode and the annular gate in FIG. 13;
  • FIG. 16 is a schematic three-dimensional structure diagram of the semiconductor structure after the gate insulating layer in FIG. 15 is removed;
  • FIG. 17 is a flowchart of a method of fabricating the semiconductor device in FIGS. 13 to 14( c );
  • 18 to 20 are schematic diagrams of intermediate structures corresponding to the process in FIG. 17;
  • 21 is a schematic three-dimensional structure diagram of a semiconductor device according to a sixth embodiment of the present invention.
  • FIG. 22 is a schematic three-dimensional structure diagram of a semiconductor device according to a seventh embodiment of the present invention.
  • FIG. 23 is a schematic three-dimensional structure diagram of a semiconductor device according to an eighth embodiment of the present invention.
  • FIG. 24 is a schematic three-dimensional structural diagram of the semiconductor structure after removing the source electrode, the drain electrode and the ring gate in FIG. 23;
  • FIG. 25 is a schematic three-dimensional structural diagram of the semiconductor structure after the gate insulating layer in FIG. 24 is removed;
  • FIG. 26 is a schematic three-dimensional structure diagram of a semiconductor device according to a ninth embodiment of the present invention.
  • the second area 10b The third area 10c
  • first support structure 11 first nanowire heterojunction 12
  • first channel layer 121 first barrier layer 122
  • first source segment 12b first drain segment 12c
  • Second channel layer 161 Second barrier layer 162
  • Second back barrier layer 163 Second anti-scattering layer 142
  • the first sacrificial layer 17 The first epitaxial layer 11'
  • the second epitaxial layer 15' The second sacrificial layer 18
  • FIG. 1 is a schematic three-dimensional structure diagram of a semiconductor device according to a first embodiment of the present invention.
  • 2( a ) and FIG. 2( b ) are cross-sectional views along line AA in FIG. 1 , wherein the structures of the first nanowire heterojunction are different.
  • FIG. 2( c ) is a schematic diagram illustrating that a first anti-scattering layer is coated around the first nanowire heterojunction of FIG. 2( a ).
  • FIG. 3 is a schematic three-dimensional structure diagram of the semiconductor structure after removing the source electrode, the drain electrode and the ring gate in FIG. 1 .
  • the semiconductor device 1 includes:
  • the substrate 10 includes a first region 10a, and a second region 10b and a third region 10c respectively located on both sides of the first region 10a;
  • the first nanowire heterojunction 12 includes a first gate segment 12a corresponding to the first region 10a, a first source segment 12b corresponding to the second region 10b, and a first source segment 12b corresponding to the second region 10b.
  • the first drain section 12c of the third region 10c; the first source section 12b and the first drain section 12c are located on the first support structure 11;
  • the material of the substrate 10 may be sapphire, silicon carbide, silicon, silicon-on-insulator (SOI), diamond, or lithium niobate or other materials.
  • the substrate 10 may have a buffer layer thereon. There may be a nucleation layer between the buffer layer and the substrate 10 .
  • the material of the nucleation layer may be a group III nitride-based material, such as AlN, AlGaN, and the like.
  • the material of the buffer layer can also be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.
  • the nucleation layer can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer and the substrate 10 .
  • the buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, such as the first support structure 11 , and improve the crystal quality.
  • the material of the first support structure 11 may be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN, or a dielectric material, such as silicon dioxide.
  • the length dimension of the first nanowire heterojunction 12 is much larger than the two-dimensional dimension on the vertical section.
  • the vertical section is the section along the thickness direction.
  • the first nanowire heterojunction 12 may include a first channel layer 121 and a first barrier layer 122 from bottom to top. Two-dimensional electron gas or two-dimensional hole gas may be formed at the interface between the first channel layer 121 and the first barrier layer 122 .
  • the first channel layer 121 is an intrinsic GaN layer
  • the first barrier layer 122 is an N-type AlGaN layer.
  • the materials of the first channel layer 121 and the first barrier layer 122 may also be at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.
  • first channel layer 121 and the first barrier layer 122 shown in FIG. 2(a) having one layer respectively; the first channel layer 121 and the first barrier layer 122 may also have multiple layers respectively, and alternately distributed; or a first channel layer 121 and two or more first barrier layers 122 to form a multi-barrier structure.
  • the first nanowire heterojunction 12 may also include a first back barrier layer 123 , a first channel layer 121 and a first barrier layer 122 from bottom to top .
  • the first back barrier layer 123 , the first channel layer 121 and the first barrier layer 122 may each have one layer; the first back barrier layer 123 , the first channel layer 121 and the first barrier layer 122 may also have one layer. They have multiple layers and are alternately distributed.
  • the advantage of this embodiment is that the first back barrier layer 123 and the first barrier layer 122 can confine the carriers in the first channel layer 121 to prevent carriers Fluid leaks.
  • the first nanowire heterojunction 12 may only include the first back barrier layer 123 and the first channel layer 121 from bottom to top.
  • the first anti-scattering layer 141 is coated around the first nanowire heterojunction 12 shown in FIG. 2( a ). In other embodiments, the first anti-scattering layer 141 may also wrap around the first nanowire heterojunction 12 shown in FIG. 2( b ). The first anti-scattering layer 141 can reduce the scattering of carriers on the outer surface of the first nanowire heterojunction 12 to prevent leakage of carriers.
  • the first anti-scattering layer 141 may sequentially include an AlN layer and an AlGaN layer from the inside out.
  • the number of the first nanowire heterojunctions 12 is three. In other embodiments, the number of the first nanowire heterojunctions 12 may be one or two.
  • Ohmic contacts are formed between the source electrode 13b and the first source segment 12b, between the drain electrode 13c and the first drain segment 12c, and between the ring gate 13a and the first gate segment 12a.
  • the material of the source electrode 13b, the drain electrode 13c, and the ring-shaped gate 13a may be metal, such as existing conductive materials such as Ti/Al/Ni/Au, Ni/Au, and the like.
  • between the source 13b and the first source section 12b, between the drain 13c and the first drain section 12c, and between the ring gate 13a and the first gate section 12a can be utilized.
  • the N-type ion heavily doped layer forms an ohmic contact.
  • the N-type ion heavily doped layer can make the gap between the source electrode 13b and the first source region 12b, between the drain electrode 13c and the first drain region 12c, and between the ring gate 13a and the first gate region 12a.
  • the ohmic contact layer can be directly formed without annealing at high temperature, and the performance of the first nanowire heterojunction 12 and the electron migration rate can be prevented from being degraded due to the high temperature in the annealing process.
  • the N-type ions may be at least one of Si ions, Ge ions, Sn ions, Se ions and Te ions.
  • the doping concentration can be greater than 1E18/cm 3 .
  • the N-type ion heavily doped layer may be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.
  • the two-dimensional electron gas carriers or two-dimensional hole gas carriers in the heterojunction 12 exhibit approximately one-dimensional transport during the migration process. In this way, the carrier mobility can be improved.
  • the ability of the ring gate 13a to control carriers is also greatly improved, so the breakdown voltage of the device can be greatly improved, the leakage problem can be reduced, and the efficiency and linearity of the radio frequency device can be improved.
  • FIG. 4 is a flowchart of a production method.
  • FIG. 5 to FIG. 8( b ) are schematic diagrams of intermediate structures corresponding to the process in FIG. 4 .
  • a substrate 10 is provided.
  • the substrate 10 includes a first region 10a, and a second region 10b and a third region 10c on both sides of the first region 10a;
  • a first support structure 11 is formed on the second region 10b and the third region 10c ;
  • a first sacrificial layer 17 is formed on the substrate 10 exposed by the first support structure 11 .
  • the material of the substrate 10 may be sapphire, silicon carbide, silicon, silicon-on-insulator (SOI), diamond, or lithium niobate or other materials.
  • a nucleation layer and a buffer layer may be grown on the substrate 10 in sequence.
  • the material of the nucleation layer may be a group III nitride-based material, such as AlN, AlGaN, and the like.
  • the material of the buffer layer can also be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.
  • the nucleation layer can alleviate the problem of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer and the substrate 10, and the buffer layer can reduce the dislocation density and defects of the epitaxially grown semiconductor layer, such as the first support structure 11 Density, improve crystal quality.
  • the epitaxial growth process of the nucleation layer and/or the buffer layer may include: atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxy (MBE, Molecular Beam Epitaxy), or Plasma Enhanced Chemical Vapor Deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or Low Pressure Chemical Vapor Deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or Metal Organic Compound Chemical Vapor Deposition (MOCVD, Metal -Organic Chemical Vapor Deposition), or a combination thereof.
  • ALD Atomic layer deposition
  • CVD Chemical Vapor Deposition
  • MBE molecular beam epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • MOCVD Metal Organic Compound Chemical Vapor Deposition
  • forming the first support structure 11 specifically includes: as shown in FIG. 6 , growing a first epitaxial layer 11 ′ on the substrate 10 ; as shown in FIG. 5 , patterning the first epitaxial layer 11 ′ and retaining the first epitaxial layer 11 ′.
  • the first epitaxial layer 11 ′ on the second region 10 b and the third region 10 c forms the first support structure 11 .
  • the material of the first epitaxial layer 11 ′ may be a group III nitride based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.
  • the patterning of the first epitaxial layer 11' may be implemented by dry etching or wet etching.
  • the first epitaxial layer 11 ′ can also be replaced with a first material layer.
  • the material of the first material layer is, for example, silicon nitride, silicon dioxide, silicon oxynitride, etc., corresponding to physical vapor deposition or chemical vapor deposition. formed by deposition.
  • forming the first support structure 11 may further include: forming a first patterned mask layer on the substrate 10, the first patterned mask layer having a first opening, and the first opening exposes the second region 10b and the third region 10 c ; using the first patterned mask layer as a mask, the first support structure 11 is epitaxially grown on the substrate 10 . After that, the first patterned mask layer is removed.
  • the material of the first patterned mask layer is, for example, silicon nitride, silicon dioxide, silicon oxynitride, etc., and is formed by physical vapor deposition or chemical vapor deposition.
  • the material of the first support structure 11 may be a group III nitride based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.
  • forming the first sacrificial layer 17 specifically includes: growing the first sacrificial layer 17 on the first supporting structure 11 and the substrate 10 exposed by the first supporting structure 11 , and removing the first sacrificial layer 17 on the first supporting structure 11 . sacrificial layer 17 .
  • the material of the first sacrificial layer 17 may be a GaN-based material, such as N-type GaN.
  • the epitaxial growth process of the first sacrificial layer 17 may refer to the epitaxial growth process of the nucleation layer and/or the buffer layer.
  • the first sacrificial layer 17 on the first support structure 11 can be removed by dry etching or wet etching.
  • the material of the first sacrificial layer 17 can also be, for example, silicon nitride, silicon dioxide, etc., and is formed by a physical vapor deposition method or a chemical vapor deposition method.
  • forming the first sacrificial layer 17 may specifically include: growing the first sacrificial layer 17 on the substrate 10 by using the first support structure 11 as a mask. This embodiment is applicable to the case where the material of the first support structure 11 is silicon nitride, silicon dioxide, etc., and the first sacrificial layer 17 cannot be grown thereon.
  • the first sacrificial layer 17 on the substrate 10 is flush with the upper surface of the first support structure 11 .
  • the upper surface of the first sacrificial layer 17 on the substrate 10 may be higher than or lower than the upper surface of the first supporting structure 11 .
  • a first nanowire heterojunction 12 is grown on the first support structure 11 and the first sacrificial layer 17 .
  • the linear heterojunction 12 includes a first gate section 12a corresponding to the first region 10a, a first source section 12b corresponding to the second region 10b, and a first drain section 12c corresponding to the third region 10c ; the first source section 12b and the first drain section 12c are located on the first support structure 11, and the first nanowire heterojunction 12 between the first source section 12b and the first drain section 12c on the first sacrificial layer 17 .
  • the first nanowire heterojunction 12 may include a first channel layer 121 and a first barrier layer 122 from bottom to top. Two-dimensional electron gas or two-dimensional hole gas may be formed at the interface between the first channel layer 121 and the first barrier layer 122 .
  • the first channel layer 121 is an intrinsic GaN layer
  • the first barrier layer 122 is an N-type AlGaN layer.
  • the materials of the first channel layer 121 and the first barrier layer 122 may also be at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.
  • first channel layer 121 and the first barrier layer 122 shown in FIG. 7(a) having one layer respectively; the first channel layer 121 and the first barrier layer 122 may also have multiple layers respectively, and alternately distributed; or a first channel layer 121 and two or more first barrier layers 122 to form a multi-barrier structure.
  • the first nanowire heterojunction 12 may also include a first back barrier layer 123 , a first channel layer 121 and a first barrier layer 122 from bottom to top .
  • the first back barrier layer 123 , the first channel layer 121 and the first barrier layer 122 may each have one layer; the first back barrier layer 123 , the first channel layer 121 and the first barrier layer 122 may also have one layer. They have multiple layers and are alternately distributed.
  • the advantage of this embodiment is that the first back barrier layer 123 and the first barrier layer 122 can confine the carriers in the first channel layer 121 to prevent carriers from being carried Fluid leaks.
  • the first nanowire heterojunction 12 may only include the first back barrier layer 123 and the first channel layer 121 from bottom to top.
  • the epitaxial growth process of the first nanowire heterojunction 12 may refer to the epitaxial growth process of the nucleation layer and/or the buffer layer.
  • first nanowire heterojunctions 12 there are three first nanowire heterojunctions 12 .
  • the number of the first nanowire heterojunctions 12 may be one or two.
  • step S3 in FIG. 4 FIG. 8( a ) and FIG. 3 , the first sacrificial layer 17 is removed, and the first nanowire heterojunction 12 is suspended.
  • the removal method is wet solution etching, such as boric acid.
  • the material of the first sacrificial layer 17 may be a GaN-based material, and the upper surface is an N-plane.
  • the material of the first nanowire heterojunction 12 can also be a GaN-based material, and the upper surface is a Ga surface.
  • the etching solution for wet etching can be H 3 PO 4 solution or KOH solution, which is corrosive on the N side and non-corrosive on the Ga side.
  • the GaN crystal has a brazinite structure, in which the Ga and N atomic layers are stacked in ABABAB hexagonal layers, and each Ga(N) atom forms bonds with the surrounding 4 N(Ga) atoms in a diamond-like tetrahedral structure.
  • the first sacrificial layer 17 can be removed by selective etching of the N-face with H 3 PO 4 solution or KOH solution.
  • the material of the first sacrificial layer 17 is silicon nitride, it is removed by hot phosphoric acid; when the material of the first sacrificial layer 17 is silicon dioxide, it is removed by hydrofluoric acid.
  • a first anti-scattering layer 141 may also be coated around the suspended first nanowire heterojunction 12 .
  • the first anti-scattering layer 141 can reduce the scattering of carriers on the outer surface of the first nanowire heterojunction 12 to prevent leakage of carriers.
  • the first anti-scattering layer 141 may sequentially include an AlN layer and an AlGaN layer from the inside out.
  • the formation method of the first anti-scattering layer 141 may refer to the epitaxial growth process of the nucleation layer and/or the buffer layer.
  • the source electrode 13 b is formed on the first source electrode section 12 b
  • the drain electrode 13 c is formed on the first drain section 12 c and the The ring gate 13a covering the first gate segment 12a.
  • the material of the source electrode 13b, the drain electrode 13c, and the ring-shaped gate 13a may be metal, such as existing conductive materials such as Ti/Al/Ni/Au, Ni/Au, and the like.
  • the entire surface can be formed by a deposition process first, and then patterned by an etching process.
  • the annular gate 13 a wraps the first anti-scattering layer 141 of the first gate section 12 a.
  • the annular gates 13 a covering each of the first nanowire heterojunctions 12 are connected together and contact the substrate 10 .
  • N-type ions are formed on the first source section 12b, the first drain section 12c and the first gate section 12a before forming the source 13b, the drain 13c and the ring gate 13a heavily doped layer.
  • the N-type ion heavily doped layer may be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.
  • the N-type ions may be at least one of Si ions, Ge ions, Sn ions, Se ions and Te ions.
  • the doping concentration can be greater than 1E18/cm 3 .
  • the N-type ion heavily doped layer can make the gap between the source electrode 13b and the first source region 12b, between the drain electrode 13c and the first drain region 12c, and between the ring gate 13a and the first gate region 12a.
  • the ohmic contact layer can be directly formed without high-temperature annealing, so that the performance of the first nanowire heterojunction 12 and the electron migration rate can be prevented from being degraded due to the high temperature in the annealing process.
  • FIG. 9 is a schematic three-dimensional structure diagram of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 10 is a schematic three-dimensional structure diagram of the semiconductor structure after removing the source electrode, the drain electrode and the ring gate in FIG. 9 .
  • the structure of the semiconductor device 2 of the second embodiment is substantially the same as that of the semiconductor device 1 of the first embodiment, the only difference being that there is a space between the first gate segment 12 a and the ring gate 13 a.
  • Gate insulating layer 14 the semiconductor device 2 has a MIS gate, and the MIS gate can reduce gate leakage current.
  • the fabrication method of the semiconductor device 2 of the second embodiment is substantially the same as the fabrication method of the semiconductor device 1 of the first embodiment, and the only difference is that in step S4 , the first gate section 12 a is covered with gate insulation first. layer 14 ; and then the ring gate 13 a is covered on the gate insulating layer 14 .
  • the insulating material layer and the metal layer may be formed on the entire surface in sequence by a deposition process, and then patterned in one process by an etching process.
  • FIG. 11 is a schematic three-dimensional structure diagram of a semiconductor device according to a third embodiment of the present invention.
  • the structure of the semiconductor device 3 of the third embodiment is substantially the same as the structure of the semiconductor devices 1 and 2 of the first and second embodiments, and the difference is only that:
  • the ring gates 13a are separated from each other.
  • the fabrication method of the semiconductor device 3 of the third embodiment is substantially the same as the fabrication method of the semiconductor devices 1 and 2 of the first and second embodiments, and the only difference is that in step S4, when the etching process patterned the metal layer, not only the removal of The metal layers between the first source section 12b and the first gate section 12a and between the first drain section 12c and the first gate section 12a also disconnect each of the first nanowire heterogeneities metal layer between junctions 12.
  • FIG. 12 is a schematic three-dimensional structure diagram of a semiconductor device according to a fourth embodiment of the present invention.
  • the structure of the semiconductor device 4 of the fourth embodiment is substantially the same as that of the semiconductor devices 1 , 2 , and 3 of the first, second, and third embodiments, and the only difference is that the gap between the ring gate 13 a and the substrate 10 is with interval.
  • the fabrication method of the semiconductor device 4 of the fourth embodiment is substantially the same as the fabrication method of the semiconductor devices 1, 2, and 3 of the first, second, and third embodiments, and the only difference is that: in step S4, the first gate region is reduced Thickness of the metal layer deposited by segment 12a.
  • FIG. 13 is a schematic three-dimensional structure diagram of a semiconductor device according to a fifth embodiment of the present invention.
  • 14( a ) and FIG. 14( b ) are cross-sectional views along line BB in FIG. 13 , wherein the structures of the second nanowire heterojunction are different.
  • FIG. 14( c ) is a schematic diagram of a second anti-scattering layer clad around the second nanowire heterojunction of FIG. 14( a ).
  • FIG. 15 is a schematic three-dimensional structural diagram of the semiconductor structure after removing the source electrode, the drain electrode and the ring gate in FIG. 13 .
  • FIG. 16 is a schematic three-dimensional structure diagram of the semiconductor structure after the gate insulating layer in FIG. 15 is removed.
  • the structure of the semiconductor device 5 of the fifth embodiment is substantially the same as the structure of the semiconductor device 4 of the fourth embodiment, the only difference being that the semiconductor device 5 further includes:
  • the second nanowire heterojunction 16 includes a second gate segment 16a corresponding to the first region 10a, a second source segment 16b corresponding to the second region 10b, and a second source segment 16b corresponding to the first region 10a.
  • the second drain section 16c of the third region 10c ; the second source section 16b and the second drain section 16c are located on the second support structure 15 .
  • the shape and size of the second nanowire heterojunction 16 may be the same as the shape and size of the first nanowire heterojunction 12 .
  • the material of the second support structure 15 may refer to the material of the first support structure 11 .
  • the second nanowire heterojunction 16 may include a second channel layer 161 and a second barrier layer 162 from bottom to top. Two-dimensional electron gas or two-dimensional hole gas may be formed at the interface between the second channel layer 161 and the second barrier layer 162 .
  • the second channel layer 161 is an intrinsic GaN layer
  • the second barrier layer 162 is an N-type AlGaN layer.
  • the materials of the second channel layer 161 and the second barrier layer 162 may also be at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.
  • the second channel layer 161 and the second barrier layer 162 shown in FIG. 14(a) may also have multiple layers respectively, and alternately distributed; or a second channel layer 161 and two or more second barrier layers 162 to form a multi-barrier structure.
  • the second nanowire heterojunction 16 may also include a second back barrier layer 163 , a second channel layer 161 and a second barrier layer 162 from bottom to top .
  • the second back barrier layer 163 , the second channel layer 161 and the second barrier layer 162 may each have one layer; the second back barrier layer 163 , the second channel layer 161 and the second barrier layer 162 may also have one layer. They have multiple layers and are alternately distributed.
  • the advantage of this embodiment is that the second back barrier layer 163 and the second barrier layer 162 can confine the carriers in the second channel layer 161 to prevent carriers from being carried Fluid leaks.
  • the second nanowire heterojunction 16 may only include the second back barrier layer 163 and the second channel layer 161 from bottom to top.
  • the second anti-scattering layer 142 is coated around the second nanowire heterojunction 16 shown in FIG. 14( a ). In other embodiments, the second anti-scattering layer 142 can also be wrapped around the second nanowire heterojunction 16 shown in FIG. 14( b ). The second anti-scattering layer 142 can reduce the scattering of carriers on the outer surface of the second nanowire heterojunction 16 to prevent leakage of carriers.
  • the second anti-scattering layer 142 may sequentially include an AlN layer and an AlGaN layer from the inside to the outside.
  • the annular gates 13a covering each of the first nanowire heterojunctions 12 and the annular gates 13a covering each of the second nanowire heterojunctions 16 are separated from each other. In addition, there is a gap between the annular gate 13 a covering each of the first nanowire heterojunctions 12 and the substrate 10 .
  • FIG. 17 is a flowchart of a production method.
  • 18 to 20 are schematic diagrams of intermediate structures corresponding to the flow in FIG. 17 .
  • the fabrication method of the semiconductor device 5 of the fifth embodiment is substantially the same as the fabrication method of the semiconductor devices 1 and 2 of the first and second embodiments, the only difference being that after step S3, the following steps S31 to S33 are also performed .
  • Step S31 as shown in FIG. 18 , a second support structure 15 is formed on the first source section 12 b and the first drain section 12 c ; the first nanowire heterojunction 12 exposed on the second support structure 15 A second sacrificial layer 18 is formed thereon.
  • forming the second support structure 15 specifically includes: referring to FIG. 19 , growing a second epitaxial layer 15 ′ on the first nanowire heterojunction 12 ; referring to FIG. 18 , patterning the second epitaxial layer 15 ′, the second epitaxial layer 15 ′ on the first source region 12 b and the first drain region 12 c is reserved to form the second support structure 15 .
  • the material of the second epitaxial layer 15' may be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.
  • the patterning of the second epitaxial layer 15' may be implemented by dry etching or wet etching.
  • the second epitaxial layer 15' can also be replaced with a second material layer, and the material of the second material layer is, for example, silicon nitride, silicon dioxide, silicon oxynitride, etc., corresponding to physical vapor deposition or chemical vapor deposition. formed by deposition.
  • forming the second support structure 15 may further include: forming a second patterned mask layer on the first nanowire heterojunction 12, the second patterned mask layer having a second opening, the second opening The first source region 12b and the first drain region 12c are exposed; the second support structure 15 is epitaxially grown on the first nanowire heterojunction 12 by using the second patterned mask layer as a mask. After that, the first patterned mask layer is removed.
  • the material of the second patterned mask layer is, for example, silicon nitride, silicon dioxide, silicon oxynitride, etc., and is formed by a physical vapor deposition method or a chemical vapor deposition method.
  • the material of the second support structure 15 may be a group III nitride based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.
  • forming the second sacrificial layer 18 specifically includes: growing the second sacrificial layer 18 on the second support structure 15 and the first nanowire heterojunction 12 exposed by the second support structure 15 , and removing the second support structure The second sacrificial layer 18 on 15 .
  • the material of the second sacrificial layer 18 may be N-type GaN.
  • the epitaxial growth process of the second sacrificial layer 18 may refer to the epitaxial growth process of the nucleation layer and/or the buffer layer.
  • the second sacrificial layer 18 on the second support structure 15 can be removed by dry etching or wet etching.
  • the material of the second sacrificial layer 18 can also be, for example, silicon nitride, silicon dioxide, etc., and is formed by physical vapor deposition or chemical vapor deposition.
  • forming the second sacrificial layer 18 may specifically include: using the second support structure 15 as a mask, growing the second sacrificial layer 18 on the first nanowire heterojunction 12 .
  • This embodiment is applicable to the case where the material of the second support structure 15 is silicon nitride, silicon dioxide, etc., and the second sacrificial layer 18 cannot be grown thereon.
  • the second sacrificial layer 18 on the first nanowire heterojunction 12 is flush with the upper surface of the second support structure 15 .
  • the upper surface of the second sacrificial layer 18 on the first nanowire heterojunction 12 may be higher than or lower than the upper surface of the second supporting structure 15 .
  • Step S32 as shown in FIG. 20 , a second nanowire heterojunction 16 is grown on the second support structure 15 and the second sacrificial layer 18 , and the second nanowire heterojunction 16 includes a second nanowire heterojunction 16 corresponding to the first region 10 a .
  • the epitaxial growth process of the second nanowire heterojunction 16 may refer to the epitaxial growth process of the nucleation layer and/or the buffer layer.
  • each of the second nanowire heterojunctions 16 may have a common second source region 16b, and/or a common second drain region 16c. That is, the second source segments 16b of the second nanowire heterojunctions 16 are connected together, and/or the second drain segments 16c of the second nanowire heterojunctions 16 are connected together.
  • Step S33 referring to FIG. 16 , the second sacrificial layer 18 is removed, and the second nanowire heterojunction 16 is suspended.
  • the removal method is wet solution etching, such as boric acid.
  • the material of the second sacrificial layer 18 may be a GaN-based material, and the upper surface is an N-plane.
  • the material of the second nanowire heterojunction 16 can also be a GaN-based material, and the upper surface is a Ga surface.
  • the etching solution for wet etching can be H 3 PO 4 solution or KOH solution, which is corrosive on the N side and non-corrosive on the Ga side.
  • the GaN crystal has a brazinite structure, in which the Ga and N atomic layers are stacked in ABABAB hexagonal layers, and each Ga(N) atom forms bonds with the surrounding 4 N(Ga) atoms in a diamond-like tetrahedral structure.
  • the second sacrificial layer 18 can be removed by selective etching of the N-face with H 3 PO 4 solution or KOH solution.
  • the material of the second sacrificial layer 18 is silicon nitride, it is removed by hot phosphoric acid; when the material of the second sacrificial layer 18 is silicon dioxide, it is removed by hydrofluoric acid.
  • Step S4 ′ forming a source electrode 13b on the first source segment 12b and the second source segment 16b , forming a drain electrode 13c on the first drain segment 12c and the second drain segment 16c and forming a cladding
  • the ring gate 13a of the first gate segment 12a and the second gate segment 16a The annular gates 13a covering each of the first nanowire heterojunctions 12 and the annular gates 13a covering each of the second nanowire heterojunctions 16 are separated from each other.
  • FIG. 21 is a schematic three-dimensional structure diagram of a semiconductor device according to a sixth embodiment of the present invention.
  • the semiconductor device 6 of the sixth embodiment and the fabrication method thereof are substantially the same as the semiconductor device 5 of the fifth embodiment and the fabrication method thereof.
  • the mass junction 12 and each second nanowire heterojunction 16 are substantially the same as the semiconductor device 5 of the fifth embodiment and the fabrication method thereof.
  • the ring-shaped gate 13 a may cover a second nanowire heterojunction 16 and the first nanowire heterojunction 12 directly below the second nanowire heterojunction 16 .
  • the vertical section of the annular gate 13a is in the shape of an "8".
  • FIG. 22 is a schematic three-dimensional structure diagram of a semiconductor device according to a seventh embodiment of the present invention.
  • the semiconductor device 7 of the seventh embodiment and the fabrication method thereof are substantially the same as the semiconductor device 6 of the sixth embodiment and the fabrication method thereof, except that the ring gate 13 a contacts the substrate 10 .
  • FIG. 23 is a schematic three-dimensional structure diagram of a semiconductor device according to an eighth embodiment of the present invention.
  • FIG. 24 is a schematic three-dimensional structural diagram of the semiconductor structure after removing the source electrode, the drain electrode and the ring gate in FIG. 23 .
  • FIG. 25 is a schematic perspective view of the semiconductor structure after the gate insulating layer in FIG. 24 is removed.
  • the semiconductor device 8 of the eighth embodiment and the manufacturing method thereof are substantially the same as the semiconductor devices 1 and 2 of the first and second embodiments and the manufacturing method thereof, except that the substrate 10 further comprises a A fourth area 10d between the first area 10a and the second area 10b, and a fifth area 10e between the first area 10a and the third area 10c; the first support structure 11 is located between the second area 10b and the fourth area 10d on the third area 10c and the fifth area 10e.
  • the dangling sections of the first nanowire heterojunction 12 of the semiconductor device 8 are shorter than the dangling sections of the first nanowire heterojunctions 12 of the semiconductor devices 1 , 2 .
  • the semiconductor device 8 of the eighth embodiment may be combined with the semiconductor devices 5, 6, and 7 of the fifth, sixth, and seventh embodiments, and the second support structure 15 may be located on the second region 10b and the fourth region 10d, and located on the third area 10c and the fifth area 10e, and may also be located on the second area 10b and the third area 10c.
  • FIG. 26 is a schematic three-dimensional structure diagram of a semiconductor device according to a ninth embodiment of the present invention.
  • the semiconductor device 9 of the ninth embodiment and the fabrication method thereof are substantially the same as the semiconductor device 8 of the eighth embodiment and the fabrication method thereof, the only difference being:
  • the ring gates 13a are separated from each other, and/or the gate insulating layer 14 is omitted.

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Abstract

一种半导体器件及其制作方法，半导体器件包括：衬底（10）、第一支撑结构（11）、第一纳米线异质结（12）、源极（13b）、漏极（13c）以及环形栅极（13a）；其中，衬底（10）包括第一区域（10a），以及分别位于第一区域（10a）两侧的第二区域（10b）与第三区域（10c）；第一支撑结构（11）至少位于第二区域（10b）与第三区域（10c）上；第一纳米线异质结（12）包括对应于第一区域（10a）的第一栅极区段（12a）、对应于第二区域（10b）的第一源极区段（12b）以及对应于第三区域（10c）的第一漏极区段（12c）；第一源极区段（12b）与第一漏极区段（12c）位于第一支撑结构（11）上；源极（13b）位于第一源极区段（12b），漏极（13c）位于第一漏极区段（12c），环形栅极（13a）包覆于第一栅极区段（12a）。由于第一纳米线异质结（12）被限域，异质结内的二维电子气或二维空穴气载流子在迁移过程中呈现近似一维的输运方式，可提高载流子迁移率、击穿电压以及降低漏电。

Description

半导体器件及其制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件及其制作方法。
背景技术
宽禁带半导体材料III族氮化物作为第三代半导体材料的典型代表，具有禁带宽度大、耐高压、耐高温、电子饱和速度和漂移速度高、容易形成高质量异质结构的优异特性，非常适合制造高温、高频、大功率电子器件。
例如AlGaN/GaN异质结由于较强的自发极化和压电极化，在AlGaN/GaN界面处存在高浓度的二维电子气(2DEG)，广泛应用于诸如高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)等半导体结构中。
平面型器件中，电流是在异质结结构形成的量子阱内沿平面流动的。器件在反向偏置条件下，电场的分布通常是不均匀的，一般而言会在栅极边缘或漏极边缘处产生严重的电场集中，且该处的电场会随着反向电压的增加快速增加，当达到临界击穿场强时，器件被击穿。
高的击穿电压意味着器件工作的电压范围更大，能够获得更高的功率密度，并且器件的可靠性更高。因此如何提高器件的击穿电压是电子器件研究人员重点关注的问题。
发明内容
本发明的发明目的是提供一种半导体器件及其制作方法，提高击穿电 压。
为实现上述目的，本发明的第一方面提供一种半导体器件，包括：
衬底，所述衬底包括第一区域，以及分别位于所述第一区域两侧的第二区域与第三区域；
至少位于所述第二区域与所述第三区域上的第一支撑结构；
第一纳米线异质结，所述第一纳米线异质结包括对应于所述第一区域的第一栅极区段、对应于所述第二区域的第一源极区段以及对应于所述第三区域的第一漏极区段；所述第一源极区段与所述第一漏极区段位于所述第一支撑结构上；
位于所述第一源极区段上的源极，位于所述第一漏极区段上的漏极以及包覆于所述第一栅极区段的环形栅极。
可选地，所述第一支撑结构仅位于所述第二区域与所述第三区域上。
可选地，所述衬底还包括位于所述第一区域与所述第二区域之间的第四区域，以及位于所述第一区域与第三区域之间的第五区域；所述第一支撑结构位于所述第二区域与所述第四区域上。
可选地，所述第一栅极区段与所述环形栅极之间具有栅极绝缘层。
可选地，所述第一纳米线异质结自下而上包括：第一沟道层与第一势垒层，或包括：第一背势垒层、第一沟道层与第一势垒层；和/或所述第一纳米线异质结周围包覆有第一抗散射层。
可选地，所述第一纳米线异质结具有多条。
可选地，各条所述第一纳米线异质结共所述第一源极区段，和/或共所述第一漏极区段。
可选地，包覆于各条所述第一纳米线异质结的所述环形栅极相互分离，或包覆于各条所述第一纳米线异质结的所述环形栅极连接在一起。
可选地，所述半导体器件还包括：
至少位于所述第一源极区段与所述第一漏极区段上的第二支撑结构；
第二纳米线异质结，所述第二纳米线异质结包括对应于所述第一区域的第二栅极区段、对应于所述第二区域的第二源极区段以及对应于所述第三区域的第二漏极区段；所述第二源极区段与所述第二漏极区段位于所述第二支撑结构上。
可选地，所述第二纳米线异质结具有多条。
可选地，各条所述第二纳米线异质结共所述第二源极区段，和/或共所述第二漏极区段。
可选地，所述环形栅极包覆于一条所述第二纳米线异质结与所述一条第二纳米线异质结正下方的所述第一纳米线异质结。
本发明的另一方面提供一种半导体器件的制作方法，包括：
提供衬底，所述衬底包括第一区域，以及分别位于所述第一区域两侧的第二区域与第三区域；至少在所述第二区域与所述第三区域上形成第一支撑结构；在所述第一支撑结构暴露出的所述衬底上形成第一牺牲层；
在所述第一支撑结构与所述第一牺牲层上生长第一纳米线异质结，所述第一纳米线异质结包括对应于所述第一区域的第一栅极区段、对应于所述第二区域的第一源极区段以及对应于所述第三区域的第一漏极区段；所述第一源极区段与所述第一漏极区段位于所述第一支撑结构上，至少所述第一栅极区段位于所述第一牺牲层上；
去除所述第一牺牲层，悬空所述第一纳米线异质结；
在所述第一源极区段上形成源极，所述第一漏极区段上形成漏极以及形成包覆所述第一栅极区段的环形栅极。
可选地，所述第一支撑结构仅位于所述第二区域与所述第三区域上； 去除所述第一牺牲层后，悬空的所述第一纳米线异质结自所述第一源极区段延伸至所述第一漏极区段。
可选地，所述衬底还包括位于所述第一区域与所述第二区域之间的第四区域，以及位于所述第一区域与第三区域之间的第五区域；所述第一支撑结构位于所述第二区域与所述第四区域上，以及位于所述第三区域与所述第五区域上；去除所述第一牺牲层后，悬空的所述第一纳米线异质结仅为所述第一栅极区段。
可选地，形成所述环形栅极前，在所述第一栅极区段上包覆栅极绝缘层；所述环形栅极包覆所述栅极绝缘层。
可选地，所述生长的第一纳米线异质结为多条。
可选地，各条所述第一纳米线异质结共所述第一源极区段，和/或共所述第一漏极区段。
可选地，所述形成第一支撑结构包括：在所述衬底上生长第一外延层；图形化所述第一外延层，至少保留所述第二区域与所述第三区域上的所述第一外延层，以形成所述第一支撑结构；
或包括：在所述衬底上形成第一图形化掩膜层，所述第一图形化掩膜层具有第一开口，所述第一开口至少暴露所述第二区域与所述第三区域；以所述第一图形化掩膜层为掩膜，在所述衬底上外延生长所述第一支撑结构。
可选地，所述形成第一牺牲层包括：在所述第一支撑结构以及所述第一支撑结构暴露出的所述衬底上生长第一牺牲层，去除所述第一支撑结构上的所述第一牺牲层；
或包括：以所述第一支撑结构为掩膜，在所述衬底上生长所述第一牺牲层。
可选地，所述半导体器件的制作方法还包括：
至少在所述第一源极区段与第一漏极区段上形成第二支撑结构；在所述第二支撑结构暴露出的所述第一纳米线异质结上形成第二牺牲层；
在所述第二支撑结构与所述第二牺牲层上生长第二纳米线异质结，所述第二纳米线异质结包括对应于所述第一区域的第二栅极区段、对应于所述第二区域的第二源极区段以及对应于所述第三区域的第二漏极区段；所述第二源极区段与所述第二漏极区段位于所述第二支撑结构上，至少所述第二栅极区段位于所述第二牺牲层上；
去除所述第二牺牲层，悬空所述第二纳米线异质结。
可选地，所述形成第二支撑结构包括：在所述第一纳米线异质结上生长第二外延层；图形化所述第二外延层，至少保留所述第一源极区段与所述第一漏极区段上的所述第二外延层，以形成所述第二支撑结构；
或包括：在所述第一纳米线异质结上形成第二图形化掩膜层，所述第二图形化掩膜层具有第二开口，所述第二开口至少暴露所述第一源极区段与所述第一漏极区段；以所述第二图形化掩膜层为掩膜，在所述第一纳米线异质结上外延生长所述第二支撑结构。
可选地，所述形成第二牺牲层包括：在所述第二支撑结构以及所述第二支撑结构暴露出的所述第一纳米线异质结上生长第二牺牲层，去除所述第二支撑结构上的所述第二牺牲层；
或包括：以所述第二支撑结构为掩膜，在所述第一纳米线异质结上生长所述第二牺牲层。
可选地，所述第一牺牲层和/或所述第二牺牲层材料为N型GaN。
可选地，去除所述第一牺牲层和/或去除所述第二牺牲层采用选择性刻蚀溶液实现。
与现有技术相比，本发明的有益效果在于：
1)半导体器件中，由于第一纳米线异质结被限域，异质结内的二维电子气载流子或二维空穴气载流子在迁移过程中呈现近似一维的输运方式，可提高载流子迁移率。此外，环形栅极对载流子的控制能力也得到极大提高，因而可以大幅提高器件的击穿电压以及降低漏电问题，并可提高射频器件的效率和线性度。
2)可选方案中，a)第一支撑结构仅位于第二区域与第三区域上；或b)衬底还包括位于第一区域与第二区域之间的第四区域，以及位于第一区域与第三区域之间的第五区域；第一支撑结构位于第二区域与第四区域上，以及位于第三区域与第五区域上。相对于b)方案，a)方案的好处在于：能增长第一纳米线异质结的悬空区段，因而能减少异质结内的载流子与接触层发生湮灭的几率。
3)可选方案中，a)环形栅极直接接触第一栅极区段；或b)环形栅极与第一栅极区段之间具有栅极绝缘层。相对于a)方案，b)方案的好处在于：MIS栅可降低栅极漏电流。
4)可选方案中，第一纳米线异质结具有多条，各条第一纳米线异质结共第一源极区段，和共第一漏极区段。好处在于：相对于一条第一纳米线异质结，多条纳米线异质结相当于提供了多个载流子迁移通道，可进一步提高载流子迁移率。
5)可选方案中，包覆于各条第一纳米线异质结的环形栅极相互分离，或包覆于各条第一纳米线异质结的环形栅极连接在一起。好处在于：可满足不同性能使用需求。
6)可选方案中，半导体器件还包括：层叠设置于第一纳米线异质结上的第二纳米线异质结。好处在于：第二纳米线异质结相当于提供了额外的载流子迁移通道，因而可进一步提高载流子迁移率。
附图说明
图1是本发明第一实施例的半导体器件的立体结构示意图；
图2(a)与图2(b)是沿着图1中的AA线的剖视图，其中，第一纳米线异质结的结构不相同；
图2(c)是在图2(a)的第一纳米线异质结周围包覆了第一抗散射层的示意图；
图3是去除图1中的源极、漏极以及环形栅极后的半导体结构的立体结构示意图；
图4是图1至图2(c)中的半导体器件的制作方法的流程图；
图5至图8(b)是图4中的流程对应的中间结构示意图；
图9是本发明第二实施例的半导体器件的立体结构示意图；
图10是去除图9中的源极、漏极以及环形栅极后的半导体结构的立体结构示意图；
图11是本发明第三实施例的半导体器件的立体结构示意图；
图12是本发明第四实施例的半导体器件的立体结构示意图；
图13是本发明第五实施例的半导体器件的立体结构示意图；
图14(a)与图14(b)是沿着图13中的BB线的剖视图，其中，第二纳米线异质结的结构不相同；
图14(c)是在图14(a)的第二纳米线异质结周围包覆了第二抗散射层的示意图；
图15是去除图13中的源极、漏极以及环形栅极后的半导体结构的立体结构示意图；
图16是去除图15中的栅极绝缘层后的半导体结构的立体结构示意图；
图17是图13至图14(c)中的半导体器件的制作方法的流程图；
图18至图20是图17中的流程对应的中间结构示意图；
图21是本发明第六实施例的半导体器件的立体结构示意图；
图22是本发明第七实施例的半导体器件的立体结构示意图；
图23是本发明第八实施例的半导体器件的立体结构示意图；
图24是去除图23中的源极、漏极以及环形栅极后的半导体结构的立体结构示意图；
图25是去除图24中的栅极绝缘层后的半导体结构的立体结构示意图；
图26是本发明第九实施例的半导体器件的立体结构示意图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
衬底10             第一区域10a
第二区域10b        第三区域10c
第四区域10d        第五区域10e
第一支撑结构11     第一纳米线异质结12
第一沟道层121      第一势垒层122
第一背势垒层123    第一栅极区段12a
第一源极区段12b    第一漏极区段12c
源极13b            漏极13c
环形栅极13a        栅极绝缘层14
第一抗散射层141    第二纳米线异质结16
第二沟道层161      第二势垒层162
第二背势垒层163    第二抗散射层142
第二栅极区段16a      第二源极区段16b
第二漏极区段16c      第二支撑结构15
第一牺牲层17         第一外延层11'
第二外延层15'        第二牺牲层18
半导体器件1、2、3、4、5、6、7、8、9
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的半导体器件的立体结构示意图。图2(a)与图2(b)是沿着图1中的AA线的剖视图，其中，第一纳米线异质结的结构不相同。图2(c)是在图2(a)的第一纳米线异质结周围包覆了第一抗散射层的示意图。图3是去除图1中的源极、漏极以及环形栅极后的半导体结构的立体结构示意图。
参照图1至图3所示，半导体器件1包括：
衬底10，衬底10包括第一区域10a，以及分别位于第一区域10a两侧的第二区域10b与第三区域10c；
位于第二区域10b与第三区域10c上的第一支撑结构11；
第一纳米线异质结12，第一纳米线异质结12包括对应于第一区域10a的第一栅极区段12a、对应于第二区域10b的第一源极区段12b以及对应于第三区域10c的第一漏极区段12c；第一源极区段12b与第一漏极区段12c位于第一支撑结构11上；
位于第一源极区段12b上的源极13b，位于第一漏极区段12c上的漏极 13c以及包覆于第一栅极区段12a的环形栅极13a。
本实施例中，衬底10的材料可以为蓝宝石、碳化硅、硅、绝缘体上硅(SOI)、金刚石或铌酸锂等材料。
衬底10上可以具有缓冲层。缓冲层与衬底10之间可以具有成核层。成核层的材料可以为Ⅲ族氮化物基材料，例如AlN、AlGaN等。缓冲层的材料也可以为Ⅲ族氮化物基材料，例如GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种。成核层可以缓解外延生长的半导体层与衬底10之间的晶格失配和热失配的问题。缓冲层可以降低外延生长的半导体层，例如第一支撑结构11的位错密度和缺陷密度，提升晶体质量。
第一支撑结构11的材料可以为Ⅲ族氮化物基材料，例如GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种，也可以为介电材料，例如二氧化硅。
参照图3所示，第一纳米线异质结12的长度尺寸远大于竖剖面上的二维尺寸。竖剖面为沿厚度方向的剖面。
参照图2(a)所示，一个实施例中，第一纳米线异质结12自下而上可以包括第一沟道层121与第一势垒层122。第一沟道层121与第一势垒层122的界面处可形成二维电子气或二维空穴气。一个可选方案中，第一沟道层121为本征GaN层，第一势垒层122为N型AlGaN层。其它可选方案中，第一沟道层121与第一势垒层122的材料还可以为GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种。此外，除了图2(a)所示的第一沟道层121与第一势垒层122分别具有一层外；第一沟道层121与第一势垒层122还可以分别具有多层，且交替分布；或一层第一沟道层121与两层或两层以上的第一势垒层122，以形成多势垒结构。
参照图2(b)所示，一个实施例中，第一纳米线异质结12自下而上也可以包括第一背势垒层123、第一沟道层121以及第一势垒层122。第一背势垒 层123、第一沟道层121以及第一势垒层122可以分别具有一层；第一背势垒层123、第一沟道层121以及第一势垒层122也可以分别具有多层，且交替分布。相对于图2(a)所示实施例，本实施例的好处在于：第一背势垒层123与第一势垒层122可将载流子限制在第一沟道层121中，防止载流子泄露。其它实施例中，第一纳米线异质结12自下而上也可以仅包括第一背势垒层123与第一沟道层121。
参照图2(c)所示，一个实施例中，图2(a)所示的第一纳米线异质结12周围包覆有第一抗散射层141。其它实施例中，第一抗散射层141也可以包覆在图2(b)所示的第一纳米线异质结12周围。第一抗散射层141可减少载流子在第一纳米线异质结12外表面的散射，防止载流子泄露。
第一抗散射层141由内而外可以依次包括：AlN层与AlGaN层。
本实施例中，第一纳米线异质结12为三条，其它实施例中，第一纳米线异质结12也为可以一条、两条等其它数目。
一些实施例中，各条第一纳米线异质结12可以共第一源极区段12b，和/或共第一漏极区段12c。即各条第一纳米线异质结12的第一源极区段12b连接在一起，和/或各条第一纳米线异质结12的第一漏极区段12c连接在一起。
源极13b与第一源极区段12b之间、漏极13c与第一漏极区段12c之间、环形栅极13a与第一栅极区段12a之间都形成欧姆接触。源极13b、漏极13c、环形栅极13a的材质可以为金属，例如Ti/Al/Ni/Au、Ni/Au等现有的导电材质。
一些实施例中，源极13b与第一源极区段12b之间、漏极13c与第一漏极区段12c之间、环形栅极13a与第一栅极区段12a之间都可以利用N型离子重掺杂层形成欧姆接触。N型离子重掺杂层能使源极13b与第一源极区段12b之间、漏极13c与第一漏极区段12c之间、环形栅极13a与第一栅极区段12a之间不通过高温退火即可直接形成欧姆接触层，以及避免退火过程中的高温造成第一纳米线异质结12的性能下降，电子迁移速率降低。
N型离子重掺杂层中，N型离子可以为Si离子、Ge离子、Sn离子、Se离子和Te离子中的至少一种。对于不同的N型离子，掺杂浓度可以大于1E18/cm 3。N型离子重掺杂层可以为Ⅲ族氮化物基材料，例如为GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种。
半导体器件1中，由于第一纳米线异质结12被限域，异质结12内的二维电子气载流子或二维空穴气载流子在迁移过程中呈现近似一维的输运方式，可提高载流子迁移率。此外，环形栅极13a对载流子的控制能力也得到极大提高，因而可以大幅提高器件的击穿电压以及降低漏电问题，并可提高射频器件的效率和线性度。
本发明第一实施例还提供了图1至图2(c)中的半导体器件的制作方法。图4是制作方法的流程图。图5至图8(b)是图4中的流程对应的中间结构示意图。
首先，参照图4中的步骤S1与图5所示，提供衬底10，衬底10包括第一区域10a，以及分别位于第一区域10a两侧的第二区域10b与第三区域10c；在第二区域10b与第三区域10c上形成第一支撑结构11；在第一支撑结构11暴露出的衬底10上形成第一牺牲层17。
本实施例中，衬底10的材料可以为蓝宝石、碳化硅、硅、绝缘体上硅(SOI)、金刚石或铌酸锂等材料。
形成第一支撑结构11前，可以先依次在衬底10上生长成核层与缓冲层。成核层的材料可以为Ⅲ族氮化物基材料，例如AlN、AlGaN等。缓冲层的材料也可以为Ⅲ族氮化物基材料，例如GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种。成核层可以缓解外延生长的半导体层与衬底10之间的晶格失配和热失配的问题，缓冲层可以降低外延生长的半导体层，例如第一支撑结构11的位错密度和缺陷密度，提升晶体质量。
成核层和/或缓冲层的外延生长工艺可以包括：原子层沉积法(ALD， Atomic layer deposition)、或化学气相沉积法(CVD，Chemical Vapor Deposition)、或分子束外延生长法(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积法(MOCVD，Metal-Organic Chemical Vapor Deposition)、或其组合方式。
本实施例中，形成第一支撑结构11具体包括：参照图6所示，在衬底10上生长第一外延层11'；参照图5所示，图形化第一外延层11'，保留第二区域10b与第三区域10c上的第一外延层11'，以形成第一支撑结构11。
第一外延层11'的材料可以为Ⅲ族氮化物基材料，例如GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种。图形化第一外延层11'可以采用干法刻蚀或湿法刻蚀实现。
其它实施例中，第一外延层11'也可以替换为第一材料层，第一材料层的材料例如为氮化硅、二氧化硅、氮氧化硅等，对应采用物理气相沉积法或化学气相沉积法形成。
其它实施例中，形成第一支撑结构11具体还可以包括：在衬底10上形成第一图形化掩膜层，第一图形化掩膜层具有第一开口，第一开口暴露第二区域10b与第三区域10c；以第一图形化掩膜层为掩膜，在衬底10上外延生长第一支撑结构11。之后，去除第一图形化掩膜层。
第一图形化掩膜层的材料例如为氮化硅、二氧化硅、氮氧化硅等，对应采用物理气相沉积法或化学气相沉积法形成。
第一支撑结构11的材料可以为Ⅲ族氮化物基材料，例如GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种。
本实施例中，形成第一牺牲层17具体包括：在第一支撑结构11以及第一支撑结构11暴露出的衬底10上生长第一牺牲层17，去除第一支撑结构 11上的第一牺牲层17。
第一牺牲层17的材料可以为GaN基材料，例如为N型GaN。第一牺牲层17的外延生长工艺可以参照成核层和/或缓冲层的外延生长工艺。去除第一支撑结构11上的第一牺牲层17可以采用干法刻蚀或湿法刻蚀去除。
其它实施例中，第一牺牲层17的材料也可以例如为氮化硅、二氧化硅等，对应采用物理气相沉积法或化学气相沉积法形成。
其它实施例中，形成第一牺牲层17可以具体包括：以第一支撑结构11为掩膜，在衬底10上生长第一牺牲层17。本实施例适用于第一支撑结构11的材料为氮化硅、二氧化硅等，第一牺牲层17无法在其上生长的情况。
参照图5所示，本实施例中，衬底10上的第一牺牲层17与第一支撑结构11的上表面齐平。其它实施例中，衬底10上的第一牺牲层17的上表面可以高于第一支撑结构11的上表面，也可以低于第一支撑结构11的上表面。
接着，参照图4中的步骤S2、图7(a)与图7(b)所示，在第一支撑结构11与第一牺牲层17上生长第一纳米线异质结12，第一纳米线异质结12包括对应于第一区域10a的第一栅极区段12a、对应于第二区域10b的第一源极区段12b以及对应于第三区域10c的第一漏极区段12c；第一源极区段12b与第一漏极区段12c位于第一支撑结构11上，第一源极区段12b与第一漏极区段12c之间的第一纳米线异质结12位于第一牺牲层17上。
参照图7(a)所示，一个实施例中，第一纳米线异质结12自下而上可以包括第一沟道层121与第一势垒层122。第一沟道层121与第一势垒层122的界面处可形成二维电子气或二维空穴气。一个可选方案中，第一沟道层121为本征GaN层，第一势垒层122为N型AlGaN层。其它可选方案中，第一沟道层121与第一势垒层122的材料还可以为GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种。此外，除了图7(a)所示的第一沟道层121与第一势垒层122分别具有一层外；第一沟道层121与第一势垒层122还可 以分别具有多层，且交替分布；或一层第一沟道层121与两层或两层以上的第一势垒层122，以形成多势垒结构。
参照图7(b)所示，一个实施例中，第一纳米线异质结12自下而上也可以包括第一背势垒层123、第一沟道层121以及第一势垒层122。第一背势垒层123、第一沟道层121以及第一势垒层122可以分别具有一层；第一背势垒层123、第一沟道层121以及第一势垒层122也可以分别具有多层，且交替分布。相对于图7(a)所示实施例，本实施例的好处在于：第一背势垒层123与第一势垒层122可将载流子限制在第一沟道层121中，防止载流子泄露。其它实施例中，第一纳米线异质结12自下而上也可以仅包括第一背势垒层123与第一沟道层121。
以下以图7(a)所示结构继续介绍后续步骤。
第一纳米线异质结12的外延生长工艺可以参照成核层和/或缓冲层的外延生长工艺。
本实施例中，参照图3所示，第一纳米线异质结12为三条，其它实施例中，第一纳米线异质结12也为可以一条、两条等其它数目。
之后，参照图4中的步骤S3、图8(a)与图3所示，去除第一牺牲层17，悬空第一纳米线异质结12。
第一牺牲层17的材料为N型GaN时，去除方法为采用湿法溶液刻蚀，例如为硼酸。
一些实施例中，第一牺牲层17的材料可以为GaN基材料，且上表面为N面。第一纳米线异质结12的材料也可以为GaN基材料，且上表面为Ga面。湿法刻蚀的刻蚀液可以为H 3PO 4溶液或KOH溶液，它在N面上是腐蚀性的，在Ga面上是非腐蚀性的。GaN晶体为钎锌矿结构，其中Ga、N原子层呈ABABAB六方层堆垛，每个Ga(N)原子都与周围的4个N(Ga)原子呈类金刚石四面体结构成键。以平行于C轴([0001]晶向)的Ga-N键作为参照，若每 一个Ga-N键中的Ga原子更远离下表面，则上表面为Ga面；若每一个Ga-N键中的N原子更远离下表面，则上表面为N面。本实施例中，可以通过H 3PO 4溶液或KOH溶液对N面的选择性腐蚀去除第一牺牲层17。
第一牺牲层17的材料为氮化硅时，采用热磷酸去除；第一牺牲层17的材料为二氧化硅时，采用氢氟酸去除。
之后，一些实施例中，参照图8(b)所示，还可以在悬空的第一纳米线异质结12周围包覆第一抗散射层141。第一抗散射层141可减少载流子在第一纳米线异质结12外表面的散射，防止载流子泄露。
第一抗散射层141由内而外可以依次包括：AlN层与AlGaN层。
第一抗散射层141的形成方法可以参照成核层和/或缓冲层的外延生长工艺。
再接着，参照图4中的步骤S4、图1至图2(c)所示，在第一源极区段12b上形成源极13b，第一漏极区段12c上形成漏极13c以及形成包覆第一栅极区段12a的环形栅极13a。
源极13b、漏极13c、环形栅极13a的材质可以为金属，例如Ti/Al/Ni/Au、Ni/Au等现有的导电材质。对应地，可以先采用沉积工艺整面形成，后通过刻蚀工艺图形化。
当悬空的第一纳米线异质结12周围包覆有第一抗散射层141时，环形栅极13a包覆第一栅极区段12a的第一抗散射层141。
本实施例中，参照图1所示，包覆于各条第一纳米线异质结12的环形栅极13a连接在一起，且接触衬底10。
一些实施例中，形成源极13b、漏极13c以及环形栅极13a之前，先在第一源极区段12b、第一漏极区段12c以及第一栅极区段12a上形成N型离子重掺杂层。N型离子重掺杂层可以为Ⅲ族氮化物基材料，例如为GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种。N型离子重掺杂层 中，N型离子可以为Si离子、Ge离子、Sn离子、Se离子和Te离子中的至少一种。对于不同的N型离子，掺杂浓度可以大于1E18/cm 3。
N型离子重掺杂层能使源极13b与第一源极区段12b之间、漏极13c与第一漏极区段12c之间、环形栅极13a与第一栅极区段12a之间不通过高温退火即可直接形成欧姆接触层，从而可以避免退火过程中的高温造成第一纳米线异质结12的性能下降，电子迁移速率降低。
图9是本发明第二实施例的半导体器件的立体结构示意图。图10是去除图9中的源极、漏极以及环形栅极后的半导体结构的立体结构示意图。
参照图9与图10所示，实施例二的半导体器件2的结构与实施例一的半导体器件1的结构大致相同，区别仅在于：第一栅极区段12a与环形栅极13a之间具有栅极绝缘层14。换言之，半导体器件2具有MIS栅，MIS栅可降低栅极漏电流。
相应地，实施例二的半导体器件2的制作方法与实施例一的半导体器件1的制作方法大致相同，区别仅在于：步骤S4中，先在第一栅极区段12a上包覆栅极绝缘层14；之后再在栅极绝缘层14上包覆环形栅极13a。
具体地，可以先采用沉积工艺依次整面形成绝缘材料层与金属层，后通过刻蚀工艺在一个工序中图形化。
图11是本发明第三实施例的半导体器件的立体结构示意图。
参照图11所示，实施例三的半导体器件3的结构与实施例一、二的半导体器件1、2的结构大致相同，区别仅在于：包覆于各条第一纳米线异质结12的环形栅极13a相互分离。
相应地，实施例三的半导体器件3的制作方法与实施例一、二的半导体器件1、2的制作方法大致相同，区别仅在于：步骤S4中，刻蚀工艺图形化金属层时，不但去除第一源极区段12b与第一栅极区段12a之间、第一漏极区段12c与第一栅极区段12a之间的金属层，还断开各条第一纳米线异质结 12之间的金属层。
图12是本发明第四实施例的半导体器件的立体结构示意图。
参照图12所示，实施例四的半导体器件4的结构与实施例一、二、三的半导体器件1、2、3的结构大致相同，区别仅在于：环形栅极13a与衬底10之间具有间隔。
相应地，实施例四的半导体器件4的制作方法与实施例一、二、三的半导体器件1、2、3的制作方法大致相同，区别仅在于：步骤S4中，减小第一栅极区段12a沉积的金属层的厚度。
图13是本发明第五实施例的半导体器件的立体结构示意图。图14(a)与图14(b)是沿着图13中的BB线的剖视图，其中，第二纳米线异质结的结构不相同。图14(c)是在图14(a)的第二纳米线异质结周围包覆了第二抗散射层的示意图。图15是去除图13中的源极、漏极以及环形栅极后的半导体结构的立体结构示意图。图16是去除图15中的栅极绝缘层后的半导体结构的立体结构示意图。
参照图13至图16所示，实施例五的半导体器件5的结构与实施例四的半导体器件4的结构大致相同，区别仅在于：半导体器件5还包括：
位于第一源极区段12b与第一漏极区段12c上的第二支撑结构15；
第二纳米线异质结16，第二纳米线异质结16包括对应于第一区域10a的第二栅极区段16a、对应于第二区域10b的第二源极区段16b以及对应于第三区域10c的第二漏极区段16c；第二源极区段16b与第二漏极区段16c位于第二支撑结构15上。
第二纳米线异质结16的形状及尺寸可以与第一纳米线异质结12的形状及尺寸相同。
第二支撑结构15的材料可以参照第一支撑结构11的材料。
参照图14(a)所示，一个本实施例中，第二纳米线异质结16自下而上可以包括第二沟道层161与第二势垒层162。第二沟道层161与第二势垒层162的界面处可形成二维电子气或二维空穴气。一个可选方案中，第二沟道层161为本征GaN层，第二势垒层162为N型AlGaN层。其它可选方案中，第二沟道层161与第二势垒层162的材料还可以为GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种。此外，除了图14(a)所示的第二沟道层161与第二势垒层162分别具有一层外；第二沟道层161与第二势垒层162还可以分别具有多层，且交替分布；或一层第二沟道层161与两层或两层以上的第二势垒层162，以形成多势垒结构。
参照图14(b)所示，一个实施例中，第二纳米线异质结16自下而上也可以包括第二背势垒层163、第二沟道层161以及第二势垒层162。第二背势垒层163、第二沟道层161以及第二势垒层162可以分别具有一层；第二背势垒层163、第二沟道层161以及第二势垒层162也可以分别具有多层，且交替分布。相对于图14(a)所示实施例，本实施例的好处在于：第二背势垒层163与第二势垒层162可将载流子限制在第二沟道层161中，防止载流子泄露。其它实施例中，第二纳米线异质结16自下而上也可以仅包括第二背势垒层163与第二沟道层161。
参照图14(c)所示，一个实施例中，图14(a)所示的第二纳米线异质结16周围包覆有第二抗散射层142。其它实施例中，第二抗散射层142也可以包覆在图14(b)所示的第二纳米线异质结16的周围。第二抗散射层142可减少载流子在第二纳米线异质结16外表面的散射，防止载流子泄露。
第二抗散射层142由内而外可以依次包括：AlN层与AlGaN层。
包覆于各条第一纳米线异质结12的环形栅极13a，以及包覆于各条第二纳米线异质结16的环形栅极13a与相互分离。此外，包覆于各条第一纳米线异质结12的环形栅极13a与衬底10之间具有间隔。
本发明第五实施例还提供了图13至图14(c)中的半导体器件的制作方法。图17是制作方法的流程图。图18至图20是图17中的流程对应的中间结构示意图。
参照图17所示，实施例五的半导体器件5的制作方法与实施例一、二的半导体器件1、2的制作方法大致相同，区别仅在于：步骤S3后，还进行如下步骤S31～步骤S33。
步骤S31，参照图18所示，在第一源极区段12b与第一漏极区段12c上形成第二支撑结构15；在第二支撑结构15暴露出的第一纳米线异质结12上形成第二牺牲层18。
本实施例中，形成第二支撑结构15具体包括：参照图19所示，在第一纳米线异质结12上生长第二外延层15'；参照图18所示，图形化第二外延层15'，保留第一源极区段12b与第一漏极区段12c上的第二外延层15'，以形成第二支撑结构15。
第二外延层15'的材料可以为Ⅲ族氮化物基材料，例如GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种。图形化第二外延层15'可以采用干法刻蚀或湿法刻蚀实现。
其它实施例中，第二外延层15'也可以替换为第二材料层，第二材料层的材料例如为氮化硅、二氧化硅、氮氧化硅等，对应采用物理气相沉积法或化学气相沉积法形成。
其它实施例中，形成第二支撑结构15具体还可以包括：在第一纳米线异质结12上形成第二图形化掩膜层，第二图形化掩膜层具有第二开口，第二开口暴露第一源极区段12b与第一漏极区段12c；以第二图形化掩膜层为掩膜，在第一纳米线异质结12上外延生长第二支撑结构15。之后，去除第一图形化掩膜层。
第二图形化掩膜层的材料例如为氮化硅、二氧化硅、氮氧化硅等，对 应采用物理气相沉积法或化学气相沉积法形成。
第二支撑结构15的材料可以为Ⅲ族氮化物基材料，例如GaN，AlN，InN，AlGaN，InGaN，AlInN与AlInGaN中的至少一种。
本实施例中，形成第二牺牲层18具体包括：在第二支撑结构15以及第二支撑结构15暴露出的第一纳米线异质结12上生长第二牺牲层18，去除第二支撑结构15上的第二牺牲层18。
第二牺牲层18的材料可以为N型GaN。第二牺牲层18的外延生长工艺可以参照成核层和/或缓冲层的外延生长工艺。去除第二支撑结构15上的第二牺牲层18可以采用干法刻蚀或湿法刻蚀去除。
其它实施例中，第二牺牲层18的材料也可以例如为氮化硅、二氧化硅等，对应采用物理气相沉积法或化学气相沉积法形成。
其它实施例中，形成第二牺牲层18可以具体包括：以第二支撑结构15为掩膜，在第一纳米线异质结12上生长第二牺牲层18。本实施例适用于第二支撑结构15的材料为氮化硅、二氧化硅等，第二牺牲层18无法在其上生长的情况。
参照图18所示，本实施例中，第一纳米线异质结12上的第二牺牲层18与第二支撑结构15的上表面齐平。其它实施例中，第一纳米线异质结12上的第二牺牲层18的上表面可以高于第二支撑结构15的上表面，也可以低于第二支撑结构15的上表面。
步骤S32，参照图20所示，在第二支撑结构15与第二牺牲层18上生长第二纳米线异质结16，第二纳米线异质结16包括对应于第一区域10a的第二栅极区段16a、对应于第二区域10b的第二源极区段16b以及对应于第三区域10c的第二漏极区段16c；第二源极区段16b与第二漏极区段16c位于第二支撑结构15上，第二源极区段16b与第二漏极区段16c之间的第二纳米线异质结16位于第二牺牲层18上。
第二纳米线异质结16的外延生长工艺可以参照成核层和/或缓冲层的外延生长工艺。
一些实施例中，各条第二纳米线异质结16可以共第二源极区段16b，和/或共第二漏极区段16c。即各条第二纳米线异质结16的第二源极区段16b连接在一起，和/或各条第二纳米线异质结16的第二漏极区段16c连接在一起。
步骤S33，参照图16所示，去除第二牺牲层18，悬空第二纳米线异质结16。
第二牺牲层18的材料为N型GaN时，去除方法为采用湿法溶液刻蚀，例如为硼酸。
一些实施例中，第二牺牲层18的材料可以为GaN基材料，且上表面为N面。第二纳米线异质结16的材料也可以为GaN基材料，且上表面为Ga面。湿法刻蚀的刻蚀液可以为H 3PO 4溶液或KOH溶液，它在N面上是腐蚀性的，在Ga面上是非腐蚀性的。GaN晶体为钎锌矿结构，其中Ga、N原子层呈ABABAB六方层堆垛，每个Ga(N)原子都与周围的4个N(Ga)原子呈类金刚石四面体结构成键。以平行于C轴([0001]晶向)的Ga-N键作为参照，若每一个Ga-N键中的Ga原子更远离下表面，则上表面为Ga面；若每一个Ga-N键中的N原子更远离下表面，则上表面为N面。本实施例中，可以通过H 3PO 4溶液或KOH溶液对N面的选择性腐蚀去除第二牺牲层18。
第二牺牲层18的材料为氮化硅时，采用热磷酸去除；第二牺牲层18的材料为二氧化硅时，采用氢氟酸去除。
步骤S4'，在第一源极区段12b与第二源极区段16b上形成源极13b，第一漏极区段12c与第二漏极区段16c上形成漏极13c以及形成包覆第一栅极区段12a与第二栅极区段16a的环形栅极13a。其中，包覆于各条第一纳米线异质结12的环形栅极13a，以及包覆于各条第二纳米线异质结16的环形栅极13a与相互分离。
图21是本发明第六实施例的半导体器件的立体结构示意图。
参照图21所示，实施例六的半导体器件6及其制作方法与实施例五的半导体器件5及其制作方法大致相同，区别仅在于：环形栅极13a包覆于各条第一纳米线异质结12与各条第二纳米线异质结16。
其它实施例中，环形栅极13a可以包覆于一条第二纳米线异质结16与该条第二纳米线异质结16正下方的第一纳米线异质结12。换言之，环形栅极13a的竖剖面呈“8”字形。
图22是本发明第七实施例的半导体器件的立体结构示意图。
参照图22所示，实施例七的半导体器件7及其制作方法与实施例六的半导体器件6及其制作方法大致相同，区别仅在于：环形栅极13a接触衬底10。
图23是本发明第八实施例的半导体器件的立体结构示意图。图24是去除图23中的源极、漏极以及环形栅极后的半导体结构的立体结构示意图。图25是去除图24中的栅极绝缘层后的半导体结构的立体结构示意图。
参照图23至图25所示，实施例八的半导体器件8及其制作方法与实施例一、二的半导体器件1、2及其制作方法大致相同，区别仅在于：衬底10还包括位于第一区域10a与第二区域10b之间的第四区域10d，以及位于第一区域10a与第三区域10c之间的第五区域10e；第一支撑结构11位于第二区域10b与第四区域10d上，以及位于第三区域10c与第五区域10e上。
可以看出，半导体器件8的第一纳米线异质结12的悬空区段短于半导体器件1、2的第一纳米线异质结12的悬空区段。
一些实施例中，实施例八的半导体器件8可以与实施例五、六、七的半导体器件5、6、7相结合，第二支撑结构15可以位于第二区域10b与第四区域10d上，以及位于第三区域10c与第五区域10e上，也可以位于第二区域10b与第三区域10c上。
图26是本发明第九实施例的半导体器件的立体结构示意图。参照图26所示，实施例九的半导体器件9及其制作方法与实施例八的半导体器件8及其制作方法大致相同，区别仅在于：包覆于各条第一纳米线异质结12的环形栅极13a相互分离，和/或省略栅极绝缘层14。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

  1. 一种半导体器件，其特征在于，包括：
    衬底(10)，所述衬底(10)包括第一区域(10a)，以及分别位于所述第一区域(10a)两侧的第二区域(10b)与第三区域(10c)；
    至少位于所述第二区域(10b)与所述第三区域(10c)上的第一支撑结构(11)；
    第一纳米线异质结(12)，所述第一纳米线异质结(12)包括对应于所述第一区域(10a)的第一栅极区段(12a)、对应于所述第二区域(10b)的第一源极区段(12b)以及对应于所述第三区域(10c)的第一漏极区段(12c)；所述第一源极区段(12b)与所述第一漏极区段(12c)位于所述第一支撑结构(11)上；
    位于所述第一源极区段(12b)上的源极(13b)，位于所述第一漏极区段(12c)上的漏极(13c)以及包覆于所述第一栅极区段(12a)的环形栅极(13a)。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述第一支撑结构(11)仅位于所述第二区域(10b)与所述第三区域(10c)上；
    或所述衬底(10)还包括位于所述第一区域(10a)与所述第二区域(10b)之间的第四区域(10d)，以及位于所述第一区域(10a)与第三区域(10c)之间的第五区域(10e)；所述第一支撑结构(11)位于所述第二区域(10b)与所述第四区域(10d)上，以及位于所述第三区域(10c)与所述第五区域(10e)上。
  3. 根据权利要求1所述的半导体器件，其特征在于，所述第一栅极区段(12a)与所述环形栅极(13a)之间具有栅极绝缘层(14)。
  4. 根据权利要求1所述的半导体器件，其特征在于，所述第一纳米线异质结(12)自下而上包括：第一沟道层(121)与第一势垒层(122)，或包括：第一背势垒层(123)、第一沟道层(121)与第一势垒层(122)；和/或所述第一纳米线异质结(12)周围包覆有第一抗散射层(141)。
  5. 根据权利要求1所述的半导体器件，其特征在于，所述第一纳米线异质结(12)具有多条。
  6. 根据权利要求5所述的半导体器件，其特征在于，各条所述第一纳米线异质结(12)共所述第一源极区段(12b)，和/或共所述第一漏极区段(12c)。
  7. 根据权利要求5或6所述的半导体器件，其特征在于，包覆于各条所述第一纳米线异质结(12)的所述环形栅极(13a)相互分离，或包覆于各条所述第一纳米线异质结(12)的所述环形栅极(13a)连接在一起。
  8. 根据权利要求1所述的半导体器件，其特征在于，所述半导体器件还包括：
    至少位于所述第一源极区段(12b)与所述第一漏极区段(12c)上的第二支撑结构(15)；
    第二纳米线异质结(16)，所述第二纳米线异质结(16)包括对应于所述第一区域(10a)的第二栅极区段(16a)、对应于所述第二区域(10b)的第二源极区段(16b)以及对应于所述第三区域(10c)的第二漏极区段(16c)；所述第二源极区段(16b)与所述第二漏极区段(16c)位于所述第二支撑结构(15)上。
  9. 根据权利要求8所述的半导体器件，其特征在于，所述第二纳米线异质结(16)具有多条。
  10. 根据权利要求9所述的半导体器件，其特征在于，各条所述第二纳米线异质结(16)共所述第二源极区段(16b)，和/或共所述第二漏极区段(16c)。
  11. 根据权利要求10所述的半导体器件，其特征在于，所述环形栅极(13a)包覆于一条所述第二纳米线异质结(16)与所述一条第二纳米线异质结(16)正下方的所述第一纳米线异质结(12)。
  12. 一种半导体器件的制作方法，其特征在于，包括：
    提供衬底(10)，所述衬底(10)包括第一区域(10a)，以及分别位于所述第一区域(10a)两侧的第二区域(10b)与第三区域(10c)；至少在所述第二区域(10b)与所述第三区域(10c)上形成第一支撑结构(11)；在所述第 一支撑结构(11)暴露出的所述衬底(10)上形成第一牺牲层(17)；
    在所述第一支撑结构(11)与所述第一牺牲层(17)上生长第一纳米线异质结(12)，所述第一纳米线异质结(12)包括对应于所述第一区域(10a)的第一栅极区段(12a)、对应于所述第二区域(10b)的第一源极区段(12b)以及对应于所述第三区域(10c)的第一漏极区段(12c)；所述第一源极区段(12b)与所述第一漏极区段(12c)位于所述第一支撑结构(11)上，至少所述第一栅极区段(12a)位于所述第一牺牲层(17)上；
    去除所述第一牺牲层(17)，以悬空所述第一纳米线异质结(12)；
    在所述第一源极区段(12b)上形成源极(13b)，所述第一漏极区段(12c)上形成漏极(13c)以及形成包覆所述第一栅极区段(12a)的环形栅极(13a)。
  13. 根据权利要求12所述的半导体器件的制作方法，其特征在于，所述第一支撑结构(11)仅位于所述第二区域(10b)与所述第三区域(10c)上；去除所述第一牺牲层(17)后，悬空的所述第一纳米线异质结(12)自所述第一源极区段(12b)延伸至所述第一漏极区段(12c)；
    或所述衬底(10)还包括位于所述第一区域(10a)与所述第二区域(10b)之间的第四区域(10d)，以及位于所述第一区域(10a)与第三区域(10c)之间的第五区域(10e)；所述第一支撑结构(11)位于所述第二区域(10b)与所述第四区域(10d)上，以及位于所述第三区域(10c)与所述第五区域(10e)上；去除所述第一牺牲层(17)后，悬空的所述第一纳米线异质结(12)仅为所述第一栅极区段(12a)。
  14. 根据权利要求12所述的半导体器件的制作方法，其特征在于，形成所述环形栅极(13a)前，在所述第一栅极区段(12a)上包覆栅极绝缘层(14)；所述环形栅极(13a)包覆所述栅极绝缘层(14)。
  15. 根据权利要求12所述的半导体器件的制作方法，其特征在于，所述生长的第一纳米线异质结(12)为多条。
  16. 根据权利要求12所述的半导体器件的制作方法，其特征在于，所述形成第一支撑结构(11)包括：在所述衬底(10)上生长第一外延层(11')； 图形化所述第一外延层(11')，至少保留所述第二区域(10b)与所述第三区域(10c)上的所述第一外延层(11')，以形成所述第一支撑结构(11)；
    或包括：在所述衬底(10)上形成第一图形化掩膜层，所述第一图形化掩膜层具有第一开口，所述第一开口至少暴露所述第二区域(10b)与所述第三区域(10c)；以所述第一图形化掩膜层为掩膜，在所述衬底(10)上外延生长所述第一支撑结构(11)。
  17. 根据权利要求12所述的半导体器件的制作方法，其特征在于，所述形成第一牺牲层(17)包括：在所述第一支撑结构(11)以及所述第一支撑结构(11)暴露出的所述衬底(10)上生长第一牺牲层(17)，去除所述第一支撑结构(11)上的所述第一牺牲层(17)；
    或包括：以所述第一支撑结构(11)为掩膜，在所述衬底(10)上生长所述第一牺牲层(17)。
  18. 根据权利要求12所述的半导体器件的制作方法，其特征在于，还包括：
    至少在所述第一源极区段(12b)与第一漏极区段(12c)上形成第二支撑结构(15)；在所述第二支撑结构(15)暴露出的所述第一纳米线异质结(12)上形成第二牺牲层(18)；
    在所述第二支撑结构(15)与所述第二牺牲层(18)上生长第二纳米线异质结(16)，所述第二纳米线异质结(16)包括对应于所述第一区域(10a)的第二栅极区段(16a)、对应于所述第二区域(10b)的第二源极区段(16b)以及对应于所述第三区域(10c)的第二漏极区段(16c)；所述第二源极区段(16b)与所述第二漏极区段(16c)位于所述第二支撑结构(15)上，至少所述第二栅极区段(16a)位于所述第二牺牲层(18)上；
    去除所述第二牺牲层(18)，悬空所述第二纳米线异质结(16)。
  19. 根据权利要求18所述的半导体器件的制作方法，其特征在于，所述形成第二支撑结构(15)包括：在所述第一纳米线异质结(12)上生长第二外延层(15')；图形化所述第二外延层(15')，至少保留所述第一源极区段(12b) 与所述第一漏极区段(12c)上的所述第二外延层(15')，以形成所述第二支撑结构(15)；
    或包括：在所述第一纳米线异质结(12)上形成第二图形化掩膜层，所述第二图形化掩膜层具有第二开口，所述第二开口至少暴露所述第一源极区段(12b)与所述第一漏极区段(12c)；以所述第二图形化掩膜层为掩膜，在所述第一纳米线异质结(12)上外延生长所述第二支撑结构(15)。
  20. 根据权利要求18所述的半导体器件的制作方法，其特征在于，形成所述第二牺牲层(18)包括：在所述第二支撑结构(15)以及所述第二支撑结构(15)暴露出的所述第一纳米线异质结(12)上生长第二牺牲层(18)，去除所述第二支撑结构(15)上的所述第二牺牲层(18)；
    或包括：以所述第二支撑结构(15)为掩膜，在所述第一纳米线异质结(12)上生长第二牺牲层(18)。
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