WO2022104653A1 - 信号处理方法、装置、设备、存储介质及计算机设备 - Google Patents

信号处理方法、装置、设备、存储介质及计算机设备 Download PDF

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Publication number
WO2022104653A1
WO2022104653A1 PCT/CN2020/130171 CN2020130171W WO2022104653A1 WO 2022104653 A1 WO2022104653 A1 WO 2022104653A1 CN 2020130171 W CN2020130171 W CN 2020130171W WO 2022104653 A1 WO2022104653 A1 WO 2022104653A1
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Prior art keywords
phase
output
pixel clock
target pixel
adjustment value
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PCT/CN2020/130171
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English (en)
French (fr)
Inventor
尹前澄
胡玉昕
杨焕刚
葛敏锋
周晶晶
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西安诺瓦星云科技股份有限公司
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Priority to CN202080094524.5A priority Critical patent/CN115486059A/zh
Priority to PCT/CN2020/130171 priority patent/WO2022104653A1/zh
Publication of WO2022104653A1 publication Critical patent/WO2022104653A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/44—Colour synchronisation
    • H04N9/45—Generation or recovery of colour sub-carriers

Definitions

  • the present invention relates to the field of display technology, and in particular, to a signal processing method, apparatus, device, storage medium and computer device.
  • the method for realizing the synchronization of the output video signal and the reference signal is: when the output field synchronization signal (VSYNC, VS for short) of the video signal is synchronized with the reference VS of the reference signal, it can be considered that the output video signal and the reference signal are realized. synchronization.
  • the output VS and the reference VS cannot be strictly synchronized.
  • Embodiments of the present invention provide a signal processing method, apparatus, device, storage medium, and computer device, to at least solve the technical problem of rough adjustment accuracy when the adjustment output VS is synchronized with the reference VS in the related art.
  • a signal processing method including: acquiring a phase difference between a first output field synchronization signal VS of a video signal and a reference field synchronization signal VS; determining a phase adjustment according to the phase difference value; according to the phase adjustment value, a target pixel clock frequency is obtained, wherein the target pixel clock frequency is used to generate the second output VS of the video signal.
  • the determining the phase adjustment value according to the phase difference includes: determining the phase adjustment value corresponding to the phase difference through a proportional-integral-derivative PID controller.
  • the determining the phase adjustment value corresponding to the phase difference by using a PID controller includes: adjusting a control coefficient of the PID controller, wherein the control coefficient includes: a proportional coefficient, an integral coefficient and a differential coefficient;
  • the phase adjustment value corresponding to the phase difference is determined by the PID controller after the adjustment coefficient.
  • the determining the phase adjustment value corresponding to the phase difference through a proportional-integral-derivative PID controller includes: determining the phase adjustment value corresponding to the phase difference in the following manner:
  • incr_phase KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase); wherein, fresh_phase is the phase difference, total_phase is the cumulative sum of fresh_phase in the counted historical adjustment times, and last_phase is the last adjustment of this adjustment Phase difference, incr_phase is the phase adjustment value, KP is the proportional coefficient, KI is the integral coefficient, and KD is the differential coefficient.
  • the obtaining the target pixel clock frequency according to the phase adjustment value includes: determining a frequency adjustment value according to the phase adjustment value; and obtaining the target pixel clock frequency according to the frequency adjustment value.
  • the obtaining the target pixel clock frequency according to the phase adjustment value includes: determining the percentage of the phase adjustment value in N frame periods, where N is a positive integer; according to the current pixel of the video signal The clock frequency, and the percentage, determine the target pixel clock frequency.
  • incr_freq_percent incr_phase/gen_vs_T
  • incr_freq_percent is the percentage
  • incr_phase is the phase adjustment value
  • gen_vs_T is the N frame period.
  • the acquiring the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS includes: receiving the phase difference sent by the programmable logic gate array FPGA chip; A phaser receives the first output VS and the reference VS, and obtains the phase difference between the first output VS and the reference VS.
  • the method further includes: generating configuration information according to the target pixel clock frequency; sending the configuration information to a clock chip, wherein the configuration information for configuring the clock chip to generate a target pixel clock according to the target pixel clock frequency.
  • the method further includes: sending a timing parameter of the video signal to a timing generator, wherein the timing parameter is used for a timing parameter generated by the clock chip.
  • the timing generator After the target pixel clocks are combined, the second output VS is generated by the timing generator.
  • the operations from obtaining the phase difference between the first output VS of the video signal and the reference VS to obtaining the target pixel clock frequency are repeatedly performed.
  • the method before the acquiring the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS, the method further includes: determining whether the periodic fluctuation of the reference VS is less than a predetermined fluctuation threshold; If the detection result is yes, determine to perform the operation of acquiring the phase difference between the first output VS of the video signal and the reference VS; and/or, if the detection result is negative, return to determine The operation of whether the periodic fluctuation of the reference VS is less than a predetermined fluctuation threshold.
  • a signal processing apparatus comprising: an acquisition module for acquiring a phase difference between a first output field synchronization signal VS of a video signal and a reference field synchronization signal VS; a determination module for using determining a phase adjustment value according to the phase difference; and a processing module for obtaining a target pixel clock frequency according to the phase adjustment value, wherein the target pixel clock frequency is used to generate the second output VS of the video signal.
  • a signal processing device comprising: a first processor, where the first processor is configured to run a program, wherein, when the program is running, any one of the signal processing methods described above is executed .
  • the apparatus further comprises: a second processor, wherein the second processor is configured to determine the phase difference between the first output VS of the video signal and the reference VS, and The phase difference is sent to the first processor.
  • the second processor includes: a phase detector and a timing generator, wherein the phase detector is configured to receive the input of the first output VS and the reference VS, and output the first output VS an output of the phase difference between the VS and the reference VS; the timing generator, configured to receive the timing parameters of the video signal sent by the processor, and generate the timing parameters according to the timing parameters and the clock chip The target pixel clock generates the second output VS.
  • the phase detector is configured to receive the input of the first output VS and the reference VS, and output the first output VS an output of the phase difference between the VS and the reference VS
  • the timing generator configured to receive the timing parameters of the video signal sent by the processor, and generate the timing parameters according to the timing parameters and the clock chip
  • the target pixel clock generates the second output VS.
  • the device further includes: the clock chip, wherein the clock chip is configured to receive configuration information sent by the first processor, wherein the configuration information is based on the first processor The target pixel clock frequency is generated; the clock chip is further configured to generate a target pixel clock according to the target pixel clock frequency configured by the configuration information.
  • a storage medium includes a stored program, wherein when the program runs, a device where the storage medium is located is controlled to execute the signal processing method described in any one of the above .
  • a computer device comprising: a memory and a third processor, where the memory stores a computer program; the third processor is configured to execute the computer program stored in the memory , when the computer program runs, the third processor executes the signal processing method described in any one of the above.
  • the phase difference method between the first output VS of the video signal and the reference VS is obtained, the phase adjustment value is determined according to the phase difference, and the target pixel clock frequency is obtained according to the phase adjustment value.
  • the phase difference determines the specific phase adjustment value, and obtains the specific target pixel clock frequency according to the specific phase adjustment value, and realizes the adjustment of the output VS of the video signal to synchronize with the reference VS, by determining the specific phase adjustment value, and by The conversion between the phase adjustment and the frequency adjustment can obtain a specific target pixel clock, thereby improving the technical effect of the adjustment accuracy, thereby solving the technical problem that the adjustment accuracy is relatively rough when the adjustment output VS is synchronized with the reference VS in the related art.
  • FIG. 1 is a schematic diagram of an application scenario 1 of a video processing device in an embodiment of the present invention
  • FIG. 2 is a schematic diagram of an application scenario 2 of a video processing device in an embodiment of the present invention
  • FIG. 3 is a schematic diagram of an output video timing sequence under a frame synchronization situation according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a scheme 1 of adjusting the output VS to synchronize with the reference VS provided by an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a second solution for adjusting the output VS to synchronize with the reference VS provided by an embodiment of the present invention
  • FIG. 6 is a schematic diagram of information obtained by a synchronization signal detection and comparison unit in a second solution provided by an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a phase difference count obtained by a synchronization signal detection and comparison unit in a second solution provided by an embodiment of the present invention.
  • FIG. 8 is a flowchart of a signal processing method according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a signal processing device for implementing a signal processing method according to an optional embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a signal processing method according to an optional embodiment of the present invention.
  • FIG. 11 is a structural block diagram of a signal processing apparatus according to Embodiment 2 of the present invention.
  • FIG. 12 is a structural block diagram of a computer terminal according to an embodiment of the present invention.
  • the line synchronization signal (HSYNC, HS for short) is used to select the valid line signal interval on the display panel.
  • the vertical synchronization signal (VSYNC, VS for short) is used to select the effective field signal interval on the display panel.
  • Genlock can synchronize one or more systems with the same synchronization source. For example, it can control the timing parameters (PCLK, HS, VS) of the output video signal of the video processing device to make it match the external reference signal. Synchronization to achieve the purpose of synchronizing the output video signal with the reference signal.
  • Frame synchronization (Framelock), the frame rate of the control device's output video signal is synchronized with the frame rate of the external reference signal to achieve the purpose of synchronizing the frame rate of the output video signal and the reference signal.
  • Frame synchronization also known as frame-level synchronization, is a video synchronization lock. A method in Genlock.
  • PID Proportion Integration Differentiation, referred to as PID controller, proportional integral derivative controller, according to the given value and the actual output value to form the control deviation, a simple algorithm, good robustness, high reliability control algorithm.
  • FPGA Field Programmable Gate Array
  • FPGA field programmable logic gate array
  • a method embodiment of a signal processing method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings may be executed in a computer system such as a set of computer-executable instructions, and, Although a logical order is shown in the flowcharts, in some cases steps shown or described may be performed in an order different from that herein.
  • the Genlock function is of great significance to the video processing equipment.
  • the following are examples of application scenarios of video processing equipment. In the following application scenarios, because the Genlock function is not used, the video signal output by the video processing equipment is abnormal.
  • FIG. 1 is a schematic diagram of an application scenario 1 of a video processing device in an embodiment of the present invention.
  • multiple video processing devices for example, video splicers
  • the video processing device 3 does not use Genlock, which causes the output picture of the video processing device 3 to be out of synchronization with the output pictures of other video processing devices.
  • FIG. 2 is a schematic diagram of an application scenario 2 of a video processing device in an embodiment of the present invention.
  • the video processing device outputs a video signal to the screen, and the camera is shooting a scene including the screen.
  • FIG. 3 is a schematic diagram of output video timing under frame synchronization according to an embodiment of the present invention.
  • the ideal state between output video timing and reference signal under frame synchronization is that the output VS remains synchronized with the reference VS.
  • Vtotal represents the cycle of outputting VS
  • Htotal represents the cycle of outputting HS.
  • the following steps can be taken: first measure the frame rate of the reference VS; input the measured frame rate of the reference VS into the clock generator to generate the output pixel clock, and according to the output resolution set by the current user for the video signal. Then, according to the output pixel clock and the output timing parameters, a timing generator is used to generate the output VS of the video signal, because the output VS of the video signal is generated according to the output pixel clock generated by the frame rate of the reference VS , therefore, the output VS of the video signal is substantially synchronized with the reference VS.
  • the output VS of the video signal and the reference VS are not strictly synchronized, and the lock between the output VS of the video signal and the reference VS is easy to lose. Therefore, the output VS of the video signal and the reference VS cannot be guaranteed to be always synchronized.
  • FIG. 4 is a schematic diagram of the solution 1 of the adjustment output VS and the reference VS synchronization provided by the embodiment of the present invention.
  • the solution 1 includes: The control unit measures the VS frame rate F VS(ref) , and then calculates F PCLK , configures the programmable clock generator according to F PCLK to obtain PCLK, and the timing generator generates video timing driven by PCLK according to the configured timing parameters.
  • FIG. 5 is a schematic diagram of the second solution for the adjustment output VS and the reference VS synchronization provided by the embodiment of the present invention.
  • the second solution includes: :
  • the synchronization signal detection and comparison unit realizes the measurement of the frame frequency F VS(ref) of the reference VS, the control unit calculates the F PCLK , configures the programmable clock generator to obtain the PCLK, and the timing generator generates the PCLK drive according to the configured timing parameters.
  • Video timing the output VS is fed back to the synchronization signal detection and comparison unit.
  • the F PCLK is fine-tuned to ensure that the output VS is always synchronized with the reference VS.
  • the synchronization signal detection and comparison unit detects and compares to obtain the following information:
  • the output can be detected
  • the phase relationship between VS and the reference VS specifically, includes phase lead and phase lag;
  • the frequency relationship between the output VS and the reference VS can also be detected, specifically, including the output VS frequency higher than the reference VS frequency and the output VS frequency lower than Reference VS frequency; may also include: phase difference count.
  • FIG. 7 is a schematic diagram of the phase difference count obtained by the synchronization signal detection and comparison unit in the second solution provided by the embodiment of the present invention. As shown in FIG. 7 , the distance between the reference VS and the high-level edge of the output VS can be recorded as the phase difference ; or the distance between the reference VS and the low-level edge of the output VS can be recorded as the phase difference.
  • the above-mentioned information obtained by the synchronization signal detection and comparison unit can obtain the change trend of the current output VS compared with the reference VS, and adjust the output PCLK frequency correspondingly under different circumstances, thereby keeping the output VS and the reference VS synchronous.
  • Table 1 is a table of feedback adjustment strategies according to the change trend of the output VS compared to the reference VS. As shown in Table 1, according to the detection of the phase difference between the reference VS and the output VS, the adjustment of the output VS can be proposed as shown in Table 1 The feedback regulation strategy shown.
  • the change trend of the current output VS compared with the reference VS can be obtained through the state parameters obtained by the synchronization signal detection and comparison unit, and the output PCLK frequency can be adjusted under different circumstances.
  • the following methods can be used: compare the phase difference between the output VS and the reference VS, and obtain the change trend of the output VS relative to the reference VS according to the phase difference, so as to adjust the pixel clock frequency accordingly (the pixel clock frequency is used to generate Pixel clock, which is used to generate the output VS).
  • the frequency of the pixel clock used to generate the pixel clock can be increased or decreased by increasing the frequency of the pixel clock. , so as to synchronize the output VS with the reference VS.
  • the adjustment of the trend is performed according to the comparison of the phase difference between the output VS and the reference VS with a threshold value, so the adjustment precision is relatively rough. Since the threshold setting of the phase difference determines the adjustment speed, when the threshold setting is too low, frequent adjustments are required; and when the threshold setting is too high, the swing of the output VS relative to the reference VS is large.
  • the preset threshold determines the maximum swing amplitude of the output VS relative to the reference VS, that is, the performance of the genlock, and limited by the hardware capabilities, the threshold cannot be set very low. Therefore, the higher preset threshold value makes the system unable to achieve high-precision phase locking, and the system cannot work in an optimal state. This adjustment method cannot obtain convergent results.
  • FIG. 8 is a flowchart of the signal processing method according to an embodiment of the present invention.
  • the method may be performed by a video processing device, where the video processing device may include: a video processor, a video switcher, or a video splicer, or other devices used for video processing or control.
  • the video processing device may include: a video processor, a video switcher, or a video splicer, or other devices used for video processing or control.
  • the method may also be performed by a processing chip, and the processing chip may include: a Microcontroller Unit (Microcontroller Unit, referred to as MCU for short, may also be referred to as a microprocessor, hereinafter referred to as MCU), an enhanced reduced instruction set A computer processor (Advanced (Reduced Instruction Set Computer, referred to as RISC) Machines, referred to as ARM) or FPGA and other chips used for data processing.
  • MCU Microcontroller Unit
  • MCU Microcontroller Unit
  • MCU Microcontroller Unit
  • RISC Reduced Instruction Set Computer
  • FPGA field-programmable gate array
  • the method includes the following steps:
  • Step S802 obtaining the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS;
  • Step S804 determining the phase adjustment value according to the phase difference
  • Step S806 obtaining the target pixel clock frequency according to the phase adjustment value, wherein the target pixel clock frequency is used to generate the second output VS of the video signal.
  • the phase difference method between the first output VS of the video signal and the reference VS is obtained, the phase adjustment value is determined according to the phase difference, and the target pixel clock frequency is obtained according to the phase adjustment value, and the determination according to the phase difference is achieved.
  • the specific phase adjustment value, and the purpose of obtaining the specific target pixel clock frequency according to the specific phase adjustment value realizes that when the output VS of the video signal is adjusted to be synchronized with the reference VS, by determining the specific phase adjustment value, and through the phase adjustment and The conversion between frequency adjustments can obtain a specific target pixel clock, thereby improving the technical effect of the adjustment accuracy, thereby solving the technical problem that the adjustment accuracy is relatively rough when the adjustment output VS is synchronized with the reference VS in the related art.
  • the above method can be applied to a video processing device, that is, the processor of the video processing device can be used as the execution body of the above method.
  • the above video processing device may be of various types, for example, may be a terminal for processing video signals, or may be a server for performing a function of processing video signals, or the like.
  • the phase adjustment value corresponding to the phase difference may be determined by a proportional integral derivative PID controller. That is, by inputting the phase difference between the output VS and the reference VS into the PID controller, the phase adjustment value is output from the PID controller.
  • the proportional-integral-derivative PID controller includes a proportional unit (P), an integral unit (I) and a differential unit (D), which can form a control deviation according to the given value and the actual output value, basically maintain the variable stability, and is an algorithm Simple, robust and reliable controller.
  • the video processing device can adjust the frequency of PCLK through the calculation result of the control algorithm, so as to achieve the best locking state of the hardware. .
  • the accuracy of Genlock can be further improved.
  • the following method may be used: adjust the control coefficient of the PID controller, wherein the control coefficient includes: proportional coefficient, integral coefficient and differential coefficient ; Determine the phase adjustment value corresponding to the phase difference through the PID controller after the setting coefficient. Tuning the control coefficient of the PID controller can balance the convergence speed and the overshoot amplitude, and obtain the core calculation formula of the algorithm.
  • the phase adjustment value corresponding to the phase difference is determined by the PID controller after setting the coefficient, and the precise phase adjustment value is obtained, which provides a basis for the subsequent obtaining of the precise target pixel clock frequency.
  • the phase adjustment value corresponding to the phase difference can be determined in the following manner:
  • incr_phase KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase); in which, fresh_phase is the phase difference, total_phase is the cumulative sum of fresh_phase in the statistical historical adjustment times, and last_phase is the phase difference of the last adjustment of this adjustment , incr_phase is the phase adjustment value, KP is the proportional coefficient, KI is the integral coefficient, and KD is the differential coefficient.
  • the parameters used may be different according to different ways of obtaining the target pixel clock frequency.
  • the target pixel clock frequency can be obtained in the following manner: first, the frequency adjustment value is obtained according to the phase adjustment value; then, the target pixel clock frequency is obtained according to the frequency adjustment value.
  • the phase adjustment value is positive and negative, that is, it indicates whether the output VS is in phase advance or lag with respect to the reference VS; therefore, the frequency adjustment value also corresponds to positive and negative, that is, on the basis of the current pixel clock frequency of the video signal plus or subtract the value corresponding to the frequency adjustment value.
  • the target pixel clock frequency can also be obtained in the following manner: first determine the percentage of the phase adjustment value in N frame periods, where N is a positive integer; according to the current pixel clock frequency of the video signal and the percentage, determine the target pixel clock frequency.
  • N frame periods represent the current phase value of the output VS of the video signal.
  • the phase adjustment value and the N frame periods referred to above may be expressed in a unified unit of time, for example, both may be expressed in seconds, or both may be expressed in nanoseconds.
  • incr_phase and gen_vs_phase can be represented by the unit of time. When the unit is not uniform, a value converted by a formula can be added to the above formula.
  • the above method of obtaining the target pixel clock frequency through the frequency adjustment value, and the method of determining the target pixel clock frequency through the current pixel clock frequency and percentage can be flexibly selected according to needs, but no matter which method is used above, Both effectively utilize the relationship between the phase and the frequency, and realize the transformation of the phase adjustment into the frequency adjustment, so that the pixel clock frequency can be conveniently and accurately configured for the subsequent clock generator.
  • the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS can be obtained in various ways. phase difference; or, receive the first output VS and the reference VS through a phase detector, and obtain the phase difference between the first output VS and the reference VS.
  • the phase difference between the first output VS and the reference VS can be obtained directly from the FPGA chip, directly from the phase detector, or can also be obtained from a combination of the FPGA chip and the phase detector (for example, the phase detector integrated in an FPGA chip).
  • the method further includes: generating configuration information according to the target pixel clock frequency; sending the configuration information to the clock chip, where the configuration information is used to configure the clock chip Generate the target pixel clock based on the target pixel clock frequency.
  • the target pixel clock frequency is configured to the clock chip, so that the clock chip can generate the target pixel clock according to the target pixel clock frequency.
  • the method further includes: sending the timing parameters of the video signal to the timing generator, wherein the timing parameters are used for combining with the target pixel clock generated by the clock chip, and then sent by The timing generator generates a second output VS.
  • the timing parameters of the video signal are sent to the timing generator, so that the timing generator generates the second output VS based on the target pixel clock generated by the clock chip and the timing parameters, thereby completing the output VS and the reference VS once Synchronized adjustment process.
  • the operation from obtaining the phase difference between the first output VS of the video signal and the reference VS to obtaining the target pixel clock frequency can be repeated according to the frame period, that is, taking one frame as the period To perform an adjustment of the output VS and the reference VS synchronization, so as to achieve high-precision frame synchronization.
  • the method before acquiring the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS, the method further includes: determining whether the periodic fluctuation of the reference VS is less than a predetermined fluctuation threshold; If the detection result is YES, determine to perform the operation of acquiring the phase difference between the first output VS of the video signal and the reference VS; and/or, if the detection result is NO, return to determine the periodic fluctuation of the reference VS Whether the operation is less than a predetermined fluctuation threshold.
  • the predetermined fluctuation threshold corresponding to the reference VS may be set differently according to the reference VS.
  • a fluctuation threshold it can be used to characterize the stability of the reference VS. The more stable the VS is, the more precise the synchronization between the output VS and the reference VS is.
  • the above-mentioned fluctuation threshold can be set as the percentage of periodic fluctuation relative to the entire statistical period of the reference VS. For example, when the fluctuation of the reference VS is less than 30% of the fluctuation threshold, the reference VS is considered to be stable and can be used for synchronization. Reference to output VS.
  • FIG. 9 is a schematic diagram of a signal processing device for implementing a signal processing method according to an optional embodiment of the present invention.
  • the signal processing device may be a video processing device, wherein the video processing device may include: a video processor, a video switcher, or a video splicer, or other devices used for video processing or control.
  • the signal processing device may include the following parts: a clock chip 6208, an MCU, and an FPGA chip (wherein, the FPGA chip may be integrated with a timing generator and a phase detector). The following describes the signal processing settings. .
  • the clock chip 6208 is used to generate the clock source of the desired frequency of the control system, that is, used to receive the configuration information of the MCU, and generate the pixel clock according to the pixel clock frequency configured by the configuration information; the MCU is used to configure the clock chip 6208 and run the control algorithm; FPGA The chip includes a timing generator and a phase detector, wherein the timing generator is used to generate the output timing (Timing_gen) of the video signal according to the pixel clock (gen_clk) and the timing parameters (Timing_para), and the phase detector (phase_det) is used to receive video.
  • the output VS of the signal and the reference VS thereby outputting the phase difference (phase_error) between the output VS and the reference VS, and pushing the phase_error to the MCU as an input parameter of the control algorithm.
  • the MCU is for more convenient configuration of the clock chip and the operation of the control algorithm, and the MCU can also be replaced with other main control devices, such as a digital signal processor (Digital Signal Processor, referred to as DSP), personal Computer (Personal Computer, referred to as PC), or even directly into the FPGA as the main control.
  • DSP Digital Signal Processor
  • PC Personal Computer
  • FIG. 10 is a schematic diagram of a signal processing method according to an optional embodiment of the present invention. As shown in FIG. 10 , the method includes the following steps:
  • Step 1) Turn on the Genlock function
  • Step 2) obtain the reference VS cycle from the FPGA chip
  • Step 3 according to the current resolution, calculate the pixel clock (PCLK) frequency, and configure the PCLK frequency to the clock chip through the configuration information;
  • Step 4) determine that the PCLK is stable from the FPGA chip, open the phase detection of the FPGA chip, that is, realize the detection of the phase difference between the output VS and the reference VS by the phase detector in the FPGA chip;
  • Step 5 After the MCU receives the interrupt, it reads the phase difference count and the reference VS cycle from the FPGA chip;
  • Step 6) judge whether the reference VS periodic fluctuation is less than 30%, if it is judged to be yes, go to step 7), if it is judged to be no, go to step 2);
  • Step 7) execute automatic adjustment algorithm, configure target pixel clock frequency
  • Step 8) After one adjustment is over, wait for the next interruption to arrive, and when the next interruption arrives, go to step 5).
  • the adjustment algorithm of the optional embodiment of the present invention is as follows:
  • incr_phase KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase);
  • fresh_phase is the latest phase difference value count obtained after each interruption * FPGA adopts the clock cycle (sample_t), that is, the above-mentioned phase difference, in ns.
  • total_phase is the cumulative sum of fresh_phases received each time, that is, the cumulative sum of fresh_phases within the historical adjustment times of the statistics mentioned above.
  • the last_phase is the last fresh_phase (that is, the phase difference of the last adjustment of this adjustment).
  • incr_phase is the phase value to be adjusted (ie, the phase adjustment value referred to above).
  • the phase value to be adjusted After calculating the phase value to be adjusted, it needs to be converted to the frequency value of the clock chip 6208 (that is, the target pixel clock frequency). According to the relationship between the clock and the phase, after deduction, the relationship between the phase and the frequency adjustment is obtained as follows:
  • the frequency adjustment percentage can be calculated from the adjustment phase value in the following ways:
  • incr_freq_percent incr_phase/(gen_vs_T*1 000 000 000), it should be noted that the 9th power of 10 is multiplied here because the unit of gen_vs_T is seconds, and the unit of incr_phase is nanoseconds. Units are converted to ns. last_freq is the last configured frequency value (that is, the above-mentioned current pixel clock frequency), in hz.
  • a new frequency value (that is, the target pixel clock frequency) is configured to the clock chip to complete an adjustment process.
  • the microprocessor MCU waits for the FPGA chip to initiate the next interrupt, and then repeats the above steps. With multiple calculation processing, the characteristics of the algorithm itself will continuously approach the Gen_VS to the reference VS (ref_VS) to achieve high-precision Genlock locking.
  • the fast locking and convergence of the video output VS to the reference VS is realized, thereby realizing the high-precision synchronization of the output VS and the reference VS.
  • the following error of the current 10us can be reduced to 150ns, an increase of 60 times. This error is determined by the accuracy of the clock chip and the phase detection frequency of the phase detector.
  • this optional implementation can push the accuracy of the Genlock to the limit that the hardware can achieve, and obtain a good performance.
  • FIG. 11 is a structural block diagram of the signal processing apparatus according to Embodiment 2 of the present invention.
  • the signal processing apparatus 1100 includes: an acquisition module 1102 that determines module 1104 and processing module 1106.
  • the signal processing apparatus 1100 will be specifically described below.
  • an acquisition module 1102 configured to acquire the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS;
  • a determining module 1104 connected to the above-mentioned obtaining module 1102, for determining the phase adjustment value according to the phase difference;
  • the processing module 1106 is connected to the above-mentioned determining module 1104, and is used for obtaining the target pixel clock frequency according to the phase adjustment value, wherein the target pixel clock frequency is used to generate the second output VS of the video signal.
  • the above-mentioned acquisition module 1102, determination module 1104 and processing module 1106 correspond to steps S402 to S406 in Embodiment 1, and the above-mentioned modules and corresponding steps implement the same examples and application scenarios, but do not It is limited to the content disclosed in the above-mentioned Embodiment 1. It should be noted that, as a part of the apparatus, the above-mentioned modules may run in the computer terminal provided in Embodiment 1.
  • a signal processing device is also provided, the signal processing device includes a first processor, and the first processor is used to run a program, wherein the embodiment in the above-mentioned Embodiment 1 is executed or optional when the program is running. Any one of the signal processing methods provided in the embodiments.
  • the type of the first processor may be various, for example, it may be the MCU described above, or an ARM or the like.
  • the above signal processing device further includes: a second processor, wherein the second processor is configured to determine the phase difference between the first output VS of the video signal and the reference VS, and convert the phase The difference is sent to the first processor.
  • the above-mentioned first processor and second processor may be the same processor, or may be two different processors.
  • the first processor may be the aforementioned MCU, and the second processor may be a field programmable logic gate array (FPGA) chip or the like.
  • FPGA field programmable logic gate array
  • the second processor may include: a phase detector and a timing generator, wherein the phase detector is configured to receive the input of the first output VS and the reference VS, and output the first output VS and The phase difference between the reference VS; the timing generator is used to receive the timing parameters of the video signal sent by the processor, and generate the second output VS according to the timing parameters and the target pixel clock generated by the clock chip.
  • the above signal processing device may further include: a clock chip, wherein the clock chip is configured to receive configuration information sent by the first processor, wherein the configuration information is configured by the first processor according to the target pixel clock Frequency generation; the clock chip is further configured to generate the target pixel clock according to the target pixel clock frequency configured by the configuration information.
  • a storage medium is also provided.
  • the above-mentioned storage medium may be used to store the program code executed by the signal processing method provided in the above-mentioned Embodiment 1.
  • the above-mentioned storage medium may be located in any computer terminal in a computer terminal group in a computer network, or in any mobile terminal in a mobile terminal group.
  • the storage medium is configured to store program codes for performing the following steps: acquiring the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS; according to the phase The difference determines the phase adjustment value; according to the phase adjustment value, the target pixel clock frequency is obtained, wherein the target pixel clock frequency is used to generate the second output VS of the video signal.
  • the storage medium is further configured to store program codes for performing the following steps: determining the phase adjustment value according to the phase difference, including: determining the phase adjustment corresponding to the phase difference through a proportional-integral-derivative PID controller value.
  • the storage medium is further configured to store program codes for performing the following steps: determining the phase adjustment value corresponding to the phase difference through the PID controller, including: adjusting the control coefficient of the PID controller, wherein , the control coefficient includes: proportional coefficient, integral coefficient and differential coefficient; the phase adjustment value corresponding to the phase difference is determined by the PID controller after setting the coefficient.
  • the storage medium is further configured to store program codes for performing the following steps: determining the phase adjustment value corresponding to the phase difference through a proportional-integral-derivative PID controller, including: determining the phase difference in the following manner Corresponding phase adjustment value:
  • incr_phase KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase); in which, fresh_phase is the phase difference, total_phase is the cumulative sum of fresh_phase in the statistical historical adjustment times, and last_phase is the phase difference of the last adjustment of this adjustment , incr_phase is the phase adjustment value, KP is the proportional coefficient, KI is the integral coefficient, and KD is the differential coefficient.
  • the storage medium is further configured to store program codes for performing the following steps: determining the frequency adjustment value according to the phase adjustment value; and obtaining the target pixel clock frequency according to the frequency adjustment value.
  • the storage medium is further configured to store program codes for performing the following steps: obtaining the target pixel clock frequency according to the phase adjustment value, including: determining the percentage of the phase adjustment value in the N frame periods , where N is a positive integer; the target pixel clock frequency is determined according to the current pixel clock frequency of the video signal and the percentage.
  • the storage medium is further configured to store program codes for performing the following steps: acquiring the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS, including : Receive the phase difference sent by the programmable logic gate array FPGA chip; or, receive the first output VS and the reference VS through a phase detector, and obtain the phase difference between the first output VS and the reference VS.
  • the storage medium is further configured to store program codes for performing the following steps: after obtaining the target pixel clock frequency according to the frequency adjustment value, further comprising: generating configuration information according to the target pixel clock frequency ; Send configuration information to the clock chip, wherein the configuration information is used to configure the clock chip to generate the target pixel clock according to the target pixel clock frequency.
  • the storage medium is further configured to store program codes for executing the following steps: after sending the configuration information to the clock chip, the method further includes: sending the timing parameters of the video signal to the timing generator, wherein , the timing parameters are used to generate the second output VS by the timing generator after being combined with the target pixel clock generated by the clock chip.
  • the storage medium is further configured to store program codes for executing the following steps: according to the frame period, repeatedly executing from acquiring the phase difference between the first output VS and the reference VS of the video signal to Get the operation of the target pixel clock frequency.
  • the storage medium is further configured to store program codes for performing the following steps: before acquiring the phase difference between the first output field sync signal VS of the video signal and the reference field sync signal VS , further comprising: determining whether the periodic fluctuation of the reference VS is less than a predetermined fluctuation threshold; if the detection result is yes, determining to perform an operation of acquiring the phase difference between the first output VS of the video signal and the reference VS; and/or , if the detection result is negative, return to the operation of determining whether the periodic fluctuation of the reference VS is less than the predetermined fluctuation threshold.
  • Embodiments of the present invention may provide a computer terminal, and the computer terminal may be any computer terminal device in a computer terminal group.
  • the above-mentioned computer terminal may also be replaced by a terminal device such as a mobile terminal.
  • the above-mentioned computer terminal may be located in at least one network device among multiple network devices of a computer network.
  • the above-mentioned computer terminal can execute the program code of the following steps in the signal processing method of the application program: acquiring the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS; according to the phase difference Determine the phase adjustment value; obtain the target pixel clock frequency according to the phase adjustment value, wherein the target pixel clock frequency is used to generate the second output VS of the video signal.
  • FIG. 12 is a structural block diagram of a computer terminal according to an embodiment of the present invention.
  • the computer terminal may include: one or more (only one is shown in the figure) a third processor 1202, a memory 1204, and the like.
  • the memory 1204 may be used to store software programs and modules, such as program instructions/modules corresponding to the signal processing method and device in the embodiments of the present invention, and the third processor 1202 executes the software programs and modules stored in the memory by running the software programs and modules.
  • the memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory may further include memory located remotely from the third processor, the remote memory being connectable to the computer terminal through a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • the third processor can call the information and the application program stored in the memory through the transmission device to perform the following steps: obtain the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS; determine according to the phase difference Phase adjustment value; according to the phase adjustment value, the target pixel clock frequency is obtained, wherein the target pixel clock frequency is used to generate the second output VS of the video signal.
  • the above-mentioned third processor may further execute the program code of the following steps: determining the phase adjustment value according to the phase difference, including: determining the phase adjustment value corresponding to the phase difference through a proportional-integral-derivative PID controller.
  • the above-mentioned third processor may also execute the program code of the following steps: determining the phase adjustment value corresponding to the phase difference through the PID controller, including: setting a control coefficient of the PID controller, wherein the control coefficient includes: a proportional coefficient, Integral coefficient and differential coefficient; determine the phase adjustment value corresponding to the phase difference through the PID controller after the tuning coefficient.
  • the above-mentioned third processor may also execute the program code of the following steps: determining the phase adjustment value corresponding to the phase difference through a proportional-integral-derivative PID controller, including: determining the phase adjustment value corresponding to the phase difference in the following manner:
  • incr_phase KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase); in which, fresh_phase is the phase difference, total_phase is the cumulative sum of fresh_phase in the statistical historical adjustment times, and last_phase is the phase difference of the last adjustment of this adjustment , incr_phase is the phase adjustment value, KP is the proportional coefficient, KI is the integral coefficient, and KD is the differential coefficient.
  • the above-mentioned third processor may further execute the program code of the following steps: determining the frequency adjustment value according to the phase adjustment value; and obtaining the target pixel clock frequency according to the frequency adjustment value.
  • the above-mentioned third processor may also execute the program code of the following steps: obtaining the target pixel clock frequency according to the phase adjustment value, including: determining the percentage of the phase adjustment value in N frame periods, where N is a positive integer; Based on the current pixel clock frequency of the video signal, and the percentage, determine the target pixel clock frequency.
  • the above-mentioned third processor may also execute the program code of the following steps: acquiring the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS, including: receiving an editable logic gate array FPGA The phase difference sent by the chip; or, the first output VS and the reference VS are received through a phase detector, and the phase difference between the first output VS and the reference VS is obtained.
  • the above-mentioned third processor may also execute the program code of the following steps: after obtaining the target pixel clock frequency according to the frequency adjustment value, it also includes: generating configuration information according to the target pixel clock frequency; sending the configuration information to the clock chip, The configuration information is used to configure the clock chip to generate the target pixel clock according to the target pixel clock frequency.
  • the above-mentioned third processor may also execute the program code of the following steps: after sending the configuration information to the clock chip, it also includes: sending the timing parameters of the video signal to the timing generator, wherein the timing parameters are used to communicate with the clock chip. After the generated target pixel clocks are combined, the second output VS is generated by the timing generator.
  • the above-mentioned third processor may further execute the program code of the following steps: according to the frame period, repeatedly perform the operation from obtaining the phase difference between the first output VS of the video signal and the reference VS to obtaining the target pixel clock frequency.
  • the above-mentioned third processor may also execute the program code of the following steps: before acquiring the phase difference between the first output field synchronization signal VS of the video signal and the reference field synchronization signal VS, the method further includes: determining the phase difference of the reference VS. Whether the periodic fluctuation is less than a predetermined fluctuation threshold; if the detection result is yes, it is determined to perform the operation of acquiring the phase difference between the first output VS of the video signal and the reference VS; and/or, in the case of the detection result being negative Next, return to the operation of determining whether the periodic fluctuation of the reference VS is smaller than the predetermined fluctuation threshold.
  • the disclosed technical content can be implemented in other ways.
  • the device embodiments described above are only illustrative, for example, the division of the units may be a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components may be combined or Integration into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of units or modules, and may be in electrical or other forms.
  • the units described as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium.
  • the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.
  • the aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes .

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Abstract

一种信号处理方法、装置、存储介质及计算机设备。该方法包括：获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差（S802）；根据相位差确定相位调整值（S804）；根据相位调整值，得到目标像素时钟频率，其中，目标像素时钟频率用于生成视频信号的第二输出VS（S806）。

Description

信号处理方法、装置、设备、存储介质及计算机设备 技术领域
本发明涉及显示技术领域，具体而言，涉及一种信号处理方法、装置、设备、存储介质及计算机设备。
背景技术
在视频信号处理设备的多种应用场景中，需要保证各台设备的输出视频信号与参考信号同步，从而实现多台设备之间的同步。相关技术中，实现输出视频信号与参考信号同步的方法是：当视频信号的输出场同步信号(VSYNC，简称VS)与参考信号的参考VS同步时，即可认为实现了输出视频信号与参考信号的同步。但在相关技术中，输出VS与参考VS并不能实现严格同步。
在相关技术中，调节输出VS与参考VS同步时，存在调节精度较为粗糙的问题。
针对上述的问题，目前尚未提出有效的解决方案。
发明内容
本发明实施例提供了一种信号处理方法、装置、设备、存储介质及计算机设备，以至少解决相关技术中调节输出VS与参考VS同步时，存在调节精度较为粗糙的技术问题。
根据本发明实施例的一个方面，提供了一种信号处理方法，包括：获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差；根据所述相位差确定相位调整值；根据所述相位调整值，得到目标像素时钟频率，其中，所述目标像素时钟频率用于生成所述视频信号的第二输出VS。
可选地，所述根据所述相位差确定相位调整值，包括：通过比例积分微分PID控制器确定所述相位差对应的相位调整值。
可选地，所述通过PID控制器确定所述相位差对应的相位调整值，包括：整定所述PID控制器的控制系数，其中，所述控制系数包括：比例系数，积分系数和微分系数；通过整定系数后的PID控制器确定所述相位差对应的相位调整值。
可选地，所述通过比例积分微分PID控制器确定所述相位差对应的相位调整值， 包括：通过以下方式确定所述相位差对应的相位调整值：
incr_phase＝KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase)；其中，fresh_phase为所述相位差，total_phase为统计的历史调整次数内fresh_phase的累积和，last_phase为此次调整的上一次调整的相位差，incr_phase为所述相位调整值，KP为所述比例系数，KI为所述积分系数，KD为所述微分系数。
可选地，所述根据所述相位调整值，得到目标像素时钟频率，包括：根据所述相位调整值，确定频率调整值；根据所述频率调整值，得到所述目标像素时钟频率。
可选地，所述根据所述相位调整值，得到目标像素时钟频率，包括：确定所述相位调整值占N个帧周期的百分比，其中，N为正整数；根据所述视频信号的当前像素时钟频率，以及所述百分比，确定所述目标像素时钟频率。
可选地，通过以下方式，确定所述相位调整值占N个帧周期的百分比：incr_freq_percent＝incr_phase/gen_vs_T，其中，incr_freq_percent为所述百分比，incr_phase为所述相位调整值，gen_vs_T为所述N个帧周期。
可选地，通过以下方式，根据所述视频信号的当前像素时钟频率，以及所述百分比，确定所述目标像素时钟频率：fresh_freq＝last_freq*(1+incr_freq_percent)，其中，fresh_freq为所述目标像素时钟频率，last_freq为所述当前像素时钟频率。
可选地，所述获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差，包括：接收可编辑逻辑门阵列FPGA芯片发送的所述相位差；或者，通过鉴相器接收所述第一输出VS与所述参考VS，并获得所述第一输出VS和所述参考VS之间的所述相位差。
可选地，在所述根据所述频率调整值，得到目标像素时钟频率之后，还包括：根据所述目标像素时钟频率生成配置信息；向时钟芯片发送所述配置信息，其中，所述配置信息用于配置所述时钟芯片根据所述目标像素时钟频率生成目标像素时钟。
可选地，在所述向所述时钟芯片发送所述配置信息之后，还包括：向时序生成器发送所述视频信号的时序参数，其中，所述时序参数用于与所述时钟芯片生成的目标像素时钟结合后，由所述时序生成器生成所述第二输出VS。
可选地，按照帧周期，重复执行从获取视频信号的第一输出VS与参考VS之间的相位差至得到目标像素时钟频率的操作。
可选地，在所述获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差之前，还包括：确定所述参考VS的周期波动是否小于预定的波动阈 值；在检测结果为是的情况下，确定执行获取所述视频信号的第一输出VS与所述参考VS之间的所述相位差的操作；和/或，在检测结果为否的情况下，返回确定所述参考VS的周期波动是否小于预定的波动阈值的操作。
根据本发明的另一方面，提供了一种信号处理装置，包括：获取模块，用于获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差；确定模块，用于根据所述相位差确定相位调整值；处理模块，用于根据所述相位调整值，得到目标像素时钟频率，其中，所述目标像素时钟频率用于生成所述视频信号的第二输出VS。
根据本发明的再一方面，提供了一种信号处理设备，包括：第一处理器，所述第一处理器用于运行程序，其中，所述程序运行时执行上述任意一项所述信号处理方法。
可选地，所述设备还包括：第二处理器，其中，所述第二处理器用于确定所述视频信号的所述第一输出VS与所述参考VS之间的所述相位差，并将所述相位差发送给所述第一处理器。
可选地，所述第二处理器包括：鉴相器和时序生成器，其中，所述鉴相器，用于接收所述第一输出VS与所述参考VS的输入，并输出所述第一输出VS和所述参考VS之间的所述相位差；所述时序生成器，用于接收所述处理器发送的所述视频信号的时序参数，并根据所述时序参数和时钟芯片生成的目标像素时钟生成所述第二输出VS。
可选地，所述设备还包括：所述时钟芯片，其中，所述时钟芯片，用于接收所述第一处理器发送的配置信息，其中，所述配置信息由所述第一处理器依据所述目标像素时钟频率生成；所述时钟芯片，还用于依据所述配置信息配置的目标像素时钟频率生成目标像素时钟。
根据本发明的又一方面，提供了一种存储介质，所述存储介质包括存储的程序，其中，在所述程序运行时控制所述存储介质所在设备执行上述任意一项所述的信号处理方法。
根据本发明的还一方面，提供了一种计算机设备，包括：存储器和第三处理器，所述存储器存储有计算机程序；所述第三处理器，用于执行所述存储器中存储的计算机程序，所述计算机程序运行时使得所述第三处理器执行上述任意一项所述的信号处理方法。
在本发明实施例中，采用获取视频信号的第一输出VS与参考VS之间的相位 差方式，通过根据相位差确定相位调整值，以及根据相位调整值，得到目标像素时钟频率，达到了根据相位差确定具体的相位调整值，以及根据具体的相位调整值，得到具体的目标像素时钟频率的目的，实现了调节视频信号的输出VS与参考VS同步时，通过确定具体相位调整值，以及通过相位调整与频率调整之间的转换，得到具体的目标像素时钟，从而提高调节精度的技术效果，进而解决了相关技术中，调节输出VS与参考VS同步时，存在调节精度较为粗糙的技术问题。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是本发明实施例中视频处理设备的应用场景1的示意图；
图2是本发明实施例中视频处理设备的应用场景2的示意图；
图3是根据本发明实施例的帧同步情况下的输出视频时序示意图；
图4是本发明实施例提供的调节输出VS与参考VS同步的方案一的示意图；
图5是本发明实施例提供的调节输出VS与参考VS同步的方案二的示意图；
图6是本发明实施例提供的方案二中的同步信号检测比较单元所得到的信息的示意图；
图7是本发明实施例提供的方案二中同步信号检测比较单元所得到的相位差计数的示意图；
图8是根据本发明实施例的信号处理方法的流程图；
图9是根据本发明可选实施方式的用于实现信号处理方法的信号处理设备的示意图；
图10是根据本发明可选实施方式的信号处理方法的示意图；
图11是根据本发明实施例2的信号处理装置的结构框图；
图12是根据本发明实施例的一种计算机终端的结构框图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
首先，在对本申请实施例进行描述的过程中出现的部分名词或术语适用于如下解释：
行同步信号，(HSYNC，简称HS)，作用是选择出显示面板上有效行信号区间。
场同步信号，(VSYNC，简称VS)，作用是选择出显示面板上有效场信号区间。
同步锁相(Genlock)，可以使一套或多套系统与同一同步源实现同步，例如，可以控制视频处理设备的输出视频信号的时序参数(PCLK、HS、VS)，使其与外部参考信号同步，达到输出视频信号与参考信号同步的目的。
帧同步(Framelock)，控制设备的输出视频信号的帧频与外部参考信号的帧频同步，达到输出视频信号与参考信号帧频同步的目的，帧同步又称帧级同步，是视频的同步锁相(Genlock)中的一种方法。
PID(Proportion Integration Differentiation，简称PID)控制器，比例积分微分控制器，根据给定值和实际输出值构成控制偏差，一种算法简单、鲁棒性好、可靠性高的控制算法。
FPGA(Field Programmable Gate Array，简称FPGA)芯片，现场可编程逻辑门阵列，属于专用集成电路领域中的半定制电路。
实施例1
根据本发明实施例，提供了一种信号处理方法的方法实施例，需要说明的是，在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行，并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
在视频处理设备的众多应用场景中，需要保证视频处理设备输出的视频信号与参考信号同步。这时，Genlock功能对视频处理设备就有重要意义。为说明Genlock功能对视频处理设备的重要意义，下面举例几种视频处理设备的应用场景，在以下几种应用场景中，由于未使用Genlock功能，均导致视频处理设备输出的视频信号异常。
例如，图1是本发明实施例中视频处理设备的应用场景1的示意图，如图1所示，多台视频处理设备(例如，视频拼接器)协同工作拼接成大视频画面时，需要保证所有视频处理设备的输出视频信号同步，因而单台视频处理设备需要开启Genlock功能使输出的视频信号同步于相同的参考信号。如果没有Genlock功能，在视频处理设备间输出图像的边缘会出现撕裂现象。如图1所示，视频处理设备3未使用Genlock，导致视频处理设备3的输出画面与其他视频处理设备的输出画面不同步。
又例如，图2是本发明实施例中视频处理设备的应用场景2的示意图，如图2所示，在演播室环境中，视频处理设备输出视频信号到屏幕，摄像机在拍摄包含屏幕的场景时，需要保证相机视频采样与屏幕上输出画面刷新保持同步，否则会造成相机拍摄到屏幕上的图像有滚动条纹。为了解决该问题，也需在视频处理设备中加入Genlock功能，例如，可以采用帧同步来实现。
图3根据本发明实施例的帧同步情况下的输出视频时序示意图，如图3所示，帧同步情况下输出视频时序与参考信号之间的理想状态，即输出VS保持与参考VS同步。图中，Vtotal表示输出VS的周期；Htotal表示输出HS的周期。
为实现帧同步，可以采用以下步骤：先对参考VS的帧频进行测量；将测量得到的参考VS的帧频输入时钟生成器，生成输出像素时钟，并根据当前用户针对视频信号设置的输出分辨率等确定输出时序参数；之后，根据输出像素时钟以及输出时序参数，采用时序生成器生成该视频信号的输出VS，由于视频信号的输出VS是根据参考VS的帧频生成的输出像素时钟生成的，因此，视频信号的输出VS基本与参考VS同步。其中，输出像素时钟频率的计算公式为： F PCLK＝F VS(ref)*Htotal*VTotal，F VS(ref)为参考VS帧频，Htotal为输出HS的周期，VTotal为输出VS的周期；3)保持输出VS与参考VS一直同步。
但采用上述同步方法，视频信号的输出VS与参考VS并非严格同步，视频信号的输出VS与参考VS之间容易失锁，因此，视频信号的输出VS与参考VS并不能保证一直同步。
为调节输出VS与参考VS一直同步，可以是采用以下方案一，图4是本发明实施例提供的调节输出VS与参考VS同步的方案一的示意图，如图4所示，该方案一包括：控制单元实现对VS帧频F VS(ref)的测量，进而计算得到F PCLK，根据F PCLK配置可编程时钟生成器得到PCLK，时序生成器根据配置的时序参数在PCLK驱动下生成视频时序。
在上述方案一中，为了保证输出VS与参考VS一直同步，每次在新的参考VS信号到来时，复位视频时序生成器，重新生成下一帧输出的视频时序，来达到输出VS与参考VS同步目的。然而上述方案一中，由于直接使用外部参考信号复位时序生成器来输出时序，由于参考信号不可控，因而存在如下缺点：首先，强制复位输出时序导致部分显示设备不能接受这种视频信号；其次，由于每一帧都复位输出时序，导致无法实现帧频转换。
为调节输出VS与参考VS一直同步，还可以是采用以下方案二，图5是本发明实施例提供的调节输出VS与参考VS同步的方案二的示意图，如图5所示，该方案二包括：同步信号检测比较单元实现对参考VS的帧频F VS(ref)的测量，控制单元计算得到F PCLK，配置可编程时钟生成器得到PCLK，时序生成器根据配置的时序参数在PCLK驱动下生成视频时序；输出VS被反馈送回同步信号检测比较单元，在同步信号检测比较单元的比较下，微调F PCLK来保证输出VS与参考VS一直同步。
图6是本发明实施例提供的方案二中的同步信号检测比较单元所得到的信息的示意图，如图6所示，同步信号检测比较单元检测可以检测并比较得出以下信息：可以检测出输出VS与参考VS的相位关系，具体的，包括相位超前与相位滞后；还可以检测出输出VS与参考VS的频率关系，具体的，包括输出VS频率高于参考VS的频率和输出VS频率低于参考VS频率；还可以包括：相位差计数。
图7是本发明实施例提供的方案二中同步信号检测比较单元所得到的相位差计数的示意图，如图7所示，可以将参考VS与输出VS的高电平边缘的距离记为相位差；或者还可以将参考VS与输出VS的低电平边缘的距离记为相位差。
通过同步信号检测比较单元获取的上述信息能够得到当前输出VS相较于参考VS的变化趋势，在不同的情况下对输出PCLK频率进行对应的调节，进而保持输出VS与参考VS同步。
表1是根据输出VS相较于参考VS的变化趋势对应进行的反馈调节策略表，如表1所示，根据对参考VS与输出VS的相位差检测，可以对输出VS的调节提出如表1所示的反馈调节策略。
表1
Figure PCTCN2020130171-appb-000001
通过同步信号检测比较单元获取的状态参数能够得到当前输出VS相较于参考VS的变化趋势，在不同的情况下对输出PCLK频率进行调整。在调整时，可以采用以下方式：比较输出VS与参考VS之间的相位差，根据该相位差得到输出VS相对于参考VS的变化趋势，从而对应调整像素时钟频率(该像素时钟频率用于生成像素时钟，该像素时钟用于生成输出VS)。例如，当输出VS与参考VS之间的相位差超过一个阈值时，得到输出VS相对于参考VS超前还是滞后的变化趋势，则通过将用于生成像素时钟的像素时钟频率调大，或者调小，从而实现输出VS与参考VS的同步。然而，在该方案中，依据输出VS与参考VS之间的相位差与一个阈值的比较来进行趋势的调节，因而调节精度比较粗糙。由于相位差的阈值设定决定了调节速度，导致当阈值设定太低时，需要很频繁的调节；而阈值设定的太高时，输出VS相对于参考VS的摆动幅度较大。预设阈值决定了输出VS相对于参考VS的最大摆动幅度，即genlock的性能，而受限于硬件能力，阈值无法设定的很低。因而，较高的预设阈值导致系统无法实现高精度锁相，系统无法在最佳状态上工作。这种调节方式无法得到收敛的结果。
.鉴于上述调节输出VS与参考VS同步时，调节精度较为粗糙的问题，在本发明实施例中，提供了一种信号处理方法，图8是根据本发明实施例的信号处理方法 的流程图。
可选地，该方法可以由视频处理设备执行，其中，该视频处理设备可以包括：视频处理器、视频切换器或视频拼接器等用于进行视频处理或控制的设备。
可选地，该方法还可以由处理芯片执行，该处理芯片可以包括：微控制单元(Microcontroller Unit，简称为MCU，也可以称为微处理器，以下均称为MCU)、增强的精简指令集计算机处理器(Advanced(Reduced Instruction Set Computer，简称为RISC)Machines，简称为ARM)或FPGA等用于进行数据处理的芯片。
如图8所示，该方法包括如下步骤：
步骤S802，获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差；
步骤S804，根据相位差确定相位调整值；
步骤S806，根据相位调整值，得到目标像素时钟频率，其中，目标像素时钟频率用于生成视频信号的第二输出VS。
通过上述步骤，采用获取视频信号的第一输出VS与参考VS之间的相位差方式，通过根据相位差确定相位调整值，以及根据相位调整值，得到目标像素时钟频率，达到了根据相位差确定具体的相位调整值，以及根据具体的相位调整值，得到具体的目标像素时钟频率的目的，实现了调节视频信号的输出VS与参考VS同步时，通过确定具体相位调整值，以及通过相位调整与频率调整之间的转换，得到具体的目标像素时钟，从而提高调节精度的技术效果，进而解决了相关技术中，调节输出VS与参考VS同步时，存在调节精度较为粗糙的技术问题。
作为一种可选的实施例，上述方法可以应用于视频处理设备中，即可以将视频处理设备的处理器作为上述方法的执行主体。需要说明的是，上述视频处理设备可以是多种类型的，例如，可以是用于处理视频信号的终端，也可以是用于执行处理视频信号功能的服务器等。
作为一种可选的实施例，在根据相位差确定相位调整值时，可以采用多种方式，例如，可以通过比例积分微分PID控制器确定相位差对应的相位调整值。即通过将输出VS与参考VS的相位差输入PID控制器，从PID控制器中输出相位调整值。该比例积分微分PID控制器，包括比例单元(P)、积分单元(I)和微分单元(D)，可以根据给定值和实际输出值构成控制偏差，基本上维持变量稳定，是一种算法简单、鲁棒性好、可靠性高的控制器。基于上述Genlock的精度问题，在本可选实施例中，通过加入PID控制器所采用的控制算法，让视频处理设备通过控制算法的计 算结果来调节PCLK的频率，从而达到硬件的最佳锁定状态。通过加入PID控制器的控制算法，可进一步地提高Genlock的精度。
作为一种可选的实施例，通过PID控制器确定相位差对应的相位调整值时，可以采用以下方式：整定PID控制器的控制系数，其中，控制系数包括：比例系数，积分系数和微分系数；通过整定系数后的PID控制器确定相位差对应的相位调整值。整定PID控制器的控制系数，可以平衡收敛速度和过冲幅度，得到算法的核心计算公式。通过整定系数后的PID控制器确定相位差对应的相位调整值，得到精确的相位调整值，为后续得到精确的目标像素时钟频率提供基础。
作为一种可选的实施例，在通过比例积分微分PID控制器确定相位差对应的相位调整值时，可以采用以下方式确定相位差对应的相位调整值：
incr_phase＝KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase)；其中，fresh_phase为相位差，total_phase为统计的历史调整次数内fresh_phase的累积和，last_phase为此次调整的上一次调整的相位差，incr_phase为相位调整值，KP为比例系数，KI为积分系数，KD为微分系数。
作为一种可选的实施例，根据相位调整值，得到目标像素时钟频率时，依据得到目标像素时钟频率的方式不同，所采用的参数也可以不同。
例如，可以采用以下方式得到目标像素时钟频率：先根据相位调整值，得到频率调整值；之后，根据频率调整值，得到目标像素时钟频率。需要说明的是，由于相位调整值有正负，即表征输出VS相对于参考VS是相位超前还是滞后；所以频率调整值也对应有正负，即在视频信号的当前像素时钟频率的基础上加上还是减去该频率调整值对应的数值。
又例如，还可以采用以下方式得到目标像素时钟频率：先确定相位调整值占N个帧周期的百分比，其中，N为正整数；根据视频信号的当前像素时钟频率，以及百分比，确定目标像素时钟频率。其中，N个帧周期表征视频信号的输出VS的当前相位值。需要说明的是，上述所指的相位调整值以及N个帧周期可以采用单位统一的时间表示，例如，均可以采用秒表示，或者均可以采用纳秒表示。
作为一种可选的实施例，在根据视频信号的当前像素时钟频率，以及百分比，确定目标像素时钟频率时，通过以下方式，确定相位调整值占N个帧周期的百分比：incr_freq_percent＝incr_phase/gen_vs_T，其中，incr_freq_percent为百分比，incr_phase为相位调整值，gen_vs_T为N个帧周期。如上述，该incr_phase和gen_vs_phase可以采用单位统一的时间表示，当单位不统一时，可以在上述公式中加入一个公式 转换的数值，例如，当gen_vs_T的单位为秒，而incr_phase的单位为纳秒时，可以将gen_vs_T乘以10的9次方，得到gen_vs_T的单位为纳秒的数值，而后依据公式计算百分比。
在确定上述百分比之后，要确定目标像素时钟频率时，可以通过以下方式，根据视频信号的当前像素时钟频率，以及百分比，确定目标像素时钟频率：fresh_freq＝last_freq*(1+incr_freq_percent)，其中，fresh_freq为目标像素时钟频率，last_freq为当前像素时钟频率。
需要指出的是，上述通过频率调整值得到目标像素时钟频率的方式，和通过当前像素时钟频率，以及百分比，确定目标像素时钟频率的方式，可以根据需要灵活选择，但不管采用上述哪种方式，均有效地利用了相位与频率之间的关系，实现了将相位调整转化为了频率调整，从而能够方便，准确地为后续的时钟生成器配置像素时钟频率。
作为一种可选的实施例，获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差可以采用多种方式，例如，可以接收可编辑逻辑门阵列FPGA芯片发送的相位差；或者，通过鉴相器接收第一输出VS与参考VS，并获得第一输出VS和参考VS之间的相位差。通过上述处理，第一输出VS与参考VS的相位差可以直接由FPGA芯片得到，也可以直接由鉴相器得到，或者还可以由FPGA芯片和鉴相器两者结合得到(例如，鉴相器集成于FPGA芯片中的情况)。
作为一种可选的实施例，在根据频率调整值，得到目标像素时钟频率之后，还包括：根据目标像素时钟频率生成配置信息；向时钟芯片发送配置信息，其中，配置信息用于配置时钟芯片根据目标像素时钟频率生成目标像素时钟。通过上述处理，实现了将目标像素时钟频率配置给时钟芯片，用于时钟芯片根据该目标像素时钟频率生成目标像素时钟。
作为一种可选的实施例，在向时钟芯片发送配置信息之后，还包括：向时序生成器发送视频信号的时序参数，其中，时序参数用于与时钟芯片生成的目标像素时钟结合后，由时序生成器生成第二输出VS。通过上述处理，实现了将视频信号的时序参数发送给时序生成器，用于时序生成器基于时钟芯片生成的目标像素时钟和该时序参数，生成第二输出VS，从而完成一次输出VS与参考VS同步的调节过程。
作为一种可选的实施例，可以按照帧周期，重复执行从获取视频信号的第一输出VS与参考VS之间的相位差至得到目标像素时钟频率的操作，即以一帧的时间为周期来进行一次输出VS与参考VS同步的调节，从而实现高精度的帧同步。
作为一种可选的实施例，在获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差之前，还包括：确定参考VS的周期波动是否小于预定的波动阈值；在检测结果为是的情况下，确定执行获取视频信号的第一输出VS与参考VS之间的相位差的操作；和/或，在检测结果为否的情况下，返回确定参考VS的周期波动是否小于预定的波动阈值的操作。
需要说明的是，参考VS对应的预定的波动阈值可以依据参考VS的不同而设置得不同。通过设定一个波动阈值，可以用于表征参考VS的稳定性。VS越稳定，用于实现输出VS与参考VS之间的同步也较为精确。例如，可以将上述波动阈值设置周期波动相对于参考VS的整个统计周期的百分比，比如，当参考VS的波动小于该波动阈值30％时，则认为该参考VS是稳定的，可以作为用于同步输出VS的参考。
基于上述实施例及可选实施例，下面对本发明的一种可选实施方式进行说明。
图9是根据本发明可选实施方式的用于实现信号处理方法的信号处理设备的示意图。可选地，该信号处理设备可以是视频处理设备，其中，该视频处理设备可以包括：视频处理器、视频切换器或视频拼接器等用于进行视频处理或控制的设备。如图9所示，该信号处理设备可以包括如下部分：时钟芯片6208，MCU，FPGA芯片(其中，该FPGA芯片可以集成有时序生成器和鉴相器)，下面对该信号处理设置进行说明。
时钟芯片6208，用于产生控制系统期望频率的时钟源，即用于接收MCU的配置信息，根据配置信息配置的像素时钟频率生成像素时钟；MCU，用于配置时钟芯片6208和运行控制算法；FPGA芯片，包括时序生成器和鉴相器，其中，时序生成器用于根据像素时钟(gen_clk)与时序参数(Timing_para)生成视频信号的输出时序(Timing_gen)，鉴相器(phase_det)，用于接收视频信号的输出VS和参考VS，从而将输出VS和参考VS之间的相位差(phase_error)输出，并将phase_error推送给MCU，作为控制算法的输入参数。
需要说明的是，上述MCU是为了更方便的配置时钟芯片和控制算法的运行，也可以把MCU替换成其他的主控器件，例如，数据信号处理器(Digital Signal Processor，简称为DSP)，个人计算机(Personal Computer，简称为PC)，甚至直接放到FPGA里面做主控。
图10是根据本发明可选实施方式的信号处理方法的示意图，如图10所示，该方法包括如下步骤：
步骤1)开启Genlock功能；
步骤2)从FPGA芯片获取参考VS周期；
步骤3)根据当前分辨率，计算像素时钟(PCLK)频率，并将PCLK频率通过配置信息配置给时钟芯片；
步骤4)从FPGA芯片确定PCLK稳定，开启FPGA芯片的相位检测，即通过FPGA芯片中的鉴相器实现对输出VS和参考VS的相位差的检测；
步骤5)MCU收到中断后，从FPGA芯片中读取相位差计数和参考VS周期；
步骤6)判断参考VS周期波动是否小于30％，如果判断为是，进入步骤7)，如果判断为否，进入步骤2)；
步骤7)执行自动调节算法，配置目标像素时钟频率；
步骤8)一次调节结束，等待下一次中断到来，当下一次中断到来时，进入步骤5)。
根据PID控制器的控制逻辑，本发明可选实施方式的调节算法如下：
incr_phase＝KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase)；
其中，fresh_phase为每次中断后获取的最新的相位差值计数*FPGA采用时钟周期(sample_t)，即上述的相位差，单位ns。
total_phase为每次收到的fresh_phase累积和，即上述所指的统计的历史调整次数内fresh_phase的累积和。
last_phase为上一次的fresh_phase(即此次调整的上一次调整的相位差)。
incr_phase为需要调节的相位值(即上述所指的相位调整值)。
通过平衡收敛速度和过冲幅度，整定三个调节系数：KP、KI、KD，即可得到控制算法的上述计算公式。
计算出需要调节的相位值之后，需要转换到时钟芯片6208的频率值(即目标像素时钟频率)，根据时钟和相位的关系，经过推演，得到相位和频率调节的关系如下：
可以采用以下方式由调节相位值计算频率调节百分比：
incr_freq_percent＝incr_phase/(gen_vs_T*1 000 000 000)，需要说明的是，此 处乘以10的9次方是因为gen_vs_T的单位是秒，而incr_phase的单位是纳秒，为了实现统一，将gen_vs_T的单位转换到了ns。last_freq为上一次配置的频率值(即上述的当前像素时钟频率)，单位hz。
最后，得到需要配置给时钟芯片的频率值(即上述的目标像素时钟频率)：
fresh_freq＝last_freq*(1+incr_freq_percent)
将新的频率值(即该目标像素时钟频率)配置给时钟芯片，完成一次调节过程。
微处理器MCU等待FPGA芯片发起下一次中断，然后重复上述步骤，随着多次的计算处理，算法本身的特性会不断的将Gen_VS逼近参考VS(ref_VS)，达到高精度的Genlock锁定。
通过上述可选实施例，实现了视频输出VS对参考VS的快速锁定收敛，从而实现输出VS与参考VS的高精度同步。经过实测，可以将目前的10us的跟随误差降低至150ns，提高了60倍。而这个误差是由于时钟芯片的精度和鉴相器的鉴相频率决定的，在不更换硬件的情况下，该可选实施方式可以使Genlock的精度推至硬件能够达到的极限，得到很好的性能。
实施例2
根据本发明实施例，还提供了一种信号处理装置，图11是根据本发明实施例2的信号处理装置的结构框图，如图11所示，该信号处理装置1100包括：获取模块1102，确定模块1104和处理模块1106。下面对该信号处理装置1100进行具体说明。
获取模块1102，用于获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差；
确定模块1104，连接于上述获取模块1102，用于根据相位差确定相位调整值；
处理模块1106，连接于上述确定模块1104，用于根据相位调整值，得到目标像素时钟频率，其中，目标像素时钟频率用于生成视频信号的第二输出VS。
此处需要说明的是，上述获取模块1102，确定模块1104和处理模块1106，对应于实施例1中的步骤S402至步骤S406，上述模块与对应的步骤所实现的实例和应用场景相同，但不限于上述实施例1所公开的内容。需要说明的是，上述模块作为装置的一部分可以运行在实施例1提供的计算机终端中。
根据本发明实施例，还提供了一种信号处理设备，该信号处理设备包括第一处理器，第一处理器用于运行程序，其中，程序运行时执行上述实施例1中的实施例 或可选实施例中所提供的任意一项信号处理方法。需要说明的是，该第一处理器的类型可以是多种，例如，可以是上述所描述的MCU，或者ARM等。
作为一种可选的实施例，上述信号处理设备，还包括：第二处理器，其中，该第二处理器用于确定视频信号的第一输出VS与参考VS之间的相位差，并将相位差发送给第一处理器。需要说明的是，上述第一处理器和第二处理器可以是同一个处理器，也可以是两个不同的处理器。例如，当第一处理器和第二处理器为不同的处理器时，该第一处理器可以是上述的MCU，该第二处理器可以是现场可编程逻辑门阵列FPGA芯片等。
作为一种可选的实施例，第二处理器可以包括：鉴相器和时序生成器，其中，鉴相器，用于接收第一输出VS与参考VS的输入，并输出第一输出VS和参考VS之间的相位差；时序生成器，用于接收处理器发送的视频信号的时序参数，并根据时序参数和时钟芯片生成的目标像素时钟生成第二输出VS。
作为一种可选的实施例，上述信号处理设备还可以包括：时钟芯片，其中，时钟芯片，用于接收第一处理器发送的配置信息，其中，配置信息由第一处理器依据目标像素时钟频率生成；时钟芯片，还用于依据配置信息配置的目标像素时钟频率生成目标像素时钟。
实施例3
根据本发明实施例，还提供了一种存储介质。可选地，在本实施例中，上述存储介质可以用于保存上述实施例1所提供的信号处理方法所执行的程序代码。
可选地，在本实施例中，上述存储介质可以位于计算机网络中计算机终端群中的任意一个计算机终端中，或者位于移动终端群中的任意一个移动终端中。
可选地，在本实施例中，存储介质被设置为存储用于执行以下步骤的程序代码：获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差；根据相位差确定相位调整值；根据相位调整值，得到目标像素时钟频率，其中，目标像素时钟频率用于生成视频信号的第二输出VS。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代码：根据相位差确定相位调整值，包括：通过比例积分微分PID控制器确定相位差对应的相位调整值。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代码：通过PID控制器确定相位差对应的相位调整值，包括：整定PID控制器的控制系数，其中，控制系数包括：比例系数，积分系数和微分系数；通过整定系数后的 PID控制器确定相位差对应的相位调整值。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代码：通过比例积分微分PID控制器确定相位差对应的相位调整值，包括：通过以下方式确定相位差对应的相位调整值：
incr_phase＝KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase)；其中，fresh_phase为相位差，total_phase为统计的历史调整次数内fresh_phase的累积和，last_phase为此次调整的上一次调整的相位差，incr_phase为相位调整值，KP为比例系数，KI为积分系数，KD为微分系数。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代码：根据相位调整值，确定频率调整值；根据频率调整值，得到目标像素时钟频率。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代码：根据相位调整值，得到目标像素时钟频率，包括：确定相位调整值占N个帧周期的百分比，其中，N为正整数；根据视频信号的当前像素时钟频率，以及百分比，确定目标像素时钟频率。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代码：通过以下方式，确定相位调整值占N个帧周期的百分比：incr_freq_percent＝incr_phase/gen_vs_T，其中，incr_freq_percent为百分比，incr_phase为相位调整值，gen_vs_T为N个帧周期。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代码：通过以下方式，根据视频信号的当前像素时钟频率，以及百分比，确定目标像素时钟频率：fresh_freq＝last_freq*(1+incr_freq_percent)，其中，fresh_freq为目标像素时钟频率，last_freq为当前像素时钟频率。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代码：获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差，包括：接收可编辑逻辑门阵列FPGA芯片发送的相位差；或者，通过鉴相器接收第一输出VS与参考VS，并获得第一输出VS和参考VS之间的相位差。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代码：在根据频率调整值，得到目标像素时钟频率之后，还包括：根据目标像素时钟频率生成配置信息；向时钟芯片发送配置信息，其中，配置信息用于配置时钟芯片根据目标像素时钟频率生成目标像素时钟。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代 码：在向时钟芯片发送配置信息之后，还包括：向时序生成器发送视频信号的时序参数，其中，时序参数用于与时钟芯片生成的目标像素时钟结合后，由时序生成器生成第二输出VS。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代码：按照帧周期，重复执行从获取视频信号的第一输出VS与参考VS之间的相位差至得到目标像素时钟频率的操作。
可选地，在本实施例中，存储介质还被设置为存储用于执行以下步骤的程序代码：在获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差之前，还包括：确定参考VS的周期波动是否小于预定的波动阈值；在检测结果为是的情况下，确定执行获取视频信号的第一输出VS与参考VS之间的相位差的操作；和/或，在检测结果为否的情况下，返回确定参考VS的周期波动是否小于预定的波动阈值的操作。
实施例4
本发明的实施例可以提供一种计算机终端，该计算机终端可以是计算机终端群中的任意一个计算机终端设备。可选地，在本实施例中，上述计算机终端也可以替换为移动终端等终端设备。
可选地，在本实施例中，上述计算机终端可以位于计算机网络的多个网络设备中的至少一个网络设备。
在本实施例中，上述计算机终端可以执行应用程序的信号处理方法中以下步骤的程序代码：获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差；根据相位差确定相位调整值；根据相位调整值，得到目标像素时钟频率，其中，目标像素时钟频率用于生成视频信号的第二输出VS。
可选地，图12是根据本发明实施例的一种计算机终端的结构框图。如图12所示，该计算机终端可以包括：一个或多个(图中仅示出一个)第三处理器1202、存储器1204等。
其中，存储器1204可用于存储软件程序以及模块，如本发明实施例中的信号处理方法和装置对应的程序指令/模块，第三处理器1202通过运行存储在存储器内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的物联网测试方法。存储器可包括高速随机存储器，还可以包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器可进一步包括相对于第三处理器远程设置的存储器，这些远程存储器可以通过网络 连接至计算机终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
第三处理器可以通过传输装置调用存储器存储的信息及应用程序，以执行下述步骤：获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差；根据相位差确定相位调整值；根据相位调整值，得到目标像素时钟频率，其中，目标像素时钟频率用于生成视频信号的第二输出VS。
可选的，上述第三处理器还可以执行如下步骤的程序代码：根据相位差确定相位调整值，包括：通过比例积分微分PID控制器确定相位差对应的相位调整值。
可选的，上述第三处理器还可以执行如下步骤的程序代码：通过PID控制器确定相位差对应的相位调整值，包括：整定PID控制器的控制系数，其中，控制系数包括：比例系数，积分系数和微分系数；通过整定系数后的PID控制器确定相位差对应的相位调整值。
可选的，上述第三处理器还可以执行如下步骤的程序代码：通过比例积分微分PID控制器确定相位差对应的相位调整值，包括：通过以下方式确定相位差对应的相位调整值：
incr_phase＝KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase)；其中，fresh_phase为相位差，total_phase为统计的历史调整次数内fresh_phase的累积和，last_phase为此次调整的上一次调整的相位差，incr_phase为相位调整值，KP为比例系数，KI为积分系数，KD为微分系数。
可选的，上述第三处理器还可以执行如下步骤的程序代码：根据相位调整值，确定频率调整值；根据频率调整值，得到目标像素时钟频率。
可选的，上述第三处理器还可以执行如下步骤的程序代码：根据相位调整值，得到目标像素时钟频率，包括：确定相位调整值占N个帧周期的百分比，其中，N为正整数；根据视频信号的当前像素时钟频率，以及百分比，确定目标像素时钟频率。
可选的，上述第三处理器还可以执行如下步骤的程序代码：通过以下方式，确定相位调整值占N个帧周期的百分比：incr_freq_percent＝incr_phase/gen_vs_T，其中，incr_freq_percent为百分比，incr_phase为相位调整值，gen_vs_T为N个帧周期。
可选的，上述第三处理器还可以执行如下步骤的程序代码：通过以下方式，根据视频信号的当前像素时钟频率，以及百分比，确定目标像素时钟频率：fresh_freq＝last_freq*(1+incr_freq_percent)，其中，fresh_freq为目标像素时钟频率，last_freq 为当前像素时钟频率。
可选的，上述第三处理器还可以执行如下步骤的程序代码：获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差，包括：接收可编辑逻辑门阵列FPGA芯片发送的相位差；或者，通过鉴相器接收第一输出VS与参考VS，并获得第一输出VS和参考VS之间的相位差。
可选的，上述第三处理器还可以执行如下步骤的程序代码：在根据频率调整值，得到目标像素时钟频率之后，还包括：根据目标像素时钟频率生成配置信息；向时钟芯片发送配置信息，其中，配置信息用于配置时钟芯片根据目标像素时钟频率生成目标像素时钟。
可选的，上述第三处理器还可以执行如下步骤的程序代码：在向时钟芯片发送配置信息之后，还包括：向时序生成器发送视频信号的时序参数，其中，时序参数用于与时钟芯片生成的目标像素时钟结合后，由时序生成器生成第二输出VS。
可选的，上述第三处理器还可以执行如下步骤的程序代码：按照帧周期，重复执行从获取视频信号的第一输出VS与参考VS之间的相位差至得到目标像素时钟频率的操作。
可选的，上述第三处理器还可以执行如下步骤的程序代码：在获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差之前，还包括：确定参考VS的周期波动是否小于预定的波动阈值；在检测结果为是的情况下，确定执行获取视频信号的第一输出VS与参考VS之间的相位差的操作；和/或，在检测结果为否的情况下，返回确定参考VS的周期波动是否小于预定的波动阈值的操作。
上述本发明实施例序号仅仅为了描述，不代表实施例的优劣。
在本发明的上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的技术内容，可通过其它的方式实现。其中，以上所描述的装置实施例仅仅是示意性的，例如所述单元的划分，可以为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，单元或模块的间接耦合或通信连接，可以是电性或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分 布到多个单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (20)

  1. 一种信号处理方法，其特征在于，包括：
    获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差；
    根据所述相位差确定相位调整值；
    根据所述相位调整值，得到目标像素时钟频率，其中，所述目标像素时钟频率用于生成所述视频信号的第二输出VS。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述相位差确定相位调整值，包括：
    通过比例积分微分PID控制器确定所述相位差对应的相位调整值。
  3. 根据权利要求2所述的方法，其特征在于，所述通过PID控制器确定所述相位差对应的相位调整值，包括：
    整定所述PID控制器的控制系数，其中，所述控制系数包括：比例系数，积分系数和微分系数；
    通过整定系数后的PID控制器确定所述相位差对应的相位调整值。
  4. 根据权利要求2或3所述的方法，其特征在于，所述通过比例积分微分PID控制器确定所述相位差对应的相位调整值，包括：
    通过以下方式确定所述相位差对应的相位调整值：
    incr_phase＝KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase)；
    其中，fresh_phase为所述相位差，total_phase为统计的历史调整次数内fresh_phase的累积和，last_phase为此次调整的上一次调整的相位差，incr_phase为所述相位调整值，KP为所述比例系数，KI为所述积分系数，KD为所述微分系数。
  5. 根据权利要求1所述的方法，其特征在于，所述根据所述相位调整值，得到目标像素时钟频率，包括：
    根据所述相位调整值，确定频率调整值；
    根据所述频率调整值，得到所述目标像素时钟频率。
  6. 根据权利要求1所述的方法，其特征在于，所述根据所述相位调整值，得到目 标像素时钟频率，包括：
    确定所述相位调整值占N个帧周期的百分比，其中，N为正整数；
    根据所述视频信号的当前像素时钟频率，以及所述百分比，确定所述目标像素时钟频率。
  7. 根据权利要求6所述的方法，其特征在于，通过以下方式，确定所述相位调整值占N个帧周期的百分比：
    incr_freq_percent＝incr_phase/gen_vs_T，
    其中，incr_freq_percent为所述百分比，incr_phase为所述相位调整值，gen_vs_T为所述N个帧周期。
  8. 根据权利要求7所述的方法，其特征在于，通过以下方式，根据所述视频信号的当前像素时钟频率，以及所述百分比，确定所述目标像素时钟频率：
    fresh_freq＝last_freq*(1+incr_freq_percent)，
    其中，fresh_freq为所述目标像素时钟频率，last_freq为所述当前像素时钟频率。
  9. 根据权利要求1所述的方法，其特征在于，所述获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差，包括：
    接收可编辑逻辑门阵列FPGA芯片发送的所述相位差；或
    通过鉴相器接收所述第一输出VS与所述参考VS，并获得所述第一输出VS和所述参考VS之间的所述相位差。
  10. 根据权利要求1所述的方法，其特征在于，在所述根据所述频率调整值，得到目标像素时钟频率之后，还包括：
    根据所述目标像素时钟频率生成配置信息；
    向时钟芯片发送所述配置信息，其中，所述配置信息用于配置所述时钟芯片根据所述目标像素时钟频率生成目标像素时钟。
  11. 根据权利要求10所述的方法，其特征在于，在所述向所述时钟芯片发送所述配置信息之后，还包括：
    向时序生成器发送所述视频信号的时序参数，其中，所述时序参数用于与所述时钟芯片生成的目标像素时钟结合后，由所述时序生成器生成所述第二输 出VS。
  12. 根据权利要求1至11中任一项所述的方法，其特征在于，按照帧周期，重复执行从获取视频信号的第一输出VS与参考VS之间的相位差至得到目标像素时钟频率的操作。
  13. 根据权利要求12所述的方法，其特征在于，在所述获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差之前，还包括：
    确定所述参考VS的周期波动是否小于预定的波动阈值；
    在检测结果为是的情况下，确定执行获取所述视频信号的第一输出VS与所述参考VS之间的所述相位差的操作；和/或，在检测结果为否的情况下，返回确定所述参考VS的周期波动是否小于预定的波动阈值的操作。
  14. 一种信号处理装置，其特征在于，包括：
    获取模块，用于获取视频信号的第一输出场同步信号VS与参考场同步信号VS之间的相位差；
    确定模块，用于根据所述相位差确定相位调整值；
    处理模块，用于根据所述相位调整值，得到目标像素时钟频率，其中，所述目标像素时钟频率用于生成所述视频信号的第二输出VS。
  15. 一种信号处理设备，其特征在于，包括：第一处理器，所述第一处理器用于运行程序，其中，所述程序运行时执行权利要求1至13中任意一项所述信号处理方法。
  16. 根据权利要求15所述的设备，其特征在于，所述设备还包括：第二处理器，其中，所述第二处理器用于确定所述视频信号的所述第一输出VS与所述参考VS之间的所述相位差，并将所述相位差发送给所述第一处理器。
  17. 根据权利要求16所述的设备，其特征在于，所述第二处理器包括：鉴相器和时序生成器，其中，
    所述鉴相器，用于接收所述第一输出VS与所述参考VS的输入，并输出所述第一输出VS和所述参考VS之间的所述相位差；
    所述时序生成器，用于接收所述处理器发送的所述视频信号的时序参数，并根据所述时序参数和时钟芯片生成的目标像素时钟生成所述第二输出VS。
  18. 根据权利要求17所述的设备，其特征在于，所述设备还包括：所述时钟芯片，其中，所述时钟芯片，用于接收所述第一处理器发送的配置信息，其中，所述配置信息由所述第一处理器依据所述目标像素时钟频率生成；所述时钟芯片，还用于依据所述配置信息配置的目标像素时钟频率生成目标像素时钟。
  19. 一种存储介质，其特征在于，所述存储介质包括存储的程序，其中，在所述程序运行时控制所述存储介质所在设备执行权利要求1至13中任意一项所述的信号处理方法。
  20. 一种计算机设备，其特征在于，包括：存储器和第三处理器，
    所述存储器存储有计算机程序；
    所述第三处理器，用于执行所述存储器中存储的计算机程序，所述计算机程序运行时使得所述第三处理器执行权利要求1至13中任意一项所述的信号处理方法。
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