WO2022089542A1 - 一种印制电路板及背板架构系统、通信设备 - Google Patents

一种印制电路板及背板架构系统、通信设备 Download PDF

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Publication number
WO2022089542A1
WO2022089542A1 PCT/CN2021/127092 CN2021127092W WO2022089542A1 WO 2022089542 A1 WO2022089542 A1 WO 2022089542A1 CN 2021127092 W CN2021127092 W CN 2021127092W WO 2022089542 A1 WO2022089542 A1 WO 2022089542A1
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Prior art keywords
hole
ground
printed circuit
circuit board
main
Prior art date
Application number
PCT/CN2021/127092
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English (en)
French (fr)
Inventor
李文亮
陈永炜
刘旭升
颜忠
汪泽文
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CA3196898A priority Critical patent/CA3196898A1/en
Priority to EP21885269.7A priority patent/EP4221468A4/en
Priority to KR1020237016582A priority patent/KR20230088464A/ko
Priority to JP2023524290A priority patent/JP2023551095A/ja
Publication of WO2022089542A1 publication Critical patent/WO2022089542A1/zh
Priority to US18/308,267 priority patent/US20230269862A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H05K1/0225—Single or multiple openings in a shielding, ground or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/14—Mounting supporting structure in casing or on frame or rack
    • H05K7/1438—Back panels or connecting means therefor; Terminals; Coding means to avoid wrong insertion
    • H05K7/1452—Mounting of connectors; Switching; Reinforcing of back panels
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09618—Via fence, i.e. one-dimensional array of vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09718—Clearance holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10189—Non-printed connector

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a printed circuit board and a backplane architecture system, and communication equipment.
  • a printed circuit board is usually used as the carrier of each electronic component, and at the same time, each component is interconnected through the traces of the printed circuit board.
  • the components are mainly connected to the printed circuit board by crimping and welding to form stable electrical and mechanical connections.
  • solder ball pins of chips with ball grid array (BGA) package are connected to the array pads on the printed circuit board, and the crimped fisheye pins of the high-speed connector are connected to the array pressure pads on the printed circuit board. Take the hole connection.
  • BGA ball grid array
  • the spacing between the pin pads is very close, and the minimum chip pad can reach about 0.4mm.
  • the order of magnitude, for the connector crimping pin pad the minimum can reach the order of magnitude of about 1.1mm.
  • the present application provides a printed circuit board, a backplane architecture system, and a communication device, which are used to improve the crosstalk problem of the backplane architecture system and improve the signal transmission effect.
  • a printed circuit board is provided, the printed circuit board is applied to a backplane architecture system, the printed circuit board includes a plurality of layer structures arranged in layers, and the plurality of layer structures are respectively different functional layers,
  • the multiple layer structure includes alternately arranged ground layers and trace layers.
  • the printed circuit board is provided with a setting surface matched with other devices, and the setting surface is a surface of the layer structure located at the outermost layer among the multiple layer structures.
  • the setting surface is provided with a differential pair unit and a shielding structure for shielding the differential pair unit.
  • the differential pair unit includes two signal vias, and each signal via passes through at least part of the ground layer and the wiring layer, and is connected to the wiring on one of the wiring layers.
  • the ground layer through which each signal via hole passes is provided with an anti-pad corresponding to the signal via hole, so as to prevent the signal via hole from being grounded.
  • the anti-pads corresponding to the two signal vias are arranged at intervals, and a part of the metal of the ground layer is spaced between the two anti-pads.
  • the above shielding structure includes two main ground holes and a first auxiliary ground hole arranged on the setting surface, wherein the two main ground holes are located on both sides of the differential pair unit, and the first auxiliary ground hole is located between the two signal vias.
  • the main grounding hole and the first auxiliary grounding hole respectively pass through part of the wiring layer and the grounding layer, and the main grounding hole and the first auxiliary grounding hole are respectively grounded and connected to the grounding layer passed through.
  • each signal corresponds to an anti-pad, and the ground layer is spaced between the anti-pads, thereby reducing the interference of the trace after the signal of the signal via or the interlayer trace passes through the anti-pad, Improves crosstalk issues within printed circuit boards.
  • the shielding structure is formed by the main grounding hole and the first auxiliary grounding hole, which reduces the crosstalk between the differential pair unit and other differential pair units, improves the crosstalk problem of the printed circuit board, and facilitates the connection of the jacks on the printed circuit board. Dense settings.
  • the traces of the trace layers on both sides of the first ground layer are located outside the anti-pad of the first ground layer; wherein, the first ground layer is each of the The ground plane through which the signal vias pass.
  • the anti-pads have different shapes such as circle, square, oval, etc., so that different anti-pads can improve the crosstalk between lines.
  • the anti-pad is circular, and the anti-pad is coaxial with the corresponding signal via, which further reduces the area of the anti-pad and improves the relationship between the signal via and the trace. It also improves the crosstalk between traces and traces.
  • the number of the differential pair units is multiple, and the main ground holes between adjacent differential pair units are shared. Reduced the number of main ground holes.
  • the width of each main ground hole in the first direction is greater than the width of each signal via hole in the first direction; the first direction is parallel to the setting surface, and a direction perpendicular to the arrangement direction of the two signal vias. Improve the shielding effect of signal vias.
  • each main grounding hole includes a main hole and at least one slave hole surrounding the main hole; wherein the main hole is in communication with and conductively connected with each of the slave holes.
  • the shielding effect of the signal via hole is improved by the cooperation of the main hole and the slave hole.
  • each main grounding hole includes two main holes, and a slave hole located between the two main holes; wherein, the slave holes communicate with the two main holes respectively and Conductive connection.
  • the shielding effect of the signal via hole is improved by the cooperation of the main hole and the slave hole.
  • the main hole can be a circular, square, oval or other via hole in different shapes.
  • the slave holes can be via holes of different shapes such as round, square, and oval.
  • the two main ground holes and the first auxiliary ground hole form a C-shaped shielding structure surrounding the differential pair unit.
  • the main grounding hole and the first auxiliary grounding hole form a C-shape to wrap the differential pair unit, so as to improve the shielding effect of the differential pair unit.
  • the main ground hole when the main ground hole includes a main hole and at least one slave hole surrounding the main hole, the connection line between the center points of the two main ground holes and the two signals pass through.
  • the center points of the holes overlap. It is convenient to arrange and set the main grounding hole.
  • the center point of the first auxiliary ground hole is located on one side of the line connecting the center points of the two signal vias. It is convenient to form a C-shaped shielding structure.
  • the number of the first auxiliary ground holes is two, and the center points of the two first auxiliary ground holes are respectively located on the line connecting the center points of the two signal via holes on both sides.
  • the shielding effect on the differential pair unit is improved.
  • the shielding structure further includes a second auxiliary ground hole disposed between the main ground hole and an adjacent signal via hole. The shielding effect of the formed shielding structure on the differential pair unit is further improved.
  • a backplane architecture system in a second aspect, includes a backplane and a connector connected to the backplane; wherein the backplane is the printed circuit board described in any one of the above.
  • each signal corresponds to an anti-pad, and the ground layer is spaced between the anti-pads, thereby reducing the interference of the trace after the signal of the signal via or the interlayer trace passes through the anti-pad, Improves crosstalk issues within printed circuit boards.
  • the shielding structure is formed by the main grounding hole and the first auxiliary grounding hole, which reduces the crosstalk between the differential pair unit and other differential pair units, improves the crosstalk problem of the printed circuit board, and facilitates the connection of the jacks on the printed circuit board. Dense settings.
  • a communication device in a third aspect, includes a machine frame and the printed circuit board according to any one of the above, wherein the printed circuit board is inserted into the machine frame.
  • each signal corresponds to an anti-pad
  • the ground layer is spaced between the anti-pads, thereby reducing the interference of the trace after the signal of the signal via or the interlayer trace passes through the anti-pad, Improves crosstalk issues within printed circuit boards.
  • the shielding structure is formed by the main grounding hole and the first auxiliary grounding hole, which reduces the crosstalk between the differential pair unit and other differential pair units, improves the crosstalk problem of the printed circuit board, and facilitates the connection of the jacks on the printed circuit board. Dense settings.
  • FIG. 1 is an exploded schematic diagram of a backplane architecture system
  • FIG. 2 is a schematic diagram of a scenario where a chip and a printed circuit board are connected;
  • FIG. 3 is a schematic structural diagram of a printed circuit board provided by an embodiment of the present application.
  • Fig. 4 is the schematic diagram of the setting surface of the printed circuit board
  • FIG. 5 is a schematic structural diagram of a main ground hole provided in an embodiment of the present application.
  • FIG. 6 is an anti-pad setting method of a ground layer provided by an embodiment of the present application.
  • FIG. 7 is a shielding structure formed by a main ground hole and an auxiliary ground hole provided in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of crosstalk between different differential pair units according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of the locations where the hole-line coupled crosstalk and the line-to-line coupled crosstalk occur according to an embodiment of the present application.
  • FIG. 10 is another schematic diagram of a printed circuit board provided by an embodiment of the application.
  • FIG. 11 is a schematic diagram of the arrangement of differential pair units according to an embodiment of the present application.
  • FIG. 12 is a differential pair unit and a corresponding shielding structure provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of another shielding structure provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of the arrangement of via holes and grounding holes of the printed circuit board matched with the chip
  • FIG. 15 is a three-dimensional schematic view of the printed circuit board shown in FIG. 14 .
  • Crosstalk refers to the coupling effect of unwanted signals passing from one network to another.
  • Anti-pad In the connector packaging area, except for the signal wiring layer, the layers in the printed circuit board are usually the power supply layer and the ground plane layer. These plane layers are actually a metal layer. Vias, via pads of various layers, package pads, etc., need to hollow out the plane metal layer (power layer plane, ground plane layer) to avoid short circuit between different network contacts. The hollowed area of these metal layers is called For the anti-pad (Anti-Pad).
  • Ground hole refers to the via hole through which the signal return current passes, and is the reference of the signal via hole (the current is a closed loop).
  • Signal vias refers to the vias through which data signals pass.
  • the package in the embodiments of this application refers to the arrangement of pads and via holes in which the printed circuit board is matched with the corresponding pins of devices such as chips and connectors.
  • Differential signal Different from the single-ended signal that needs to use one wire to transmit the signal between the transmitter and the receiver, the differential signal needs to use two wires to transmit the signal, and the signals on the two wires are the same in size and opposite in polarity.
  • the final sampled signal is half of the difference between the two wires; a pair of traces or vias that form a differential signal transmission path is often referred to as a differential pair.
  • SerDes is the abbreviation of English Serializer (serializer)/Deserializer (deserializer), that is, multi-channel low-speed parallel signals are converted into high-speed serial signals at the sending end, and the high-speed serial signals are converted into high-speed serial signals at the receiving end after passing through the transmission medium. Reconvert to low speed parallel signal.
  • the application scenarios of the printed circuit boards provided by the embodiments of the present application are first introduced.
  • the printed circuit boards provided by the embodiments of the present application are applied to equipment of a communication system.
  • FIG. 1 shows an exploded schematic diagram of a backplane architecture system.
  • the backplane architecture system includes a backplane 10 , a male connector 30 , a female connector 40 and a single board 10 .
  • the backplane 10 has a package 50 corresponding to the male connector 30 .
  • the package 50 is a part of the backplane 10 , and is specifically an area formed by a group of regularly arranged via holes and corresponding anti-pad hollows. In a system implementation, some of the vias in the package 50 accommodate the crimp pins 70 of the connector 30, thereby mounting the connector 30 on the backplane 10 and providing electrical connections.
  • the single board 20 has a package 60 corresponding to the female connector 40 , the package 60 is a part of the single board 20 , and the package 60 is specifically a group of regularly arranged via holes and an area formed by hollowing out corresponding anti-pads. In a system implementation, some of the vias in the package 60 accommodate the crimp pins 80 of the connector 40, thereby mounting the connector 60 on the single board 20 and providing electrical interconnection.
  • the printed circuit board provided by the embodiment of the present invention can be either a single board in a backplane architecture system, or a backplane.
  • FIG. 2 shows a schematic diagram of a connection between the chip 100 and the printed circuit board 200 , wherein the chip 100 has solder ball pins 101 , and the printed circuit board 200 is provided with a package 201 corresponding to the chip solder balls 101 .
  • the package 201 is specifically a combination of surface pads corresponding to the solder ball pins of the chip package and vias, inner layer wirings and anti-pads that are connected to the surface pads in the adjacent area to realize the wiring change layer and outlet.
  • part of the surface pads in the package 201 are connected to the solder ball pins 101 of the chip 100, so that the chip 100 is mounted and fixed on the printed circuit board 200, and electrical interconnection is provided.
  • the signal when the signal data rate is increased to 90Gbps+, the signal mostly adopts PAM4 (4 Pulse Amplitude Modulation, the fourth generation of pulse amplitude modulation, the fourth generation of pulse amplitude modulation Signal, as a popular signal transmission technology for high-speed signal interconnection in next-generation data centers, is widely used in 200G/400G interface electrical or optical signal transmission) level modulation to ensure increased rates while reducing interconnect bandwidth and even costs. challenge.
  • the voltage pitch of the signal encoded by PAM4 is 1/3 of that of the NRZ (Not Return to Zero) signal, resulting in a loss of 9.5dB in the signal-to-noise ratio.
  • the requirements for noise performance are more stringent when transmitting data through PAM4 encoding. Even though NRZ level modulation is still used, the increased bandwidth due to the rate increase still requires that the noise be restrained in the higher bandwidth. As one of the passive indicators of high-speed signal integrity, crosstalk is more difficult to optimize when the rate is higher, and because the SerDes active circuit has very limited ability to suppress crosstalk, the optimization of crosstalk in high-speed design is also very limited. Usually the top priority. However, when the printed circuit board in the prior art is connected to a chip or a connector, in the high-sealed packaging area of the device, the signal transmission path is transmitted through the signal vias and the vias of each layer inside the printed circuit board.
  • the embodiments of the present application provide a printed circuit board, which is used to improve the crosstalk between vias or between vias and traces when the printed circuit board is in use.
  • FIG. 3 shows a schematic structural diagram of a printed circuit board provided by an embodiment of the present application.
  • a reference coordinate system XYZ is established, wherein the X direction, the Y direction and the Z direction are perpendicular to each other.
  • the three adjacent sides of the printed circuit board are in a one-to-one correspondence with the X direction, the Y direction and the Z direction, respectively.
  • the setting surface of the printed circuit board is defined, and the setting surface is parallel to the XY plane.
  • the setting surface is used for corresponding connection with other devices.
  • the setting surface is the surface on which the single board or the backplane is mated with the connector; the chip shown in FIG. 2 In the system, the setting surface is the surface where the printed circuit board is matched with the chip.
  • the printed circuit board 500 provided by the embodiment of the present application has multiple layer structures, and the multiple layer structures are stacked and arranged along the Z direction.
  • the multiple layer structures may be layer structures with different functions, for example, the multiple layer structures include a wiring layer and a ground layer 505 .
  • the wiring layer is an internal wiring layer of the printed circuit board 500, and the wiring layer is used for arranging the wiring to transmit signals.
  • the ground layer 505 is used as the reference ground plane of the printed circuit board 500 to realize the grounding effect.
  • the ground layer 505 is used as a ground plane used as a reference for traces in the layered structure of the printed circuit board 500, and the ground layer 505 provides a plane return path for signals.
  • the installation surface of the printed circuit board 500 is one surface located at the outermost layer among the above-mentioned multiple layer structures.
  • the outermost layer is the ground layer 505
  • the setting surface is an exposed surface of the grounding layer 505
  • the outermost layer is a wiring layer
  • the setting surface is an exposed surface of the wiring layer.
  • the setting surface of the printed circuit board 500 is provided with a differential pair unit, and the differential pair unit includes two signal vias 501 for transmitting differential signals.
  • the connector is provided with two pairs of crimp pins, and the two signal vias 501 are connected to the two crimp pins in a one-to-one correspondence to transmit paired signals.
  • each signal via hole 501 of the differential pair unit is located on the setting surface, and each signal via hole 501 extends to the inner layer of the printed circuit board 500 along the Z direction.
  • the signal via 501 passes through at least part of the ground layer 505 and the wiring layers, and is connected to the wiring on one of the wiring layers.
  • the two signal vias 501 are respectively connected to two traces located on the same trace layer in a one-to-one correspondence. Through the signal vias 501 and the traces, the transition of the signals from vertically running along the vias to running along the trace plane of the printed circuit board 500 is realized.
  • the inner sidewall of the signal via hole 501 is metallized to have conductivity.
  • the signal via hole 501 needs to accommodate the crimp pins of the connector to complete the reliable electrical connection between the printed circuit board 500 and the connector.
  • the interconnection is also responsible for the vertical (in the Z direction) transmission of the signal to realize the transmission of the signal of the connector to the inner layer trace transmission of the printed circuit board 500 .
  • the signal vias 501 are responsible for interconnecting the chip pads with the inner layer traces of the printed circuit board 500 to realize vertical signal transmission and layer change.
  • the depth of the signal vias 501 is generally less than or equal to the thickness of the printed circuit board 500 , but greater than the depth of the layer where the signal vias 501 are correspondingly connected.
  • the ground layer 505 that each signal via 501 passes through is provided with an anti-pad 504 (not shown in the figure) corresponding to the signal via 501 to avoid signal Via 501 is grounded.
  • FIG. 4 shows a schematic view of the setting surface of the printed circuit board.
  • the spacing between the signal vias 501 set on the printed circuit board is very close.
  • the minimum size of the hole 501 can reach about 0.4mm, and the minimum size of the signal via hole 501 corresponding to the connector can reach about 1.1mm.
  • the signal vias 501 are arranged in an array along the X direction and the Y direction.
  • the printed circuit board provided by the embodiment of the present application is provided with a shielding structure for shielding the differential pair unit on the setting surface.
  • the shielding structure is used to isolate adjacent differential pair units to avoid crosstalk.
  • the differential pair unit that generates interference is named as a disturbed pair
  • the disturbed differential pair unit is named as a disturbed pair.
  • the shielding structure includes two main ground holes 502 and a first auxiliary ground hole 503 on the setting surface, wherein the two main ground holes 502 are located on both sides of the differential pair unit, and the first auxiliary ground hole 503 is located in the two signal vias 501 between.
  • the main ground vias 502 corresponding to each differential pair unit are arranged in a row (along the X direction) with the two signal vias 501 of the differential pair unit.
  • the main ground holes 502 are provided, the main ground holes 502 are arranged on both sides of the differential pair unit along the arrangement direction of the two signal via holes 501 .
  • the first auxiliary ground hole 503 is disposed between the two signal via holes 501 .
  • the two main grounding holes 502 and the first auxiliary grounding hole 503 form a "C"-shaped shielding structure surrounding the two signal vias 501 .
  • the above-mentioned shielding structure will be described in detail below with reference to the accompanying drawings.
  • the main grounding hole 502 and the first auxiliary grounding hole 503 respectively pass through part of the wiring layer and the grounding layer 505
  • the main grounding hole 502 and the first auxiliary grounding hole 503 respectively pass through the wiring layer and the grounding layer 505 .
  • the ground plane 505 is connected to ground.
  • the ground layer 505 is provided with an anti-pad 504 corresponding to each signal via.
  • the main ground vias 502 between adjacent differential pair units are shared. That is, in the same row of differential pair units, only one main ground hole 502 is required between two adjacent differential pair units, and the main ground hole 502 participates in the shielding structure of the two adjacent differential pair units. Therefore, the number of the main grounding holes 502 can be reduced.
  • FIG. 5 shows a schematic structural diagram of the main grounding hole 502 .
  • Each main ground hole 502 is a master-slave ground hole, and along the Z direction, the master-slave ground hole passes through each layer structure of the printed circuit board, and communicates with each ground layer in the printed circuit board through which it passes.
  • the signal is transmitted in the printed circuit board through the signal via hole and its connected wiring, and the main ground hole 502 is used to transmit the return current of the signal, which is an important component of the signal propagation path.
  • the master-slave ground hole is a combination of several connected ground vias on the printed circuit board, each master-slave ground hole includes at least one master hole 5021 and at least one slave hole 5022, and the master hole 5021 and each slave hole 5022 connected and conductively connected.
  • the main hole 5021 of the master-slave ground hole accommodates the ground pin of the connector, completes the reliable electrical interconnection between the printed circuit board and the connector, and also connects the ground plane through which it passes on the printed circuit board.
  • the slave hole 5022 of the master-slave grounding hole does not need to accommodate the ground pins, so a smaller hole diameter can generally be applied, that is, the diameter of the slave hole 5022 is smaller than that of the main hole 5021 .
  • the slave hole 5022 needs to be connected to the main hole 5021 and connected to the ground plane through which it passes on the printed circuit board.
  • the master-slave ground hole is responsible for interconnecting the ground pad of the chip with the ground reference layer in the printed circuit board.
  • the hole connecting the ground pad is the main hole 5021, which is distributed around the periphery.
  • the hole is the slave hole 5022, the main hole 5021 and the slave hole 5022 are connected to the ground layer in the printed circuit board that they pass through. It should be understood that no matter which of the above application scenarios, the depth of the master-slave ground hole is not less than the depth of the signal via.
  • the main grounding hole 502 is composed of at least one main hole 5021 and four slave holes 5022 near the main hole 5021.
  • the four slave holes 5022 are arranged around the main hole 5021 and are arranged in a “plum blossom” shape. Structure.
  • Part of the side wall of the main hole 5021 is a part of the side wall of the slave hole 5022 .
  • the main hole 5021 is completed by hole and electroplating.
  • the main hole 5021 can be a via hole of different shapes such as a circle, a square, and an ellipse.
  • the slave hole 5022 can be a via hole of different shapes such as a circle, a square, an ellipse, and the like.
  • holes of any shape can be used for combination.
  • the first auxiliary grounding hole 503 is a small-diameter slave hole on the printed circuit board, usually in the aspect ratio of the processing technology (referring to the board thickness/aperture, that is, the thickness of the printed circuit board and the hole The ratio of diameters) is the smallest diameter via hole that can be realized on the printed circuit board under extreme conditions.
  • the first auxiliary grounding hole 503 is not directly connected to the pins of the connector or chip, but to the through layer on the printed circuit board. ground plane interconnects in .
  • the first auxiliary grounding hole 503 cooperates with the main grounding hole 502 to form a shielding structure for shielding the differential pair unit, which helps to improve the crosstalk in the packaging area.
  • the number of the first auxiliary grounding holes 503 is not limited to one, but can also be two.
  • the number of the first auxiliary grounding holes is two, the number of the two first auxiliary grounding holes
  • the center points are located on both sides of the connection line between the center points of the two signal vias, thereby forming an "O"-shaped shielding structure and improving the shielding effect on the differential pair unit.
  • FIG. 6 shows the arrangement of the anti-pad 504 of the ground layer 505 .
  • the anti-pad 504 is a hollow area corresponding to the signal via 501 provided on the ground layer 505 through which the signal via 501 passes, so as to prevent the signal via 501 from conducting electricity with the ground layer 505 .
  • the two signal vias 501 included therein correspond to one anti-pad 504 respectively.
  • the anti-pads 504 corresponding to the two signal vias 501 are arranged at intervals, and a part of the metal of the ground layer 505 is spaced between the two anti-pads 504 .
  • the above-mentioned anti-pad 504 is a hollow area of the metal layer designed in order to avoid the signal via hole 501 in the ground layer 505 of the printed circuit board. Any ground layer 505 that the signal via 501 passes through needs to be designed with an anti-pad 504 .
  • the anti-pad 504 in the embodiment of the present application adopts the design of double anti-pad 504 , that is, one signal via 501 in each differential pair unit corresponds to one anti-pad 504 .
  • the anti-pad 504 has different shapes such as a circle, a square, and an ellipse, and it is only necessary to realize the electrical isolation between the signal via 501 and the ground layer 505 .
  • the anti-pad 504 is circular, and the anti-pad 504 is disposed coaxially with the corresponding signal via 501 , so that the size of the anti-pad 504 can be reduced.
  • the printed circuit board provided by the embodiment of the present application is designed through a column of vertically oriented ground hole arrays (main ground holes and first auxiliary ground holes), combined with double anti-pads
  • the 504 constructs a three-dimensional small-sized grid in the packaging area, constraining electromagnetic field propagation interference to the greatest extent, and achieving low crosstalk performance.
  • the following describes in detail how each structure in the printed circuit board in the embodiment of the present application realizes the shielding of signals.
  • the crosstalk in the package area of the printed circuit board can be decomposed into hole-to-hole coupling (coupling between differential pair units and signal vias 501 in the differential pair unit), hole-to-line coupling (coupling of signal vias 501 and traces), and line-to-line coupling (Coupling of trace to trace). Since the main body of the package area is determined by the signal via 501 and the ground via, the via-hole coupling crosstalk is usually the first consideration.
  • the hole-hole coupling can be divided into electric field coupling and magnetic field coupling from the principle of electromagnetic coupling. The electric field coupling is usually significant when the two signal vias 501 are close to each other.
  • the interference caused by it is positively correlated with the mutual capacitance between the signal vias 501 ; magnetic field coupling is ubiquitous, and the interference caused by it is positively correlated with the mutual inductance between the signal vias 501 .
  • the main way is to reduce the facing of the attack hole (signal via 501 that generates the crosstalk signal) and the victim hole (the signal via 501 that is crosstalked).
  • the main method is to improve the return flow of the signal via hole 501, set the nearest reference ground hole, avoid the return current from crossing the division, and constrain the distribution of the electromagnetic field.
  • the printed circuit board provided by the embodiment of the present application constructs a “C” type ground hole array (main ground hole 502 and first auxiliary ground hole 503 ), which isolates and reduces the difference The opposite area between the signal vias 501 of the differential pair unit to reduce electric field coupling.
  • the return flow of the signal vias 501 is improved through the ground hole array, and the electromagnetic field of the signal vias 501 of each differential pair unit is confined in the "C" type ground hole array to reduce the magnetic field coupling, and finally achieve the suppression of the hole-hole coupling.
  • FIG. 8 illustrates a situation of crosstalk between different differential pair units.
  • the differential pair unit is divided into an interference pair and a disturbed pair according to the crosstalk situation.
  • the disturbing pair refers to the differential pair unit whose transmitted signal interferes with other differential pair units
  • the disturbed pair refers to the differential pair unit that is interfered by the signals of other differential pair units.
  • one of the signal vias is adjacent to each other, such as the first signal via 5011 of the interference pair and the second signal via 5012 of the victim pair 1, if the first signal passes through A conventional ground hole is spaced between the hole 5011 and the second signal via hole 5012, so the isolation effect is insufficient. Therefore, in the embodiment of the present application, a “plum blossom”-shaped main ground hole 502 is used, and the secondary holes other than the main hole are used to increase the distance. The diameter of a single main ground hole 502 is enlarged.
  • the “plum blossom”-shaped main ground hole 502 increases the area of the return path. At the same time, the direct electric field coupling of the signal vias on both sides of the main grounding hole 502 obtains a larger area of shielding, so the "plum blossom"-shaped main grounding hole 502 significantly reduces the crosstalk of the interference pair to the victim pair 1.
  • a first auxiliary ground hole 503 is provided at a position offset upward between the two signal vias of the differential pair unit, and the crosstalk of the disturbing pair to the disturbed pair 2 is effectively isolated through the first auxiliary grounding hole 503 .
  • the main grounding hole 502 and the first auxiliary grounding hole 503 in the "plum blossom” shape not only play the above role in reducing crosstalk, but also have other functions.
  • the main grounding hole 502 in the "plum blossom” shape can also improve the return flow of the differential pair.
  • the electromagnetic field of the differential pair is more confined near the differential pair unit, reducing the reference to the adjacent ground holes (the main ground hole 502 or the first auxiliary ground hole 503 ) of other distant differential pair units, so it can also reduce the interlaced differential to crosstalk between cells.
  • the "plum blossom"-shaped main ground hole 502 and the first auxiliary ground hole 503 should be regarded as a whole, in a printed circuit board with a plurality of differential pair units, such as shown in FIG. 8
  • the "C"-shaped shielding structure composed of multiple groups of "plum blossom"-shaped main grounding holes 502 and first auxiliary grounding holes 503 surrounds a plurality of differential pair units respectively, so as to ensure that the signals along the holes are perpendicular to the setting surface of the printed circuit board.
  • each differential pair When propagating in the direction (Z direction), each differential pair has a good vertical shielding structure to isolate crosstalk.
  • the "C"-shaped shielding structure provided by the present application can shield the function of the differential pair unit, and mainly improves the hole-hole coupling crosstalk.
  • the printed circuit board in the embodiment of the present application is not only the hole-hole coupling part that simply considers the crosstalk, but also can improve the hole-to-line coupling crosstalk and the line-to-line coupling crosstalk.
  • FIG. 9 shows a schematic diagram of the locations where the hole-to-line coupled crosstalk and the line-to-line coupled crosstalk occur.
  • the vias signal vias and ground vias
  • FIG. 9 shows only the vias (signal vias and ground vias) in the row where the disturbing pair 5052 and the disturbed pair 5051 are located, and the vias in other rows are hidden for convenience. It should be understood that only one disturbing pair 5052 and one disturbed pair 5051 are used as examples for description in this FIG. 9 .
  • the hole-to-line coupling and line-to-line coupling are relatively small due to the lower effective bandwidth.
  • the role of hole-to-line coupling and line-to-line coupling cannot be ignored and may even be a key bottleneck.
  • a ground layer 505 is spaced between the trace 5052 and the trace 5061. To distinguish other ground layers, the ground layer 505 is named as the first ground layer.
  • the traces ( 5061 and 5062 ) of the trace layers on both sides of the first ground layer are located outside the anti-pad 504 of the first ground layer.
  • the wiring 5062 is closer to the interference pair 5051 when routing.
  • the area where the crosstalk coupling is most severe is where the two (interfering pair 5051 and trace 5062) intersect adjacently.
  • the strongest interference is through the part near the layer where the trace 5061 is located.
  • the trace 5061 the most disturbed part is the part near the interference pair 5051.
  • the interference pair 5051 that generates the interference is perpendicular to the setting surface of the printed circuit board, while the disturbed trace 5061 is located in the printed circuit board and parallel to the setting surface, so the transmission direction of the interference is mainly three-dimensional, so it cannot be formed only by grounding holes.
  • the adjustment of the shielding structure improves the hole-line coupling crosstalk, and it is also necessary to isolate the components of the interference transmitted in the vertical direction through the ground layer.
  • the anti-pad 504 of the signal via For the ground layer, its hollow is usually the anti-pad 504 of the signal via, so the effect of the ground layer isolation interference depends on the size of the anti-pad 504.
  • the double anti-pad 504 is used for the signal via pair in the differential pair unit, and the intermediate ground layer of a pair of signal via holes keeps the interconnection and intercommunication without being split, so that the hollowed-out area of the ground layer is minimized It can minimize the transmission of interference components transmitted in the vertical direction, and further improve the suppression of hole-line coupling based on the isolation of the "C"-shaped shielding structure.
  • the anti-pad 504 corresponds to the signal vias one-to-one, so that the opening of the anti-pad 504 is small, and only the signal with a shorter wavelength can pass through the anti-pad 504, and the signal with a longer wavelength cannot pass through the anti-pad 504. With the anti-pad 504, more line-to-line coupling disturbances can thus be suppressed.
  • the double anti-pad 504 retains the connection of the ground layer in the middle of a pair of signal vias, so that the interference of the anti-pad 504 to the signal return is smaller, and the traces 5061 and 5062 will not be affected by each other. Larger return paths have stronger mutual inductance, resulting in relatively less coupling.
  • the interference signal is not only propagated in a direction perpendicular to the setting surface, nor is it only propagated in a direction parallel to the setting surface, and the propagation direction of the interference signal is three-dimensional. Therefore, the printed circuit board provided by the embodiment of the present application does not act on vertical interference and horizontal interference separately through the double anti-pad 504 and the ground hole array, but constitutes a package through the double anti-pad 504 and the ground hole array.
  • a three-dimensional overall shielding structure in the area provides the signal with the nearest return reference in all directions in a limited space, thereby suppressing the transmission of interfering signals.
  • the double anti-pad 504 optimizes the segmentation of the ground plane and improves the planar reflow, the ground hole array improves the reflow in the vertical direction, the ground hole array and the grounding using the double anti-pad 504
  • the layer divides the space in the printed circuit board into grid units of small size, and signals passing through each grid unit have a good reflow reference, thereby suppressing the external transmission of interference.
  • FIG. 10 shows another schematic diagram of the printed circuit board provided by the embodiment of the present application.
  • the printed circuit board includes a plurality of differential pair units, and each differential pair unit includes two signal vias 604 , and the signal vias 604 pass through part of the layer structure of the printed circuit board along the Z direction.
  • FIG. 11 shows a schematic diagram of the arrangement of the differential pair units.
  • a plurality of differential pair units are arranged in an array.
  • the first row of differential pair units includes signal vias A1, B1, C1, D1, E1, and F1;
  • the second row of differential pair units includes signal vias A2, B2, C2, D2, E2, and F2;
  • the third row of differential pairs The cells include signal vias A3, B3, C3, D3, E3, and F3. It should be understood that in FIG. 11 , only three rows of differential pair units are used as an example for description, and in an actual printed circuit board, different rows of differential pair units may be set according to actual needs.
  • FIG. 12 shows a differential pair unit and the corresponding shielding structure.
  • Each differential pair unit includes two signal vias 601 .
  • the shielding structure includes a main ground via 602 and three auxiliary ground holes 603.
  • the three auxiliary ground holes 603 are respectively the first auxiliary ground holes arranged between the two signal vias 601, and the main ground holes 602 and the signal vias 603 respectively.
  • a second auxiliary ground hole between the holes 601 is respectively.
  • the direction in which the signal vias 601 of a differential pair unit are arranged is the second direction (X direction), and its vertical direction is called the first direction (Y direction), that is, the first direction is parallel to the setting surface and perpendicular to the two signals
  • the direction of the arrangement direction of the via holes 601 There is one main ground hole 602 on both sides of the signal via hole 601 along the second direction.
  • the main ground hole 602 is composed of a main hole and four slave holes. The slave holes are distributed around the ground hole with the main hole as the center, and any slave hole forms an electrical connection with the main hole through its metallized hole wall or its connected ground plane. connect.
  • the number of slave holes in a single master hole may be less than that in this embodiment, but the number of slave holes should not be less than one.
  • the overall width of the main ground holes 602 in the first direction needs to be increased, that is, the width of each main ground hole 602 in the first direction is greater than the width of each signal via hole 601 in the first direction , thereby enhancing the shielding effect.
  • the connection between the center points of the two main grounding holes 602 overlaps with the connection between the center points of the two signal vias 601, so as to facilitate the arrangement of more rows of differential pair units.
  • the center point of the auxiliary ground hole 603 is located on one side of the line connecting the center points of the two signal vias 601 , so as to cooperate with the main ground hole 602 to form a C-shaped shielding structure.
  • three auxiliary grounding holes 603 are distributed on one side of the signal via hole 601 and form a C-shaped shielding structure with the main grounding hole 602 .
  • the number of auxiliary ground holes 603 may be less than the number in this embodiment, but not less than one, and there is at least one auxiliary ground hole 603 between the two signal vias 601 of the differential pair unit, so as to be the same ground hole Form a "C" type ground hole shielding array.
  • adjacent differential pair units arranged in the second direction share one main ground hole 602 , and the distance between the differential pair units along the second direction may be 1.3 mm. Taking the center of the hole as a reference, three differential pair units can be arranged in a row within 10.8mm. In this embodiment, the spacing between adjacent rows is 1.8 mm. In order to avoid strong crosstalk caused by the vertical alignment of the signal vias in the first direction, the second row is shifted to the left in the second direction relative to the first row. , for example, the offset distance may be 1 mm.
  • the crosstalk between the differential pair units in adjacent rows is also reduced by arranging auxiliary ground holes 603 .
  • the multiple auxiliary grounding holes 603 and the multiple main grounding holes 602 of different units form a one-row grounding hole array to form an effective shield for inter-row crosstalk.
  • the auxiliary grounding hole 603 cooperates with the main grounding hole 602 to form a "C" type shielding structure for the differential pair unit, and only one side of the signal via hole along the first direction is opened for wiring out.
  • the sidewalls of the signal vias 601 are plated with metal to form a conductive layer to transmit signals.
  • the metal layer of the signal vias 601 may penetrate the entire thickness of the printed circuit board, or may be blind holes or backsides. The process form of the drill does not penetrate the entire thickness of the printed circuit board.
  • the direction perpendicular to the thickness of the printed circuit board is called the third direction (Z direction), which is perpendicular to the plane where the second direction and the first direction are located.
  • Z direction The direction perpendicular to the thickness of the printed circuit board.
  • the length of the metal layer of the sidewall of the hole along the first direction should not be less than the length of the signal via hole 601 along the first direction.
  • the metal of the sidewall of the via hole includes, but is not limited to, conductive metal materials such as copper, aluminum, and silver, and its processing technology includes but is not limited to electroplating, evaporation, sputtering, electroless plating, or vapor deposition.
  • a ground layer for signal reference is provided inside the printed circuit board.
  • an anti-pad 604 corresponding to each signal via hole of the differential pair unit is applied on each ground layer that passes through the differential pair unit, that is, a double inverse is used.
  • the pads 604 correspond to the signal vias 604 of one differential pair unit.
  • the double anti-pad 604 not only realizes the conventional function of the ground layer avoiding the reference signal and via impedance control, but also retains the interconnection of the ground layer in the middle of the signal vias, so that the opening of the single anti-pad 604 on the ground layer is relatively small.
  • the shape of the anti-pad includes but is not limited to circular, rectangular, square, oval, etc., but needs to ensure that the double anti-pad can preserve the interconnection of the ground plane in the middle of the signal via.
  • the main hole of the main grounding hole 602 is a crimping via hole, and the secondary holes are distributed around the main hole. Since the secondary holes do not need to accommodate the connector pins, the hole diameter can be made smaller and usually The hole pads will also be made relatively small.
  • FIG. 13 shows a schematic diagram of another shielding structure provided by an embodiment of the present application.
  • the vias on the printed circuit board include signal vias 6001 , main grounding holes 6002 , and auxiliary grounding holes 6003 .
  • the main ground hole 6002 is a master-slave ground hole including two main holes 60021 and one slave hole 60022.
  • the slave hole 60022 is located between the two main holes 60021 and communicates with the main hole 60021 respectively and is electrically connected.
  • the secondary hole 60022 is located in the middle of the two main holes 60021, and the three are arranged along the first direction, or are arranged in a direction inclined relative to the first direction.
  • the two main holes 60021 are connected to the ground pins of the connector, while the slave holes 60022 are directly connected to different connector pins, and the two main holes 60021 are connected to the two main holes 60021 by the metal of the side walls in the holes, so that the entire main-slave ground hole is connected.
  • the width of the 6002 in the first direction is significantly larger than the width of the signal via hole 6001 in the first direction, thereby improving the isolation between different differential pair units in the row in the first direction.
  • the auxiliary ground holes are in the first direction of the center of the two via holes 6001 of the differential pair unit to form a "C" type ground hole shielding array with the main ground holes 6002 .
  • Anti-pad 6004 takes a rectangular shape in FIG. 13 .
  • the printed circuit board provided in this embodiment has lower coupling crosstalk effect between holes compared with the conventional printed circuit board.
  • the double anti-pad used in this embodiment can minimize the degradation of hole-to-line coupling and line-to-line coupling caused by layer deviation.
  • the double-round anti-pad is matched with the "C" type shielding ground hole
  • the hole-line coupling suppression gains of the array reach MDNEXT gains of 3.6dB@14GHz and 4.1dB@28GHz, and MDFEXT gains of 3.6dB@14GHz and 4.8dB@28GHz.
  • the line-to-line coupling suppression gain of the double-round anti-pad with the "C" type shielded ground hole array reaches the MDNEXT gain of 4.2 dB@14GHz and 6.1dB@28GHz, MDFEXT gains 6.6dB@14GHz and 6.2dB@28GHz.
  • FIG. 14 is a schematic diagram showing the arrangement of via holes and grounding holes of the printed circuit board matched with the chip
  • FIG. 15 is a schematic diagram of a three-dimensional structure corresponding to FIG. 14 .
  • a part of the printed circuit board corresponds to the pads of all pins of the chip and their corresponding via areas, and the printed circuit board has multiple groups of differential pair units.
  • the chip pads 2012 in this embodiment are distributed in a matrix of 4 ⁇ 8 equidistant spacing in rows and columns. In other embodiments, the chip pads can be equidistantly or unequally spaced in a regular period. Sex distribution. Within the 4 ⁇ 8 die pads 2012 , 8 pairs of differential pair units can be arranged at a high density with good signal integrity. According to different attributes of the assigned signal network, the chip pad 2012 is divided into a signal pad 20121 and a ground pad 20122, which correspond to the signal pins and ground pins of the chip, respectively.
  • the straight line where the pair of signal pads 20121 are located is the first direction
  • the direction perpendicular to the first direction along the plane of the printed circuit board is the second direction.
  • two adjacent chip signal pads 20121 are a group of differential pair units, there is a ground pad 20122 on both sides of the signal pad 20121, and the adjacent two groups of differential pair units are separated by a ground. Pad 20122.
  • the two groups of adjacent differential pair units are shifted in the first direction by a length of one chip pad interval, so as to avoid large crosstalk caused by the positive pairs of the two groups of differential unit pairs in adjacent rows.
  • a signal via hole 2013 is set in the middle of the chip pad 20121, and the hole diameter is 8 mil, which is usually completed by the hole-in-disk process.
  • a main ground via 2014 is arranged in the middle of the ground pads 20122. The three distributed ground vias are formed, and the drill diameter is 8 mils, and the center distance of each via in the second direction is 7 mils.
  • the via hole located in the ground pad 20122 is the main hole
  • the via holes on both sides distributed along the second direction are the slave holes
  • the hole wall metal of the two slave holes is electrically connected with the hole wall metal of the main hole, so that the three The length of the main ground via 2014 formed by the two vias in the second direction is greater than the length of the signal via 2013 in the second direction, so as to effectively isolate the crosstalk between adjacent differential pair units in the first direction.
  • an auxiliary grounding hole 2015 is provided at a position of 7 mils upward along the second direction, and the drilling diameter thereof is 8 mils.
  • the auxiliary ground hole 2015 can effectively improve the crosstalk between the differential pair units between adjacent rows.
  • an auxiliary ground hole 2015 cooperates with the main ground via holes 2014 on both sides to form a "C" type ground hole shield. C" type ground hole shielding array, effectively improving hole-hole coupling crosstalk.
  • the reference ground plane is not set on the top layer where the chip pads 2012 are located, and a multi-layer ground layer 2011 is set on the inner layer of the printed circuit board according to design requirements.
  • the grounding layer 2011 is hollowed out with the signal vias as the center to form an anti-pad 2016, which is circular in this embodiment.
  • both the above-mentioned main ground via 2014 and auxiliary ground via 2015 need to be connected to the reference ground layer 2011 .
  • the double anti-pad 2016 cooperates with the "C" type ground hole shielding array, which can effectively improve the line-to-line coupling crosstalk and the hole-line coupling crosstalk in the packaging area.
  • Embodiments of the present application also provide a backplane architecture system, where the backplane architecture system includes a backplane and a connector connected to the backplane.
  • the backplane architecture system includes a backplane and a connector connected to the backplane.
  • the backplane is the printed circuit board of any of the above.
  • each signal corresponds to an anti-pad, and the ground layer is spaced between the anti-pads, thereby reducing the interference of the trace after the signal of the signal via or the interlayer trace passes through the anti-pad, Improves crosstalk issues within printed circuit boards.
  • the shielding structure is formed by the main grounding hole and the first auxiliary grounding hole, which reduces the crosstalk between the differential pair unit and other differential pair units, improves the crosstalk problem of the printed circuit board, and facilitates the connection of the jacks on the printed circuit board. Dense settings.
  • An embodiment of the present application further provides a communication device, which may be a communication device such as a base station or a cabinet in a computer room, and the communication device includes a machine frame and the printed circuit board described in any one of the above, and the printed circuit board A circuit board is inserted into the chassis.
  • a communication device which may be a communication device such as a base station or a cabinet in a computer room
  • the communication device includes a machine frame and the printed circuit board described in any one of the above, and the printed circuit board A circuit board is inserted into the chassis.
  • each signal corresponds to an anti-pad
  • the ground layer is spaced between the anti-pads, thereby reducing the interference of the trace after the signal of the signal via or the interlayer trace passes through the anti-pad, Improves crosstalk issues within printed circuit boards.
  • the shielding structure is formed by the main grounding hole and the first auxiliary grounding hole, which reduces the crosstalk between the differential pair unit and other differential pair units, improves the crosstalk problem of the printed circuit board, and facilitates the connection of the jacks on the printed circuit board. Dense settings.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Structure Of Printed Boards (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

本申请提供了印制电路板及背板架构系统、通信设备，印制电路板包括层叠设置的多个层结构，印制电路板具有设置面。设置面设置有差分对单元以及用于屏蔽该差分对单元的屏蔽结构。差分对单元包括两个信号过孔，每个信号过孔穿过多个层结构，每个信号过孔穿过的接地层设置有与该信号过孔对应的反焊盘，以避免信号过孔接地。两个反焊盘之间间隔有接地层的部分金属。通过采用每个信号对应一个反焊盘，反焊盘之间间隔了地层，降低了信号过孔或隔层走线的信号穿过反焊盘后干扰走线，改善了印刷电路板内的串扰问题。通过屏蔽结构降低了差分对单元与其他差分对单元之间的串扰，改善了印制电路板的串扰问题，便于印制电路板上插孔的密集化设置。

Description

一种印制电路板及背板架构系统、通信设备
相关申请的交叉引用
本申请要求在2020年10月29日提交中国专利局、申请号为202011180015.2、申请名称为“一种印制电路板及背板架构系统、通信设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及到通信技术领域，尤其涉及到一种印制电路板及背板架构系统、通信设备。
背景技术
当前电子设备中，通常以印制电路板作为各个电子元器件的载体，同时通过印制电路板的走线将各个元器件互连。各元器件主要通过压接、焊接的方式同印制电路板形成稳定电气连接和机械连接。
当一个元器件具有多个信号需要连接到印制电路板时，印制电路板上就需要有足够多的焊盘或过孔同对应于多个信号的多个引脚相连，典型的场景是具有球栅阵列(BGA)封装形式的芯片的焊球引脚同印制电路板上的阵列式焊盘连接，以及高速连接器的压接鱼眼引脚同印制电路板上的阵列式压接过孔连接。
对于这种多个信号的多引脚封装，为了尽量减小芯片在板面积和连接器在板面积，各引脚焊盘之间的间距非常近，对于芯片焊盘最小可以达到0.4mm左右的量级，对于连接器压接脚焊盘最小可以达到1.1mm左右的量级。无论是芯片场景还是连接器场景，这些信号都需要在有限的封装面积内完成走线出线，这需要利用大量的过孔完成器件到板上各层走线的互连。高密封装区域内的大量信号过孔、走线彼此邻近，将引起串扰问题。
发明内容
本申请提供了一种印制电路板及背板架构系统、通信设备，用于改善背板架构系统的串扰问题，改善信号传输效果。
第一方面，提供了一种印制电路板，该印制电路板应用于背板架构系统，该印制电路板包括层叠设置的多个层结构，多个层结构分别为不同的功能层，如多个层结构中包括交替排布的接地层和走线层。另外，为与其他器件配合，印制电路板设置有与其他器件配合的设置面，该设置面为多个层结构中位于最外层的层结构的一表面。该设置面设置有差分对单元以及用于屏蔽该差分对单元的屏蔽结构。其中，差分对单元包括两个信号过孔，每个信号过孔穿过至少部分的接地层和走线层，并与其中的一个走线层上的走线连接。另外，每个信号过孔穿过的接地层设置有与该信号过孔对应的反焊盘，以避免信号过孔接地。在具体设置两个反焊盘时，两个信号过孔对应的反焊盘之间间隔排列，两个反焊盘之间间隔有接地层的部分金属。上述屏蔽结构包括设置在设置面的两个主接地孔以及第一辅助接地孔，其中，两个主接地孔位于差分对单元的两侧，第一辅助接地孔位于两个信号过孔之间。上述主接地孔及第一辅助接地孔分别穿设过部分走线层和接地层，且主接地孔和第一辅助 接地孔分别与穿设过的接地层接地连接。在上述技术方案中，通过采用每个信号对应一个反焊盘，且反焊盘之间间隔了地层，从而降低了信号过孔或隔层走线的信号穿过反焊盘后干扰走线，改善了印刷电路板内的串扰问题。另外，通过主接地孔和第一辅助接地孔组成屏蔽结构，降低了差分对单元与其他差分对单元之间的串扰，改善了印制电路板的串扰问题，便于印制电路板上插孔的密集化设置。
在一个具体的可实施方案中，第一接地层的两侧的走线层的走线位于所述第一接地层的反焊盘的外侧；其中，所述第一接地层为所述每个信号过孔穿设过的接地层。通过反焊盘中间的接地层互连及邻近的主地孔和辅助地孔，最小化两侧走线层走线彼此耦合干扰，改善了印制电路板的效果。
在一个具体的可实施方案中，反焊盘为圆形、方形、椭圆形等不同的形状，从而实现不同的反焊盘改善线与线之间的串扰。
在一个具体的可实施方案中，反焊盘为圆形，且反焊盘与对应的信号过孔同轴设置，进一步的降低了反焊盘的面积，改善了信号过孔与走线的之间的串扰，也改善了走线与走线之间的串扰。
在一个具体的可实施方案中，所述差分对单元的个数为多个，且相邻的差分对单元之间的主接地孔共用。降低了主接地孔的个数。
在一个具体的可实施方案中，每个主接地孔在第一方向的宽度大于所述每个信号过孔在所述第一方向的宽度；所述第一方向为平行于所述设置面，且垂直于所述两个信号过孔排列方向的方向。改善对信号过孔的屏蔽效果。
在一个具体的可实施方案中，每个主接地孔包括主孔，以及环绕所述主孔的至少一个从孔；其中，所述主孔与每个从孔连通并导电连接。通过主孔与从孔的配合改善对信号过孔的屏蔽效果。
在一个具体的可实施方案中，每个主接地孔包括两个主孔，以及位于所述两个主孔之间的从孔；其中，所述从孔分别与所述两个主孔连通并导电连接。通过主孔与从孔的配合改善对信号过孔的屏蔽效果。
在一个具体的可实施方案中，主孔可为圆形、方形、椭圆形等不同形状的过孔。从孔可为圆形、方形、椭圆形等不同形状的过孔。
在一个具体的可实施方案中，所述两个主接地孔及所述第一辅助接地孔组成包裹所述差分对单元的C形屏蔽结构。通过主接地孔与第一副接地孔组成一个C形的形状包裹差分对单元，改善对差分对单元的屏蔽效果。
在一个具体的可实施方案中，在所述主接地孔包括主孔以及环绕所述主孔的至少一个从孔时，所述两个主接地孔的中心点连线与所述两个信号过孔的中心点连线重叠。方便排布设置主接地孔。
在一个具体的可实施方案中，所述第一辅助接地孔的中心点位于所述两个信号过孔的中心点连线的一侧。方便形成C形的屏蔽结构。
在一个具体的可实施方案中，所述第一辅助接地孔的个数为两个，且两个所述第一辅助接地孔的中心点分别位于所述两个信号过孔的中心点连线的两侧。从而提高对差分对单元的屏蔽效果。
在一个具体的可实施方案中，所述屏蔽结构还包括设置在所述主接地孔与相邻的信号过孔之间的第二辅助接地孔。进一步改善形成的屏蔽结构对差分对单元的屏蔽效果。
第二方面，提供了一种背板架构系统，该背板架构系统包括背板以及与背板连接的连接器；其中，所述背板为上述任一项所述的印制电路板。在上述技术方案中，通过采用每个信号对应一个反焊盘，且反焊盘之间间隔了地层，从而降低了信号过孔或隔层走线的信号穿过反焊盘后干扰走线，改善了印刷电路板内的串扰问题。另外，通过主接地孔和第一辅助接地孔组成屏蔽结构，降低了差分对单元与其他差分对单元之间的串扰，改善了印制电路板的串扰问题，便于印制电路板上插孔的密集化设置。
第三方面，提供了一种通信设备，该通信设备包括机框以及上述任一项所述的印制电路板，所述印制电路板被插入所述机框内。在上述技术方案中，通过采用每个信号对应一个反焊盘，且反焊盘之间间隔了地层，从而降低了信号过孔或隔层走线的信号穿过反焊盘后干扰走线，改善了印刷电路板内的串扰问题。另外，通过主接地孔和第一辅助接地孔组成屏蔽结构，降低了差分对单元与其他差分对单元之间的串扰，改善了印制电路板的串扰问题，便于印制电路板上插孔的密集化设置。
附图说明
图1为一种背板架构系统的分解示意图；
图2为一种芯片和印刷电路板连接的场景示意图；
图3为本申请实施例提供的印刷电路板的结构示意图；
图4为印刷电路板的设置面的示意图；
图5为本申请实施例提供的主接地孔的结构示意图；
图6为本申请实施例提供的接地层的反焊盘设置方式；
图7为本申请实施例提供的主接地孔及辅助接地孔形成的屏蔽结构；
图8为本申请实施例提供的不同的差分对单元之间的串扰示意图；
图9为本申请实施例提供的孔线耦合串扰和线线耦合串扰发生的位置示意图；
图10为本申请实施例提供的印刷电路板的另一示意图；
图11为本申请实施例提供的差分对单元的排布示意图；
图12为本申请实施例提供的一个差分对单元及对应的屏蔽结构；
图13为本申请实施例提供的另一种屏蔽结构的示意图；
图14为与芯片配合的印刷电路板的过孔及接地孔的排布示意图；
图15为图14所示的印刷电路板的三维示意图。
具体实施方式
下面将结合附图对本申请实施例作进一步描述。
首先介绍本申请实施例介绍的几个概念：
串扰：串扰指的是有害信号从一个网络传递到另一个网络的耦合效应。
反焊盘：在连接器封装区域，印刷电路板内的各层结构除信号布线层外，其余通常为电源层、地平面层，这些平面层实际上就是一层金属层，为了避让垂直走向的过孔、各层的过孔焊盘、封装焊盘等，需要对平面金属层(电源层平面、地平面层)掏空避让，以免不同网络接触形成短路，这些金属层掏空的区域被称为反焊盘(Anti-Pad)。
接地孔：指的是信号返回电流通过的过孔，是信号过孔的参考(电流是个闭合的环路)。
信号过孔：指的是数据信号通过的过孔。
封装：本申请实施例中的封装指的是印制电路板同芯片、连接器等器件对应引脚配合的焊盘及过孔排布方式。
差分信号：同单端信号需要采用一条导线在发送器到接收器之间传递信号不同，差分信号需要采用两个导线来传递信号，并且两根导线上的信号大小相同，极性相反，接收器最终采样的信号取两根导线上的信号差值的一半；构成差分信号传输路径的一对走线或过孔常被称为差分对。
SerDes:SerDes是英文Serializer(串行器)/Deserializer(解串器)的简称，即在发送端多路低速并行信号被转换成高速串行信号，经过传输媒介后在接收端将高速串行信号重新转换成低速并行信号。
为方便理解本申请实施例提供的印刷电路板，首先介绍本申请实施例提供的印刷电路板的应用场景，本申请实施例提供的印刷电路板应用于通信系统的设备中。
参考图1，图1给出了一种背板架构系统的分解示意图。背板架构系统包括背板10、公端连接器30、母端连接器40和单板10。背板10上有对应于公端连接器30的封装50，该封装50为背板10的一部分，具体为一组规律排列的过孔和相应反焊盘掏空构成的区域。在系统实现中，封装50中部分过孔容纳连接器30的压接引脚70，从而将连接器30安装固定在背板10，并提供电气连接。单板20上有对应于母端连接器40的封装60，封装60是单板20的一部分，封装60具体为一组规律排列的过孔和相应反焊盘掏空构成的区域。在系统实现中，封装60中部分过孔容纳连接器40的压接引脚80，从而将连接器60安装固定在单板20上，并提供电气互连。本发明实施例提供的印刷电路板即可为背板架构系统中的单板，也可为背板。
图2示出了一种芯片100和印刷电路板200连接的场景示意图，其中芯片100具有焊球引脚101，印刷电路板200上设置有对应于芯片焊球101的封装201。封装201具体为芯片封装指的焊球引脚对应的表层焊盘和在临近区域内与表层焊盘对应连接实现走线换层出线的过孔、内层走线和反焊盘的组合。在系统实现中，封装201中部分表层焊盘与芯片100的焊球引脚101连接，从而将芯片100安装固定在印刷电路板200上，并提供电气互连。
在上述图1和图2所示的印刷电路板的应用场景中，当信号数据速率提升到90Gbps+时，信号多采用PAM4(4 Pulse Amplitude Modulation，第四代脉冲幅度调制，第四代脉冲幅度调制信号作为下一代数据中心中高速信号互联的热门信号传输技术，被广泛应用于200G/400G接口的电信号或光信号传输)电平调制，以确保速率提高的同时降低对互连带宽乃至成本的挑战。然而PAM4编码的信号电压阶距是NRZ(Not Return to Zero，不归零码)信号的1/3，导致信噪比损失9.5dB，因此通过PAM4编码传输数据时对于噪声性能要求更加严苛。即使仍旧使用NRZ电平调制，速率提高带来的带宽增加仍然要求在更高的带宽内约束噪声。而串扰作为高速信号完整性无源指标中的一种，在速率越高的情况下优化越难，并且由于SerDes有源电路上针对串扰的抑制能力也非常有限，因此在高速设计中串扰的优化通常是重中之重。而现有技术中的印刷电路板在与芯片或连接器连接时，在器件高密封装区域，信号传输路径经过信号过孔和在印刷电路板内部各层的过孔出线进行传递，在此密集空间内垂直走向的过孔和平面走向的走线彼此都产生耦合干扰。为此本申请实施例提供了一种印刷电路板，用于改善印刷电路板在使用时过孔与过孔之间的串扰或过 孔和走线之间的串扰。
参考图3，图3示出了本申请实施例提供的印刷电路板的结构示意图。为方便理解本申请实施例提供的印刷电路板上的各个结构的相对位置关系，建立参考坐标系XYZ，其中，X方向、Y方向及Z方向相互垂直。印刷电路板相邻的三个侧边分别一一对应与X方向、Y方向及Z方向平行。另外，定义了印刷电路板的设置面，设置面平行于XY平面。该设置面用于与其他器件对应连接，示例性的，如图1中所示的背板架构系统中，设置面为单板或背板与连接器配合的表面；如图2所示的芯片系统中，设置面为印刷电路板与芯片配合的表面。
本申请实施例提供的印刷电路板500具有多个层结构，多个层结构沿Z方向层叠排布。多个层结构可为具有不同功能的层结构，如多个层结构中包括走线层和接地层505。走线层为印刷电路板500的内部布线层，走线层用于布置走线传递信号。接地层505作为印刷电路板500的参考地平面，用于实现接地效果。接地层505作为印刷电路板500层叠的层结构中用于作为走线参考的地平面，接地层505提供信号的平面返回路径。
印刷电路板500的设置面即为上述多个层结构中位于最外层的一个表面。如最外层为接地层505时，设置面为该接地层505外露的一个表面；若最外层为走线层时，设置面为该走线层外露的一个表面。
为实现印刷电路板500与其他部件(如芯片或连接器)的电连接，印刷电路板500的设置面设置有差分对单元，该差分对单元包括两个用于传输差分信号的信号过孔501，如与连接器配合时，连接器设置有成对的两个压接引脚，两个信号过孔501与两个压接引脚一一对应插拔连接，以传输成对的信号。
差分对单元的每个信号过孔501的开口位于设置面，每个信号过孔501沿Z方向延伸到印刷电路板500的内层。信号过孔501沿Z方向延伸时穿过至少部分的接地层505和走线层，并与其中的一个走线层上的走线连接。示例性的，两个信号过孔501分别与位于同一个走线层的两个走线一一对应连接。通过信号过孔501与走线，实现信号沿过孔垂直走向到沿印刷电路板500走线平面走向的过渡。
信号过孔501的内侧壁金属化以具有导电性，在印刷电路板500与连接器配合时，信号过孔501需要容纳连接器的压接引脚，完成印刷电路板500与连接器的可靠电互连，同时负责信号的垂直(沿Z方向)传递以实现将连接器的信号传递到印刷电路板500的内层走线传递。在印刷电路板500与芯片配合时，信号过孔501负责将芯片焊盘同印刷电路板500的内层走线互连，实现信号的垂直传递和换层。应理解，在具体设置信号过孔501时，信号过孔501的深度通常小于等于印刷电路板500的厚度，而大于该信号过孔501对应连接的走线层所在层的深度。在上述信号过孔501穿设接地层505时，每个信号过孔501穿过的接地层505设置有与该信号过孔501对应的反焊盘504(图中未示出)，以避免信号过孔501接地。
一并参考图4，图4示出了印刷电路板的设置面的示意图。对于多个差分对单元，通常为了尽量减小芯片在板面积和连接器在板面积以及考虑其他系统规格，印刷电路板设置的信号过孔501之间的间距非常近，对于芯片对应的信号过孔501最小可以达到0.4mm左右的量级，对于连接器对应的信号过孔501最小可以达到1.1mm左右的量级。
如图4中所示，信号过孔501沿X方向及Y方向呈阵列排列。在布置上述信号过孔501时，大量信号过孔501彼此邻近，将引起串扰问题。为改善信号过孔501之间的串扰 问题，本申请实施例提供的印刷电路板在设置面设置有用于屏蔽差分对单元的屏蔽结构。该屏蔽结构用于隔离相邻的差分对单元，避免产生串扰。为方便描述在下文中将产生干扰的差分对单元命名为干扰对，将被干扰的差分对单元命名为受扰对。
屏蔽结构包括在设置面的两个主接地孔502以及第一辅助接地孔503，其中，两个主接地孔502位于差分对单元的两侧，第一辅助接地孔503位于两个信号过孔501之间。如图4中所示，每个差分对单元对应的主接地孔502与该差分对单元的两个信号过孔501排列成一行(沿X方向)。在设置主接地孔502时，沿两个信号过孔501的排布方向，主接地孔502分列在差分对单元的两侧。而第一辅助接地孔503设置在两个信号过孔501之间。在设置面上，两个主接地孔502及第一辅助接地孔503组成一个“C”形的包裹两个信号过孔501的屏蔽结构。下面结合附图对上述屏蔽结构详细描述。
结合图3所示的层结构，主接地孔502及第一辅助接地孔503分别穿设过部分走线层和接地层505，且主接地孔502和第一辅助接地孔503分别与穿设过的接地层505接地连接。而信号过孔501在穿过接地层505时，接地层505设置与每个信号过孔对应的反焊盘504。
在差分对单元的个数为多个时，相邻的差分对单元之间的主接地孔502共用。即在同一行差分对单元中，相邻的两个差分对单元之间只需设置一个主接地孔502即可，该主接地孔502参与其相邻的两个差分对单元的屏蔽结构。从而减少主接地孔502的设置个数。
一并参考图5，图5示出了主接地孔502的结构示意图。每个主接地孔502为主从式地孔，沿Z方向，主从式地孔穿过印刷电路板的各个层结构，并连通自身穿过的印刷电路板内的各个接地层。在传输信号时，信号通过信号过孔及其连接的走线实现在印刷电路板内的传递，而主接地孔502用于传递信号的返回电流，是信号传播路径的重要组成。
主从式地孔是印刷电路板上数个相连的接地过孔的组合，每个主从式地孔包括至少一个主孔5021和至少一个从孔5022，并且主孔5021与每个从孔5022连通并导电连接。在连接器应用场景下，主从式地孔的主孔5021容纳连接器的接地引脚，完成印刷电路板与连接器的可靠电互连，同时也连通印刷电路板上其穿过的接地层。主从式接地孔的从孔5022不需要容纳接地引脚，因此通常可以应用更小的孔径，即从孔5022的直径小于主孔5021的直径。从孔5022需要同主孔5021实连接，并连通印刷电路板上其穿过的接地层。在芯片应用场景下，主从式地孔负责将芯片的接地焊盘同印刷电路板内的地参考层互连互通，其中连接接地焊盘的孔为主孔5021，以它为中心分布于周边的孔为从孔5022，主孔5021和从孔5022连通印刷电路板内其穿过的接地层。应理解，无论上述哪种应用场景，主从式地孔的深度不小于信号过孔的深度。
示例性的，如图5所示，主接地孔502由至少一个主孔5021和主孔5021附近四个从孔5022构成，四个从孔5022环绕主孔5021设置，排布成“梅花”状的结构。主孔5021的部分侧壁为从孔5022的侧壁的一部分。在具体实现中，先在印刷电路板内沿Z方向上钻孔形成数个从孔5022并镀铜，然后利用如树脂等材料塞孔后，再在数个从孔5022之间的中央位置钻孔并电镀完成主孔5021。
作为一个可选的方案，主孔5021可为圆形、方形、椭圆形等不同形状的过孔。同理，从孔5022可为圆形、方形、椭圆形等不同形状的过孔。在具体设置主孔5021和从孔5022时，可以采用任意形状的孔进行组合。
继续参考图4，第一辅助接地孔503是印刷电路板上的一种小直径的从孔，通常是在 加工工艺厚径比(指的是板厚/孔径，即印刷电路板的厚度与孔直径的比值)极限条件下可以在印刷电路板上实现的最小孔径的过孔，第一辅助接地孔503不直接同连接器或芯片的引脚相连，而是对印刷电路板上其穿过层中的接地层互连。在使用时，第一辅助接地孔503与主接地孔502配合，一起组成屏蔽差分对单元的屏蔽结构，有助于改善封装区域的串扰。作为一个可选的方案，第一辅助接地孔503的个数不限于一个，还可为两个，在第一辅助接地孔的个数为两个时，两个所述第一辅助接地孔的中心点分别位于两个信号过孔的中心点连线的两侧，从而形成一个“O”形的屏蔽结构，提高对差分对单元的屏蔽效果。
参考图6，图6示出了接地层505的反焊盘504设置方式。反焊盘504为信号过孔501穿过的接地层505上设置的与该信号过孔501对应的掏空区域，以避免信号过孔501与接地层505导电。针对每个差分对单元，其包含的两个信号过孔501分别对应一个反焊盘504。两个信号过孔501对应的反焊盘504之间间隔排列，且两个反焊盘504之间间隔有接地层505的部分金属。上述反焊盘504是印刷电路板的接地层505中，为了避让信号过孔501设计的金属层掏空区域。凡是信号过孔501穿越的接地层505都需要设计反焊盘504。在本申请实施例中的反焊盘504采用双反焊盘504设计，即每个差分对单元中一个信号过孔501对应一个反焊盘504。
作为一个可选的方案，反焊盘504为圆形、方形、椭圆形等不同的形状，只需要实现信号过孔501与接地层505之间的电隔离即可。作为一个可选的方案，反焊盘504为圆形，且反焊盘504与对应的信号过孔501同轴设置，从而可降低反焊盘504的尺寸。
在本申请实施例中，针对印刷电路板内的串扰，本申请实施例提供的印刷电路板通过垂直走向的地孔阵(主接地孔及第一辅助接地孔)列设计，结合双反焊盘504构造封装区域内三维空间小尺寸网格，最大程度约束电磁场传播干扰，实现低串扰性能。下面详细说明本申请实施例中印刷电路板中的各结构如何实现对信号的屏蔽。
印刷电路板的封装区域的串扰可以分解为孔孔耦合(差分对单元与差分对单元中的信号过孔501的耦合)、孔线耦合(信号过孔501与走线的耦合)和线线耦合(走线与走线的耦合)。由于封装区域主体是由信号过孔501和接地孔决定的，因而孔孔耦合串扰通常是首要考虑的对象。孔孔耦合从电磁耦合原理上可以分为电场耦合和磁场耦合，电场耦合通常在两个信号过孔501彼此距离接近的情况下较为显著，如同行信号过孔501中，不同差分对单元的相邻信号过孔501之间，其导致的干扰与信号过孔501之间的互容正相关；磁场耦合则普遍存在，其导致的干扰与信号过孔501之间的互感大小正相关。
从干扰的来源出发，抑制电场耦合应当从减小互容着手，主要的方式是减小攻击孔(产生串扰信号的信号过孔501)和受害孔(被串扰的信号过孔501)的正对面积或者拉远彼此的距离；抑制磁场耦合应当从减小互感着手，主要的方法是改善信号过孔501的回流，设置就近参考地孔，避免返回电流跨越分割，约束电磁场的分布。
基于以上工作原理，如图7所示，本申请实施例提供的印刷电路板构造了一种“C”型地孔阵列(主接地孔502及第一辅助接地孔503)，隔离并减小不同差分对单元的信号过孔501之间的正对面积以降低电场耦合。另外，通过地孔阵列改善信号过孔501的回流，将各个差分对单元的信号过孔501的电磁场约束在“C”型地孔阵列内从而降低磁场耦合，最终达成孔孔耦合的抑制。
参考图8，图8示例出了不同的差分对单元之间的串扰情况，为方便描述，根据串扰情况将差分对单元划分为干扰对和受扰对。其中，干扰对指代的是发送的信号干扰其他差 分对单元的差分对单元，受扰对指代的是受到其他差分对单元的信号干扰的差分对单元。
对于位于同行的干扰对和受扰对1，各自的其中一个信号过孔位置临近，如干扰对的第一信号过孔5011和受扰对1的第二信号过孔5012，倘若第一信号过孔5011和第二信号过孔5012之间间隔以一个常规地孔，则隔离的效果不足，因此在本申请实施例中采用“梅花”状的主接地孔502，通过主孔以外的从孔增大了单个主接地孔502的直径，从两侧的信号过孔(第一信号过孔5011和第二信号过孔5012)来看，“梅花”状的主接地孔502使得回流路径的面积增大，同时主接地孔502两侧的信号过孔直接的电场耦合得到了更大面积的屏蔽，因此“梅花”状主接地孔502显著发挥了降低干扰对对受扰对1的串扰的作用。
然后，考虑干扰对对受扰对2的串扰，虽然通常大多数封装会对相邻行进行偏移以降低相邻行差分对的串扰，然而，在速率提高到50Gbps+情况下，这种偏移已经无法保证在高带宽内足够的低封装串扰效果。因此，在差分对单元的两信号过孔中间偏移向上的位置设置一个第一辅助接地孔503，通过第一辅助接地孔503有效隔离了干扰对对受扰对2的串扰。
须知，“梅花”形的主接地孔502和第一辅助接地孔503不是仅仅发挥以上作用降低串扰的作用，还具备其他作用，例如“梅花”形的主接地孔502还可改善差分对的回流，差分对的电磁场更多约束在差分对单元附近，减少了对远处其他差分对单元的临近地孔(主接地孔502或第一辅助接地孔503)的参考，因此也能降低隔行的差分对单元之间的串扰。
在本申请实施例中，应当把“梅花”形的主接地孔502和第一辅助接地孔503视作一个整体，在一个具有多个差分对单元的印刷电路板中，例如图8中所示的多组“梅花”形的主接地孔502和第一辅助接地孔503构成的“C”型屏蔽结构屏蔽分别包围多个差分对单元，从而确保信号在沿孔垂直于印刷电路板的设置面方向(Z方向)传播时，各差分对单元之间具备良好的垂直屏蔽结构以隔离串扰。
由上述描述可看出，本申请提供的“C”形屏蔽结构可屏蔽差分对单元的作用，主要改善了孔孔耦合串扰。但是，本申请实施例中的印刷电路板并非仅仅是简单地考虑串扰的孔孔耦合部分，还可改善孔线耦合串扰和线线耦合串扰。
图9示出了孔线耦合串扰和线线耦合串扰发生的位置示意图。为了便于显示说明信号过孔与走线之间的串扰，仅仅展示了干扰对5052和受扰对5051所在行的过孔(信号过孔及接地孔)，其他行的过孔都被隐藏以便于说明，应理解，在本图9中仅以一个干扰对5052和受扰对5051为例进行的说明。在印刷电路板中存在多个差分对单元时，可存在多个如图9相类似的结构。孔线耦合串扰和线线耦合串扰在任何印刷电路板中均有发生，在信号速率低的情况下，由于有效带宽较低，这孔线耦合和线线耦合相对较小，然而在速率提高以及串扰的规格要求提升后，这孔线耦合和线线耦合的作用不可忽视甚至可能是关键瓶颈。
在干扰对5051和受扰对5052与印刷电路板内的走线连接时，干扰对5051中的信号过孔连接走线5062，受扰对5052中的信号过孔连接走线5061。走线5052和走线5061之间间隔有接地层505，为区分其他的接地层，将接地层505命名为第一接地层。第一接地层的两侧的走线层的走线(5061及5062)位于第一接地层的反焊盘504的外侧。
走线5062在布线时，距离干扰对5051较近。串扰耦合最严重的区域在两者(干扰对5051与走线5062)交叉相邻的位置。对于干扰对5051来说，其干扰最强的是穿过走线5061所在层附近的部分。对于走线5061来说，其受扰最严重的是它经过干扰对5051附近的部 分。产生干扰的干扰对5051垂直于印刷电路板的设置面，而受扰的走线5061是位于印刷电路板内且平行于设置面，因此干扰的传递方向主要是三维，所以不能仅仅靠接地孔组成的屏蔽结构调整改善孔线耦合串扰，还需通过接地层隔离干扰沿垂直方向传递的分量。
对于接地层而言，它的掏空通常就是信号过孔的反焊盘504，因此接地层隔离干扰的效果取决于反焊盘504的尺寸，反焊盘504的尺寸越大，接地层上的非金属区域越大，信号穿过接地层的可能性就大，接地层隔离干扰的效果就差；反之，反焊盘504的尺寸较小，接地层的金属区域越小，接地层的隔离干扰的效果就越好。而在本申请实施例中，对于差分对单元中的信号过孔对采用双反焊盘504，一对信号过孔的中间接地层保持互连互通不割裂，使得接地层产生掏空的区域最小化，最大程度抑制干扰沿垂直方向传递的分量传递，也就在“C”形屏蔽结构隔离的基础上进一步提升了孔线耦合的抑制。
在线线耦合串扰中，考虑受扰走线为走线5061，侵扰走线为走线5062，他们彼此不在同一层但是共用了一个接地层505。由于信号过孔在接地层需要对应设置反焊盘504504，因此在接地层505无法做到完全封闭没有开孔，造成走线5062的能量能够透过反焊盘504耦合到隔层的走线5061。因此反焊盘504开孔的面积对线线耦合有较大影响。而在本申请实施例中，反焊盘504与信号过孔一一对应，使得反焊盘504的开孔较小，只有波长较短的信号可通过反焊盘504，波长较长的信号无法通过反焊盘504，因此可抑制更多的线线耦合干扰。从另一个角度来看，双反焊盘504保留了一对信号过孔中间的接地层的连接，使得反焊盘504对信号回流的干扰更小，走线5061和走线5062不会因为彼此较大的回流路径有较强的互感，产生的耦合相对较小。
由上述描述可以看出，干扰信号不是单一沿垂直于设置面方向传播，也不是单一沿平行于设置面方向传播的，干扰信号的传播方向是三维的。因此，本申请实施例提供的印刷电路板通过双反焊盘504和地孔阵列不是分别单独地对垂直方向干扰和水平方向干扰起作用，而是通过双反焊盘504和地孔阵列构成封装区域内的一个三维整体屏蔽结构，在有限空间内给信号提供各方向的就近回流参考，从而抑制干扰信号传递。在印刷电路板的多层空间内，双反焊盘504优化了接地层的分割，改善了平面回流，地孔阵列改善了垂直方向上的回流，地孔阵列和采用双反焊盘504的接地层将印刷电路板内的空间划分为一个个小尺寸的网格单元，信号穿过一个个网格单元均具有良好的回流参考，从而抑制了干扰的对外传递。
图10示出了本申请实施例提供的印刷电路板的另一示意图。印刷电路板包含多个差分对单元，每个差分对单元包括两个信号过孔604，信号过孔604沿Z方向穿过印刷电路板的部分层结构。
参考图11，图11示出了差分对单元的排布示意图。多个差分对单元呈阵列排列。第一行差分对单元中包含信号过孔A1、B1、C1、D1、E1、F1；第二行差分对单元包括信号过孔A2、B2、C2、D2、E2、F2；第三行差分对单元包括信号过孔A3、B3、C3、D3、E3、F3。应理解，在图11中仅以三行差分对单元为例进行说明，在实际的印刷电路板中，可根据实际需要设置不同行数的差分对单元。
一并参考图12，图12示出了一个差分对单元及对应的屏蔽结构。每个差分对单元包括两个信号过孔601。对应于信号过孔601穿过的各接地层上对应设置的圆形的反焊盘604604。屏蔽结构包括主接地过孔602和三个辅助接地孔603，三个辅助接地孔603分别为设置在两个信号过孔601之间的第一辅助接地孔，以及位于主接地孔602和信号过孔601 之间的第二辅助接地孔。
以一个差分对单元的信号过孔601排列的方向为第二方向(X方向)，其垂直方向称第一方向(Y方向)，即第一方向为平行于设置面，且垂直于两个信号过孔601排列方向的方向。沿第二方向在信号过孔601两侧各有一个主接地孔602。主接地孔602由主孔和四个从孔构成，从孔以主孔为中心分布于地孔四周，且任一从孔通过其金属化的孔壁或其连接的地平面与主孔形成电气连接。应理解，在一些示例中，单个主孔的从孔可以少于本实施例的数目，但从孔的个数应不少于一个。从孔在分布时，需要使得主接地孔602整体在第一方向上的宽度增大，即达到每个主接地孔602在第一方向的宽度大于每个信号过孔601在第一方向的宽度，从而提升屏蔽效果。另外，主接地孔602设置时，两个主接地孔602的中心点连线与两个信号过孔601的中心点连线重叠，以方便排布更多行的差分对单元。
在设置辅助接地孔603时，辅助接地孔603的中心点位于两个信号过孔601的中心点连线的一侧，以便于与主接地孔602配合形成C形的屏蔽结构。如图12中所示，三个辅助接地孔603分布于信号过孔601的一侧，并同主接地孔602组成C形的屏蔽结构。在一些实现中，辅助接地孔603可以少于本实施例的数目，但不少于一个，且至少有一个辅助接地孔603在差分对单元的两个信号过孔601之间，以同地孔构成“C”型地孔屏蔽阵列。
一并参考图11及图12，沿第二方向排布的相邻差分对单元共用一个主接地孔602，差分对单元沿第二方向的间距可为1.3mm。以孔中心为参考，在10.8mm内一行可以排布三个差分对单元。在本实施例中，相邻行的间距为1.8mm，为了避免信号过孔在第一方向上垂直正对导致较强的串扰，第二行相对于第一行向左沿第二方向偏移，示例性的，偏移距离可为1mm。除采用行错位改善不同行的差分对单元串扰外，还通过设置辅助接地孔603减少相邻行的差分对单元之间的串扰。沿第二方向看，不同单元的多个辅助接地孔603和多主接地孔602构成一行地孔阵列，形成行间串扰的有效屏蔽。由上述描述可看出，辅助接地孔603与主接地孔602配合构成对差分对单元的“C”型屏蔽结构，仅在信号过孔沿第一方向的一侧开放以便走线出线。
在本实施例中，信号过孔601的侧壁上电镀金属以形成导电层传递信号，在一些实现中，信号过孔601的金属层可以贯穿整个印刷电路板厚度，也可以以盲孔或者背钻的工艺形式不贯穿整个印刷电路板厚度。把垂直于印刷电路板厚度的方向称第三方向(Z方向)，它垂直于第二方向和第一方向所在的平面。对于主接地孔602和辅助接地孔603，其孔侧壁金属层沿第一方向上的长度应不小于信号过孔601沿第一方向上的长度。过孔侧壁金属包括不限于铜、铝、银等导电金属材料，其加工工艺包括不限于电镀、蒸镀、溅射、化学镀或气相沉积等方式。
印刷电路板内部设置有用于信号参考的接地层，针对一个差分对单元，在其通过的各接地层上应用了与差分对单元的每个信号过孔对应的反焊盘604，即采用双反焊盘604与一个差分对单元的信号过孔604对应。双反焊盘604既实现了接地层避让参考信号和过孔阻抗控制的常规作用，还保留了接地层在信号过孔中间的互连，使得单个反焊盘604在接地层上的开孔较小，并且同前面的地孔屏蔽阵列构成三维横纵交错的接地互连网格，同时提升对孔孔耦合、孔线耦合和线线耦合的串扰抑制效果。在一些其他实现中，反焊盘的形状包括不限于圆形、矩形、方形、椭圆形等，但需要确保双反焊盘能够保留接地层在信号过孔中间的互连。
在本实施例中，主接地孔602的主孔为压接过孔，从孔分布于主孔的四周，由于从孔 不需要容纳连接器引脚，其孔径可以做得更小而且通常其过孔焊盘也会做得相对较小。
参考图13，图13示出了本申请实施例提供的另一种屏蔽结构的示意图。印刷电路板上的过孔包括信号过孔6001、主接地孔6002、辅助接地孔6003。主接地孔6002是包含了两个主孔60021和一个从孔60022的主从式地孔，从孔60022位于两个主孔60021之间，并与分别与主孔60021连通并导电连接。示例性的，从孔60022位于两个主孔60021的中间，三者沿第一方向排列，或相对第一方向倾斜的方向排列。
两个主孔60021同连接器接地引脚相连接，而从孔60022不同连接器引脚直接相连，而其利用其孔内的侧壁金属连通两个主孔60021，使得整个主从式地孔6002在第一方向上的宽度显著大于信号过孔6001在第一方向上的宽度，从而改善了在第一方向上同行间不同差分对单元之间的隔离度。此外，辅助接地孔在差分对单元的两过孔6001中心的第一方向上，以同主接地孔6002构成“C”型地孔屏蔽阵列。特别地，为了配合“C”型地孔屏蔽阵列，需要在信号过孔6001穿过的参考地平面6005上设置双反焊盘6004。在图13中反焊盘6004采用矩形形状。
为方便理解本申请实施例提供的印刷电路板对信号串扰的效果，对本申请实施例提供给的印刷电路板和现有技术中的印刷电路板进行全波仿真，仿真结果参考表1，在表1中以图10中的C2D2为干扰对，分别考虑其周边八个差分对同时带来近端或远端串扰时的综合串扰。
表1
Figure PCTCN2021127092-appb-000001
由表1可看出，本实施例提供的印刷电路板与现有常规的印刷电路板相比，具备更低的孔间耦合串扰效果。此外，本实施例采用的双反焊盘，最大程度抑制层偏导致的孔线耦合和线线耦合劣化。
在印刷电路板制备时，由于各层制备时的偏差使得反焊盘沿第二方向偏离7mil时，相对于传统的单反焊盘掏空设计，双圆反焊盘配合“C”型屏蔽地孔阵列的孔线耦合抑制收益达到MDNEXT收益3.6dB@14GHz和4.1dB@28GHz，MDFEXT收益3.6dB@14GHz和4.8dB@28GHz。
在层偏使得反焊盘沿第二方向偏离7mil时，相对于传统的单反焊盘掏空设计，双圆反焊盘配合“C”型屏蔽地孔阵列的线线耦合抑制收益达到MDNEXT收益4.2dB@14GHz和6.1dB@28GHz，MDFEXT收益6.6dB@14GHz和6.2dB@28GHz。
图14示出了与芯片配合的印刷电路板的过孔及接地孔的排布示意图，图15为图14对应的三维结构示意图。
印刷电路板上一部分对应于芯片所有引脚的焊盘及其相应的过孔区域，印刷电路板具有多组差分对单元。如图14所示，本实施例的芯片焊盘2012按行和列呈4×8等间距矩阵式分布，在其他一些实施方式中芯片焊盘可以按照等间距或不等间距地按一定规律周期 性分布。在4×8个芯片焊盘2012内，可以高密度地排布8对差分对单元，同时具备良好的信号完整性。根据分配的信号网络属性不同，芯片焊盘2012分为信号焊盘20121和接地焊盘20122，分别对应于芯片的信号引脚和接地引脚。为方便描述，将一对信号焊盘20121所在的直线为第一方向，沿印刷电路板平面垂直于第一方向的方向为第二方向。
沿第一方向，两个临近的芯片信号焊盘20121为一组差分对单元，在信号焊盘20121两侧各有一个接地焊盘20122，相邻的两组差分对单元之间间隔以一个接地焊盘20122。沿第二方向，两组最临近的差分对单元之间在第一方向上错位一个芯片焊盘间隔的长度，以避免相邻行的两组差分单元对正对造成较大的串扰。
尽管以上排布已经通过间隔接地焊盘和隔行差分对单元错位的方法来尽量降低串扰，在紧凑的空间内信号焊盘、走线间仍将有较明显的封装串扰制约链路性能。
为了将芯片焊盘上的信号引出到印刷电路板不同层走线，在芯片焊盘20121中间设置信号过孔2013，其钻孔直径为8mil，通常采用盘中孔工艺来完成。为了隔离不同差分对单元的信号过孔2013之间的串扰，同时为信号过孔2013传输的信号提供接地返回路径，在接地焊盘20122中间设置主接地过孔2014，它由沿第二方向上分布的三个接地过孔构成，钻孔直径都是8mil，在第二方向上各过孔的中心距离为7mil。其中，位于接地焊盘20122的过孔为主孔，沿第二方向分布的两侧过孔为从孔，两个从孔的孔壁金属都与主孔的孔壁金属电气相连，从而使得三个过孔形成的主接地过孔2014在第二方向上的长度大于信号过孔2013在第二方向上的长度，以有效地隔离沿第一方向上相邻差分对单元之间的串扰。
此外，在任一差分对单元的两信号焊盘20121中间，沿第二方向向上7mil的位置设置一个辅助接地孔2015，其钻孔直径为8mil。辅助接地孔2015能有效地改善相邻行间的差分对单元之间的串扰。在一对差分对单元内，一个辅助接地孔2015配合两侧的主接地过孔2014，构成了“C”型地孔屏蔽，从整个封装来看，多个这种组合形成了封装内的“C”型地孔屏蔽阵列，有效改善了孔孔耦合串扰。
在本实施例中，芯片焊盘2012所在的顶层不设置参考地平面，而在印刷电路板内层按照设计需要设置了多层接地层2011。为了避让信号过孔2013，在信号过孔2013穿过的接地层2011上以信号过孔为中心对接地层2011掏空金属构成反焊盘2016，它在本实施例中的形状为圆形。应立即，上述的主接地过孔2014和辅助接地孔2015均需要同参考接地层2011相连。双反焊盘2016配合“C”型地孔屏蔽阵列，能够有效地改善封装区域内的线线耦合串扰和孔线耦合串扰。
本申请实施例还提供了一种背板架构系统，该背板架构系统包括背板以及与背板连接的连接器。具体连接方式可参考图1中的连接方式。背板为上述任一项的印制电路板。在上述技术方案中，通过采用每个信号对应一个反焊盘，且反焊盘之间间隔了地层，从而降低了信号过孔或隔层走线的信号穿过反焊盘后干扰走线，改善了印刷电路板内的串扰问题。另外，通过主接地孔和第一辅助接地孔组成屏蔽结构，降低了差分对单元与其他差分对单元之间的串扰，改善了印制电路板的串扰问题，便于印制电路板上插孔的密集化设置。
本申请实施例还提供了一种通信设备，该通信设备可为基站或者机房内的机柜等通信装置，该通信设备包括机框以及上述任一项所述的印制电路板，所述印制电路板被插入所述机框内。在上述技术方案中，通过采用每个信号对应一个反焊盘，且反焊盘之间间隔了地层，从而降低了信号过孔或隔层走线的信号穿过反焊盘后干扰走线，改善了印刷电路板内的串扰问题。另外，通过主接地孔和第一辅助接地孔组成屏蔽结构，降低了差分对单元 与其他差分对单元之间的串扰，改善了印制电路板的串扰问题，便于印制电路板上插孔的密集化设置。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

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  1. 一种印制电路板，其特征在于，包括层叠设置的多个层结构；所述多个层结构中包括交替排布的接地层和走线层；所述多个层结构中位于最外层的层结构具有设置面；
    所述印制电路板还包括设置在所述设置面的差分对单元以及用于屏蔽所述差分对单元的屏蔽结构；
    所述差分对单元包括两个信号过孔，每个信号过孔穿过至少部分的接地层和走线层，并与其中的一个走线层上的走线连接；每个信号过孔穿过的接地层设置有与该信号过孔对应的反焊盘，且所述两个信号过孔对应的反焊盘之间间隔排列；
    所述屏蔽结构包括设置在所述设置面的两个主接地孔以及第一辅助接地孔，所述两个主接地孔位于所述差分对单元的两侧，所述第一辅助接地孔位于所述两个信号过孔之间；所述主接地孔及所述第一辅助接地孔分别穿设过部分所述走线层和接地层，且所述主接地孔和第一辅助接地孔分别与穿设过的接地层接地连接。
  2. 根据权利要求1所述的印制电路板，其特征在于，第一接地层的两侧的走线层的走线位于所述第一接地层的反焊盘的外侧；其中，所述第一接地层为所述每个信号过孔穿设过的接地层。
  3. 根据权利要求1所述的印制电路板，其特征在于，所述差分对单元的个数为多个，且相邻的差分对单元之间的主接地孔共用。
  4. 根据权利要求3所述的印制电路板，其特征在于，每个主接地孔在第一方向的宽度大于所述每个信号过孔在所述第一方向的宽度；
    所述第一方向为平行于所述设置面，且垂直于所述两个信号过孔排列方向的方向。
  5. 根据权利要求4所述的印制电路板，其特征在于，每个主接地孔包括主孔，以及环绕所述主孔的至少一个从孔；其中，所述主孔与每个从孔连通并导电连接。
  6. 根据权利要求4所述的印制电路板，其特征在于，每个主接地孔包括两个主孔，以及位于所述两个主孔之间的从孔；其中，所述从孔分别与所述两个主孔连通并导电连接。
  7. 根据权利要求1～6任一项所述的印制电路板，其特征在于，所述两个主接地孔及所述第一辅助接地孔组成包裹所述差分对单元的C形屏蔽结构。
  8. 根据权利要求7所述的印制电路板，其特征在于，在所述主接地孔包括主孔以及环绕所述主孔的至少一个从孔时，
    所述两个主接地孔的中心点连线与所述两个信号过孔的中心点连线重叠。
  9. 根据权利要求7或8所述的印制电路板，其特征在于，所述第一辅助接地孔的中心点位于所述两个信号过孔的中心点连线的一侧。
  10. 根据权利要求7或8所述的印制电路板，其特征在于，所述第一辅助接地孔的个数为两个，且两个所述第一辅助接地孔的中心点分别位于所述两个信号过孔的中心点连线的两侧。
  11. 根据权利要求7～10任一项所述的印制电路板，其特征在于，所述屏蔽结构还包括设置在所述主接地孔与相邻的信号过孔之间的第二辅助接地孔。
  12. 一种背板架构系统，其特征在于，包括背板以及与背板连接的连接器；其中，所述背板为如权利要求1～11任一项所述的印制电路板。
  13. 一种通信设备，其特征在于，包括机框以及如权利要求1～11任一项所述的印制电 路板，所述印制电路板被插入所述机框内。
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CN115767884A (zh) * 2022-11-25 2023-03-07 维沃移动通信有限公司 电路板组件及电路板组件的制备方法
CN116682800B (zh) * 2023-06-08 2024-02-23 合芯科技有限公司 一种导体结构、半导体封装结构及电路板
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