WO2022077564A1 - 驱动电路板及其制作方法 - Google Patents

驱动电路板及其制作方法 Download PDF

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Publication number
WO2022077564A1
WO2022077564A1 PCT/CN2020/124478 CN2020124478W WO2022077564A1 WO 2022077564 A1 WO2022077564 A1 WO 2022077564A1 CN 2020124478 W CN2020124478 W CN 2020124478W WO 2022077564 A1 WO2022077564 A1 WO 2022077564A1
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WO
WIPO (PCT)
Prior art keywords
layer
terminal
circuit board
driving circuit
protective layer
Prior art date
Application number
PCT/CN2020/124478
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English (en)
French (fr)
Inventor
罗传宝
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/734,492 priority Critical patent/US20220123030A1/en
Publication of WO2022077564A1 publication Critical patent/WO2022077564A1/zh
Priority to US18/354,321 priority patent/US20230361134A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

Definitions

  • the present application relates to the field of display, and in particular, to a driving circuit board and a manufacturing method thereof.
  • the driving circuit board in the backlight module of the existing display device has a complicated manufacturing process, requiring 7 masks to form, and the high temperature process in the driving circuit board easily leads to oxidation of the metal layer in the driving circuit board, which affects the product quality.
  • the present application provides a driving circuit board and a manufacturing method thereof, which are used to solve the problem that the driving circuit board in the backlight module of the existing display device affects the product quality due to the complicated manufacturing process.
  • the application provides a driving circuit board, the driving circuit board includes a substrate, a thin film transistor located on the substrate, and a first terminal and a second terminal located on both sides of the thin film transistor;
  • At least one metal layer in the first terminal and/or the second terminal is provided in the same layer as the gate layer and/or the source/drain layer in the thin film transistor.
  • the first terminal and the second terminal include a metal layer disposed on the same layer as the gate layer.
  • the driving circuit board further includes a first protective layer on the gate layer, the first terminal, and the second terminal;
  • the material of the first protective layer is metal oxide.
  • the driving circuit board further includes a connection terminal located on the second terminal, and the connection terminal passes through at least one first opening between the connection terminal and the second terminal Electrically connected to the second terminal, the first opening is located on the first protective layer corresponding to the second terminal.
  • the driving circuit board further includes a light source corresponding to the second terminal, and the light source is electrically connected to the second terminal through the first opening.
  • the driving circuit board further includes a second protective layer located on the source-drain layer or/and the connection terminal;
  • the material of the second protective layer is at least one of metals or alloys of molybdenum, titanium and nickel.
  • the connecting terminal is electrically connected to the light source through at least one second opening between the connecting terminal and the light source, and the second opening is located in the first opening corresponding to the connecting terminal. on the second protective layer.
  • a first angle formed between the first side surface of the first protective layer and the substrate is less than or equal to 90 degrees.
  • the second angle formed by the second side surface of the second protective layer and the substrate is less than or equal to 90 degrees.
  • the first surface of the first protective layer in contact with the connection terminal may be provided with a plurality of first protrusions and/or a plurality of first concave surfaces;
  • the first protective layer is nested with the connection terminal through the first protrusion and/or the first concave surface.
  • the material of the first protective layer is at least one of indium tin oxide or indium zinc oxide.
  • the thickness of the first protective layer is 600 angstroms to 1800 angstroms.
  • the third side surface of at least one of the first terminal, the gate layer, the source-drain layer, or the second terminal is formed with the substrate.
  • the third included angle is greater than 30 degrees and less than 75 degrees.
  • the present application also provides a method for manufacturing a drive circuit board, comprising:
  • the third metal layer is subjected to a first predetermined process to form a second protective layer
  • the first metal layer includes a gate layer of a thin film transistor of the driving circuit board, a first terminal and a second terminal located on both sides of the thin film transistor;
  • the second metal layer includes a source and drain layer of the thin film transistor and a connection terminal on the second terminal.
  • the thickness of the first metal layer is 4000 angstroms to 9600 angstroms.
  • the steps of forming the first metal layer and the first protective layer on the substrate include:
  • the first metal material layer and the first metal oxide layer are patterned to form the first metal layer and the first protective layer.
  • the steps of forming the second metal layer and the third metal layer on the first protective layer include:
  • a second metal layer and a third metal layer are formed on the active layer.
  • the step of forming the second protective layer on the third metal layer through the first predetermined process includes:
  • the third metal layer corresponding to the connection terminal is removed to form the second protective layer.
  • the third metal layer corresponding to the connecting terminal is removed by dry etching with plasma under a first power and a first fluorine-to-oxygen ratio.
  • the first power is 10.4 kilowatts to 26.4 kilowatts
  • the first fluorine-oxygen ratio is 2.4:1 to 7.2:1.
  • the mask used in the process of the driving circuit board is reduced It simplifies the manufacturing process, saves the manufacturing cost of the product, and improves the product yield.
  • FIG. 1 is a schematic diagram of the first structure of the driving circuit board of the present application.
  • FIG. 2 is a schematic diagram of a second structure of the driving circuit board of the present application.
  • FIG. 3 is a schematic diagram of a third structure of the driving circuit board of the present application.
  • FIG. 4 is a flowchart of a manufacturing method of a driving circuit board of the present application.
  • 5a to 5g are schematic diagrams of a manufacturing method of a driving circuit board of the present application.
  • the present application provides a driving circuit board and a manufacturing method thereof.
  • the present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.
  • the driving circuit board in the backlight module of the existing display device has a problem of affecting product quality due to the complicated manufacturing process. Based on this, the present application proposes a driving circuit board and a manufacturing method thereof.
  • the driving circuit board 100 includes a substrate 101 , a thin film transistor 102 located on the substrate 101 , and a first terminal 103 and a second terminal 104 located on both sides of the thin film transistor 102 .
  • At least one metal layer in the first terminal 103 and/or the second terminal 104 is disposed in the same layer as the gate layer and/or the source/drain layer 106 in the thin film transistor 102 .
  • the thin film transistor 102 may be a bottom gate type thin film transistor, or a top gate type thin film transistor or other types of thin film transistors, which are not specifically limited herein.
  • the driving circuit board 100 can be used in a backlight module of a display device.
  • the material of the metal layer may be molybdenum or molybdenum-copper alloy. at least one.
  • the material of the metal layer may include molybdenum, titanium, copper At least one of metals or alloys, such as molybdenum/copper alloy, molybdenum titanium/copper alloy, etc.
  • the first terminal 103 may be used for electrical connection between the driving circuit board 100 and other components in the display device, such as electrical connection with a chip on film.
  • the second terminal 104 may be used to form an electrical connection with the light source.
  • the driving circuit board 100 further includes a gate insulating layer and an active layer between the gate layer 105 and the source and drain layers 106 .
  • the material of the gate insulating layer may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, aluminum oxide, and aluminum nitride.
  • the gate insulating layer may be formed of a single material, such as silicon oxide and aluminum nitride; the gate insulating layer may also be formed by stacking multiple materials, such as being formed of a stack of silicon oxide and silicon nitride, or It is formed by laminating silicon oxide, silicon nitride, and silicon oxynitride, or laminating silicon oxide, silicon nitride, and aluminum oxide.
  • the gate layer 105 is formed by stacking multiple materials, the stacking manner between different materials is not specifically limited herein.
  • the driving circuit board 100 further includes a passivation layer on the source and drain layers 106 .
  • the material of the passivation layer may include at least one of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride.
  • the passivation layer can be formed from a single material, such as silicon oxide or aluminum nitride; the passivation layer can also be formed by stacking multiple materials, such as silicon oxide and silicon nitride stacks or oxides Silicon, silicon nitride and aluminum oxide are formed by stacking layers, and the stacking method between different materials is not specifically limited herein.
  • At least one metal layer in the first terminal 103 or the second terminal 104 is disposed in the same layer as the gate layer 105 and/or the source/drain layer 106 , thereby reducing the mask used in the process of driving the circuit board 100 It simplifies the manufacturing process, saves the manufacturing cost of the product, and improves the product yield.
  • the first terminal 103 and the second terminal 104 include a metal layer disposed at the same layer as the gate layer 105 .
  • the driving circuit board 100 further includes a first protective layer 107 on the gate layer 105 , the first terminal 103 , and the second terminal 104 .
  • the material of the first protective layer 107 is metal oxide.
  • the metal layers of the first terminal 103 and the second terminal 104 may be formed of the same material and the same process as the gate layer 105 .
  • the first terminal 103 and the second terminal 104 may be formed of only one metal layer.
  • the first protective layer 107, the gate layer 105, the first terminal 103, and the second terminal 104 may be formed in the same process.
  • the material of the first protective layer 107 may be at least one of indium tin oxide, indium zinc oxide or other metal oxides.
  • the setting of the first protective layer 107 is used to avoid forming the gate layer 105, the first terminal 103, and the metal material of the second terminal 104, such as copper metal, on the driving circuit board
  • metal ions enter other film layers, such as the gate insulating layer, and the performance of the driving circuit board 100 is affected. And it affects the quality of products using the driving circuit board 100 .
  • the metal layers of the first terminals 103 and the second terminals 104 are disposed in the same layer as the gate layer 105 , so that the metal layers of the first terminals 103 and the second terminals 104 are the same as those of the gate layers 105 .
  • the gate layer 105 can be formed by the same process and the same material, which reduces the number of masks used in the process of the driving circuit board 100, simplifies the process, saves the manufacturing cost of the product, and improves the product yield.
  • this embodiment is the same as or similar to the first embodiment, the difference is:
  • the driving circuit board 100 further includes a connection terminal 109 located on the second terminal 104 , and the connection terminal 109 passes through at least a first connection between the connection terminal 109 and the second terminal 104 .
  • An opening 110 is electrically connected to the second terminal 104 , and the first opening 110 is located on the first protective layer 107 corresponding to the second terminal 104 .
  • connection terminals 109 may be disposed in the same layer as the source and drain layers 106 .
  • connection terminals 109 and the source and drain layers 106 may be formed of the same material and in the same process.
  • connection terminal 109 When the connection terminal 109 is electrically connected to the second terminal 104 through the first opening 110 , the connection terminal 109 and the first protective layer 107 are increased by the arrangement of the first opening 110 . It is beneficial to increase the adhesion between the connection terminal 109 and the first protective layer 107, and is beneficial to prevent the connection terminal 109 from detaching from the first protective layer 107, resulting in the The quality of the driving circuit board 100 is affected; in addition, through the arrangement of the first opening 110 , the connection terminal 109 can be in direct contact with the second terminal 104 , reducing the number of the connection terminal 109 and the second terminal The resistance between 104 is beneficial to reduce the power consumption of the driving circuit board 100 during use.
  • connection terminal 109 may be used for electrical connection between the light source and the second terminal 104 .
  • the first surface of the first protective layer 107 in contact with the connection terminal 109 may be provided with a plurality of first protrusions and/or a plurality of first concave surfaces.
  • the first protective layer 107 is nested with the connection terminal 109 through the first protrusion and/or the first concave surface.
  • the nested arrangement of the first protective layer 107 and the connecting terminal 109 is beneficial to increase the contact area between the connecting terminal 109 and the first protective layer 107 , and enhance the connection between the connecting terminal 109 and the first protective layer 107 .
  • the adhesion between the protective layers 107 is beneficial to prevent the connection terminals 109 from being detached from the first protective layer 107 , resulting in the quality of the driving circuit board 100 being affected.
  • the driving circuit board 100 further includes a light source corresponding to the second terminal 104 , and the light source is electrically connected to the second terminal 104 through the first opening 110 .
  • the light source may be a light emitting diode.
  • the light source is electrically connected to the second terminal 104 through a surface mount process.
  • the bonding force with the solder paste is weak, therefore, Through the arrangement of the first opening 110 , the solder paste is in direct contact with the second terminal 104 , which enhances the adhesion between the solder paste and the second terminal 104 , which is beneficial to avoid the first protective layer 107
  • the setting will lead to insufficient adhesion of the solder paste, causing the light source to fall off.
  • connection terminal 109 Since the material of the connection terminal 109 is a metal material, which is conducive to the adhesion of solder paste, the setting of the connection terminal 109 also avoids that the setting of the first protective layer 107 causes insufficient adhesion of the solder paste, causing the Falling off of the light source.
  • the protection of the connection terminal 109 and the first protection is improved.
  • the adhesion between the layers 107 is beneficial to prevent the connection terminals 109 from detaching from the first protective layer 107; when the light source and the second terminals 104 are electrically connected through the first opening 110, It is beneficial to avoid the insufficient adhesion of the solder paste due to the disposition of the first protective layer 107 and the falling off of the light source.
  • this embodiment is the same as or similar to Embodiment 1 and Embodiment 2, except that:
  • the driving circuit board 100 further includes a second protective layer 108 located on the source and drain layers 106 or/and the connection terminals 109 .
  • the material of the second protective layer 108 is at least one of metals or alloys of molybdenum, titanium, and nickel, such as molybdenum-titanium alloy, titanium, nickel metal, and the like.
  • the second protective layer 108 may be formed in the same process as the source/drain layer 106 or/and the connection terminal 109 .
  • the material of the second protective layer 108 is a metal that is resistant to high temperature and oxidation, and is used to avoid forming the metal material of the source and drain layers 106 or/and the connection terminals 109, such as copper metal, during the driving process.
  • the circuit board 100 is oxidized due to the high temperature process, which affects the performance of the driving circuit board 100 and affects the quality of products using the driving circuit board 100 .
  • the second protective layer 108 may be located on the source and drain layers 106 .
  • the second protective layer 108 may also be located on the source and drain layers 106 and the connection terminals 109 .
  • connection terminal 109 is electrically connected to the light source through at least one second opening between the connection terminal 109 and the light source, and the second opening is located at the second opening corresponding to the connection terminal 109 . on the protective layer 108 .
  • the solder paste is in direct contact with the connection terminals 109, which improves the adhesion of the solder paste and helps to avoid the adhesion of the solder paste caused by the arrangement of the first protective layer 107. Insufficient, causing the light source to fall off, affecting product quality.
  • the arrangement of the second protective layer 108 is beneficial to avoid oxidation of the source-drain layer 106 or/and the connection terminal 109 in the subsequent process of the driving circuit board 100 , thereby improving product quality;
  • the second protective layer 108 can be formed in the same process as the source/drain layer 106 or/and the connection terminal 109 , which avoids adding additional processes, and saves process costs while improving product quality.
  • the first angle formed between the first side surface of the first protective layer 107 and the substrate 101 is less than or equal to 90 degrees, and/or the second side surface of the second protective layer 108 is The second included angle formed by the substrate 101 is less than or equal to 90 degrees.
  • the first included angle is greater than 90 degrees, the side of the first protective layer 107 away from the substrate 101 forms an acute angle with the first side surface, which is easy to pierce other parts around the first protective layer 107
  • a film layer, such as a gate insulating layer, causes the performance of the driving circuit board 100 to be affected.
  • the side of the second protective layer 108 away from the substrate 101 forms an acute angle with the second side surface, which is easy to pierce the second protective layer 108
  • the third side surface of at least one of the first terminal 103 , the gate layer 105 , the source/drain layer 106 , or the second terminal 104 and the substrate 101 The formed third angle is greater than 30 degrees and less than 75 degrees, preferably 45 to 60 degrees. When the third included angle is less than 30 degrees, the third included angle is too small, which will cause a significant delay in signal transmission of the driving circuit board 100; when the third included angle is greater than 75 degrees, the third included angle is too small.
  • the triangular included angle is too large, causing other film layers on the film layer forming the third included angle to break during formation, which affects the product quality of the driving circuit board 100; when the third included angle is between 45 and 60 When the angle is between two degrees, it will neither cause a significant delay in the signal transmission of the driving circuit board 100 nor cause other film layers on the film layer forming the third included angle to be broken during formation.
  • the present application also provides a manufacturing method of the driving circuit board 100 , including:
  • S1 a first metal layer and a first protective layer 107 are formed on the substrate 101 .
  • the first metal layer includes a gate layer 105 of the thin film transistor 102 of the driving circuit board 100 , a first terminal 103 and a second terminal 104 located on both sides of the thin film transistor 102 .
  • step S1 includes:
  • the first metal material layer and the first metal oxide layer may be formed by deposition, such as physical vapor sputtering deposition.
  • the material of the first metal material layer may be at least one of molybdenum or molybdenum-copper alloy.
  • the material of the first metal oxide layer may be at least one of indium tin oxide, indium zinc oxide or other metal oxides.
  • the first metal material layer and the first metal oxide layer are patterned to form the first metal layer and the first protective layer 107 .
  • the first metal layer and the first protective layer 107 may be formed by wet etching.
  • the first metal layer is formed by a first etching solution, and the first etching solution includes hydrogen peroxide.
  • the first protective layer 107 is formed by a second etching solution, and the second etching solution includes oxalic acid.
  • the thickness of the first metal layer may be 4000 to 9600 angstroms, preferably 5000 to 8000 angstroms.
  • the thickness of the first protective layer 107 may be 600 to 1800 angstroms, preferably 750 to 1500 angstroms.
  • the thickness of a protective layer 107 is too small, which is not conducive to the thermal oxidation protection of the first metal layer in the high temperature process and prevents ions in the first metal layer from thermally diffusing into other film layers; when the first protection layer is When the thickness of the layer 107 is greater than 1800 angstroms, the thickness of the first protective layer 107 is too thick, and the resistance of the first protective layer 107 increases significantly, resulting in increased power consumption of the display device using the driving circuit board 100 ; When the thickness of the first protective layer 107 is 750 to 1500 angstroms, the first protective layer 107 will neither be too thin to completely protect the first metal layer in the high temperature process, nor
  • a second metal layer and a third metal layer are formed on the first protective layer 107 .
  • the second metal layer includes the source and drain layers 106 of the thin film transistor 102 and the connection terminal 109 located on the second terminal 104 .
  • the thickness of the second metal layer may be 4000 angstroms to 9600 angstroms, preferably 5000 angstroms to 8000 angstroms.
  • step S2 includes:
  • step S22 includes:
  • the material of the semiconductor layer includes at least one of indium gallium zinc oxide, indium gallium zinc tin oxide, indium zinc oxide, and indium gallium tin oxide.
  • the semiconductor layer is subjected to a second predetermined process to form an active layer.
  • the semiconductor layer is subjected to thermal annealing and photolithography to form the active layer.
  • the etching solution used in the photolithography process may include oxalic acid.
  • the material of the second metal layer may include at least one of molybdenum, titanium, copper metals or alloys, such as molybdenum/copper alloy, molybdenum titanium/copper alloy, and the like.
  • the material of the third metal layer may include at least one of metals or alloys of molybdenum, titanium, and nickel, for example, molybdenum-titanium alloys, titanium, and nickel metals.
  • step S23 includes:
  • the first insulating material layer forms a first insulating layer.
  • the first metal material layer and the third metal material layer are formed on the active layer by physical vapor deposition.
  • the second metal layer and the third metal layer are subjected to a third predetermined process to form the second metal layer and the third metal layer.
  • the second metal layer and the third metal layer may be formed by wet etching.
  • the second metal layer and the third metal layer are formed by a fourth etching solution, and the fourth etching solution includes hydrogen peroxide.
  • the third metal layer is subjected to a first predetermined process to form a second protective layer 108.
  • step S3 includes:
  • step S31 includes:
  • the first insulating layer is processed by a fifth preset process to form a gate insulating layer.
  • the second insulating layer is subjected to a fourth predetermined process to form a passivation layer.
  • the passivation layer includes a third opening corresponding to the first terminal 103 and a fourth opening corresponding to the second terminal 104 .
  • the gate insulating layer includes a fifth opening located between the first terminal 103 and the third opening, and a fifth opening located between the fourth opening and the second terminal 104 Six openings.
  • the fourth opening exposes the third metal layer corresponding to the connection terminal 109 .
  • the gate insulating layer and the passivation layer may be formed by dry etching.
  • the gate insulating layer and the passivation layer may be formed by dry etching with a strong oxidizing gas containing fluorine.
  • the material of the gate insulating layer may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, aluminum oxide, and aluminum nitride.
  • the gate insulating layer may be formed of a single material, such as silicon oxide and aluminum nitride; the gate insulating layer may also be formed by stacking multiple materials, such as being formed of a stack of silicon oxide and silicon nitride, or It is formed by laminating silicon oxide, silicon nitride, and silicon oxynitride, or laminating silicon oxide, silicon nitride, and aluminum oxide.
  • the gate layer 105 is formed by stacking multiple materials, the stacking manner between different materials is not specifically limited herein.
  • the material of the passivation layer may include at least one of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride.
  • the passivation layer can be formed from a single material, such as silicon oxide or aluminum nitride; the passivation layer can also be formed by stacking multiple materials, such as silicon oxide and silicon nitride stacks or oxides Silicon, silicon nitride and aluminum oxide are formed by stacking layers, and the stacking method between different materials is not specifically limited here.
  • the third metal layer corresponding to the connection terminal 109 is removed by etching to form the second protective layer 108 .
  • the second protective layer 108 is formed by dry etching the third metal layer.
  • the second protective layer 108 is formed by dry etching with plasma under a first power and a first fluorine-to-oxygen ratio.
  • the first power may be 10.4 kW to 26.4 kW, preferably 13 kW to 20 kW.
  • the first power does not exceed 26.4 kWh, and the first power is sufficient to meet the requirements for etching the third metal layer corresponding to the connection terminal 109, so the first power does not need to exceed 26.4 kW;
  • the first power is 13 kW to 20 kWh, it can ensure that the etching of the third metal layer corresponding to the connection terminal 109 is fast and sufficient.
  • the first fluorine to oxygen ratio may be 2.4:1 to 7.2:1, preferably 3:1 to 6:1.
  • the plasma contains insufficient fluorine or oxygen, which affects the oxidizing property of the plasma and is not conducive to the third Etching of the metal layer;
  • the first fluorine-to-oxygen ratio is 3:1 to 6:1, the fluorine content and oxygen content of the plasma are appropriate, which ensures the strong oxidizing property of the plasma and makes the connection terminals
  • the etching of the third metal layer corresponding to 109 is fast and sufficient.
  • the driving circuit board 100 when used in a backlight module of a display device, the light source is mounted on the driving circuit board 100 through a surface mount process.
  • At least one metal layer in the first terminal 103 or the second terminal 104 is disposed in the same layer as the gate layer 105 and/or the source/drain layer 106, thereby reducing the number of driving circuits
  • the number of photomasks used in the manufacturing process of the board 100 simplifies the manufacturing process, saves the manufacturing cost of the product, and improves the product yield.
  • the present application proposes a driving circuit board and a manufacturing method thereof.
  • the driving circuit board includes: a substrate, a thin film transistor on the substrate, and a first terminal and a second terminal on both sides of the thin film transistor.
  • at least one metal layer in the first terminal or the second terminal is disposed in the same layer as the gate layer and/or the source and drain layers in the thin film transistor.
  • the mask used in the process of the driving circuit board is reduced It simplifies the manufacturing process, saves the manufacturing cost of the product, and improves the product yield.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Thin Film Transistor (AREA)

Abstract

一种驱动电路板（100）及其制作方法。该驱动电路板（100）包括衬底（101）、位于衬底（101）上的薄膜晶体管（102）、及位于薄膜晶体管（102）两侧的第一端子（103）及第二端子（104）。第一端子（103）或第二端子（104）中的至少一金属层与薄膜晶体管（102）中的栅极层（105）和/或源漏极层（106）同层设置，减少了驱动电路板（100）的工艺制程中使用的光罩，节约了产品的制造成本，提升了产品良率。

Description

驱动电路板及其制作方法 技术领域
本申请涉及显示领域，尤其涉及一种驱动电路板及其制作方法。
 背景技术
随着人们对于显示装置的要求的提升，对于显示装置的背光模组中背板的优化，是一大重要的发展方向。
现有的显示装置的背光模组中的驱动电路板，制程复杂，需要7道光罩才能形成，且其中的高温制程易导致驱动电路板中的金属层氧化，影响产品质量。
因此，亟需一种新的驱动电路板及其制作方法以解决上述技术问题。
 技术问题
本申请提供了一种驱动电路板及其制作方法，用于解决现有的显示装置的背光模组中的驱动电路板由于制程复杂，影响产品质量的问题。
 技术解决方案
本申请提出了一种驱动电路板，所述驱动电路板包括衬底、位于所述衬底上的薄膜晶体管、及位于所述薄膜晶体管两侧的第一端子及第二端子；
其中，所述第一端子和/或所述第二端子中的至少一金属层与所述薄膜晶体管中的栅极层和/或源漏极层同层设置。
本申请提供的驱动电路板中，所述第一端子及所述第二端子包括一与所述栅极层同层设置的金属层。
本申请提供的驱动电路板中，所述驱动电路板还包括位于所述栅极层、所述第一端子、以及所述第二端子上的第一保护层；
其中，所述第一保护层的材料为金属氧化物。
本申请提供的驱动电路板中，所述驱动电路板还包括位于所述第二端子上的连接端子，所述连接端子通过所述连接端子与所述第二端子之间的至少一第一开口与所述第二端子电连接，所述第一开口位于所述第二端子对应的所述第一保护层上。
本申请提供的驱动电路板中，所述驱动电路板还包括与所述第二端子对应的光源，所述光源通过第一开口与所述第二端子电连接。
本申请提供的驱动电路板中，所述驱动电路板还包括位于所述源漏极层或/和连接端子上的第二保护层；
其中，所述第二保护层的材料为钼、钛、镍的金属或合金中的至少一种。
本申请提供的驱动电路板中，所述连接端子通过所述连接端子与光源之间的至少一第二开口与所述光源电连接，所述第二开口位于所述连接端子对应的所述第二保护层上。
本申请提供的驱动电路板中，所述第一保护层的第一侧面与所述衬底形成的第一夹角小于或等于90度。
本申请提供的驱动电路板中，所述第二保护层的第二侧面与所述衬底形成的第二夹角小于或等于90度。
本申请提供的驱动电路板中，所述第一保护层与连接端子接触的第一表面可以设置有多个第一凸起和/或多个第一凹面；
所述第一保护层通过所述第一凸起和/或所述第一凹面与所述连接端子嵌套设置。
本申请提供的驱动电路板中，所述第一保护层的材料为氧化铟锡或氧化铟锌中的至少一种。
本申请提供的驱动电路板中，所述第一保护层的厚度为600埃米至1800埃米。
本申请提供的驱动电路板中，所述第一端子、所述栅极层、所述源漏极层、或所述第二端子中的至少一者的第三侧面与所述衬底形成的第三夹角大于30度且小于75度。
本申请还提供了一种驱动电路板的制作方法，包括：
在衬底上形成第一金属层以及第一保护层；
在所述第一保护层上形成第二金属层以及第三金属层；
所述第三金属层经第一预定工艺形成第二保护层；
其中，所述第一金属层包括所述驱动电路板的薄膜晶体管的栅极层、位于所述薄膜晶体管两侧的第一端子及第二端子；
所述第二金属层包括所述薄膜晶体管的源漏极层、及位于所述第二端子上的连接端子。
本申请提供的驱动电路板的制作方法中，所述第一金属层的厚度为4000埃米至9600埃米。
本申请提供的驱动电路板的制作方法中，在衬底上形成第一金属层以及第一保护层的步骤包括：
在所述衬底上形成一第一金属材料层以及一第一金属氧化物层；
所述第一金属材料层以及所述第一金属氧化物层经图案化处理形成所述第一金属层以及所述第一保护层。
本申请提供的驱动电路板的制作方法中，在所述第一保护层上形成第二金属层以及第三金属层的步骤包括：
在所述第一保护层上形成第一绝缘物层；
在所述栅极层上形成有源层；
在所述有源层上形成第二金属层以及第三金属层。
本申请提供的驱动电路板的制作方法中，所述第三金属层经第一预定工艺形成第二保护层的步骤包括：
去除所述连接端子对应的所述第三金属层以形成所述第二保护层。
本申请提供的驱动电路板的制作方法中，所述连接端子对应的所述第三金属层通过在第一功率、第一氟氧比下的等离子体进行干法刻蚀去除。
本申请提供的驱动电路板的制作方法中，所述第一功率为10.4千瓦至26.4千瓦，所述第一氟氧比为2.4:1至7.2:1。
 有益效果
本申请通过将驱动电路板中的第一端子或第二端子中的至少一金属层与栅极层和/或源漏极层同层设置，减少了驱动电路板的工艺制程中使用的光罩的数量，简化了制程工艺，节约了产品的制造成本，提升了产品良率。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请的驱动电路板的第一种结构示意图。
图2为本申请的驱动电路板的第二种结构示意图。
图3为本申请的驱动电路板的第三种结构示意图。
图4为本申请的驱动电路板的制作方法流程图。
图5a~5g为本申请的驱动电路板的制作方法的示意图。
 本发明的实施方式
本申请提供一种驱动电路板及其制作方法，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
现有的显示装置的背光模组中的驱动电路板，由于制程工艺复杂，影响产品质量的问题。基于此，本申请提出了一种驱动电路板及其制作方法。
请参阅图1~3，所述驱动电路板100包括衬底101、位于所述衬底101上的薄膜晶体管102、及位于所述薄膜晶体管102两侧的第一端子103及第二端子104。
其中，所述第一端子103和/或所述第二端子104中的至少一金属层与所述薄膜晶体管102中的栅极层和/或源漏极层106同层设置。
本实施例中，所述薄膜晶体管102可以为底栅极型薄膜晶体管，也可以为顶栅极型薄膜晶体管或其他类型的薄膜晶体管，在此不作具体限定。
本实施例中，所述驱动电路板100可以用于显示装置的背光模组中。
本实施例中，当所述第一端子103或所述第二端子104中的至少一金属层与所述栅极层同层设置时，该金属层的材料可以是钼或钼铜合金中的至少一种。
本实施例中，当所述第一端子103或所述第二端子104中的至少一金属层与所述源漏极层106同层设置时，该金属层的材料可以包括钼、钛、铜金属或合金中的至少一种，例如：钼/铜合金、钼钛/铜合金等。
本实施例中，所述第一端子103可以用于所述驱动电路板100与显示装置中的其他部件的电连接，如与覆晶薄膜的电连接。
本实施例中，所述第二端子104可以用于与光源形成电连接。
本实施例中，所述驱动电路板100还包括位于所述栅极层105和所述源漏极层106之间的栅极绝缘层、以及有源层。
本实施例中，所述栅极绝缘层的材料可以包括硅的氧化物、硅的氮化物、及硅的氮氧化合物、氧化铝、氮化铝中的至少一种。所述栅极绝缘层可以由单一材料形成，例如由氧化硅、氮化铝形成；所述栅极绝缘层也可以由多种材料叠加形成，例如由氧化硅与氮化硅叠层形成，或由氧化硅、氮化硅与硅的氮氧化合物叠层形成，或氧化硅、氮化硅与氧化铝叠层形成。当所述栅极层105由多种材料叠加形成时，不同材料之间的叠层方式在此不作具体限定。
本实施例中，所述驱动电路板100还包括位于所述源漏极层106上的钝化层。
本实施例中，所述钝化层的材料可以包括硅的氧化物、硅的氮化物、氧化铝、氮化铝中的至少一种。所述钝化层可以由单一材料形成，如，由氧化硅或氮化铝形成；所述钝化层也可以由多种材料叠加形成，如，由氧化硅与氮化硅叠层形成或氧化硅、氮化硅与氧化铝叠层形成，不同材料之间的叠层方式在此不作具体限定。
本申请通过第一端子103或第二端子104中的至少一金属层与栅极层105和/或源漏极层106的同层设置，减少了驱动电路板100的工艺制程中使用的光罩的数量，简化了制程工艺，节约了产品的制造成本，提升了产品良率。
现结合具体实施例对本申请的技术方案进行描述。
实施例一
请参阅图1，所述第一端子103及所述第二端子104包括一与所述栅极层105同层设置的金属层。
本实施例中，所述驱动电路板100还包括位于所述栅极层105、所述第一端子103、以及所述第二端子104上的第一保护层107。
其中，所述第一保护层107的材料为金属氧化物。
本实施例中，所述第一端子103及所述第二端子104的金属层可以与所述栅极层105同材料、同工序形成。
本实施例中，所述第一端子103以及所述第二端子104可以只由一金属层构成。
本实施例中，所述第一保护层107与所述栅极层105、所述第一端子103、以及所述第二端子104可以在同一工序中形成。
本实施例中，所述第一保护层107的材料可以为氧化铟锡、氧化铟锌或其他金属氧化物中的至少一种。
所述第一保护层107的设置，用于避免形成所述栅极层105、所述第一端子103、以及所述第二端子104的金属材料，如，铜金属，在所述驱动电路板100的后序工艺制程中，由于高温制程而受到氧化，或是发生离子热扩散，导致金属离子进入至其他膜层，如，栅极绝缘层，导致所述驱动电路板100的性能受影响，并且影响使用所述驱动电路板100的产品质量。
本实施例通过所述第一端子103及所述第二端子104的金属层与所述栅极层105同层设置，使所述第一端子103及所述第二端子104的金属层与所述栅极层105能通过同工序、同材料形成，减少了驱动电路板100的工艺制程中使用的光罩的数量，简化了制程工艺，节约了产品的制造成本，提升了产品良率。
实施例二
请参阅图2，本实施例与实施例一相同或相似，不同之处在于：
本实施例中，所述驱动电路板100还包括位于所述第二端子104上的连接端子109，所述连接端子109通过所述连接端子109与所述第二端子104之间的至少一第一开口110与所述第二端子104电连接，所述第一开口110位于所述第二端子104对应的所述第一保护层107上。
本实施例中，所述连接端子109可以与所述源漏极层106同层设置。
本实施例中，所述连接端子109可以与所述源漏极层106同材料，同工序形成。
当所述连接端子109通过所述第一开口110与所述第二端子104电连接时，通过所述第一开口110的设置，增大了所述连接端子109与所述第一保护层107的接触面积，有利于增大所述连接端子109与所述第一保护层107之间的粘附力，有利于防止所述连接端子109从所述第一保护层107上脱离，导致所述驱动电路板100的质量受影响；此外，通过所述第一开口110的设置，所述连接端子109可以与所述第二端子104直接接触，减少了所述连接端子109与所述第二端子104之间的电阻，有利于减少所述驱动电路板100在使用时的耗电量。
本实施例中，所述连接端子109可以用于所述光源与所述第二端子104的电连接。
本实施例中，所述第一保护层107与所述连接端子109接触的第一表面可以设置有多个第一凸起和/或多个第一凹面。
所述第一保护层107通过所述第一凸起和/或所述第一凹面与所述连接端子109嵌套设置。
通过所述第一保护层107与所述连接端子109的嵌套设置，有利于增大所述连接端子109与所述第一保护层107的接触面积，增强所述连接端子109与所述第一保护层107之间的粘附力，有利于防止所述连接端子109从所述第一保护层107上脱离，导致所述驱动电路板100的质量受影响。
本实施例中，所述驱动电路板100还包括与所述第二端子104对应的光源，所述光源通过所述第一开口110与所述第二端子104电连接。
本实施例中，所述光源可以为发光二极管。
本实施例中，所述光源通过表面贴装工艺实现与所述第二端子104的电连接。
由于所述光源通过表面贴装工艺后，通过锡膏实现与所述第二端子104的电连接，而第一保护层107的材料为金属氧化物，与锡膏的结合力较弱，因此，通过所述第一开口110的设置，使锡膏与所述第二端子104直接接触，增强了锡膏与所述第二端子104的粘附力，有利于避免由于所述第一保护层107的设置而导致锡膏的附着力不足，引起所述光源的脱落。
由于所述连接端子109的材料为金属材料，有利于锡膏的附着，所以所述连接端子109的设置同样避免了所述第一保护层107的设置导致锡膏的附着力不足，引起所述光源的脱落。
本实施例通过所述第一开口110的设置，当所述连接端子109与所述第二端子104通过所述第一开口110电连接时，提高了所述连接端子109与所述第一保护层107之间的粘附力，有利于防止所述连接端子109从所述第一保护层107上脱离；当所述光源与所述第二端子104通过所述第一开口110电连接时，有利于避免所述第一保护层107的设置导致锡膏的附着力不足，引起所述光源的脱落。
实施例三
请参阅图3，本实施例与实施例一、实施例二相同或相似，不同之处在于：
所述驱动电路板100还包括位于所述源漏极层106或/和连接端子109上的第二保护层108。
其中，所述第二保护层108的材料为钼、钛、镍的金属或合金中的至少一种，例如：钼钛合金，钛、镍金属等。
本实施例中，所述第二保护层108可以与所述源漏极层106或/和所述连接端子109同工序形成。
所述第二保护层108的材料为耐高温、抗氧化的金属，用于避免形成所述源漏极层106或/和所述连接端子109的金属材料，如，铜金属，在所述驱动电路板100的后序工艺制程中，由于高温制程而受到氧化，导致所述驱动电路板100的性能受影响，并且影响使用所述驱动电路板100的产品质量。
本实施例中，所述第二保护层108可以位于所述源漏极层106上。
本实施例中，所述第二保护层108也可以位于所述源漏极层106以及所述连接端子109上。
本实施例中，所述连接端子109通过所述连接端子109与光源之间的至少一第二开口与所述光源电连接，所述第二开口位于所述连接端子109对应的所述第二保护层108上。
由于所述光源通过表面贴装工艺后，通过锡膏实现与所述连接端子109的电连接，而所述第二保护层108的材料与锡膏的结合力较弱，不利于锡膏的附着，因此，通过所述第二开口的设置，使锡膏与所述连接端子109直接接触，提高了锡膏的附着力，有利于避免所述第一保护层107的设置导致锡膏的附着力不足，引起所述光源的脱落，影响产品质量。
本实施例通过所述第二保护层108的设置，有利于避免所述源漏极层106或/和所述连接端子109在所述驱动电路板100的后续制程中的氧化，提高产品质量；此外，所述第二保护层108可以与所述源漏极层106或/和所述连接端子109在同一工序中形成，避免了增加额外制程，在提高产品质量的同时节约了制程成本。
上述各实施例中，所述第一保护层107的第一侧面与所述衬底101形成的第一夹角小于或等于90度，和/或所述第二保护层108的第二侧面与所述衬底101形成的第二夹角小于或等于90度。当所述第一夹角大于90度时，所述第一保护层107远离所述衬底101的一侧与所述第一侧面呈锐角，易刺破所述第一保护层107周围的其他膜层，如栅极绝缘层，导致所述驱动电路板100性能受影响。同理，当所述第二夹角大于90度时，所述第二保护层108远离所述衬底101的一侧与所述第二侧面呈锐角，易刺破所述第二保护层108周围的其他膜层，如钝化层，导致所述驱动电路板100性能受影响。
上述各实施例中，所述第一端子103、所述栅极层105、所述源漏极层106、或所述第二端子104中的至少一者的第三侧面与所述衬底101形成的第三夹角大于30度且小于75度，优选为45至60度。当所述第三夹角小于30度时，所述第三夹角过小，会造成所述驱动电路板100的信号传输延迟明显；当所述第三夹角大于75度时，所述第三夹角过大，导致形成所述第三夹角的膜层上的其他膜层在形成时发生断裂，影响所述驱动电路板100的产品质量；当所述第三夹角在45至60度之间时，既不会造成所述驱动电路板100的信号传输的明显延迟，也不会造成形成所述第三夹角的膜层上的其他膜层在形成时发生断裂。
请参阅图4，以及图5a~5g，本申请还提出了一种驱动电路板100的制作方法，包括：
请参阅图5a，S1、在衬底101上形成第一金属层以及第一保护层107。
本实施例中，所述第一金属层包括所述驱动电路板100的薄膜晶体管102的栅极层105、位于所述薄膜晶体管102两侧的第一端子103及第二端子104。
本实施例中，步骤S1包括：
S11、在所述衬底101上形成一第一金属材料层以及一第一金属氧化物层。
本实施例中，所述第一金属材料层以及所述第一金属氧化物层可以通过沉积，例如物理气相溅射沉积形成。
本实施例中，所述第一金属材料层的材料可以为钼或钼铜合金中的至少一种。
本实施例中，所述第一金属氧化物层的材料可以为氧化铟锡、氧化铟锌或其他金属氧化物中的至少一种。
S12、所述第一金属材料层以及所述第一金属氧化物层经图案化处理形成所述第一金属层以及所述第一保护层107。
本实施例中，所述第一金属层及所述第一保护层107可以通过湿法刻蚀形成。
本实施例中，所述第一金属层通过第一刻蚀液形成，所述第一刻蚀液包括过氧化氢。
所述第一保护层107通过第二刻蚀液形成，所述第二刻蚀液包括草酸。
本实施例中，所述第一金属层的厚度可以为4000至9600埃米，优选为5000至8000埃米。
所述第一保护层107的厚度可以为600至1800埃米，优选为750至1500埃米。在后续工艺中通过刻蚀形成其他膜层时，由于过刻蚀的存在对所述第一保护层107的减薄，当所述第一保护层107的厚度小于600埃米时，所述第一保护层107的厚度过小，不利于对所述第一金属层在高温制程中的热氧化保护以及防止所述第一金属层中的离子热扩散进入其他膜层；当所述第一保护层107的厚度大于1800埃米时，所述第一保护层107的厚度过厚，所述第一保护层107的电阻明显增加，导致使用所述驱动电路板100的显示装置耗电量增大；当所述第一保护层107的厚度为750至1500埃米时，所述第一保护层107既不会因为过薄而在高温制程中对所述第一金属层无法完全保护，也不会因为过厚而增加使用所述驱动电路板100的显示装置的耗电量。
请参阅图5b~5e，S2、在所述第一保护层107上形成第二金属层以及第三金属层。
本实施例中，所述第二金属层包括所述薄膜晶体管102的源漏极层106、及位于所述第二端子104上的连接端子109。
本实施例中，所述第二金属层的厚度可以为4000埃米至9600埃米，优选为5000埃米至8000埃米。
本实施例中，步骤S2包括：
S21、在所述第一保护层107上形成第一绝缘物层。
S22、在所述栅极层105上形成有源层。
本实施例中，步骤S22包括：
S22a、在所述栅极层105上形成一半导体层。
本实施例中，所述半导体层的材料包括铟镓锌氧化物、铟镓锌锡氧化物、氧化铟锌、铟镓锡氧化物中的至少一种。
S22b、所述半导体层经第二预定工艺形成有源层。
本实施例中，所述半导体层经热退火处理、光刻工艺后形成所述有源层。
光刻工艺中所用的蚀刻液可以包括草酸。
S23、在所述有源层上形成第二金属层以及第三金属层。
本实施例中，所述第二金属层的材料可以包括钼、钛、铜金属或合金中的至少一种，例如：钼/铜合金、钼钛/铜合金等。
所述第三金属层的材料可以包括钼、钛、镍的金属或合金中的至少一种，例如：钼钛合金，钛、镍金属等。
本实施例中，步骤S23包括：
S23a、所述第一绝缘物层形成第一绝缘层。
S23b、在所述有源层上形成一第二金属材料层以及一第三金属材料层。
本实施例中，所述第一金属材料层以及所述第三金属材料层通过物理气相沉积形成在所述有源层上。
S23c、所述第二金属材料层、所述第三金属材料层经第三预定工艺形成所述第二金属层以及所述第三金属层。
本实施例中，所述第二金属层以及所述第三金属层可以通过湿法刻蚀形成。
本实施例中，所述第二金属层以及所述第三金属层通过第四刻蚀液形成，所述第四刻蚀液包括过氧化氢。
请参阅图5f以及图5g，S3、所述第三金属层经第一预定工艺形成第二保护层108。
本实施例中，步骤S3包括：
S31、去除所述连接端子109对应的所述第三金属层以形成所述第二保护层108。
本实施例中，步骤S31包括：
S31a、所述第一绝缘层经第五预设工艺处理形成栅极绝缘层。
S31b、在所述第三金属层上形成一第二绝缘物层。
S31c、所述第二绝缘物层经第四预定工艺形成钝化层。
本实施例中，所述钝化层包括与所述第一端子103对应的第三开口以及与所述第二端子104对应的第四开口。
本实施例中，所述栅极绝缘层包括位于所述第一端子103和所述第三开口之间的第五开口，以及位于所述第四开口和所述第二端子104之间的第六开口。
其中，所述第四开口使所述连接端子109对应的所述第三金属层裸露。
本实施例中，所述栅极绝缘层和所述钝化层可以通过干法刻蚀形成。
本实施例中，所述栅极绝缘层和所述钝化层可以通过含氟的强氧化性气体进行干法蚀刻形成。
本实施例中，所述栅极绝缘层的材料可以包括硅的氧化物、硅的氮化物、及硅的氮氧化合物、氧化铝、氮化铝中的至少一种。所述栅极绝缘层可以由单一材料形成，例如由氧化硅、氮化铝形成；所述栅极绝缘层也可以由多种材料叠加形成，例如由氧化硅与氮化硅叠层形成，或由氧化硅、氮化硅与硅的氮氧化合物叠层形成，或氧化硅、氮化硅与氧化铝叠层形成。当所述栅极层105由多种材料叠加形成时，不同材料之间的叠层方式在此不作具体限定。
本实施例中，所述钝化层的材料可以包括硅的氧化物、硅的氮化物、氧化铝、氮化铝中的至少一种。所述钝化层可以由单一材料形成，如，由氧化硅或氮化铝形成；所述钝化层也可以由多种材料叠加形成，如，由氧化硅与氮化硅叠层形成或氧化硅、氮化硅与氧化铝叠层形成，不同材料之间的叠层方式在此不作具体限定。
S31d、刻蚀去除所述连接端子109对应的所述第三金属层以形成所述第二保护层108。
本实施例中，所述第二保护层108通过对所述第三金属层的干法蚀刻形成。
本实施例中，所述第二保护层108通过在第一功率、第一氟氧比下的等离子体进行干法刻蚀形成。
所述第一功率可以为10.4千瓦至26.4千瓦，优选为13千瓦至20千瓦。当所述第一功率小于10.4千瓦时，所述第一功率过小，对所述连接端子109对应的所述第三金属层的刻蚀的时间过长，不利于制程效率的提升；由于所述第一功率不超过26.4千瓦时，所述第一功率已足以满足对所述连接端子109对应的所述第三金属层的刻蚀的需求，因此所述第一功率不需要超过26.4千瓦；所述第一功率为13千瓦至20千瓦时，即能保证所述连接端子109对应的所述第三金属层的刻蚀快速且充分。
所述第一氟氧比可以为2.4:1至7.2:1，优选为3:1至6:1。当所述第一氟氧比小于2.4:1或大于7.2:1时，等离子体含氟或含氧量不足，影响等离子体的氧化性，不利于对所述连接端子109对应的所述第三金属层的刻蚀；当所述第一氟氧比为3:1至6:1时，等离子体的含氟量以及含氧量合适，保证了等离子体的强氧化性，使所述连接端子109对应的所述第三金属层的刻蚀快速且充分。
本实施例中，当所述驱动电路板100应用于显示装置的背光模组中时，光源通过表面贴装工艺贴装于所述驱动电路板100上。
本申请提供的驱动电路板100的制作方法，通过使第一端子103或第二端子104中的至少一金属层与栅极层105和/或源漏极层106同层设置，减少了驱动电路板100的工艺制程中使用的光罩的数量，简化了制程工艺，节约了产品的制造成本，提升了产品良率。
本申请提出了一种驱动电路板及其制作方法。该驱动电路板包括：衬底、位于衬底上的薄膜晶体管、及位于薄膜晶体管两侧的第一端子及第二端子。其中，第一端子或第二端子中的至少一金属层与薄膜晶体管中的栅极层和/或源漏极层同层设置。本申请通过将驱动电路板中的第一端子或第二端子中的至少一金属层与栅极层和/或源漏极层同层设置，减少了驱动电路板的工艺制程中使用的光罩的数量，简化了制程工艺，节约了产品的制造成本，提升了产品良率。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种驱动电路板，其中，包括衬底、位于所述衬底上的薄膜晶体管、及位于所述薄膜晶体管两侧的第一端子及第二端子；
    其中，所述第一端子和/或所述第二端子中的至少一金属层与所述薄膜晶体管中的栅极层和/或源漏极层同层设置。
  2. 根据权利要求1所述的驱动电路板，其中，所述第一端子及所述第二端子包括一与所述栅极层同层设置的金属层。
  3. 根据权利要求2所述的驱动电路板，其中，所述驱动电路板还包括位于所述栅极层、所述第一端子、以及所述第二端子上的第一保护层；
    其中，所述第一保护层的材料为金属氧化物。
  4. 根据权利要求3所述的驱动电路板，其中，所述驱动电路板还包括位于所述第二端子上的连接端子，所述连接端子通过所述连接端子与所述第二端子之间的至少一第一开口与所述第二端子电连接，所述第一开口位于所述第二端子对应的所述第一保护层上。
  5. 根据权利要求3所述的驱动电路板，其中，所述驱动电路板还包括与所述第二端子对应的光源，所述光源通过第一开口与所述第二端子电连接。
  6. 根据权利要求3所述的驱动电路板，其中，所述驱动电路板还包括位于所述源漏极层或/和连接端子上的第二保护层；
    其中，所述第二保护层的材料为钼、钛、镍的金属或合金中的至少一种。
  7. 根据权利要求6所述的驱动电路板，其中，所述连接端子通过所述连接端子与光源之间的至少一第二开口与所述光源电连接，所述第二开口位于所述连接端子对应的所述第二保护层上。
  8. 根据权利要求6所述的驱动电路板，其中，所述第一保护层的第一侧面与所述衬底形成的第一夹角小于或等于90度。
  9. 根据权利要求6所述的驱动电路板，其中，所述第二保护层的第二侧面与所述衬底形成的第二夹角小于或等于90度。
  10. 根据权利要求3所述的驱动电路板，其中，所述第一保护层与连接端子接触的第一表面可以设置有多个第一凸起和/或多个第一凹面；
    所述第一保护层通过所述第一凸起和/或所述第一凹面与所述连接端子嵌套设置。
  11. 根据权利要求3所述的驱动电路板，其中，所述第一保护层的材料为氧化铟锡或氧化铟锌中的至少一种。
  12. 根据权利要求3所述的驱动电路板，其中，所述第一保护层的厚度为600埃米至1800埃米。
  13. 根据权利要求2所述的驱动电路板，其中，所述第一端子、所述栅极层、所述源漏极层、或所述第二端子中的至少一者的第三侧面与所述衬底形成的第三夹角大于30度且小于75度。
  14. 一种驱动电路板的制作方法，其中，包括：
    在衬底上形成第一金属层以及第一保护层；
    在所述第一保护层上形成第二金属层以及第三金属层；
    所述第三金属层经第一预定工艺形成第二保护层；
    其中，所述第一金属层包括所述驱动电路板的薄膜晶体管的栅极层、位于所述薄膜晶体管两侧的第一端子及第二端子；
    所述第二金属层包括所述薄膜晶体管的源漏极层、及位于所述第二端子上的连接端子。
  15. 根据权利要求14所述的驱动电路板的制作方法，其中，所述第一金属层的厚度为4000埃米至9600埃米。
  16. 根据权利要求14所述的驱动电路板的制作方法，其中，在衬底上形成第一金属层以及第一保护层的步骤包括：
    在所述衬底上形成一第一金属材料层以及一第一金属氧化物层；
    所述第一金属材料层以及所述第一金属氧化物层经图案化处理形成所述第一金属层以及所述第一保护层。
  17. 根据权利要求14所述的驱动电路板的制作方法，其中，在所述第一保护层上形成第二金属层以及第三金属层的步骤包括：
    在所述第一保护层上形成第一绝缘物层；
    在所述栅极层上形成有源层；
    在所述有源层上形成第二金属层以及第三金属层。
  18. 根据权利要求14所述的驱动电路板的制作方法，其中，所述第三金属层经第一预定工艺形成第二保护层的步骤包括：
    去除所述连接端子对应的所述第三金属层以形成所述第二保护层。
  19. 根据权利要求18所述的驱动电路板的制作方法，其中，所述连接端子对应的所述第三金属层通过在第一功率、第一氟氧比下的等离子体进行干法刻蚀去除。
  20. 根据权利要求19所述的驱动电路板的制作方法，其中，所述第一功率为10.4千瓦至26.4千瓦，所述第一氟氧比为2.4:1至7.2:1。
PCT/CN2020/124478 2020-10-16 2020-10-28 驱动电路板及其制作方法 WO2022077564A1 (zh)

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