WO2022075238A1 - チップ抵抗器、及び製造方法 - Google Patents

チップ抵抗器、及び製造方法 Download PDF

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Publication number
WO2022075238A1
WO2022075238A1 PCT/JP2021/036549 JP2021036549W WO2022075238A1 WO 2022075238 A1 WO2022075238 A1 WO 2022075238A1 JP 2021036549 W JP2021036549 W JP 2021036549W WO 2022075238 A1 WO2022075238 A1 WO 2022075238A1
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Prior art keywords
resistor
electrode
chip
film thickness
thickness direction
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English (en)
French (fr)
Japanese (ja)
Inventor
大輔 末次
憲路 野口
達也 浦川
裕貴 小田
大輔 上山
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to US18/247,704 priority Critical patent/US12537119B2/en
Priority to CN202180065194.1A priority patent/CN116195012A/zh
Priority to JP2022555451A priority patent/JPWO2022075238A1/ja
Publication of WO2022075238A1 publication Critical patent/WO2022075238A1/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/06—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material including means to minimise changes in resistance with changes in temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors
    • H01C1/142—Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors the terminals or tapping points being coated on the resistive element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
    • H01C17/065—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thick film techniques, e.g. serigraphy
    • H01C17/06506—Precursor compositions therefor, e.g. pastes, inks, glass frits or green body
    • H01C17/06513—Precursor compositions therefor, e.g. pastes, inks, glass frits or green body characterised by the resistive component
    • H01C17/06553—Precursor compositions therefor, e.g. pastes, inks, glass frits or green body characterised by the resistive component composed of a combination of metals and oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
    • H01C17/075—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin-film techniques
    • H01C17/12—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin-film techniques by sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/28—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
    • H01C17/288—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals by thin film techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/003—Thick film resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/006—Thin film resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
    • H01C17/065—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thick film techniques, e.g. serigraphy
    • H01C17/06506—Precursor compositions therefor, e.g. pastes, inks, glass frits or green body
    • H01C17/06513—Precursor compositions therefor, e.g. pastes, inks, glass frits or green body characterised by the resistive component
    • H01C17/0656—Precursor compositions therefor, e.g. pastes, inks, glass frits or green body characterised by the resistive component composed of silicides

Definitions

  • the present disclosure relates to a chip resistor in general and a manufacturing method, and more particularly to a chip resistor used in an electronic device and a manufacturing method of the chip resistor.
  • Patent Document 1 describes a thin film resistor (chip resistor) including a Si substrate (insulated substrate) and a thin film resistor formed on the Si substrate.
  • the resistor is composed of, for example, Cr, Si, Al, and B.
  • the resistor has a high specific resistance of 4000 ⁇ ⁇ cm or more, but the resistance temperature coefficient (TCR: Temperature Coefficient of Resistance) is ⁇ 300 to 500 ppm / K or less. Yes, low TCR could not be obtained.
  • TCR Temperature Coefficient of Resistance
  • An object of the present disclosure is to provide a chip resistor capable of achieving both high resistivity and low TCR, and a manufacturing method.
  • the chip resistor includes an insulating substrate, a resistor, and an electrode.
  • the resistor contains Cr, Si and N and is provided on the insulating substrate.
  • the electrode contains at least one refractory metal and is provided on the resistor.
  • the refractory metal is a metal having a melting point of 800 ° C. or higher.
  • the atomic ratio of Si to Cr in the resistor is at least 2/3 or more and 4 or less at the center of the resistor in the film thickness direction of the resistor.
  • the atomic percentage of N in the resistor is at least 50 atom% or less at the center of the resistor in the film thickness direction.
  • the chip resistor includes an insulating substrate, a resistor, and an electrode.
  • the resistor contains Cr, Si, N and Al and is provided on the insulating substrate.
  • the electrode contains at least one refractory metal and is provided on the resistor.
  • the refractory metal is a metal having a melting point of 800 ° C. or higher.
  • the atomic ratio of Si to Cr in the resistor is at least 2/3 or more and 4 or less at the center of the resistor in the film thickness direction of the resistor.
  • the atomic percentage of N in the resistor is at least 50 atom% or less at the center of the resistor in the film thickness direction.
  • the atomic percentage of Al in the resistor is at least 30 atom% or less at the center of the resistor in the film thickness direction.
  • the manufacturing method is the manufacturing method of the chip resistor.
  • the manufacturing method includes an electrode forming step and a pattern forming step.
  • the electrode forming step is a step of forming the electrode on the resistor by sputtering.
  • the pattern forming step is a step of forming a pattern of the electrode on the resistor by etching.
  • the manufacturing method is the manufacturing method of the chip resistor.
  • the manufacturing method includes an electrode forming step.
  • the electrode forming step is a step of forming the electrode on the resistor by mask sputtering and forming a pattern of the electrode.
  • FIG. 1 is a cross-sectional view of a chip resistor according to an embodiment.
  • FIG. 2 is an image showing the crystal structure of the resistor with respect to the same chip resistor.
  • FIG. 3 is a graph showing the relationship between the atomic ratio of Cr and Si and the specific resistance of the same chip resistor.
  • FIG. 4 is a graph showing the relationship between the heat treatment temperature, the specific resistance, and the TCR with respect to the same chip resistor.
  • FIG. 5 is a graph showing the relationship between the N ratio and the molar ratio in the resistor with respect to the same chip resistor. It represents the ratio of substances in an equilibrium state obtained by thermodynamic equilibrium calculation by Factsage (Computational Dynamics Research Center Co., Ltd.).
  • FIG. 1 is a cross-sectional view of a chip resistor according to an embodiment.
  • FIG. 2 is an image showing the crystal structure of the resistor with respect to the same chip resistor.
  • FIG. 3 is a graph showing the relationship between the atomic ratio of Cr and Si and the
  • FIG. 6 is a graph showing the relationship between the analysis depth and the quantitative conversion value in the resistor with respect to the chip resistor of the same as above.
  • FIG. 7 is a graph showing the relationship between the film thickness of the resistor and the sheet resistance with respect to the same chip resistor.
  • each of the figures described in the following embodiments and the like is a schematic view, and the ratio of the size and the thickness of each component in each figure does not necessarily reflect the actual dimensional ratio. Not always.
  • the chip resistor 10 according to the present embodiment is, for example, a chip resistor for surface mounting (SMT: Surface Mount Technology) mounted on the surface (mounting surface) of a printed circuit board using a surface mounter (chip mounter). Is. Further, the chip resistor 10 according to the present embodiment is, for example, a thin film chip resistor.
  • SMT Surface Mount Technology
  • the chip resistor 10 includes an insulating substrate 1, a resistor 2, and a top electrode (electrode) 3.
  • the resistor 2 contains Cr (chromium), Si (silicon) and N (nitrogen).
  • the resistor 2 is provided on the insulating substrate 1.
  • the top electrode 3 contains at least one refractory metal.
  • the "high melting point metal” as used in the present disclosure means a metal having a melting point of 800 ° C. or higher.
  • the top electrode 3 is provided on the resistor 2.
  • the atomic ratio of Si to Cr in the resistor 2 is at least 2/3 or more and 4 or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2.
  • the atomic percentage of N in the resistor 2 is at least 50 atom% or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2.
  • the atomic ratio of Si to Cr in the resistor 2 is at least 2/3 or more at the center of the resistor 2 in the film thickness direction D1 of the resistor 2. And it is 4 or less. This makes it possible to lower the temperature coefficient of resistance of the resistor 2 (hereinafter, also referred to as “TCR”).
  • the atomic percentage of N in the resistor 2 is at least 50 atom% or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2. This makes it possible to increase the specific resistance of the resistor 2. That is, according to the chip resistor 10 according to the present embodiment, it is possible to achieve both high resistivity and low TCR.
  • the top electrode 3 contains at least one refractory metal.
  • the resistor 2 can be heat-treated with the top electrode 3 formed on the resistor 2, and as a result, the surface oxynitride layer 9 is formed at the contact portion between the resistor 2 and the top electrode 3. Is difficult to form, so it is possible to stabilize the electrical connection between the resistor 2 and the top electrode 3.
  • the chip resistor 10 includes an insulating substrate 1, a resistor 2, and a pair of top electrodes (electrodes) 3. Further, the chip resistor 10 further includes a first protective film 4, a second protective film 5, a pair of end face electrodes 6, a pair of plating layers 7, and a pair of back surface electrodes 8.
  • the insulated substrate 1 is, for example, an alumina substrate containing 96% to 99% of Al 2 O 3 (alumina).
  • the shape of the insulating substrate 1 in a plan view is, for example, a rectangular shape.
  • the resistor 2 is a thin film and is provided on one surface (upper surface of FIG. 1) of the insulating substrate 1.
  • the resistor 2 is composed of, for example, an alloy containing Cr (chromium), Si (silicon), and N (nitrogen). That is, the resistor 2 contains Cr, Si and N.
  • the atomic ratio of Si to Cr in the resistor 2 is at least 2/3 or more and 4 or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2. In other words, the atomic ratio of Cr and Si in the resistor 2 is 3: 2 or more and 1: 4 or less.
  • the total atomic amount of N among the total atomic amounts of the metals constituting the resistor 2 is, for example, 50 atom% or less. In other words, the atomic percentage of N in the resistor 2 is at least 50 atom% or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2.
  • the resistor 2 further contains O (oxygen).
  • the atomic percentage of O in the resistor 2 is at least 10 atom% or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2.
  • the "film thickness direction D1" referred to in the present disclosure refers to a direction along the thickness direction of the insulating substrate 1 in the resistor 2.
  • the resistor 2 is formed into a substantially rectangular shape by forming a thin film conductor on almost the entire surface of the insulating substrate 1 using, for example, a thin film process such as sputtering, and then removing unnecessary portions of the thin film conductor using a photolithography process. ing.
  • the atomic composition ratio of the resistor 2 is set on the upper surface or the cross section of the resistor 2 by using, for example, the energy dispersive X-ray spectroscopy TEM-EDX attached to the transmission electron microscope TEM or the electron energy loss spectroscopy TEX-EELS. On the other hand, it is calculated from the spectral ratios obtained for each element of Cr, Si, N, and O. Alternatively, it is calculated by correcting each atomic composition ratio evaluated using X-ray photoelectron spectroscopy XPS based on the correction coefficient of each element evaluated using the Rutherford backscattering analysis method RBS.
  • the resistor 2 includes a crystalline phase 21 and an amorphous phase 22.
  • the crystalline phase 21 is composed of Cr Si 2 or Cr 5 Si 3 and the like, and affects TCR.
  • the amorphous phase 22 is composed of Si 3 N 4 or SiO 2 , and affects the improvement of specific resistance. That is, the presence of these two phases makes it possible to achieve both improvement in specific resistance and low TCR.
  • a surface oxynitride layer 9 is formed between the resistor 2 and the first protective film 4 in the film thickness direction D1 of the resistor 2.
  • the surface oxynitride layer 9 is provided on the surface (upper surface of FIG. 2) 23 on the side of the resistor 2 opposite to the insulating substrate 1.
  • the surface oxynitride layer 9 is made of an oxynitride film containing at least one of Cr and Al and Si.
  • the surface oxynitride layer 9 is made of an oxynitride film containing Cr and Si. More specifically, the surface oxynitride layer 9 contains a Cr oxide and a SiON.
  • the surface oxynitride layer 9 is formed by heat-treating the resistor 2 by a heat treatment step described later.
  • the surface oxynitride layer 9 there is an advantage that a passivation film is formed by the Cr oxide contained in the surface oxynitride layer 9, thereby improving the oxidation resistance. Further, the surface oxynitride layer 9 has an advantage that the gas barrier property is improved by the SiON contained in the surface oxynitride layer 9. That is, by forming such a surface oxynitride layer 9 on the surface 23 of the resistor 2, it is possible to improve the environmental resistance of the resistor 2.
  • the surface oxynitride layer 9 is provided not on the entire surface 23 of the resistor 2 but on a part of the surface 23. More specifically, the surface oxynitride layer 9 is provided on the surface 23 of the resistor 2 excluding the contact portion with the pair of top electrodes 3. In short, the surface oxynitride layer 9 is provided on the portion of the surface 23 of the resistor 2 opposite to the insulating substrate 1 except for the portion where the pair of top electrodes 3 are formed. As described above, since the surface oxynitride layer 9 is not provided at the contact portion between the resistor 2 and the pair of top electrodes 3, the electrical connection between the resistor 2 and the pair of top electrodes 3 is stabilized. Is possible.
  • Each of the pair of top electrodes (electrodes) 3 contains at least one refractory metal.
  • the refractory metal is a metal having a melting point of 800 ° C. or higher.
  • Refractory metals include, for example, W (tungsten), Re (rhenium), Os (osmium), Ta (tantal), Mo (molybdenum), Ir (iridium), Ru (ruthenium), B (boronium), Rh (rhodium).
  • each of the pair of top electrodes 3 contains W (tungsten) as a refractory metal.
  • the pair of top surface electrodes 3 are provided so as to cover a part of the top surface (surface 23) of the resistor 2 at both ends in the longitudinal direction (left-right direction in FIG. 1) of the resistor 2.
  • the pair of top electrodes 3 are formed by, for example, forming a metal film on the entire top surface of the resistor 2 by sputtering and then removing the film at the center portion by wet etching.
  • the first protective film (inorganic protective film) 4 is a film for protecting the resistor 2.
  • the first protective film 4 is made of, for example, Al 2 O 3 (alumina).
  • the first protective film 4 is located on the upper surface of the resistor 2. Further, the first protective film 4 covers a part of the pair of upper surface electrodes 3 at both ends in the longitudinal direction (left-right direction in FIG. 1). That is, the first protective film 4 covers the boundary between the resistor 2 and the pair of top electrodes 3 when viewed from the film thickness direction D1 of the resistor 2 (thickness direction of the insulating substrate 1), and the resistor 2 It continuously covers at least a part of the pair of top electrodes 3.
  • the first protective film 4 is formed by, for example, forming a protective film on the entire resistor 2 and the pair of top electrodes 3 by sputtering, and then removing both ends by wet etching.
  • the first protective film 4 may be a metal oxide other than alumina or a metal nitride. Further, the first protective film 4 may be omitted.
  • the second protective film (resin protective film) 5 is made of, for example, an epoxy resin.
  • the second protective film 5 covers the entire surface of the first protective film 4 and a part of the pair of upper surface electrodes 3. That is, the second protective film 5 covers the boundary between the first protective film 4 and the pair of top electrodes 3 when viewed from the film thickness direction D1 of the resistor 2 (thickness direction of the insulating substrate 1), and is second. 1
  • the protective film 4 is continuously covered with at least a part of the pair of top electrodes 3.
  • the second protective film 5 is formed by, for example, applying an epoxy resin by screen printing and then irradiating with ultraviolet rays to cure the epoxy resin.
  • the pair of top electrodes 3 it is located between both ends (the portion covering the pair of top electrodes 3) in the longitudinal direction (left-right direction in FIG. 1) of the first protective film 4 and the plating layer 7. The portion is directly covered with the second protective film 5.
  • Each of the pair of end face electrodes 6 is made of, for example, CuNi.
  • the pair of end face electrodes 6 are located at both ends of the insulating substrate 1 in the longitudinal direction (left-right direction in FIG. 1).
  • the pair of end face electrodes 6 are formed at both ends of the insulating substrate 1 in the longitudinal direction by, for example, sputtering.
  • Each of the pair of end face electrodes 6 is electrically connected to the corresponding top electrode 3 of the pair of top electrodes 3.
  • Each of the pair of plating layers 7 includes a Ni plating layer 71 and a Sn plating layer 72, as shown in FIG. Each of the pair of plating layers 7 is electrically connected to a part of the corresponding top electrode 3 of the pair of top electrodes 3 and is in contact with the second protective film 5. Further, each of the pair of plating layers 7 covers the corresponding end face electrode 6 of the pair of end face electrodes 6.
  • Each of the pair of backside electrodes 8 is made of, for example, an epoxy resin containing Ag (silver) as a conductive material.
  • the pair of back surface electrodes 8 are located at both ends of the back surface (lower surface of FIG. 1) of the insulating substrate 1 in the longitudinal direction (left-right direction of FIG. 1).
  • the pair of back surface electrodes 8 are formed by, for example, applying epoxy resin to both ends of the back surface of the insulating substrate 1 in the longitudinal direction by screen printing and then irradiating with ultraviolet rays to cure the epoxy resin.
  • the pair of back surface electrodes 8 has a one-to-one correspondence with the pair of top surface electrodes 3.
  • the pair of back surface electrodes 8 may be omitted.
  • the manufacturing method according to the present embodiment is a method for manufacturing the above-mentioned chip resistor 10.
  • the manufacturing method according to the present embodiment includes an electrode forming step of forming the upper surface electrode 3 on the resistor 2 and a pattern forming step of forming a pattern of the upper surface electrode 3 (hereinafter, also referred to as “first pattern forming step”). , Have. Further, the manufacturing method according to the present embodiment is also referred to as a resistor forming step of forming the resistor 2 on the insulating substrate 1 and a pattern forming step of forming the pattern of the resistor 2 (hereinafter, "second pattern forming step”). ), And further.
  • the resistor 2 is formed on the insulating substrate 1 by, for example, reactive sputtering reacted with nitrogen or reactive sputtering reacted with nitrogen and oxygen.
  • the sputtering target of reactive sputtering contains, for example, Cr, Si, and O, the atomic ratio of Cr to Si is 3: 7, and the atomic percentage of O is 20 atom%. That is, the sputtering target of reactive sputtering contains oxygen (O) of 20 atom% or less.
  • the resistor 2 is etched by the photolithography method to form the pattern of the resistor 2.
  • an etching solution containing hydrofluoric acid is used.
  • the top electrode 3 is formed on the resistor 2 by sputtering.
  • the sputtering target includes, for example, W (tungsten).
  • the pattern of the upper surface electrode 3 is formed by wet etching.
  • an etching solution containing hydrofluoric acid, sulfuric acid, nitric acid or hydrochloric acid is used.
  • the manufacturing method according to the present embodiment further includes a heat treatment step.
  • the heat treatment step is a step of heat-treating the resistor 2 in a state where the pattern of the upper surface electrode 3 is formed on the resistor 2 by the first pattern forming step. That is, in the present embodiment, the heat treatment step is executed after the first pattern forming step.
  • the heat treatment temperature is 500 ° C. or higher and 800 ° C. or lower. In this embodiment, as an example, the heat treatment temperature is 520 ° C. ⁇ 5 ° C.
  • the "heat treatment temperature” referred to here is the actual (actual) temperature of the resistor 2 in the present embodiment, but may be an atmospheric temperature. Further, in the heat treatment step, the oxygen concentration is 1000 ppm or less.
  • each of the pair of top electrodes 3 does not contain a refractory metal.
  • the resistor 2 is heat-treated with the pair of top electrodes 3 formed on the resistor 2, the pair of top electrodes 3 may melt depending on the heat treatment temperature. Therefore, in this case, after the resistor 2 is heat-treated, a pair of top electrodes 3 are formed on the resistor 2.
  • the surface oxynitride layer 9 is formed on the surface of the resistor 2 by heat-treating the resistor 2, the surface oxynitride layer 9 forms the surface oxynitride layer 9 with the resistor 2 and the pair of top electrodes 3. The electrical connection with and may be reduced.
  • each of the pair of top electrodes 3 contains a refractory metal, and the pair of top electrodes 3 is formed on the resistor 2. It is possible to heat-treat the resistor 2 in this state. As a result, the surface oxynitride layer 9 is unlikely to be formed at the contact portion between the resistor 2 and the pair of top electrodes 3, so that the electrical connection between the resistor 2 and the pair of top electrodes 3 can be stabilized. It will be possible.
  • the resistor 2 is formed by reactive sputtering in the resistor forming step, so that the ratio of the elements contained in the target of the resistor 2 is the target composition. It's almost the same. Therefore, it is possible to control the chemical composition of the resistor 2.
  • the heat treatment step is executed on the resistor 2 formed in the resistor forming step. This makes it possible to form the surface oxynitride layer 9 on the surface 23 of the resistor 2.
  • the resistor 2 contains Cr, Si, N and O, and does not contain Al (aluminum).
  • the specific resistance of the resistor 2 changes from about 500 ⁇ ⁇ cm to about 10,000 ⁇ ⁇ cm by changing the atomic ratio of Cr and Si in the resistor 2 from 3: 2 to 1: 4 (Fig.). See the black circle and solid line in 3).
  • the specific resistance of the resistor 2 when Al is not contained is about 6000 ⁇ ⁇ cm.
  • the specific resistance of the resistor 2 when 21% of Al is contained (added) is about 15,000 ⁇ ⁇ cm (see the black square in FIG. 3). That is, the specific resistance of the resistor 2 when 21% of Al is contained is about 2.5 times the specific resistance of the resistor 2 when Al is not contained. Therefore, when the atomic ratio of Cr and Si in the resistor 2 is 1: 4, the specific resistance of the resistor 2 when Al is contained in 21% is about 25,000 ⁇ ⁇ cm. From the above, in the chip resistor 10 according to the present embodiment, the specific resistance of the resistor 2 is preferably 500 ⁇ ⁇ cm or more and 20000 ⁇ ⁇ cm or less.
  • the chip resistor 10 according to the present embodiment, it is possible to adjust the specific resistance of the resistor 2 by changing the chemical composition of the resistor 2.
  • the horizontal axis of FIG. 4 is the heat treatment temperature in the above-mentioned heat treatment step.
  • the vertical axis on the left side of FIG. 4 is the specific resistance of the resistor 2
  • the vertical axis on the right side of FIG. 4 is the TCR of the resistor 2.
  • the atomic ratio of Cr and Si in the resistor 2 is 3: 2.
  • the atomic ratio of Si to Cr in the resistor 2 is 2/3.
  • the atomic percentage of N in the resistor 2 is 12 atom%.
  • the heat treatment temperature in the heat treatment step is 520 ° C ⁇ 5 ° C as described above. Therefore, in the example of FIG. 4, by setting the heat treatment temperature to 520 ° C. ⁇ 5 ° C., the TCR of the resistor 2 can be -25 ppm / K or more and + 25 ppm / K or less (FIG. 4). See the solid line in). That is, in the chip resistor 10 according to the present embodiment, the temperature coefficient of resistance (TCR) of the resistor 2 is ⁇ 25 ppm / ° C. or higher and + 25 ppm / ° C. or lower.
  • the TCR of the resistor 2 can be -25 ppm / ° C. or higher and + 25 ppm / ° C. or lower, so that both high resistivity and low TCR can be achieved at the same time. Is possible.
  • the broken line in FIG. 4 shows the change in the specific resistance of the resistor 2 with respect to the heat treatment temperature.
  • the horizontal axis of FIG. 5 is the atomic ratio (N ratio) of N in the resistor 2, and the vertical axis of FIG. 5 is the molar ratio of each crystal contained in the resistor 2.
  • the atomic ratio of Cr and Si in the resistor 2 is 1: 4.
  • the atomic ratio of Si to Cr in the resistor 2 is 4.
  • the atomic percentage (N ratio) of N in the resistor 2 is at least 50 atom% or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2. preferable. According to this configuration, it is possible to increase the specific resistance of the resistor 2.
  • the atomic percentage of N in the resistor 2 may be 1 atom% or more. That is, the atomic percentage of N in the resistor 2 may be at least 1 atm% or more and 50 atm% or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2.
  • FIG. 6 shows the result of forming a film of the resistor 2 on the glass substrate and performing elemental analysis.
  • the horizontal axis of FIG. 6 is the analysis depth in the resistor 2, and the vertical axis of FIG. 6 is the quantitative conversion value (atomic percentage) of each element.
  • the atomic ratio of Cr and Si in the resistor 2 is 1: 2.
  • the atomic ratio of Si to Cr in the resistor 2 is 2.
  • the atomic percentage of N in the resistor 2 is 30 atom%.
  • the film thickness Ft1 of the resistor 2 is 100 nm.
  • the resistor 2 includes Cr, Si, N and O.
  • the film thickness Ft1 of the resistor 2 is 100 nm. Therefore, in this case, the center of the resistor 2 in the film thickness direction D1 of the resistor 2 is 50 nm.
  • the atomic percentage (quantitative conversion value) of O in the resistor 2 is about 2 atom% (see the solid line in FIG. 6). That is, in the chip resistor 10 according to the present embodiment, the atomic percentage of O in the resistor 2 is at least 10 atom% or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2.
  • the chip resistor 10 it is possible to increase the specific resistance of the resistor 2 by containing O (oxygen) in the resistor 2.
  • the surface oxynitride layer 9 is formed on the surface 23 of the resistor 2, and the film thickness of the surface oxynitride layer 9 is, for example, 10 nm. That is, in FIG. 6, the surface oxynitride layer 9 has an analysis depth in the range of 0 nm to 10 nm. That is, as shown in FIG. 6, the surface oxynitride layer 9 has a composition from the surface 91 of the surface oxynitride layer 9 (see FIG. 2) to the inside of the surface oxynitride layer 9 in the film thickness direction D1 of the resistor 2. It has a slope. As a result, the stress is relaxed in the surface oxynitride layer 9, so that there is an advantage that the surface oxynitride layer 9 is not easily peeled off from the resistor 2.
  • the surface oxynitride layer 9 has a depth from the surface 91 of the surface oxynitride layer 9 up to 10 nm, and the atomic ratio of Si is the atomic ratio of Cr and the atomic ratio of Al. It is higher than the sum of. As a result, a very stable passivation is formed, which has an advantage that the protection performance of the resistor 2 is improved. Further, as shown in FIG. 6, on the surface (outermost surface) 91 of the surface oxynitride layer 9, the atomic ratio of Cr to Si is higher than that of the center of the resistor 2 in the film thickness direction D1.
  • the atomic percentage (quantitative conversion value) of O in the resistor 2 is about 2 atom%, but it may be 10 atom% or less. Further, the atomic percentage of O in the resistor 2 may be 0 atom% or more. That is, the atomic percentage of O in the resistor 2 may be 0 atom% or more and 10 atom% or less. More preferably, the atomic percentage of O in the resistor 2 is 0.1 atm% or more and 10 atom% or less.
  • the horizontal axis of FIG. 7 is the sheet resistance of the resistor 2, and the vertical axis of FIG. 7 is the film thickness Ft1 of the resistor 2 (see FIG. 1).
  • the atomic ratio of Cr and Si in the resistor 2 is 1: 2.
  • the atomic ratio of Si to Cr in the resistor 2 is 2.
  • the atomic percentage of N in the resistor 2 is 30 atom%.
  • the sheet resistance of the resistor 2 is about 10 ⁇ / ⁇ when the film thickness Ft1 of the resistor 2 is about 800 nm, and about 7500 ⁇ / ⁇ when the film thickness Ft1 of the resistor 2 is about 5 nm. ⁇ (see the solid line in Fig. 7).
  • the film thickness Ft1 of the resistor 2 is preferably 5 nm or more and 1000 nm or less.
  • the chip resistor 10 includes an insulating substrate 1, a resistor 2, and a top electrode (electrode) 3.
  • the resistor 2 contains Cr, Si and N, and is provided on the insulating substrate 1.
  • the top electrode 3 contains at least one refractory metal and is provided on the resistor 2.
  • the refractory metal is a metal having a melting point of 800 ° C. or higher.
  • the atomic ratio of Si to Cr in the resistor 2 is at least 2/3 or more and 4 or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2.
  • the atomic percentage of N in the resistor 2 is at least 50 atom% or less at the center of the resistor 2 in the film thickness direction D1.
  • the atomic ratio of Si to Cr in the resistor 2 is at least 2/3 or more at the center of the resistor 2 in the film thickness direction D1 of the resistor 2. And it is 4 or less. This makes it possible to lower the TCR of the resistor 2.
  • the atomic percentage of N in the resistor 2 is at least 50 atom% or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2. This makes it possible to increase the specific resistance of the resistor 2. That is, according to the chip resistor 10 according to the present embodiment, it is possible to achieve both high resistivity and low TCR.
  • the top electrode 3 provided on the resistor 2 contains a refractory metal. Therefore, the heat treatment can be performed with the upper surface electrode 3 formed on the resistor 2, and as a result, the surface oxynitride layer 9 is difficult to be formed at the contact portion between the resistor 2 and the upper surface electrode 3, so that the resistance It is also possible to stabilize the electrical connection between the body 2 and the top electrode 3.
  • the resistor 2 contains Cr, Si, N and O, but the resistor 2 may contain Al (aluminum) in addition to Cr, Si, N and O.
  • the resistor 2 contains Cr, Si, N and Al.
  • the atomic percentage of Al in the resistor 2 is preferably 30 atom% or less at least at the center of the resistor 2 in the film thickness direction D1 of the resistor 2.
  • the atomic ratio of Si to Cr in the resistor 2 is at least 2/3 or more and 4 or less at the center of the resistor 2 in the film thickness direction D1 of the resistor 2. Is preferable. Further, in the chip resistor 10 according to the first modification, the atomic percentage of N in the resistor 2 is preferably 50 atom% or less at least at the center of the resistor 2 in the film thickness direction D1 of the resistor 2.
  • each of the pair of top electrodes (electrodes) 3 contains at least one refractory metal and is provided on the resistor 2.
  • the refractory metal is a metal having a melting point of 800 ° C. or higher.
  • the resistor 2 contains Al in addition to Cr, Si, N and O. This makes it possible to increase the specific resistance of the resistor 2 as compared with the case where the resistor 2 does not contain Al.
  • each of the pair of top electrodes 3 contains a refractory metal. Therefore, it is possible to heat the resistor 2 with the upper surface electrode 3 formed on the resistor 2, and as a result, the surface oxynitride layer 9 is formed at the contact portion between the resistor 2 and the upper surface electrode 3. Since it is difficult to form, it is possible to stabilize the electrical connection between the resistor 2 and the top electrode 3.
  • each of the pair of top electrodes 3 contains W (tungsten) as the refractory metal, but the present invention is not limited to this.
  • Each of the pair of top electrodes 3 may contain, for example, a metal other than W among the above-mentioned refractory metals. Further, each of the pair of top electrodes 3 may contain two or more melting point metals. In this case, each of the pair of top electrodes 3 may have a single-layer structure of an alloy composed of two or more refractory metals, or a laminated structure in which two or more refractory metals are laminated. May be good.
  • the top electrode 3 is patterned by wet etching in the first pattern forming step, but the top electrode 3 may be patterned by dry etching, for example.
  • the top electrode 3 is formed on the resistor 2 by sputtering, and then the top electrode 3 is patterned by wet etching, but the present invention is not limited to this.
  • the upper surface electrode 3 may be formed by mask sputtering, and the upper surface electrode 3 may be patterned. That is, the method for manufacturing the chip resistor 10 may include an electrode forming step of forming the upper surface electrode 3 on the resistor 2 by mask sputtering and forming a pattern of the upper surface electrode 3. More specifically, masking is performed except for the portion of the surface 23 of the resistor 2 that forms the pattern of the top electrode 3.
  • the chip resistor (10) includes an insulating substrate (1), a resistor (2), and an electrode (3).
  • the resistor (2) contains Cr, Si and N and is provided on the insulating substrate (1).
  • the electrode (3) contains at least one refractory metal and is provided on the resistor (2).
  • the refractory metal is a metal having a melting point of 800 ° C. or higher.
  • the atomic ratio of Si to Cr in the resistor (2) is at least 2/3 or more and 4 or less at the center of the resistor (2) in the film thickness direction (D1) of the resistor (2).
  • the atomic percentage of N in the resistor (2) is at least 50 atom% or less at the center of the resistor (2) in the film thickness direction (D1).
  • the chip resistor (10) includes an insulating substrate (1), a resistor (2), and an electrode (3).
  • the resistor (2) contains Cr, Si, N and Al and is provided on the insulating substrate (1).
  • the electrode (3) contains at least one refractory metal and is provided on the resistor (2).
  • the refractory metal is a metal having a melting point of 800 ° C. or higher.
  • the atomic ratio of Si to Cr in the resistor (2) is at least 2/3 or more and 4 or less at the center of the resistor (2) in the film thickness direction (D1) of the resistor (2).
  • the atomic percentage of N in the resistor (2) is at least 50 atom% or less at the center of the resistor (2) in the film thickness direction (D1).
  • the atomic percentage of Al in the resistor (2) is at least 30 atom% or less at the center of the resistor (2) in the film thickness direction (D1).
  • the resistor (2) further includes O.
  • the atomic percentage of O in the resistor (2) is at least 10 atom% or less at the center of the resistor (2) in the film thickness direction (D1).
  • the specific resistance of the resistor (2) is 500 ⁇ ⁇ cm or more and 20000 ⁇ ⁇ cm or less. be.
  • the temperature coefficient of resistance of the resistor (2) is ⁇ 25 ppm / ° C. or higher and + 25 ppm / ° C. It is as follows.
  • the chip resistor (10) according to the sixth aspect further includes a surface oxynitride layer (9) in any one of the first to fifth aspects.
  • the surface oxynitride layer (9) is composed of an oxynitride film containing at least one of Cr and Al and Si.
  • the surface oxynitride layer (9) is provided on the surface (23) of the resistor (2) opposite to the insulating substrate (1) except for the portion where the electrode (3) is formed. ..
  • the manufacturing method according to the seventh aspect is the manufacturing method of the chip resistor (10) according to any one of the first to sixth aspects.
  • the manufacturing method includes an electrode forming step and a pattern forming step.
  • the electrode forming step is a step of forming the electrode (3) on the resistor (2) by sputtering.
  • the pattern forming step is a step of forming a pattern of the electrode (3) on the resistor (2) by etching.
  • the manufacturing method according to the eighth aspect is the manufacturing method of the chip resistor (10) according to any one of the first to sixth aspects.
  • the manufacturing method includes an electrode forming step.
  • the electrode forming step is a step of forming the electrode (3) on the resistor (2) by mask sputtering and forming the pattern of the electrode (3).
  • the manufacturing method according to the ninth aspect further includes a heat treatment step in the seventh or eighth aspect.
  • the heat treatment step is a step of heat-treating the resistor (2) and the electrode (3) formed on the resistor (2).
  • the surface oxynitride layer (9) is formed on the resistor (2) while making it difficult for the surface oxynitride layer (9) to be formed between the resistor (2) and the electrode (3). It becomes possible to do.
  • the heat treatment temperature is 500 ° C. or higher and 800 ° C. or lower in the heat treatment step.
  • a stronger surface oxynitride layer (9) can be formed on the resistor (2).
  • the configuration according to the third to sixth aspects is not an essential configuration for the chip resistor (10) and can be omitted as appropriate.
  • the configurations according to the ninth to tenth aspects are not essential configurations for the manufacturing method and can be omitted as appropriate.
  • the film thickness (Ft1) of the resistor (2) is 5 nm or more and 1000 nm or less. ..
  • the resistor (2) has a crystalline phase (21) and an amorphous phase. (22) and.
  • the surface oxynitride layer (9) is the resistor (2) in the surface oxynitride layer (9) in the film thickness direction (D1). It has a composition gradient from the surface (91) on the opposite side to the inside of the surface oxynitride layer (9).
  • the surface oxynitride layer (9) is the outermost surface (91) in the film thickness direction (D1) in the film thickness direction (D1).
  • the atomic ratio of Cr to Si is higher than that of the center of the resistor (2).
  • the manufacturing method according to the fifteenth aspect is the manufacturing method of the chip resistor (10) according to any one of the first to sixth and tenth to fourteenth aspects.
  • the manufacturing method includes a resistor forming step and a pattern forming step.
  • the resistor forming step is a step of forming the resistor (2) on the insulating substrate (1) by reactive sputtering.
  • the pattern forming step is a step of etching the resistor (2) by the photolithography method to form a pattern of the resistor (2) on the insulating substrate (1).
  • the sputtering target of the reactive sputtering contains O of 20 atom% or less.
  • the production method according to the seventeenth aspect further includes a heat treatment step in the fifteenth or sixteenth aspect.
  • the heat treatment step is a step of heat-treating the resistor (2) formed by the pattern forming step.
  • the heat treatment temperature is 300 ° C. or higher and 800 ° C. or lower in the heat treatment step.
  • the oxygen concentration is 1000 ppm or less in the heat treatment step.
  • an etching solution containing hydrofluoric acid is used in the pattern forming step.
  • the pattern of the resistor (2) can be formed on the insulating substrate (1).

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Non-Adjustable Resistors (AREA)
PCT/JP2021/036549 2020-10-06 2021-10-04 チップ抵抗器、及び製造方法 Ceased WO2022075238A1 (ja)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025053030A1 (ja) * 2023-09-04 2025-03-13 パナソニックＩｐマネジメント株式会社 抵抗器及び抵抗器の製造方法
WO2025164036A1 (ja) * 2024-01-30 2025-08-07 パナソニックＩｐマネジメント株式会社 チップ抵抗器

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI909992B (zh) * 2025-03-14 2025-12-21 國巨股份有限公司 薄膜電阻及其製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05347202A (ja) * 1992-06-15 1993-12-27 Tdk Corp 電子部品及び電子部品の抵抗値調整方法
JPH08264304A (ja) * 1995-03-09 1996-10-11 Philips Electron Nv ＣｒＳｉ抵抗薄膜を含む抵抗素子
JPH10144501A (ja) * 1996-09-11 1998-05-29 Matsushita Electric Ind Co Ltd チップ抵抗器及びその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5907274A (en) * 1996-09-11 1999-05-25 Matsushita Electric Industrial Co., Ltd. Chip resistor
JP3738313B2 (ja) 1999-05-13 2006-01-25 カシオ計算機株式会社 発熱抵抗体とその製造方法
JP2000340413A (ja) * 1999-05-26 2000-12-08 Matsushita Electric Ind Co Ltd 多連チップ抵抗器およびその製造方法
JP3664655B2 (ja) 2000-03-13 2005-06-29 進工業株式会社 高比抵抗材料とその製造方法
WO2017047512A1 (ja) * 2015-09-16 2017-03-23 Ｓｅｍｉｔｅｃ株式会社 抵抗器及び温度センサ
JP6572143B2 (ja) * 2016-01-27 2019-09-04 Koa株式会社 チップ抵抗器およびその製造方法
US11765824B2 (en) * 2020-07-21 2023-09-19 Panasonic Intellectual Property Management Co., Ltd. Laminated ceramic sintered body board for electronic device, electronic device, chip resistor, and method for manufacturing chip resistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05347202A (ja) * 1992-06-15 1993-12-27 Tdk Corp 電子部品及び電子部品の抵抗値調整方法
JPH08264304A (ja) * 1995-03-09 1996-10-11 Philips Electron Nv ＣｒＳｉ抵抗薄膜を含む抵抗素子
JPH10144501A (ja) * 1996-09-11 1998-05-29 Matsushita Electric Ind Co Ltd チップ抵抗器及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025053030A1 (ja) * 2023-09-04 2025-03-13 パナソニックＩｐマネジメント株式会社 抵抗器及び抵抗器の製造方法
WO2025164036A1 (ja) * 2024-01-30 2025-08-07 パナソニックＩｐマネジメント株式会社 チップ抵抗器

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