WO2022068428A1 - 一种显示基板及其制造方法、显示装置 - Google Patents

一种显示基板及其制造方法、显示装置 Download PDF

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Publication number
WO2022068428A1
WO2022068428A1 PCT/CN2021/112656 CN2021112656W WO2022068428A1 WO 2022068428 A1 WO2022068428 A1 WO 2022068428A1 CN 2021112656 W CN2021112656 W CN 2021112656W WO 2022068428 A1 WO2022068428 A1 WO 2022068428A1
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Prior art keywords
isolation
layer
metal pattern
area
metal
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PCT/CN2021/112656
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English (en)
French (fr)
Inventor
孙开鹏
程羽雕
龙跃
王本莲
金度岭
郑海
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/788,614 priority Critical patent/US20230225173A1/en
Publication of WO2022068428A1 publication Critical patent/WO2022068428A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • AA Hole design that is, an opening design is set in the active display area (Active Area, referred to as: AA area), so that sensors such as cameras can be placed on the AA Below the hole (Hole) in the area, in order to reduce the screen frame and improve the screen ratio.
  • the frame structure around the opening mainly includes isolation columns.
  • the isolation columns are mainly used to isolate the water and oxygen where the opening is cut from eroding to the display area, and to protect the organic light-emitting material (Electro-Luminescence) in the display area. , referred to as the EL layer) is not affected.
  • the inner and outer isolation columns of AA Hole are formed by using EB Mask (electron beam mask) to etch away the inorganic layer. This structure requires a separate EB Mask design. The number of masks in the manufacturing process is large and the cost is high. The process is cumbersome.
  • the present invention provides a display substrate, a manufacturing method thereof, and a display device, which can reduce the number of masks, reduce costs, and simplify processes.
  • Embodiments of the present disclosure provide a display substrate, including a base substrate, the base substrate including an opening area, an isolation area surrounding the opening area, and a display area surrounding the isolation area, the isolation area At least one isolation column is provided, and each isolation column is arranged in a circle around the opening area; a light-emitting layer covering the isolation column is arranged in the display area and the isolation area, and the The isolation column separates the light-emitting layer between the opening area and the display area; the isolation column includes: multi-layer metal patterns stacked on the base substrate in sequence; and an insulating film layer , the insulating film layer is a stacked layer conformally covering the metal pattern.
  • the multi-layered metal patterns include: a first metal pattern, a second metal pattern and a third metal pattern stacked in sequence from a side close to the base substrate to a side away from the base substrate ;
  • At least one layer of metal patterns in the first metal pattern, the second metal pattern and the third metal pattern is the same layer and material as the gate, and at least another layer of metal patterns is the same as the source and drain. Very same layer and same material.
  • the display area includes a first gate metal pattern and a second gate metal pattern arranged in layers, and at least one of the first gate metal pattern and the second gate metal pattern is the gate;
  • the first metal pattern and the first gate metal pattern are arranged in the same layer and with the same material;
  • the second metal pattern and the second gate metal pattern are arranged in the same layer and with the same material;
  • the insulating film layer includes: a first insulating layer located between the first metal pattern and the second metal pattern, and a first insulating layer located between the second metal pattern and the third metal pattern.
  • the isolation pillar includes a first side located on a side close to the display area and a second side located on a side close to the aperture area;
  • the difference between the radial widths of the metal steps of two adjacent metal patterns in a direction parallel to the base substrate is greater than or equal to 1 micrometer; on the second side, The difference between the radial widths of the metal steps in the direction parallel to the base substrate of the two adjacent metal patterns is greater than or equal to 1 micrometer.
  • the isolation pillars are provided in the isolation area, the at least two isolation pillars include an inner isolation pillar and an outer isolation pillar, and the inner isolation pillar is located near the display area of the outer isolation pillar.
  • An isolation dam is arranged between the inner isolation column and the outer isolation column, and an organic packaging frame covering the inner isolation column is arranged between the isolation dam and the display area.
  • Embodiments of the present disclosure further provide a display device, including: the display substrate provided by the embodiments of the present disclosure.
  • Embodiments of the present disclosure also provide a method for manufacturing a display substrate, the method comprising:
  • the base substrate including an aperture area, an isolation area surrounding the aperture area, and a display area surrounding the isolation area;
  • At least one isolation column is formed in the isolation area, wherein each isolation column is arranged in a circle around the opening area; the light-emitting layer, and the isolation column separates the light-emitting layer between the opening area and the display area; the isolation column includes: multilayer metal layers stacked on the base substrate in sequence and a multi-layered insulating film layer conformally covering the metal pattern.
  • the display area is provided with a thin film transistor, and the thin film transistor includes a gate electrode, a source electrode and a drain electrode; and forming at least one isolation column in the isolation area specifically includes:
  • a patterned first metal pattern, a second metal pattern and a third metal are formed on the base substrate, wherein at least one layer of the first metal pattern, the second metal pattern and the third metal pattern
  • the metal pattern is formed by the same patterning process as the gate, and at least another layer of the metal pattern is formed by the same patterning process as the source and drain.
  • the isolation column is directly formed with multi-layer steps by multi-layer metal patterns. , and is formed by an insulating film layer covering the metal pattern with the shape.
  • the same mask can be used to directly form the corresponding metal in the isolation column.
  • EB Mask ion beam mask
  • FIG. 1 shows a schematic diagram of the overall structure of a display panel in the related art
  • Fig. 2 shows the structure schematic diagram of A-A direction isolation region in Fig. 1;
  • FIG. 3 is a schematic diagram showing the overall structure of a display substrate provided in an embodiment of the present disclosure
  • Fig. 4 shows the structural representation of A'-A' in Fig. 3 to the isolation region
  • FIG. 5 is a schematic structural diagram of a spacer column in a display substrate provided by an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of the structure of the isolation area from the AA area to the opening area in the OLED display panel shown in FIG. 1.
  • FIG. 2 is a partial cross-sectional view of the OLED display panel shown in FIG. 1 with A-A as the cutting line. The structure from the area to the open area.
  • the display screen includes an opening area (Hole area) 10 , an isolation area 20 surrounding the opening area 10 , and a display area (AA area) surrounding the isolation area 20 .
  • an isolation frame structure needs to be set in the isolation area 20 to isolate the EL layer 40 between the AA area 10 and the opening area 30 to prevent water vapor and oxygen from being transmitted to the AA area 10 along the EL layer, which will cause the display The display of the panel fails.
  • the isolation frame structure mainly includes: isolation pillars 21, isolation dams 22 and organic packaging frame 23, wherein the isolation pillars 21 are mainly used to isolate the water and oxygen at the cutting of the hole area 30 from eroding to the AA area 10, and protect the organic light-emitting material ( Electro-Luminescence, referred to as the EL layer) is not affected; the isolation dam 22 is used to prevent the inkjet printing (Ink Jet Printing, referred to as: IJP) material forming the organic packaging frame 23 from overflowing, so as to ensure the organic packaging frame (TFE packaging) outside the Dam. )23 effectiveness, thereby ensuring product reliability.
  • IJP Ink Jet Printing
  • the isolation column in the isolation area adopts an ion beam mask (EB Mask), and the inorganic layer is etched away by the EB Mask to form a film layer fault, and the isolation column is formed,
  • EB Mask ion beam mask
  • the embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device, which can reduce the number of masks, reduce costs, and simplify processes.
  • FIG. 3 is a schematic diagram of the overall structure of the display substrate provided in the embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of the structure of the isolation area from the AA area to the opening area in the display substrate shown in the figure, and FIG. 4 is specifically:
  • the display substrate shown in FIG. 1 is a partial cross-sectional view with A'-A' as the cutting line, and the cutting line A'-A' represents the structure from the AA area to the opening area.
  • a display substrate provided by an embodiment of the present disclosure includes a base substrate 100 , and the base substrate 100 includes an opening area 200 , an isolation area 300 surrounding the opening area 200 , and an isolation area 300 surrounding the opening area 200 .
  • the isolation pillars 500 are formed by: before the light emitting layer 600 is vapor-deposited on the base substrate 100, the overall structure of the isolation pillars 500 is formed first. When the light-emitting layer 600 is evaporated, the formed isolation column 500 can be used to separate the light-emitting layer 600 between the opening area 200 and the display area 400 .
  • the isolation column 500 is formed by stacking multiple metal patterns 500a, and each metal pattern 500a is a pattern surrounding the opening area 200.
  • the sidewall of the multilayer metal pattern 500a can form a film layer fracture
  • the difference is used to block the light-emitting layer 600, and the insulating film layer 500b can be disposed between adjacent metal patterns 500a, and the insulating film layer 500b covers the metal pattern 500a conformally, and finally forms the The isolation column 500 is described.
  • the insulating film layer 500b includes multiple insulating layers, and each insulating layer is a continuous film layer. That is, the insulating film layer 500b is conformally covered on the metal step at the sidewall of the metal step. , rather than being disconnected by etching.
  • metal film layers such as thin film transistors and electrode layers can be provided in the display area 400, so that the metal layer in the display area 400 can be directly formed in the display substrate manufacturing process.
  • EB Mask ion beam mask
  • the display substrate provided by the embodiments of the present disclosure will be described in more detail below.
  • FIG. 4 is a schematic structural diagram of a display substrate provided in some exemplary embodiments of the present disclosure, wherein only a part of the structure of the display substrate is shown, but not the whole structure is shown.
  • an inorganic layer 110 is further provided on the base substrate 100 , and the inorganic layer 110 includes a barrier layer (Barrier) and a buffer layer that are sequentially stacked in a direction away from the base substrate 100 .
  • layer (Buffer) the base substrate 100 may be a flexible substrate or a glass substrate composed of polyimide (PI) or the like.
  • the display substrate also includes some conventional structures, such as: thin film transistor (TFT), planarization layer (PLN), pixel definition layer (PDL), light emitting layer 600 (EL layer), first inorganic encapsulation layer, organic layer and the first Two inorganic encapsulation layers, any material of the first inorganic encapsulation layer and the second inorganic encapsulation layer may be SiNx, SiCN, SiO2, or the like.
  • the first inorganic encapsulation layer and the second inorganic encapsulation layer can be formed by chemical vapor deposition, physical vapor deposition, atomic force deposition, and the like.
  • the organic layer may include acrylic-based polymers, silicon-based polymers, and the like.
  • the organic layer may be formed on the side of the first inorganic encapsulation layer facing away from the base substrate 100 by means of inkjet printing, spray coating, or the like.
  • the display area 400 is provided with a thin film transistor (TFT), the thin film transistor includes a gate electrode, a source electrode and a drain electrode;
  • the multi-layered metal pattern 500a includes : the first metal pattern 510 , the second metal pattern 520 and the third metal pattern 530 stacked in sequence from the side close to the base substrate 100 to the side far from the base substrate 100 ;
  • the first metal pattern 510 At least one metal pattern of the pattern 510, the second metal pattern 520 and the third metal pattern 530 is the same layer and material as the gate, and at least another metal pattern is the same as the source and drain layer and the same material.
  • the multi-layer metal pattern 500a of the isolation pillar 500 at least one layer of metal pattern and the gate electrode of the display area 400 are in the same layer and the same material, that is, at least one layer of metal pattern in the isolation pillar 500 is the same as that of the display area 400.
  • the gate metal patterns in the area 400 are formed using the same mask and using the same patterning process; at least one layer of metal patterns 500a is formed using the same mask as the source and drain metal patterns in the display area 400, using the same patterning process. form. In this way, compared with the method of etching the inorganic layer to form the isolation column 500 in the related art, the number of masks can be reduced and the cost can be reduced.
  • the multi-layer metal patterns 500a in the isolation pillars 500 may also be formed by using other metal film layers.
  • at least one layer of metal patterns may also be It is formed using a cathode layer or an anode layer of the display area 400 or the like.
  • a plurality of TFTs are provided in the display area 400, and the TFTs may be top-gate TFTs, bottom-gate TFTs or double-gate TFTs.
  • the type is not limited.
  • the thin film transistor includes an active layer disposed on the side of the buffer layer facing away from the base substrate 100, a gate insulating layer (GI) disposed on the side of the active layer facing away from the base substrate 100, and a gate insulating layer (GI) disposed on the side facing away from the gate insulating layer
  • the gate on the side of the base substrate 100 is disposed on the interlayer dielectric layer (ILD) on the side of the gate insulating layer facing away from the base substrate 100, and the conductive layer on the side of the interlayer dielectric layer facing away from the base substrate 100,
  • the conductive layer includes a source electrode and a drain electrode of the thin film transistor, and the source electrode and the drain electrode are respectively electrically connected to the active layer.
  • the display area 400 includes a first gate metal pattern ( GI1 ) and a second gate metal pattern ( GI2 ) arranged in layers, and the first gate metal pattern ( At least one of GI1) and the second gate metal pattern (GI2) is the gate; the first metal pattern 510 and the first gate metal pattern (GI1) are arranged in the same layer and with the same material; the The second metal pattern 520 and the second gate metal pattern ( GI2 ) are arranged in the same layer and material; the third metal pattern 530 is arranged in the same layer and material as the source and drain electrodes.
  • the insulating film layer 500b includes: a first insulating layer 550 located between the first metal pattern 510 and the second metal pattern 520 and a a second insulating layer 540 located between the second metal pattern 520 and the third metal pattern 530; wherein at least one of the first insulating layer 550 and the second insulating layer 540 includes a gate electrode
  • the insulating layer, at least another film layer includes an interlayer dielectric layer and a buffer layer.
  • the metal patterns 500a and the insulating film layers 500b are not specifically limited, as long as the metal patterns 500a can be stacked to form a film break. , the insulating film layer 500b conforms to cover the metal pattern 500a, and finally the isolation column 500 structure is formed, all of which should fall within the protection scope of the display substrate provided by the present disclosure.
  • the isolation pillar 500 includes a first side located on a side close to the display area 400 and a side located close to the aperture area 200 in the isolation column 500, from the side close to the base substrate 100 to the side away from the base substrate 100, the metal patterns 500a of each layer are parallel to the base substrate
  • the radial width in the direction of 100 gradually decreases, that is to say, as shown in FIG.
  • the radial widths of the metal pattern 520 (Gate2) and the third metal pattern 530 (SD) are gradually reduced, so that the first side and the second side form a plurality of stepped structures.
  • a first metal pattern 510 is first formed to form a first step, and then a first metal pattern 510 is conformally covered with a layer of first metal pattern 510 .
  • An insulating layer eg, the first inorganic layer GI1 , so that the first insulating layer will have a stepped transition at the first step formed by the first metal pattern 510 , and then continue on the step of the first metal pattern 510 A second metal pattern 520 is then formed.
  • the radial width of the steps of the first metal pattern 510 is greater than the radial width of the steps of the second metal pattern 520, thereby forming a second layer of steps.
  • the second metal pattern 520 is conformally covered.
  • the second insulating layer eg, an interlayer insulating layer and a buffer layer
  • the second insulating layer will be at the first step formed by the first metal pattern 510 and the second layer formed by the second metal pattern 520, respectively
  • There is a stepped transition at each step that is to say, there will be two stepped transitions on the second insulating layer, and so on, and other layers of metal patterns 500a and other insulating layers are gradually formed, so that the first The side and the second side form a plurality of stepped structures.
  • the metal patterns 500a of each layer in the isolation pillar 500 are the same, then the metal patterns 500a of each layer will cause a larger film layer break between the first side and the second side of the isolation pillar 500 , for the insulating layer, there may be risks such as rupture damage, and the function of blocking water and oxygen from entering the AA area may be lost.
  • the difference between the radial widths of metal steps in a direction parallel to the base substrate 100 between two adjacent metal patterns 500 a is D1 is greater than or equal to 1 micrometer; on the second side, the difference D2 of the radial widths of metal steps between two adjacent metal patterns 500a in a direction parallel to the base substrate 100 is greater than or equal to 1 micrometer.
  • the distance between the steps of the first metal pattern 510 and the steps of the second metal pattern 520 is the distance between the two adjacent
  • the value D1 of the radial width difference D1 of the metal steps in the direction parallel to the base substrate 100 of the metal pattern 500a is greater than or equal to 1 ⁇ m.
  • the steps of the second metal pattern 520 and the third metal pattern 530 The value of the distance D2 between them is greater than or equal to 1 micron. This value is verified by the actual process. If it is less than 1 micron, there may be risks such as cracking and damage of the isolation pillar 500.
  • Such a design can also make the isolation pillar 500 structure and related technologies.
  • the structure of the isolation pillar 500 obtained by etching the inorganic layer using EB Mask maintains substantially the same structure design of the isolation pillar 500 .
  • the difference between the radial widths of the metal steps of two adjacent metal patterns 500 a in a direction parallel to the base substrate 100 is greater than or equal to 1 ⁇ m.
  • the cross-sectional shape of each metal pattern 500 a in a direction perpendicular to the base substrate 100 is a trapezoid, and in other embodiments , the cross-sectional shape of the metal pattern 500a of each layer may also be other shapes such as a rectangle, which is not limited.
  • the insulating film layer conforms to the shape and covers the metal pattern, and the slope angle that can be formed ranges from 30 to 60 degrees. In this way, it is conducive to the breaking of the EL light-emitting layer, and at the same time, it can ensure that the encapsulation layer (TFE) 700 does not break. good for packaging.
  • TFE encapsulation layer
  • the metal pattern 500a of each layer is The radial width in the direction parallel to the base substrate 100 gradually decreases, but in other embodiments, the relationship between the radial widths of the metal patterns 500a of each layer is not limited to this, and will not be repeated here. Repeat.
  • At least two isolation pillars 500 are provided in the isolation region 300 , and the at least two isolation pillars 500 include an inner isolation pillar 501 and an outer isolation pillar 500 .
  • Isolation pillars 502 the inner isolation pillars 501 are located on the side of the outer isolation pillars 502 close to the display area 400, and an isolation dam 503 is provided between the inner isolation pillars 501 and the outer isolation pillars 502,
  • An organic package frame 504 covering the inner isolation pillar 501 is disposed between the isolation dam 503 and the display area 400 .
  • the isolation pillars 500 may be provided, and the multiple isolation pillars 500 are distributed at intervals, and a recess is formed between two adjacent isolation pillars 500 to disconnect the light emitting layer 600 , the increase in the number of the isolation columns 500 can increase the effectiveness of cutting off the water and oxygen intrusion channels. It should be noted that the increase in the number of the isolation pillars 500 may increase the difficulty of the manufacturing process of the display panel and increase the production cost. Therefore, in practical applications, the specific number of the isolation pillars 500 can be selected according to actual needs. For the isolation pillars 500 The specific number is not limited.
  • the distance between two adjacent isolation pillars 500 in a direction parallel to the base substrate 100 ranges from 80 to 130 ⁇ m, wherein adjacent The distance between the two isolation pillars 500 in the direction parallel to the base substrate 100 specifically refers to the closest distance between the third metal patterns 530 in the two adjacent isolation pillars 500 .
  • isolation dam 503 is arranged between the isolation dam 503 and the outer isolation pillar 502, and an organic package frame 504 is formed between the isolation dam 503 and the display area 400.
  • the inner isolation pillar and the outer isolation pillar are parallel to each other. The spacing in the direction of the base substrate 100 (X direction in FIG.
  • the isolation column 500 is preferably 127 ⁇ 0.5 ⁇ m; in some specific embodiments of the present disclosure, two isolation columns 500 are arranged on the base substrate 100 at intervals, close to the display area
  • the isolation column 500 on the side of 400 is the inner isolation column 501
  • the isolation column 500 on the side close to the opening area 200 is the outer isolation column 502.
  • the isolation column 500 can improve the ability of the isolation column 500 to cut off the water and oxygen intrusion channels. Effectiveness, and can avoid excessive production cost caused by too many isolation columns 500 .
  • the isolation area is provided with only one isolation column, an isolation dam is provided between the isolation column and the opening area, and an organic packaging frame is formed between the isolation dam and the display area;
  • the number of isolation pillars set in the isolation area is more than two, and an isolation dam may be set between every two isolation pillars, wherein an organic package frame is formed between one isolation dam and the display area, for example , an organic encapsulation frame is formed between the isolation dam set between the two isolation columns closest to the display area and the display area; or, the isolation dam set between the two isolation columns closest to the opening area and the display area are formed an organic packaging frame; or, an organic packaging frame is formed between the isolation dam set between the two middle isolation pillars and the display area; between two adjacent isolation pillars 500 in a direction parallel to the base substrate 100
  • the value range of the spacing is 80 ⁇ 130 ⁇ m;
  • the number of isolation columns set in the isolation area is more than two, only one isolation dam is set between the two isolation columns farthest from the display area, and an organic package is formed between the isolation dam and the display area frame; alternatively, only one isolation dam is set between the two isolation columns farthest from the opening area, and an organic packaging frame is formed between the isolation dam and the display area; or, only one isolation dam is set between the two intermediate isolation columns
  • the isolation dam, an organic package frame is formed between the isolation dam and the display area; the distance between two adjacent isolation columns 500 in the direction parallel to the base substrate 100 ranges from 80 to 130 ⁇ m.
  • an isolation dam 503 (Dam) is provided in the interval between two adjacent isolation pillars 500, and the inner isolation pillar 501 and the outer isolation pillar 502 are mainly used to isolate the The water and oxygen where the hole area 200 is cut erodes to the AA area, which protects the organic light-emitting material (Electro-Luminescence, EL layer for short) light-emitting material of the display area 400 from being affected; between the isolation dam 503 and the display area 400
  • the organic packaging frame 504 covering the inner isolation column 501, the organic packaging frame 504 can be a packaging structure formed by using inkjet printing materials, and the isolation dam 503 is used to prevent the overflow of inkjet printing (IJP) materials to ensure Dam The effectiveness of the outer TFE package is guaranteed to ensure product reliability.
  • a cut heat-affected zone (margin) 504 is further provided in the isolation region, and the cut heat-affected zone 504 is used to separate the isolation region
  • the upper film layers and the opening area can avoid the influence of the film layer in the isolation area during laser cutting in the opening area.
  • the number of the isolation pillars is plural and extends to the vicinity of the heat-affected zone, or extends into the heat-affected zone.
  • each film layer in the isolation region may be as follows:
  • the value range of the film thickness of the first metal pattern (Gate1) is:
  • the value range of the film thickness of the second metal pattern (Gate2) is:
  • the third metal pattern (SD) is a stacked structure, and includes a first metal portion, The second metal part and the third metal part, wherein the material of the first metal part and the third metal part may be Ti (titanium), the material of the second metal part may be Al (aluminum), and the film layer of the first metal part
  • the thickness range is:
  • the value range of the film thickness of the second metal part is
  • the value range of the film thickness of the third metal part is
  • the value range of the film thickness of the first insulating layer (GI1) is:
  • the value range of the film thickness of the buffer layer (GI2) in the second insulating layer is:
  • the interlayer dielectric layer (IDL) in the second insulating layer may include a silicon oxide layer and a silicon nitride layer, wherein the film thickness of the silicon nitride layer ranges from:
  • the film thickness of the silicon oxide layer is
  • the film thickness of the first metal pattern (Gate1) is:
  • the film thickness of the second metal pattern (Gate2) is:
  • the third metal pattern (SD) is a stacked structure, and includes a first metal portion, a first metal portion, a first metal portion, a second metal portion, a first metal portion, a first metal portion, a second metal portion, a first metal portion, a second metal portion, a first metal portion, a first metal portion, a second metal portion and a second metal portion, which are sequentially stacked from the side away from the base substrate to the side close to the base substrate (ie, from top to bottom).
  • the film thickness of the first metal part and the third metal part can be Ti (titanium), the material of the second metal part can be Al (aluminum), and the film thickness of the first metal part for:
  • the film thickness of the second metal part is
  • the film thickness of the third metal part is
  • the film thickness of the first insulating layer (GI1) is:
  • the value range of the film thickness of the buffer layer (GI2) in the second insulating layer is:
  • the interlayer dielectric layer (IDL) in the second insulating layer may include a silicon oxide layer and a silicon nitride layer, wherein the film thickness of the silicon nitride layer is The film thickness of the silicon oxide layer is
  • the film thickness of the first metal pattern (Gate1) is:
  • the film thickness of the second metal pattern (Gate2) is:
  • the third metal pattern (SD) is a laminated structure, including a first metal part, a second metal part and a third metal part stacked in sequence from a side away from the base substrate to a side close to the base substrate
  • the material of the first metal part and the third metal part can be Ti (titanium), the material of the second metal part can be Al (aluminum), and the film thickness of the first metal part is:
  • the film thickness of the second metal part is
  • the film thickness of the third metal part is
  • the film thickness of the first insulating layer (GI1) is:
  • the value range of the film thickness of the buffer layer (GI2) in the second insulating layer is:
  • the interlayer dielectric layer (IDL) in the second insulating layer may include a silicon oxide layer and a silicon nitride layer, wherein the film thickness of the silicon nitride layer is: The
  • each film layer can be reasonably selected according to actual needs, and will not be listed one by one here.
  • the film thickness ratio of the first metal pattern and the second metal pattern is (0.73 ⁇ 1.37);
  • the film thickness ratio of a metal part is (3.51-5.78);
  • the film thickness ratio of the second metal part in the first metal pattern and the third metal pattern is (0.35-0.59);
  • the first metal pattern The film thickness ratio between the pattern and the third metal portion in the third metal pattern is (2.01-2.87);
  • the film thickness ratio between the first metal layer and the first insulating layer is (1.63-2.61);
  • the film thickness ratio of the first insulating layer and the buffer layer in the second insulating layer is (0.36-1.07);
  • the thickness of the buffer layer and the silicon nitride layer in the interlayer dielectric layer in the second insulating layer is The film thickness ratio is (0.37-1.11), and the film thickness ratio between the buffer layer and the silicon oxide layer is (0.50-1.73).
  • the film thickness ratio of the first metal pattern and the second metal pattern is 1.37; the film thickness of the first metal portion in the first metal pattern and the third metal pattern is The ratio is 3.51; the film thickness ratio of the second metal part in the first metal pattern and the third metal pattern is 0.35; the film thickness of the third metal part in the first metal pattern and the third metal pattern is 0.35;
  • the layer thickness ratio is 2.01; the film thickness ratio between the first metal layer and the first insulating layer is 1.63; the film thickness ratio between the first insulating layer and the buffer layer in the second insulating layer is 0.36 ;
  • the film thickness ratio between the buffer layer and the silicon nitride layer in the interlayer dielectric layer in the second insulating layer is 0.37, and the film thickness ratio between the buffer layer and the silicon oxide layer is 0.50.
  • the film thickness ratio of the first metal pattern and the second metal pattern is 0.73; the film thickness of the first metal portion in the first metal pattern and the third metal pattern is The ratio is 5.78; the film thickness ratio of the second metal part in the first metal pattern and the third metal pattern is 0.59; the film thickness of the third metal part in the first metal pattern and the third metal pattern is 0.59;
  • the layer thickness ratio is 2.87; the film thickness ratio between the first metal layer and the first insulating layer is 2.61; the film thickness ratio between the first insulating layer and the buffer layer in the second insulating layer is 1.07 ;
  • the film thickness ratio between the buffer layer and the silicon nitride layer in the interlayer dielectric layer in the second insulating layer is 1.11), and the film thickness ratio between the buffer layer and the silicon oxide layer is 1.73.
  • the film thickness ratio of the first metal pattern and the second metal pattern is 1; the film thickness ratio of the first metal portion in the first metal pattern and the third metal pattern is 4.55; the film thickness ratio of the second metal part in the first metal pattern and the third metal pattern is 0.45; the film thickness of the third metal part in the first metal pattern and the third metal pattern
  • the ratio is 5; the film thickness ratio between the first metal layer and the first insulating layer is 2.1; the film thickness ratio between the first insulating layer and the buffer layer in the second insulating layer is 0.92;
  • the film thickness ratio of the buffer layer to the silicon nitride layer in the interlayer dielectric layer in the second insulating layer is 0.43, and the film thickness ratio of the buffer layer to the silicon oxide layer is 0.65.
  • the verification method is, for example, a focused ion beam (Focused Ion beam, abbreviated as: FIB) process. It can be seen from the FIB result: , the isolation column 500 has no fracture phenomenon and no fracture risk.
  • FIB focused ion beam
  • the display device can be any product or component with display function, such as LCD TV, LCD, digital photo frame, mobile phone, tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.
  • an embodiment of the present disclosure also provides a method for manufacturing a display substrate, the method comprising:
  • Step S01 providing a base substrate 100 , the base substrate 100 including an opening area 200 , an isolation area 300 surrounding the opening area 200 , and a display area 400 surrounding the isolation area 300 ;
  • Step S02 forming at least one isolation column 500 in the isolation area 300 , wherein each isolation column 500 is arranged in a circle around the opening area 200 ; in the display area 400 and the isolation area 300 A light emitting layer 600 covering the isolation pillar 500 is provided, and the isolation pillar 500 separates the light emitting layer 600 between the opening area 200 and the display area 400; the isolation pillar 500 It includes: multiple layers of the metal pattern 500a stacked on the base substrate 100 in sequence; and multiple layers of the insulating film layer 500b conformally covering the metal pattern 500a.
  • the display area 400 is provided with a thin film transistor, and the thin film transistor includes a gate electrode, a source electrode and a drain electrode; the step S02 specifically includes:
  • a patterned first metal pattern 510 , a second metal pattern 520 and a third metal pattern are formed on the base substrate 100 , wherein the first metal pattern 510 , the second metal pattern 520 and the third metal pattern At least one layer of metal patterns in 530 is formed by the same patterning process as the gate, and at least another layer of metal patterns is formed by the same patterning process as the source and drain electrodes.
  • the inorganic layer includes a barrier layer (Barrier) and a buffer layer (Buffer) and the like.
  • the above method also includes the steps of forming some conventional structures in the display substrate, such as: thin film transistor (TFT), flat layer (PLN), pixel definition layer (PDL), light emitting layer 600 (EL layer) ), the first inorganic encapsulation layer, the organic layer and the second inorganic encapsulation layer, any material of the first inorganic encapsulation layer and the second inorganic encapsulation layer may be SiNx, SiCN, SiO2 or the like.
  • the first inorganic encapsulation layer and the second inorganic encapsulation layer can be formed by chemical vapor deposition, physical vapor deposition, atomic force deposition, and the like.
  • the organic layer may include acrylic-based polymers, silicon-based polymers, and the like.
  • the organic layer may be formed on the side of the first inorganic encapsulation layer facing away from the base substrate 100 by means of inkjet printing, spray coating, or the like. This will not be repeated here.
  • the display area 400 includes a first gate metal pattern (GI1) and a second gate metal pattern (GI2) arranged in different layers, the first gate metal pattern (GI1) and the second gate metal pattern At least one of (GI2) is the gate; the step S01 specifically includes:
  • Step S011 using the same patterning process to form the first metal pattern 510 and the first gate metal pattern (GI1);
  • the first gate metal layer is deposited on the base substrate 100.
  • the first gate metal layer may be deposited on the completed substrate 100 by sputtering or thermal evaporation with a thickness of about
  • the gate metal layer, the first gate metal layer can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals, the first gate metal layer can be a single layer Structure or multi-layer structure, multi-layer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc.; then, coat a layer of photoresist on the first gate metal layer, and use a mask to detect the light The photoresist is exposed, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to the first gate metal pattern (GI1) of the display area 400 (for example, the gate line and gate electrode, etc.) and the first metal pattern
  • Step S012 forming a first insulating layer on the first metal pattern 510;
  • the first insulating layer can be deposited on the substrate 100 by a plasma-enhanced chemical vapor deposition (PECVD) method with a thickness of
  • PECVD plasma-enhanced chemical vapor deposition
  • the gate insulating layer can be selected from oxides, nitrides or oxygen-nitrogen compounds, and the corresponding reactive gases are SiH4, NH3, N2 or SiH2Cl2, NH3, N2.
  • Step S013 using the same patterning process to form the second metal pattern 520 and the second gate metal pattern (GI2);
  • the second gate metal layer is deposited on the base substrate 100, and the second gate metal layer may be deposited on the completed substrate 100 by sputtering or thermal evaporation with a thickness of about
  • the gate metal layer, the second gate metal layer can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals, the second gate metal layer can be a single layer Structure or multi-layer structure, multi-layer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc.; then, coat a layer of photoresist on the second gate metal layer, and use a mask to detect the light The photoresist is exposed, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to the second gate metal pattern (GI2) of the display area 400 (for example, the grid Line and gate electrode, etc.) and the second metal pattern
  • Step S014 forming a second insulating layer on the first metal pattern 510;
  • the second insulating layer may be an inorganic film layer including an interlayer dielectric layer and a buffer layer, and the interlayer dielectric layer may be deposited by magnetron sputtering, thermal evaporation, PECVD or other film forming methods Thickness is
  • the interlayer dielectric layer can be selected from oxides, nitrides or oxynitrides.
  • the material of the interlayer dielectric layer can be SiNx, SiOx or Si(ON)x.
  • the interlayer dielectric layer can be a single-layer structure or a two-layer structure composed of silicon nitride and silicon oxide.
  • the reactive gases corresponding to silicon oxides may be SiH4, N2O; the gases corresponding to nitrides or oxygen-nitrogen compounds may be SiH4, NH3, N2 or SiH2Cl2, NH3, N2.
  • the buffer layer can be deposited on the substrate 100 by a plasma enhanced chemical vapor deposition (PECVD) method with a thickness of
  • PECVD plasma enhanced chemical vapor deposition
  • oxides, nitrides or oxygen-nitrogen compounds can be selected, and the corresponding reactive gases are SiH4, NH3, N2 or SiH2Cl2, NH3, N2.
  • Step S015 using the same patterning process to form the third metal pattern 530 and the source and drain electrodes.
  • step S015 includes:
  • the source-drain metal layer is deposited on the base substrate 100, and the source-drain metal layer can be deposited on the completed substrate 100 by sputtering or thermal evaporation with a thickness of about
  • the source and drain metal layers can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals.
  • the source and drain metal layers can be a single-layer structure or a multi-layer structure.
  • Layer structure multi-layer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, Ti ⁇ Al ⁇ Ti, etc.; then, coat a layer of photoresist on the source and drain metal layers, and use a mask Expose the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to the source and drain metal patterns 500a of the display area 400 (for example, the gate line and gate electrode, etc.) and the third metal pattern 530 of the isolation region 300 and other patterns, the photoresist unreserved area corresponds to the area other than the above-mentioned patterns; the development process is performed, and the photoresist unreserved area is lithography The photoresist is completely removed, and the photoresist thickness in the photoresist reserved area remains unchanged; the gate metal film in the photoresist unreserved area is completely etched by

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Abstract

本发明提供一种显示基板及其制造方法、显示装置，所述显示基板包括衬底基板，所述衬底基板包括开孔区、围绕所述开孔区的隔离区以及围绕所述隔离区的显示区，所述隔离区内设有至少一个隔离柱，每个所述隔离柱绕所述开孔区一圈设置；在所述显示区和所述隔离区内设置有覆盖于所述隔离柱上的发光层，且所述隔离柱将所述开孔区与所述显示区之间的所述发光层隔断开；所述隔离柱包括：依次堆叠于所述衬底基板之上的多层金属图形；及，绝缘膜层，所述绝缘膜层为随形覆盖于所述金属图形上的叠层。本发明提供的显示基板及其制造方法、显示装置，能够减少掩模板数量，降低成本，简化工艺。

Description

一种显示基板及其制造方法、显示装置
相关申请的交叉引用
本申请主张在2020年09月29日在中国提交的中国专利申请号No.202011057999.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制造方法、显示装置。
背景技术
当下全面屏成为发展趋势，消费者对窄边框、超窄边框，甚至无边框显示产品的要求也越来越强烈。为了进一步提高屏占比，许多显示产品屏幕用了AA Hole设计，即，在有效显示区域(Active Area，简称：AA区)设置开孔设计，这样，可以将摄像头等传感器(Sensor)放在AA区的开孔(Hole)下方，以期减小屏幕边框，提高屏占比。
在相关技术中，AA Hole设计的屏幕，开孔周边的边框结构主要包括隔离柱，隔离柱主要用来隔断开孔切割处水氧向显示区侵蚀，保护显示区的有机发光材料(Electro-Luminescence，简称EL层)不受影响。目前AA Hole的内、外隔离柱是采用EB Mask(电子束掩模)，将无机层刻蚀掉而形成，这种结构需要单独设计EB Mask，制造工艺中掩模板的数量多，成本高，工艺繁琐。
发明内容
为了解决上述技术问题，本发明提供一种显示基板及其制造方法、显示装置，能够减少掩模板数量，降低成本，简化工艺。
为了达到上述目的，本发明采用的技术方案是：
本公开实施例提供了一种显示基板，包括衬底基板，所述衬底基板包括开孔区、围绕所述开孔区的隔离区以及围绕所述隔离区的显示区，所述隔离 区内设有至少一个隔离柱，每个所述隔离柱绕所述开孔区一圈设置；在所述显示区和所述隔离区内设置有覆盖于所述隔离柱上的发光层，且所述隔离柱将所述开孔区与所述显示区之间的所述发光层隔断开；所述隔离柱包括：依次堆叠于所述衬底基板之上的多层金属图形；及，绝缘膜层，所述绝缘膜层为随形覆盖于所述金属图形上的叠层。
示例性的，多层所述金属图形包括：从靠近所述衬底基板侧一侧向远离所述衬底基板的一侧，依次堆叠的第一金属图形、第二金属图形和第三金属图形；
所述显示区设有薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极；
所述第一金属图形、所述第二金属图形和第三金属图形中的至少一层金属图形，与所述栅极为同层且同材质，至少另一层金属图形与所述源极、漏极为同层且同材质。
示例性的，所述显示区包括层叠设置的第一栅金属图形和第二栅金属图形，所述第一栅金属图形和所述第二栅金属图形中的至少一个为所述栅极；
所述第一金属图形与所述第一栅金属图形同层且同材质设置；
所述第二金属图形与所述第二栅金属图形同层且同材质设置；
所述第三金属图形与所述源极、漏极同层且同材质设置。
示例性的，所述绝缘膜层包括：位于所述第一金属图形和所述第二金属图形之间的第一绝缘层和位于所述第二金属图形和所述第三金属图形之间的第二绝缘层；其中所述第一绝缘层和所述第二绝缘层中的至少一个膜层包括栅极绝缘层，至少另一个膜层包括层间介质层和缓冲层。
示例性的，所述隔离柱包括位于靠近所述显示区的一侧的第一侧和位于靠近所述开孔区的一侧的第二侧；
所述隔离柱中，自靠近所述衬底基板的一侧向远离所述衬底基板的一侧，各层所述金属图形在平行于所述衬底基板方向上的径向宽度逐渐减小，以使所述第一侧和所述第二侧形成多个台阶结构。
示例性的，在所述第一侧，相邻两个所述金属图形在平行于所述衬底基板方向上的金属台阶径向宽度差值大于或等于1微米；在所述第二侧，相邻 两个所述金属图形在平行于所述衬底基板方向上的金属台阶径向宽度差值大于或等于1微米。
示例性的，在所述隔离区设置有至少两个所述隔离柱，至少两个隔离柱包括内隔离柱和外隔离柱，所述内隔离柱位于所述外隔离柱的靠近所述显示区的一侧，且所述内隔离柱和所述外隔离柱之间设有隔离坝，所述隔离坝与所述显示区之间设有覆盖所述内隔离柱的有机封装边框。
本公开实施例还提供一种显示装置，包括：本公开实施例提供的显示基板。
本公开实施例还提供一种显示基板的制造方法，所述方法包括：
提供衬底基板，所述衬底基板包括开孔区、围绕所述开孔区的隔离区以及围绕所述隔离区的显示区；
在所述隔离区内形成至少一个隔离柱，其中，每个所述隔离柱绕所述开孔区一圈设置；在所述显示区和所述隔离区内设置有覆盖于所述隔离柱上的发光层，且所述隔离柱将所述开孔区与所述显示区之间的所述发光层隔断开；所述隔离柱包括：依次堆叠于所述衬底基板之上的多层金属图形；及，随形覆盖于所述金属图形上的多层所述绝缘膜层。
示例性的，所述显示区设有薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极；所述在所述隔离区内形成至少一个隔离柱，具体包括：
在所述衬底基板上形成图案化的第一金属图形、第二金属图形和第三金属，其中，所述第一金属图形、所述第二金属图形和第三金属图形中的至少一层金属图形，与所述栅极采用同一次构图工艺形成，至少另一层金属图形与所述源极、漏极采用同一次构图工艺形成。
本公开实施例所带来的有益效果如下：
本公开实施例提供的显示基板及其制造方法、显示装置中，在对显示区内设置的开孔区(AA Hole)的边框封装设计时，隔离柱是由多层金属图形直接形成多层台阶，并由绝缘膜层随形覆盖于金属图形之上而形成，这样，可以直接利用显示基板制造工艺中形成显示区内的金属层时，采用同一掩模板，来直接形成隔离柱内对应的金属图形，从而取代相关技术中采用离子束掩模 板(EB Mask)刻蚀无机层形成开孔区的隔离柱台阶，从而达到减少掩模板数量的目的，简化工艺，降低成本。
附图说明
图1表示相关技术中显示面板的整体结构示意图；
图2表示图1中A-A向隔离区的结构示意图；
图3表示本公开一种实施例中提供的显示基板的整体结构示意图；
图4表示图3中A’-A’向隔离区的结构示意图；
图5表示对本发明实施例提供的显示基板中隔离柱的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在对本公开实施例提供的显示基板及其制造方法、显示装置进行详细说明之前，有必要对于相关技术进行以下说明。
为了进一步提高屏占比，许多显示产品屏幕用了AA Hole设计，即，将开孔设置在屏幕内。图1所示OLED显示面板中从AA区到开孔区之间的隔离区结构示意图，图2具体为图1所示OLED显示面板以A-A为切割线的局部剖面图，切割线A-A表示从AA区到开孔区域之间的结构。如图1至图2所示，以OLED显示面板为例，以显示屏幕包括开孔区(Hole区)10、围绕开孔区10的隔离区20、及围绕隔离区20的显示区(AA区)30，在隔离区20内需要设置隔离边框结构，用于将AA区10和开孔区30之间的EL层40隔断，防止水汽和氧气沿EL层传输到AA区10，从而会导致显示面板的显示失效。该隔离边框结构主要包括：隔离柱21、隔离坝22及有机封装边框23，其中隔离柱21主要用来隔断开孔区30切割处水氧向AA区10侵蚀，保护显示区的有机发光材料(Electro-Luminescence，简称EL层)不受影响；隔离坝22用以防止形成有机封装边框23的喷墨印刷(Ink Jet Printing，简称为：IJP)材料溢出，以保证Dam外有机封装边框(TFE封装)23的有效性，从而保证产品信赖性。
申请人发现，在相关技术AA Hole设计中隔离区内的隔离柱是采用离子束掩模板(EB Mask)，通过EB Mask将无机层刻蚀掉，来形成膜层断差，而形成隔离柱，这种方式，相较于传统的屏幕周边区域开孔设计来说，需要单独再设计EB Mask来刻蚀无机绝缘层(例如，层间介质层ILD)形成隔离柱，也就是说，在正常的显示基板制备过程中需要增加掩模板(EB Mask)，这样势必导致成本增加，工艺繁琐。
为了解决上述技术问题，本公开实施例提供了一种显示基板及其制造方法、显示装置，能够减少掩模板数量，降低成本，简化工艺。
图3所示为本公开实施例中提供的显示基板的整体结构示意图；图4所示为图所示的显示基板中从AA区到开孔区之间的隔离区结构示意图，图4具体为图1所示的显示基板以A’-A’为切割线的局部剖面图，切割线A’-A’表示从AA区到开孔区之间的结构。
如图3和图4所示，本公开实施例提供的显示基板，包括衬底基板100，所述衬底基板100包括开孔区200、围绕所述开孔区200的隔离区300以及 围绕所述隔离区300的显示区400，所述隔离区300内设有至少一个隔离柱500，每个所述隔离柱500绕所述开孔区200一圈设置；在所述显示区400和所述隔离区300内设置有覆盖于所述隔离柱500上的发光层600，且所述隔离柱500将所述开孔区200与所述显示区400之间的所述发光层600隔断开；所述隔离柱500包括：依次堆叠于所述衬底基板100之上的多层所述金属图形500a，；及，绝缘膜层500b，所述绝缘膜层500b为随形覆盖于所述金属图形500a上的叠层。
本公开实施例提供的显示基板，所述隔离柱500的形成方式为：在所述衬底基板100上蒸镀所述发光层600之前，先形成所述隔离柱500的整体结构，这样，在蒸镀发光层600时即可利用形成的隔离柱500结构来将开孔区200和显示区400之间的发光层600隔断开。其中，所述隔离柱500由多层金属图形500a堆叠形成，每层金属图形500a为围绕所述开孔区200一圈的图形，这样，多层金属图形500a的侧壁即可形成膜层断差，用于阻断发光层600，而所述绝缘膜层500b可设置于相邻金属图形500a之间，且所述绝缘膜层500b随形覆盖于所述金属图形500a上，而最终形成所述隔离柱500。其中所述绝缘膜层500b包括多层绝缘层，每层绝缘层均为连续膜层，也就是说，所述绝缘膜层500b在所述金属台阶的侧壁处是随形覆盖于金属台阶上，而并非被刻蚀断开。
此外，本公开实施例提供的显示基板中，在所述显示区400内可设置薄膜晶体管以及电极层等金属膜层，这样，可以直接利用显示基板制造工艺中形成显示区400内的金属层时，采用同一掩模板，来直接形成隔离柱500内对应的金属图形500a，从而取代相关技术中采用离子束掩模板(EB Mask)刻蚀无机层形成开孔区200的隔离柱500台阶，从而达到减少掩模板数量的目的，简化工艺，降低成本。
以下对本公开实施例提供的显示基板进行更为详细的说明。
图4所示为本公开一些示例性实施例中提供的显示基板的结构示意图，其中仅示意了显示基板的部分结构，未示意出全部结构。
如图4所示，所述显示基板中，在所述衬底基板100上还设有无机层110， 无机层110包括在远离衬底基板100方向上依次层叠设置的阻挡层(Barrier)和缓冲层(Buffer)，衬底基板100可为聚酰亚胺(PI)等构成的柔性基板或玻璃基板。此外，显示基板中还包括一些常规结构，例如：薄膜晶体管(TFT)、平坦层(PLN)、像素定义层(PDL)、发光层600(EL层)、第一无机封装层、有机层以及第二无机封装层，第一无机封装层和第二无机封装层中任一种材料可以为SiNx、SiCN、SiO2等。第一无机封装层和第二无机封装层可采用化学气相沉积、物理气相沉积、原子力沉积等方式形成。有机层可包括丙烯酸基聚合物、硅基聚合物等。有机层可采用喷墨打印、喷涂等方式形成于第一无机封装层背向衬底基板100的一侧。
在一些示例性的实施例中，如图4所示，所述显示区400设有薄膜晶体管(TFT)，所述薄膜晶体管包括栅极、源极和漏极；多层所述金属图形500a包括：从靠近所述衬底基板100侧一侧向远离所述衬底基板100的一侧，依次堆叠的第一金属图形510、第二金属图形520和第三金属图形530；所述第一金属图形510、所述第二金属图形520和第三金属图形530中的至少一层金属图形，与所述栅极为同层且同材质，至少另一层金属图形与所述源极、漏极为同层且同材质。
所述隔离柱500的多层金属图形500a中，至少一层金属图形与显示区400的栅极同层且同材质，也就是，所述隔离柱500中至少一层金属图形是与所述显示区400内的栅金属图形采用同一掩模板，利用同一次构图工艺形成；至少还有一层金属图形500a是与所述显示区400内的源、漏金属图形采用同一掩模板，利用同一次构图工艺形成。这样，相较于相关技术中对无机层刻蚀形成隔离柱500的方式，可以减少掩模板数量，降低成本。
需要说明的是，在实际应用中，所述隔离柱500中的多层金属图形500a也可以是利用其他金属膜层来形成，例如，以OLED显示基板为例，至少一层金属图形还可以是利用显示区400的阴极层或阳极层等来形成。
此外，需要说明的是，以OLED显示基板为例，在显示区400内设有多个TFT，TFT可以为顶栅型TFT、底栅型TFT或双栅型TFT，本公开实施例中对TFT的类型不做限制。例如，薄膜晶体管包括设置在缓冲层背向衬底基 板100一侧的有源层，设置在有源层背向衬底基板100一侧的栅绝缘层(GI)，设置在栅绝缘层背向衬底基板100一侧的栅极，设置在栅绝缘层背向衬底基板100一侧的层间介质层(ILD)，设置在层间介质层背向衬底基板100一侧的导电层，导电层包括薄膜晶体管的源极和漏极，源极和漏极分别与有源层电连接。
在一些示例性的实施例中，如图4所示，所述显示区400包括层叠设置的第一栅金属图形(GI1)和第二栅金属图形(GI2)，所述第一栅金属图形(GI1)和所述第二栅金属图形(GI2)中的至少一个为所述栅极；所述第一金属图形510与所述第一栅金属图形(GI1)同层且同材质设置；所述第二金属图形520与所述第二栅金属图形(GI2)同层且同材质设置；所述第三金属图形530与所述源极、漏极同层且同材质设置。
此外，在一些示例性的实施例中，如图4所示，所述绝缘膜层500b包括：位于所述第一金属图形510和所述第二金属图形520之间的第一绝缘层550和位于所述第二金属图形520和所述第三金属图形530之间的第二绝缘层540；其中所述第一绝缘层550和所述第二绝缘层540中的至少一个膜层包括栅极绝缘层，至少另一个膜层包括层间介质层和缓冲层。
需要说明的是，以上仅是一种示例，在其他实施例中，对于各层金属图形500a以及各层绝缘膜层500b不进行具体限定，只要是能够使得金属图形500a堆叠而形成膜层断差，绝缘膜层500b随形覆盖金属图形500a，最终形成隔离柱500结构，均应落入本公开提供的显示基板保护范围内。
此外，在本公开一些示例性的实施例中，如图所示，所述隔离柱500包括位于靠近所述显示区400的一侧的第一侧和位于靠近所述开孔区200的一侧的第二侧；所述隔离柱500中，自靠近所述衬底基板100的一侧向远离所述衬底基板100的一侧，各层所述金属图形500a在平行于所述衬底基板100的方向(图中X方向)上的径向宽度逐渐减小，也就是说，如图4所示，各层所述金属图形500a从下至上的第一金属图形510(Gate1)、第二金属图形520(Gate2)和第三金属图形530(SD)的径向宽度逐渐减小，以使所述第一侧和所述第二侧形成多个台阶结构。
采用上述方案，在形成隔离柱500内的每层金属图形500a之后，绝缘膜层500b会随形覆盖金属图形500a的台阶之上，具体的，在形成AA Hole处的隔离柱500时，在衬底基板100的阻挡层(Barrier)和缓冲层(Buffer)之上，首先做一层第一金属图形510，形成第一层台阶，之后在该第一金属图形510上随形覆盖一层第一绝缘层(例如，第一无机层GI1)，这样，第一绝缘层会在第一金属图形510所形成的第一层台阶处具有台阶状过渡，之后，继续在第一金属图形510的台阶上再形成第二金属图形520，第一金属图形510的台阶径向宽度大于第二金属图形520的台阶径向宽度，从而形成第二层台阶，然后，再在第二金属图形520上随形覆盖第二绝缘层(例如，层间绝缘层和缓冲层)，这样，第二绝缘层会在第一金属图形510所形成的第一层台阶处以及分别第二金属图形520所形成的第二层台阶处分别具有一个台阶状过渡，也就是说，第二绝缘层上会存在两个台阶状过渡，依次类推，逐渐形成其他层金属图形500a及其他绝缘层，使得隔离柱500的所述第一侧和所述第二侧形成多个台阶结构。这样设计的目的是，若隔离柱500中各层金属图形500a的径向宽度相同，那么，各层金属图形500a会使得隔离柱500的第一侧和第二侧产生较大的膜层断差，对于绝缘层来说，则可能会出现破裂损害等风险，而丧失阻隔水氧进入AA区的功能。
在一些示例性的实施例中，如图4所示，在所述第一侧，相邻两个所述金属图形500a在平行于所述衬底基板100方向上的金属台阶径向宽度差值D1大于或等于1微米；在所述第二侧，相邻两个所述金属图形500a在平行于所述衬底基板100方向上的金属台阶径向宽度差值D2大于或等于1微米。
采用上述方案，在隔离柱500的第一侧(即，图中左侧)，所述第一金属图形510的台阶与第二金属图形520的台阶之间的距离，即相邻两个所述金属图形500a在平行于所述衬底基板100方向上的金属台阶径向宽度差值D1的数值为大于或等于1微米，同样的，第二金属图形520的台阶和第三金属图形530的台阶之间的距离D2的数值大于或等于1微米，该数值通过实际工艺验证，若小于1微米，则可能出现隔离柱500破裂损害等风险，这样的设计还能够使得隔离柱500结构与相关技术中使用EB Mask刻蚀无机层得到 的隔离柱500结构保持大致相同的隔离柱500结构设计。同样的，在隔离柱500的第二侧，相邻两个所述金属图形500a在平行于所述衬底基板100方向上的金属台阶径向宽度差值大于或等于1微米。
此外，需要说明的是，如图4所示，在一些示例性的实施例中，每层金属图形500a在垂直于所述衬底基板100的方向上的横截面形状为梯形，在其他实施例中，每层金属图形500a的横截面形状也可以是矩形等其他形状，对此不限定。
所述绝缘膜层随形覆盖在所述金属图形上，可以形成的坡度角范围为30～60度，这样，有利于EL发光层断裂，同时又可以保证封装层(TFE)700不断裂，有利于封装。
此外，还需要说明的是，上述实施例中，所述隔离柱500中，自靠近所述衬底基板100的一侧向远离所述衬底基板100的一侧，各层所述金属图形500a在平行于所述衬底基板100方向上的径向宽度逐渐减小，但是在另一些实施例中，各层金属图形500a的径向宽度之间的关系并不局限于此，在此不再赘述。
此外，在一些示例性的实施例中，如图3和图4所示，在所述隔离区300设置有至少两个所述隔离柱500，至少两个隔离柱500包括内隔离柱501和外隔离柱502，所述内隔离柱501位于所述外隔离柱502的靠近所述显示区400的一侧，且所述内隔离柱501和所述外隔离柱502之间设有隔离坝503，所述隔离坝503与所述显示区400之间设有覆盖所述内隔离柱501的有机封装边框504。
在上述实施例中，所述隔离柱500可设置有两个或两个以上，且多个隔离柱500间隔分布，相邻两个隔离柱500之间形成凹陷部，以使发光层600断开，隔离柱500的数量的增加，能够增加对截断水氧入侵通道的有效性。需要说明的是，隔离柱500数量的增加，可能会增加显示面板的制造工艺难度，增加生产成本，因此，在实际应用中，可根据实际需求来选择隔离柱500的具体数量，对于隔离柱500的具体数量不限定。
此外，当所述隔离柱500的数量为两个以上时，相邻两个隔离柱500之 间在平行于所述衬底基板100的方向上的间距取值范围为80～130μm，其中相邻两个隔离柱500之间在平行于所述衬底基板100的方向上的间距，具体是指，相邻两个隔离柱500中第三金属图形530的最近距离。
例如，在一些实施例中，所述隔离柱仅设置有两个(如图4所示)，其中一个隔离柱为内隔离柱501，另一个隔离柱为外隔离柱502，在内隔离柱501和外隔离柱502之间设置所述隔离坝503，所述隔离坝503与显示区400之间形成有机封装边框504，图4所示实施例中内隔离柱和外隔离柱之间在平行于所述衬底基板100的方向(图4中X方向)的间距优选为127±0.5μm；在本公开一些具体实施例中，衬底基板100上间隔设有两个隔离柱500，靠近显示区400一侧的隔离柱500为内隔离柱501，靠近开孔区200一侧的隔离柱500为外隔离柱502，通过设置两个隔离柱500，既能提高隔离柱500截断水氧入侵通道的有效性，又能避免隔离柱500数量过多导致生产成本过大。在另一些实施例中，所述隔离区仅设置有一个隔离柱，在该隔离柱与所述开孔区之间设置隔离坝，所述隔离坝与所述显示区之间形成有机封装边框；
在另一些实施例中，所述隔离区设置的隔离柱数量为两个以上，在每两个隔离柱之间可设置一个隔离坝，其中一个隔离坝与显示区之间形成有机封装边框，例如，最接近显示区的两个隔离柱之间设置的隔离坝与显示区之间形成有机封装边框；或者，最接近开孔区的两个隔离柱之间设置的隔离坝与显示区之间形成有机封装边框；或者，中间的两个隔离柱之间所设置的隔离坝与显示区之间形成有机封装边框；相邻两个隔离柱500之间在平行于所述衬底基板100的方向上的间距取值范围为80～130μm；
在另一些实施例中，所述隔离区设置的隔离柱数量为两个以上，仅在距离显示区最远的两个隔离柱之间设置一个隔离坝，隔离坝与显示区之间形成有机封装边框；或者，仅在距离开孔区最远的两个隔离柱之间设置一个隔离坝，隔离坝与显示区之间形成有机封装边框；或者，仅在中间的两个隔离柱之间设置一个隔离坝，隔离坝与显示区之间形成有机封装边框；相邻两个隔离柱500之间在平行于所述衬底基板100的方向上的间距取值范围为80～130μm。
此外，在上述实施例中，在隔离区300内，在相邻两个隔离柱500之间的间距内设有隔离坝503(Dam)，内隔离柱501和外隔离柱502主要用来隔断开孔区200切割处水氧向AA区侵蚀，保护显示区400的有机发光材料(Electro-Luminescence，简称EL层)发光材料不受影响；所述隔离坝503与所述显示区400之间设有覆盖所述内隔离柱501的有机封装边框504，该有机封装边框504可以为采用喷墨印刷材料形成的封装结构，所述隔离坝503用以防止喷墨印刷(IJP)材料溢出，以保证Dam外TFE封装有效性，从而保证产品信赖性。
此外，如图4所示，本公开实施例提供的显示基板中，在所述隔离区，还设置有切割热影响区(Margin)504，该切割热影响区504用于隔开所述隔离区上各膜层与开孔区，以避免开孔区激光切割时对隔离区膜层影响。所述隔离柱的数量为多个，并延伸至所述热影响区附近，或者延伸进所述热影响区。
此外，本公开一示例性实施例提供的显示基板中，所述隔离区内各膜层的厚度可以如下：
第一金属图形(Gate1)的膜层厚度取值范围为：
Figure PCTCN2021112656-appb-000001
第二金属图形(Gate2)的膜层厚度取值范围为：
Figure PCTCN2021112656-appb-000002
所述第三金属图形(SD)为叠层结构，包括自远离所述衬底基板一侧向靠近所述衬底基板的一侧(即，自上而下)依次堆叠的第一金属部、第二金属部和第三金属部，其中，第一金属部和第三金属部的材料可以为Ti(钛)，第二金属部的材料可以为Al(铝)，第一金属部的膜层厚度取值范围为：
Figure PCTCN2021112656-appb-000003
第二金属部的膜层厚度取值范围为
Figure PCTCN2021112656-appb-000004
第三金属部的膜层厚度取值范围为
Figure PCTCN2021112656-appb-000005
所述第一绝缘层(GI1)的膜层厚度取值范围为：
Figure PCTCN2021112656-appb-000006
所述第二绝缘层中缓冲层(GI2)的膜层厚度取值范围为：
Figure PCTCN2021112656-appb-000007
Figure PCTCN2021112656-appb-000008
所述第二绝缘层中层间介质层(IDL)可以包括氧化硅层和氮化硅层，其中所述氮化硅层的膜层厚度取值范围为：
Figure PCTCN2021112656-appb-000009
所述氧化硅层的膜层厚度为
Figure PCTCN2021112656-appb-000010
例如，在一些实施例中，第一金属图形(Gate1)的膜层厚度为：
Figure PCTCN2021112656-appb-000011
第二金属图形(Gate2)的膜层厚度为：
Figure PCTCN2021112656-appb-000012
所述第三金属图形(SD)为叠层结构，包括自远离所述衬底基板一侧向靠近所述衬底基板的一侧(即自上而下)依次堆叠的第一金属部、第二金属部和第三金属部，其中，第一金属部和第三金属部的材料可以为Ti(钛)，第二金属部的材料可以为Al(铝)，第一金属部的膜层厚度为：
Figure PCTCN2021112656-appb-000013
第二金属部的膜层厚度为
Figure PCTCN2021112656-appb-000014
第三金属部的膜层厚度为
Figure PCTCN2021112656-appb-000015
所述第一绝缘层(GI1)的膜层厚度为：
Figure PCTCN2021112656-appb-000016
所述第二绝缘层中缓冲层(GI2)的膜层厚度取值范围为：
Figure PCTCN2021112656-appb-000017
所述第二绝缘层中层间介质层(IDL)可以包括氧化硅层和氮化硅层，其中所述氮化硅层的膜层厚度为
Figure PCTCN2021112656-appb-000018
所述氧化硅层的膜层厚度为
Figure PCTCN2021112656-appb-000019
例如，在一些实施例中，第一金属图形(Gate1)的膜层厚度为：
Figure PCTCN2021112656-appb-000020
第二金属图形(Gate2)的膜层厚度为：
Figure PCTCN2021112656-appb-000021
所述第三金属图形(SD)为叠层结构，包括自远离所述衬底基板一侧向靠近所述衬底基板的一侧依次堆叠的第一金属部、第二金属部和第三金属部，其中，第一金属部和第三金属部的材料可以为Ti(钛)，第二金属部的材料可以为Al(铝)，第一金属部的膜层厚度为：
Figure PCTCN2021112656-appb-000022
第二金属部的膜层厚度为
Figure PCTCN2021112656-appb-000023
第三金属部的膜层厚度为
Figure PCTCN2021112656-appb-000024
所述第一绝缘层(GI1)的膜层厚度为：
Figure PCTCN2021112656-appb-000025
所述第二绝缘层中缓冲层(GI2)的膜层厚度取值范围为：
Figure PCTCN2021112656-appb-000026
所述第二绝缘层中层间介质层(IDL)可以包括氧化硅层和氮化硅层，其中所述氮化硅层的膜层厚度为：
Figure PCTCN2021112656-appb-000027
所述氧化硅层的膜层厚度为
Figure PCTCN2021112656-appb-000028
例如，在一些实施例中，第一金属图形(Gate1)的膜层厚度为：
Figure PCTCN2021112656-appb-000029
第二金属图形(Gate2)的膜层厚度为：
Figure PCTCN2021112656-appb-000030
所述第三金属图形(SD)为叠层结构，包括自远离所述衬底基板一侧向靠近所述衬底基板的一侧依次堆叠的第一金属部、第二金属部和第三金属部，其中，第一金属部和第三金属部的材料可以为Ti(钛)，第二金属部的材料可以为Al(铝)，第一金属部的膜层厚度为：
Figure PCTCN2021112656-appb-000031
第二金属部的膜层厚度为
Figure PCTCN2021112656-appb-000032
第三金属部的膜层厚度为
Figure PCTCN2021112656-appb-000033
所述第一绝缘层(GI1)的膜层厚度为：
Figure PCTCN2021112656-appb-000034
所述第二绝缘层中缓冲层(GI2)的膜层厚度取值范围为：
Figure PCTCN2021112656-appb-000035
所述第二绝缘层中层间介质层 (IDL)可以包括氧化硅层和氮化硅层，其中所述氮化硅层的膜层厚度为：
Figure PCTCN2021112656-appb-000036
所述氧化硅层的膜层厚度为
Figure PCTCN2021112656-appb-000037
应当理解的是，各膜层厚度可以根据实际需求进行合理选择，在此不再一一列举。
此外，在本公开一些实施例中，所述第一金属图形和所述第二金属图形的膜层厚度比值为(0.73～1.37)；所述第一金属图形与第三金属图形中所述第一金属部的膜层厚度比值为(3.51～5.78)；所述第一金属图形与第三金属图形中所述第二金属部的膜层厚度比值为(0.35～0.59)；所述第一金属图形与所述第三金属图形中第三金属部的膜层厚度比值为(2.01～2.87)；所述第一金属层与所述第一绝缘层的膜层厚度比值为(1.63～2.61)；所述第一绝缘层与所述第二绝缘层中缓冲层的膜层厚度比值为(0.36～1.07)；所述缓冲层与所述第二绝缘层中层间介质层中氮化硅层的膜层厚度比值为(0.37～1.11)，所述缓冲层与与所述氧化硅层的膜层厚度比值为(0.50～1.73)。
例如，一些实施例中，所述第一金属图形和所述第二金属图形的膜层厚度比值为1.37；所述第一金属图形与第三金属图形中所述第一金属部的膜层厚度比值为3.51；所述第一金属图形与第三金属图形中所述第二金属部的膜层厚度比值为0.35；所述第一金属图形与所述第三金属图形中第三金属部的膜层厚度比值为2.01；所述第一金属层与所述第一绝缘层的膜层厚度比值为1.63；所述第一绝缘层与所述第二绝缘层中缓冲层的膜层厚度比值为0.36；所述缓冲层与所述第二绝缘层中层间介质层中氮化硅层的膜层厚度比值为0.37，所述缓冲层与与所述氧化硅层的膜层厚度比值为0.50。
例如，一些实施例中，所述第一金属图形和所述第二金属图形的膜层厚度比值为0.73；所述第一金属图形与第三金属图形中所述第一金属部的膜层厚度比值为5.78；所述第一金属图形与第三金属图形中所述第二金属部的膜层厚度比值为0.59；所述第一金属图形与所述第三金属图形中第三金属部的膜层厚度比值为2.87；所述第一金属层与所述第一绝缘层的膜层厚度比值为2.61；所述第一绝缘层与所述第二绝缘层中缓冲层的膜层厚度比值为1.07；所述缓冲层与所述第二绝缘层中层间介质层中氮化硅层的膜层厚度比值为 1.11)，所述缓冲层与与所述氧化硅层的膜层厚度比值为1.73。
一些实施例中，所述第一金属图形和所述第二金属图形的膜层厚度比值为1；所述第一金属图形与第三金属图形中所述第一金属部的膜层厚度比值为4.55；所述第一金属图形与第三金属图形中所述第二金属部的膜层厚度比值为0.45；所述第一金属图形与所述第三金属图形中第三金属部的膜层厚度比值为5；所述第一金属层与所述第一绝缘层的膜层厚度比值为2.1；所述第一绝缘层与所述第二绝缘层中缓冲层的膜层厚度比值为0.92；所述缓冲层与所述第二绝缘层中层间介质层中氮化硅层的膜层厚度比值为0.43，所述缓冲层与与所述氧化硅层的膜层厚度比值为0.65。
应当理解的是，各膜层厚度比值可以根据实际需求进行合理选择，在此不再一一列举。
此外，对本发明实施例提供的显示面板进行了产品剖面验证，验证方式例如聚焦离子束(Focused Ion beam，简称为：FIB)工艺方式，从FIB结果可以看出：本公开实施例提供的显示基板，隔离柱500无断裂现象发生，且无断裂风险。
此外，本公开实施例中还提供了一种显示装置，包括：本公开实施例提供的显示基板。
所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
该显示装置中，所述开孔区200的下方可以设置包括以下一项或多项：摄像头、传感器、实体按键和显示屏的边框等。通常，显示装置在制作过程中，可以为其内部的硬件结构预留开孔区，即显示区400内部的开孔区200，例如包括上述摄像头、传感器和实体按键等。
此外，本公开实施例还提供一种显示基板的制造方法，所述方法包括：
步骤S01、提供衬底基板100，所述衬底基板100包括开孔区200、围绕所述开孔区200的隔离区300以及围绕所述隔离区300的显示区400；
步骤S02、在所述隔离区300内形成至少一个隔离柱500，其中，每个所 述隔离柱500绕所述开孔区200一圈设置；在所述显示区400和所述隔离区300内设置有覆盖于所述隔离柱500上的发光层600，且所述隔离柱500将所述开孔区200与所述显示区400之间的所述发光层600隔断开；所述隔离柱500包括：依次堆叠于所述衬底基板100之上的多层所述金属图形500a；及，随形覆盖于所述金属图形500a上的多层所述绝缘膜层500b。
示例性的，所述显示区400设有薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极；所述步骤S02具体包括：
在所述衬底基板100上形成图案化的第一金属图形510、第二金属图形520和第三金属，其中，所述第一金属图形510、所述第二金属图形520和第三金属图形530中的至少一层金属图形，与所述栅极采用同一次构图工艺形成，至少另一层金属图形与所述源极、漏极采用同一次构图工艺形成。
需要说明的是，上述方案中，在衬底基板100上形成第一金属图形510、第二金属图形520和第三金属图形530之前，还可以包括：在衬底基板100上形成无机层，例如，所述无机层包括阻挡层(Barrier)和缓冲层(Buffer)等。
此外，需要说明的是，上述方法中，还包括显示基板中一些常规结构的形成步骤，例如：薄膜晶体管(TFT)、平坦层(PLN)、像素定义层(PDL)、发光层600(EL层)、第一无机封装层、有机层以及第二无机封装层，第一无机封装层和第二无机封装层中任一种材料可以为SiNx、SiCN、SiO2等。第一无机封装层和第二无机封装层可采用化学气相沉积、物理气相沉积、原子力沉积等方式形成。有机层可包括丙烯酸基聚合物、硅基聚合物等。有机层可采用喷墨打印、喷涂等方式形成于第一无机封装层背向衬底基板100的一侧。对此均不再赘述。
示例性的，所述显示区400包括不同层设置的第一栅金属图形(GI1)和第二栅金属图形(GI2)，所述第一栅金属图形(GI1)和所述第二栅金属图形(GI2)中的至少一个为所述栅极；所述步骤S01具体包括：
步骤S011、采用同一次构图工艺，形成所述第一金属图形510和所述第一栅金属图形(GI1)；
具体的，首先，在衬底基板100上沉积的第一栅金属层，所述第一栅金 属层可以是采用溅射或热蒸发的方法在完成衬底100上沉积厚度约为
Figure PCTCN2021112656-appb-000038
Figure PCTCN2021112656-appb-000039
的栅金属层，第一栅金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，第一栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo,Ti\Cu\Ti，Mo\Al\Mo等；然后，在第一栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于所述显示区400的第一栅金属图形(GI1)(例如，栅线和栅电极等)以及所述隔离区300的第一金属图形510等图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属薄膜，剥离剩余的光刻胶，形成所述显示区400的第一栅金属图形(GI1)、以及所述隔离区300的第一金属图形510。
步骤S012、在所述第一金属图形510上形成第一绝缘层；
具体的，所述第一绝缘层可以采用等离子体增强化学气相沉积(PECVD)方法，在衬底100上沉积厚度为
Figure PCTCN2021112656-appb-000040
的栅绝缘层，栅绝缘层可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH4、NH3、N2或SiH2Cl2、NH3、N2。
步骤S013、采用同一次构图工艺，形成所述第二金属图形520和所述第二栅金属图形(GI2)；
具体的，首先，在衬底基板100上沉积的第二栅金属层，所述第二栅金属层可以是采用溅射或热蒸发的方法在完成衬底100上沉积厚度约为
Figure PCTCN2021112656-appb-000041
Figure PCTCN2021112656-appb-000042
的栅金属层，第二栅金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，第二栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo,Ti\Cu\Ti，Mo\Al\Mo等；然后，在第二栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于所述显示区400的第二栅金属图形(GI2)(例如，栅线和栅电极等)以及所述隔离区300的第二金属图形520等图形所在区域，光刻胶未保留区域对应于上述 图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属薄膜，剥离剩余的光刻胶，形成所述显示区400的第二栅金属图形(GI2)、以及所述隔离区300的第二金属图形520。
步骤S014、在所述第一金属图形510上形成第二绝缘层；
具体的，所述第二绝缘层可以为包括层间介质层和缓冲层等在内的无机膜层，所述层间介质层可以采用磁控溅射、热蒸发、PECVD或其它成膜方法沉积厚度为
Figure PCTCN2021112656-appb-000043
的层间介质层，层间介质层可以选用氧化物、氮化物或者氧氮化合物，具体地，层间介质层材料可以是SiNx，SiOx或Si(ON)x。层间介质层可以是单层结构，也可以是采用氮化硅和氧化硅构成的两层结构。其中，硅的氧化物对应的反应气体可以为SiH4，N2O；氮化物或者氧氮化合物对应气体可以是SiH4，NH3，N2或SiH2Cl2，NH3，N2。
所述缓冲层可以采用等离子体增强化学气相沉积(PECVD)方法，在衬底100上沉积厚度为
Figure PCTCN2021112656-appb-000044
的无机层，可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH4、NH3、N2或SiH2Cl2、NH3、N2。
步骤S015、采用同一次构图工艺，形成所述第三金属图形530和所述源极、漏极。
具体的，步骤S015包括：
具体的，首先，在衬底基板100上沉积的源漏金属层，所述源漏金属层可以是采用溅射或热蒸发的方法在完成衬底100上沉积厚度约为
Figure PCTCN2021112656-appb-000045
的金属层，源漏金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，源漏金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo,Ti\Cu\Ti，Mo\Al\Mo,Ti\Al\Ti等；然后，在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于所述显示区400的源、漏金属图形500a(例如，栅线和栅电极等)以及所述隔离区300的第三金属图形530等图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留 区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属薄膜，剥离剩余的光刻胶，形成所述显示区400的源、漏金属图形500a、以及所述隔离区300的第三金属图形530。
应当注意，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种显示基板，包括衬底基板，所述衬底基板包括开孔区、围绕所述开孔区的隔离区以及围绕所述隔离区的显示区，所述隔离区内设有至少一个隔离柱，每个所述隔离柱绕所述开孔区一圈设置；在所述显示区和所述隔离区内设置有覆盖于所述隔离柱上的发光层，且所述隔离柱将所述开孔区与所述显示区之间的所述发光层隔断开；其特征在于，
    所述隔离柱包括：依次堆叠于所述衬底基板之上的多层金属图形；及，绝缘膜层，所述绝缘膜层为随形覆盖于所述金属图形上的叠层。
  2. 根据权利要求1所述的显示基板，其特征在于，
    多层所述金属图形包括：从靠近所述衬底基板侧一侧向远离所述衬底基板的一侧，依次堆叠的第一金属图形、第二金属图形和第三金属图形；
    所述显示区设有薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极；
    所述第一金属图形、所述第二金属图形和第三金属图形中的至少一层金属图形，与所述栅极为同层且同材质，至少另一层金属图形与所述源极、漏极为同层且同材质。
  3. 根据权利要求2所述的显示基板，其特征在于，
    所述显示区包括层叠设置的第一栅金属图形和第二栅金属图形，所述第一栅金属图形和所述第二栅金属图形中的至少一个为所述栅极；
    所述第一金属图形与所述第一栅金属图形同层且同材质设置；
    所述第二金属图形与所述第二栅金属图形同层且同材质设置；
    所述第三金属图形与所述源极、漏极同层且同材质设置。
  4. 根据权利要求2所述的显示基板，其特征在于，
    所述绝缘膜层包括：位于所述第一金属图形和所述第二金属图形之间的第一绝缘层和位于所述第二金属图形和所述第三金属图形之间的第二绝缘层；其中所述第一绝缘层和所述第二绝缘层中的至少一个膜层包括栅极绝缘层，至少另一个膜层包括层间介质层和缓冲层。
  5. 根据权利要求2所述的显示基板，其特征在于，
    所述隔离柱包括位于靠近所述显示区的一侧的第一侧和位于靠近所述开 孔区的一侧的第二侧；
    所述隔离柱中，自靠近所述衬底基板的一侧向远离所述衬底基板的一侧，各层所述金属图形在平行于所述衬底基板方向上的径向宽度逐渐减小，以使所述第一侧和所述第二侧形成多个台阶结构。
  6. 根据权利要求5所述的显示基板，其特征在于，
    在所述第一侧，相邻两个所述金属图形在平行于所述衬底基板方向上的金属台阶径向宽度差值大于或等于1微米；在所述第二侧，相邻两个所述金属图形在平行于所述衬底基板方向上的金属台阶径向宽度差值大于或等于1微米。
  7. 根据权利要求1至6任一项所述的显示基板，其特征在于，
    在所述隔离区设置有至少两个所述隔离柱，至少两个隔离柱包括内隔离柱和外隔离柱，所述内隔离柱位于所述外隔离柱的靠近所述显示区的一侧，且所述内隔离柱和所述外隔离柱之间设有隔离坝，所述隔离坝与所述显示区之间设有覆盖所述内隔离柱的有机封装边框。
  8. 一种显示装置，其特征在于，包括：如权利要求1至7任一项所述的显示基板。
  9. 一种显示基板的制造方法，其特征在于，所述方法包括：
    提供衬底基板，所述衬底基板包括开孔区、围绕所述开孔区的隔离区以及围绕所述隔离区的显示区；
    在所述隔离区内形成至少一个隔离柱，其中，每个所述隔离柱绕所述开孔区一圈设置；在所述显示区和所述隔离区内设置有覆盖于所述隔离柱上的发光层，且所述隔离柱将所述开孔区与所述显示区之间的所述发光层隔断开；所述隔离柱包括：依次堆叠于所述衬底基板之上的多层金属图形；及，随形覆盖于所述金属图形上的多层所述绝缘膜层。
  10. 根据权利要求9所述的方法，其特征在于，所述显示区设有薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极；所述在所述隔离区内形成至少一个隔离柱，具体包括：
    在所述衬底基板上形成图案化的第一金属图形、第二金属图形和第三金 属，其中，所述第一金属图形、所述第二金属图形和第三金属图形中的至少一层金属图形，与所述栅极采用同一次构图工艺形成，至少另一层金属图形与所述源极、漏极采用同一次构图工艺形成。
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