WO2022062852A1 - 芯片试验装置、系统及方法 - Google Patents

芯片试验装置、系统及方法 Download PDF

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Publication number
WO2022062852A1
WO2022062852A1 PCT/CN2021/115474 CN2021115474W WO2022062852A1 WO 2022062852 A1 WO2022062852 A1 WO 2022062852A1 CN 2021115474 W CN2021115474 W CN 2021115474W WO 2022062852 A1 WO2022062852 A1 WO 2022062852A1
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WIPO (PCT)
Prior art keywords
circuit board
test
plug
chip
circuit
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PCT/CN2021/115474
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English (en)
French (fr)
Inventor
李文文
袁瑞铭
谭志强
郭皎
巨汉基
周丽霞
姜振宇
庞富宽
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国网冀北电力有限公司计量中心
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Publication of WO2022062852A1 publication Critical patent/WO2022062852A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2889—Interfaces, e.g. between probe and tester
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
    • G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a chip testing device, system and method.
  • the working life of the chip can be estimated by the method of temperature-accelerated aging. Applying a voltage at a certain temperature is a harsh way of working. Under the action of temperature and electric field, devices with poor quality will fail. Judging the manufacturing level of the chip can also be used to judge the quality of the production batch.
  • the high-temperature aging test of the chip, in the terminal product, is mostly soldered into the product to perform the product performance test, so as to reverse the chip performance test result through the test result of the product. This test method is slow in efficiency, difficult to operate, and soldering To test in the product, it takes up the equipment space, and is not suitable for the test of the product with too many chips.
  • the invention provides a chip testing device, system and method, which can be used to test multiple chips to be tested at the same time, has simple operation and high testing efficiency, and is suitable for chip testing of various products.
  • an embodiment of the present invention provides a chip testing device, which includes: a power plug-in circuit board, a device testing circuit board, a device plug-in circuit board, and a connector; the power plug-in circuit board and the The device testing circuit board is communicatively connected; the device testing circuit board is respectively communicatively connected to a plurality of the device insertion circuit boards through a plurality of the connecting pieces; the device insertion circuit board is used for communication connection with the chip to be tested, Acquire the test parameters of the chip to be tested, and send the test parameters to the device test circuit board through the connector; the device test circuit board is used to receive the test parameters, and send the test parameters to the device test circuit board. Sent to the test module, so that the test module generates chip test results.
  • an embodiment of the present invention further provides a chip testing system, which includes a testing module and the above-mentioned chip testing device.
  • an embodiment of the present invention further provides a chip testing method, which is applied to the above-mentioned chip testing device, and the method includes: the device insertion circuit board is communicatively connected to the chip to be tested, and obtaining the information of the chip to be tested is obtained. test parameters, and send the test parameters to the device test circuit board through the connector; the device test circuit board receives the test parameters, and sends the test parameters to the test module, so that the The test module generates chip test results.
  • an embodiment of the present invention further provides a computer device, including a memory, a processor, and a computer program stored in the memory and running on the processor, where the processor implements the above-mentioned chip test when executing the computer program method.
  • an embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program for executing the above-mentioned chip testing method.
  • the embodiment of the present invention brings the following beneficial effects: the embodiment of the present invention provides a chip test scheme, the scheme includes a power supply plug-in circuit board, a device test circuit board, a device plug-in circuit board and a connector, a power supply
  • the plug-in circuit board is communicatively connected with the device test circuit board; the device test circuit board is respectively connected in communication with a plurality of device plug-in circuit boards through a plurality of connectors; the device plug-in circuit board is communicatively connected with the chip to be tested to obtain the chip to be tested
  • the test parameters are sent to the device test circuit board through the connector; the test parameters are received through the device test circuit board, and the test parameters are sent to the test module, so that the test module generates chip test results.
  • the embodiment of the present invention can simultaneously connect multiple chips to be tested through multiple device insertion circuit boards to obtain test parameters of the chip testing process, with simple operation and high testing efficiency, and is suitable for chip testing of various products.
  • FIG. 1 is a structural block diagram of a chip testing device provided by an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a chip test apparatus provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a device insertion circuit board provided by an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a power plug-in circuit board provided by an embodiment of the present invention.
  • FIG. 5 is a flowchart of a chip testing method provided by an embodiment of the present invention.
  • FIG. 6 is a structural block diagram of a computer device provided by an embodiment of the present invention.
  • the chip testing device should take into account that a large number of devices can be tested at the same time, the cost is not high, and the equipment space is saved, especially after the temperature test, which is convenient for testing.
  • a chip testing apparatus, system and method provided by the embodiments of the present invention can improve the testing efficiency of chips.
  • An embodiment of the present invention provides a chip testing device.
  • the device includes: a power plug-in circuit board 14 , a device testing circuit board 13 , a device plug-in circuit board 11 and connectors 12.
  • the power plug-in circuit board is communicatively connected with the device test circuit board; the device test circuit board is respectively connected in communication with the plurality of device plug-in circuit boards through a plurality of connectors; the device plug-in circuit board is used for communication connection with the chip to be tested to obtain The test parameters of the chip are measured, and the test parameters are sent to the device test circuit board through the connector; the device test circuit board is used to receive the test parameters and send the test parameters to the test module, so that the test module generates the chip test result.
  • each device test circuit board is provided with a plurality of connectors, each connector is connected to a device plug-in circuit board, and each device plug-in circuit board can be connected to a chip to be tested, so as to realize the Multiple chips are tested and tested, and the device insertion circuit board obtains the test parameter information of the chip such as the voltage, current and frequency of the chip, and then sends the test parameters to the device test circuit board through the connector, and the device test circuit board sends the test parameters.
  • the test module compares the obtained chip parameters such as voltage, current and frequency with the preset chip rated parameters to determine whether the quality of the tested chip passes the test, and then obtains the chip test result.
  • the device can acquire test parameters of multiple chips to be tested at the same time, so as to test multiple chips to be tested at the same time, which improves the chip testing efficiency, has simple operation and reduces costs.
  • the device insertion circuit board can be soldered to the chip to be tested.
  • D1-D7 are the integrated circuit chips to be tested
  • C1-C7 are The peripheral circuits required for the normal operation of the integrated circuit chip are mainly chip capacitors
  • D1 and C1 are a group of experimental units.
  • the embodiment of the present invention provides a chip test scheme, the scheme includes a power plug-in circuit board, a device test circuit board, a device plug-in circuit board and a connector, and the power plug-in circuit board is communicatively connected with the device test circuit board. ;
  • the device test circuit board is connected to a plurality of device plug-in circuit boards through a plurality of connectors respectively; the device plug-in circuit board is communicated with the chip to be tested, the test parameters of the chip to be tested are obtained, and the test parameters are passed through the connectors.
  • Send to the device test circuit board receive test parameters through the device test circuit board, and send the test parameters to the test module, so that the test module generates chip test results.
  • the embodiment of the present invention can simultaneously connect multiple chips to be tested through multiple device insertion circuit boards to obtain test parameters of the chip testing process, with simple operation and high testing efficiency, and is suitable for chip testing of various products.
  • the device test circuit board and the power plug-in circuit board are fixedly or movably connected.
  • the device testing circuit board may be integrated with the power plug-in circuit board, and may be disposed on the power plug-in circuit board, or may be independent of another circuit board.
  • the device also includes:
  • At least one device plug-in circuit board is communicatively connected to the power plug-in circuit board through at least one connector; at least one device plug-in circuit board is used to communicate with the chip to be tested, obtain the second test parameter of the chip to be tested, and use the first The second test parameters are sent to the power plug-in circuit board through at least one connector; the power plug-in circuit board is also used for receiving the second test parameters and sending the second test parameters to the test module, so that the test module generates chip test results.
  • the data types contained in the second test parameters are less than the test parameters.
  • the power plug-in circuit board can be communicated with the device plug-in circuit board through a connector, and the device plug-in circuit board The circuit board is installed to obtain the second test parameter of the chip to be tested, and the second test parameter is sent to the test module, so as to obtain the chip test result, thereby further improving the test efficiency of the chip.
  • the connector is movably connected with the device plug-in circuit board.
  • the dotted line in the figure represents an active connection
  • the solid line represents a fixed connection
  • positioning holes are provided on the power plug-in circuit board.
  • the four corners of the power plug-in circuit board have four positioning holes. Through the positioning holes, positioning posts can be used to vertically stack multiple power plug-in circuit boards at a certain height, thereby saving space.
  • the positioning hole can be determined according to the size of the positioning column actually used, and the diameter is generally 3mm.
  • the power plug-in circuit board includes a power circuit module and a plug-in pad circuit module; the plug-in pad circuit module includes a spare jumper unit and a device plug-in circuit connection unit.
  • the power plug-in circuit board is composed of two circuits, one is a power circuit, which is directly connected to the power source, and the other is a parallel connection circuit of several identical plug-in pad circuits.
  • the minimum spacing between the plug-in pad circuits is 6mm; the maximum spacing is determined by the total length of the plug-in circuit board and the number of plug-in circuit boards.
  • P1-P8 are the connectors that are fixedly connected to the power plug-in circuit board;
  • P_test is the fixed connection to the device test circuit board.
  • the connectors, P1, P11, R11, P12, R12: are a group of experimental units.
  • the plug-in pad circuit includes a spare jumper circuit and a design circuit corresponding to the device plug-in circuit.
  • the spare jumper circuit is a pair of jumper pins and jumper caps, or two pads and no device is soldered between the two pads or directly short-circuited with solder; the spare jumper circuit is used for short-circuit testing.
  • the device insertion circuit connection unit is a design circuit correspondingly connected to the device insertion circuit.
  • the size of the device plug-in circuit connection unit is consistent with the size of the connector.
  • the length and width of the designed circuit connected corresponding to the device insertion circuit need to be consistent with the length and width of the connector, so as to facilitate reliable circuit connection.
  • the device test circuit board includes an external device connection module and a device plug-in circuit connection module.
  • the device test circuit board is composed of two circuits and connectors, one circuit corresponds to the device insertion pad circuit and is used for the device insertion circuit board insertion test; the other is a conventional circuit with a spacing of 2.54mm.
  • the plug-in circuit is used to connect with the external test equipment; the connecting piece is the same as the above-mentioned connecting piece.
  • the device plug-in circuit board includes a power plug-in circuit connection module and a device pad circuit module; the power plug-in circuit connection module is communicatively connected with the device plug-in circuit connection unit; the device pad circuit module is connected with the device plug-in circuit. Module communication connection.
  • the device plug-in circuit board is composed of two circuits, one circuit is a plurality of identical device pad circuits, and the other is a design circuit corresponding to the power plug-in circuit.
  • One side of each device pad circuit is connected to the design circuit correspondingly connected to the power plug-in circuit.
  • the device pad circuit is designed according to the package specification and size of the device and the application conditions.
  • the device is an integrated circuit material, especially a clock chip.
  • the minimum distance between the device pad circuits is the width of the device + 3mm, and the maximum distance is determined according to the length of the device insertion circuit board and the number of soldered devices.
  • the design circuit corresponding to the power plug-in circuit adopts the form of gold finger plug-in, so as to facilitate quick connection or disconnection with the connector.
  • the internal circuit of the connector needs to be consistent with the power plug-in circuit and the device plug-in circuit, so that the circuit connection is reliable.
  • the connecting piece is a gold finger socket bus slot.
  • the pin end of the connector is welded and fixed with the power plug-in circuit board.
  • the socket end of the connector is inserted into the device insertion circuit board.
  • the device insertion circuit board can be pulled out from the socket end of the connector for testing as needed.
  • the connector is a plug-in gold finger socket bus slot, generally 44 cores, and the spacing between each core is 3.96mm.
  • the embodiments of the present invention provide a chip testing device, system and method.
  • the device is extremely convenient in specific application through the clever design and layout of the circuit; multiple devices can be tested at the same time, and each device can be inserted into the circuit board according to the needs.
  • Solder multiple devices, such as 7 in one embodiment, and each power plug-in circuit board can be connected to multiple device plug-in circuit boards at the same time, such as 8 in one embodiment, one test device can be carried out at the same time.
  • more devices can be welded according to the actual situation, the number of samples to be tested at the same time is increased, and the test efficiency is greatly improved; there are positioning holes on the power plug-in circuit board, and multiple test devices can be positioned at a certain height through the positioning column.
  • the vertical connection saves the horizontal space occupied by the devices placed in the test box; the device plug-in circuit boards connected to each power plug-in circuit board are implemented in parallel, and the device plug-in circuit boards can be extracted arbitrarily according to the bad condition of the device or the test needs.
  • the circuit board is placed on the device test circuit board for testing without affecting other circuit boards, and the operation is convenient; if the device test circuit is designed with the device plug-in circuit board, it can be tested under test conditions; the device plug-in circuit board can be tested under test conditions;
  • the device pad circuit can be designed and modified according to the integrated circuit package used, and it is suitable for other types of packaging types, with good applicability; in addition, the entire experimental device is easy to obtain materials, and the cost is low, and compared to soldering into the finished circuit To test, greatly save time and cost.
  • An embodiment of the present invention further provides a chip testing system, which includes any of the above-mentioned chip testing apparatuses.
  • the embodiments of the present invention also provide a chip testing method, as described in the following embodiments. Since the principle of the method for solving the problem is similar to that of the chip testing device, the implementation of the method can refer to the implementation of the chip testing device, and the repetition will not be repeated. Referring to the flowchart of the chip test method shown in FIG. 5 , the method includes the following steps:
  • step S502 the device insertion circuit board is communicatively connected to the chip to be tested, the test parameters of the chip to be tested are acquired, and the test parameters are sent to the device test circuit board through the connector.
  • Step S504 the device test circuit board receives the test parameters, and sends the test parameters to the test module, so that the test module generates a chip test result.
  • the pin end of the connector is welded to the power plug-in circuit board, and the device plug-in circuit board with the welded device is inserted into the connector slot, and placed in the test box In the test, the device insertion circuit board after the test can be pulled out from the card slot arbitrarily as required, inserted into the connector card slot of the device test circuit board, and connected with the test equipment for testing.
  • An embodiment of the present invention also provides a computer device.
  • the computer device includes a memory 61, a processor 62, and a computer program stored in the memory and running on the processor. The steps of any of the above chip testing methods are implemented when the computer executes the computer program.
  • Embodiments of the present invention further provide a computer-readable storage medium, where the computer-readable storage medium stores a computer program for executing any one of the foregoing chip testing methods.
  • embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions
  • the apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

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Abstract

一种芯片试验装置、系统及方法，涉及半导体技术领域，该装置包括：电源插装电路板(14)、器件测试电路板(13)、器件插装电路板(11)和连接件(12)；电源插装电路板(14)与器件测试电路板(13)通信连接；器件测试电路板(13)通过多个连接件(12)分别和多个器件插装电路板(11)通信连接；器件插装电路板(11)用于与待测芯片通信连接，获取待测芯片的测试参数，并将测试参数通过连接件(12)发送至器件测试电路板(13)(S502)；器件测试电路板(13)用于接收测试参数，并将测试参数发送至测试模块，以使测试模块生成芯片测试结果(S504)。通过多个器件插装电路板(11)同时连接多个待测试芯片，获取芯片试验过程的测试参数，操作简单，测试效率高，适用于多种产品的芯片测试。

Description

芯片试验装置、系统及方法 技术领域
本发明涉及半导体技术领域，尤其是涉及一种芯片试验装置、系统及方法。
背景技术
芯片的工作寿命可以通过温度加速老化的方法估算得出，在一定温度下施加电压是一种严酷的工作方式，在温度和电场的作用下，质量差的器件就会失效，用这种方式可以判断芯片的制造水平，也可以用于判断生产批的质量好坏。芯片的高温老化测试，在终端产品中，多焊接到产品中进行产品的性能测试，以通过产品的测试结果来反推芯片的性能测试结果，这种测试方法，效率慢，操作困难，而且焊接到产品中测试，占用设备空间，不适合芯片数量太多的产品测试中。
发明内容
本发明提供了一种芯片试验装置、系统及方法，该装置可以用于同时对多个待测芯片进行测试，操作简单，测试效率高，适用于多种产品的芯片测试。
第一方面，本发明实施例提供了一种芯片试验装置，该装置包括：电源插装电路板、器件测试电路板、器件插装电路板和连接件；所述电源插装电路板与所述器件测试电路板通信连接；所述器件测试电路板通过多个所述连接件分别和多个所述器件插装电路板通信连接；所述器件插装电路板用于与待测芯片通信连接，获取所述待测芯片的测试参数，并将所述测试参数通过所述连接件发送至所述器件测试电路板；所述器件测试电路板用于接收所述测试参数，并将所述测试参数发送至测试模块，以使所述测试模块生成芯片测试结果。
第二方面，本发明实施例还提供一种芯片试验系统，该系统包括测试模块和上述芯片试验装置。
第三方面，本发明实施例还提供一种芯片试验方法，该方法应用于上述芯片试验装置，该方法包括：所述器件插装电路板与待测芯片通信连接，获取所述待测芯片的 测试参数，并将所述测试参数通过所述连接件发送至所述器件测试电路板；所述器件测试电路板接收所述测试参数，并将所述测试参数发送至测试模块，以使所述测试模块生成芯片测试结果。
第四方面，本发明实施例还提供一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现上述芯片试验方法。
第五方面，本发明实施例还提供一种计算机可读存储介质，所述计算机可读存储介质存储有执行上述芯片试验方法的计算机程序。
本发明实施例带来了以下有益效果：本发明实施例提供了一种芯片试验方案，该方案，该方案包括电源插装电路板、器件测试电路板、器件插装电路板和连接件，电源插装电路板与器件测试电路板通信连接；器件测试电路板通过多个连接件分别和多个器件插装电路板通信连接；通过器件插装电路板与待测芯片通信连接，获取待测芯片的测试参数，并将测试参数通过连接件发送至器件测试电路板；通器件测试电路板接收测试参数，并将测试参数至测试模块，以使测试模块生成芯片测试结果。本发明实施例可以通过多个器件插装电路板同时连接多个待测试芯片，获取芯片试验过程的测试参数，操作简单，测试效率高，适用于多种产品的芯片测试。
本发明的其他特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
为使本发明的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本发明具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的芯片试验装置结构框图；
图2为本发明实施例提供的芯片试验装置结构示意图；
图3为本发明实施例提供的器件插装电路板结构示意图；
图4为本发明实施例提供的电源插装电路板结构示意图；
图5为本发明实施例提供的芯片试验方法流程图；
图6为本发明实施例提供的计算机设备结构框图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图对本发明的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
芯片的试验装置既要考虑到可以同时试验多个数量的器件，成本不高，而且节省设备空间，尤其在温度试验之后，便于测试。
基于此，本发明实施例提供的一种芯片试验装置、系统及方法，可以提升芯片的测试效率。
为便于对本实施例进行理解，首先对本发明实施例所公开的一种芯片试验装置进行详细介绍。
本发明实施例提供了一种芯片试验装置，参见图1所示的芯片试验装置结构框图，该装置包括：电源插装电路板14、器件测试电路板13、器件插装电路板11和连接件12。
电源插装电路板与器件测试电路板通信连接；器件测试电路板通过多个连接件分别和多个器件插装电路板通信连接；器件插装电路板用于与待测芯片通信连接，获取待测芯片的测试参数，并将测试参数通过连接件发送至器件测试电路板；器件测试电路板用于接收测试参数，并将测试参数发送至测试模块，以使测试模块生成芯片测试结果。
在本发明实施例中，每个器件测试电路板上设置有多个连接件，每个连接件连接一个器件插装电路板，每个器件插装电路板可以连接一个待测芯片，从而实现对多个芯片进行测试试验，器件插装电路板获取芯片的电压，电流及频率等芯片的测试参数信息，之后，通过连接件将测试参数发送至器件测试电路板，器件测试电路板将测试参数发送至测试模块，测试模块将获取的电压，电流及频率等芯片参数，与预设的芯 片额定参数进行比较，以确定被测芯片质量是否通过测试，进而得到芯片测试结果。该装置可以同时获取多个待测芯片的测试参数，从而同时对多个待测芯片进行测试，提升了芯片测试效率，且操作简单，降低成本。
需要说明的是，器件插装电路板焊接可与待测芯片焊接，例如，参见图3所示的器件插装电路板结构示意图，图中D1-D7为待实验集成电路芯片，C1-C7为集成电路芯片正常运行所需外围电路，主要为贴片电容，D1与C1为一组实验单元。
本发明实施例提供了一种芯片试验方案，该方案，该方案包括电源插装电路板、器件测试电路板、器件插装电路板和连接件，电源插装电路板与器件测试电路板通信连接；器件测试电路板通过多个连接件分别和多个器件插装电路板通信连接；通过器件插装电路板与待测芯片通信连接，获取待测芯片的测试参数，并将测试参数通过连接件发送至器件测试电路板；通器件测试电路板接收测试参数，并将测试参数至测试模块，以使测试模块生成芯片测试结果。本发明实施例可以通过多个器件插装电路板同时连接多个待测试芯片，获取芯片试验过程的测试参数，操作简单，测试效率高，适用于多种产品的芯片测试。
为了提升该装置的适用性，器件测试电路板与电源插装电路板为固定连接或活动连接。
在本发明实施例中，器件测试电路板可以与电源插装电路板进行集成，设置在电源插装电路板上，也可以独立于另外一个电路板上。
考虑到不同的试验过程需要的测试参数不同，为了提升该装置的适用范围，该装置还包括：
至少一个器件插装电路板通过至少一个连接件与电源插装电路板通信连接；至少一个器件插装电路板用于与待测芯片通信连接，获取待测芯片的第二测试参数，并将第二测试参数通过至少一个连接件发送至电源插装电路板；电源插装电路板还用于接收第二测试参数，并将第二测试参数发送至测试模块，以使测试模块生成芯片测试结果。
在本发明实施例中，第二测试参数中包含的数据种类少于测试参数，为了能够同时进行不同需求测试，电源插装电路板可以通过连接件与器件插装电路板通信连接，通过器件插装电路板获取待测芯片的第二测试参数，将该第二测试参数发送至测试模块，从而得到芯片测试结果，从而进一步提升芯片的测试效率。
为了便于操作，连接件与器件插装电路板为活动连接。
参见图2所示的芯片试验装置结构示意图，图中虚线表示为活动连接，实线表示为固定连接。
为了节省空间，电源插装电路板上设置有定位孔。
在本发明实施例中，电源插装电路板的四边角有四个定位孔，通过定位孔可以采用定位柱将多个电源插装电路板按一定的高度垂直叠加起来，从而节省空间。
需要说明的是，定位孔可以根据实际使用的定位柱尺寸定，一般直径为3mm。
为了便于连接，电源插装电路板包括电源电路模块和插装焊盘电路模块；插装焊盘电路模块包括备用跳线单元和器件插装电路连接单元。
在本发明实施例中，电源插装电路板由两路电路组成，一路为电源电路，直接与电源连接，另外一路为若干路相同的插装焊盘电路并联连接电路。插装焊盘电路相互之间的最小间隔为6mm；最大间隔根据插装电路板的总长和插装焊盘电路的个数决定。
电源插装电路板的具体结构，参见图4所示的电源插装电路板结构示意图，其中，P1-P8为与电源插装电路板固定连接的连接件；P_test为与器件测试电路板固定连接的连接件，P1，P11，R11，P12，R12：为一组实验单元。
插装焊盘电路包括备用跳线电路和与器件插装电路相对应连接的设计电路。其中，备用跳线电路为配对的跳线针和跳线帽，或者为两个焊盘且两个焊盘之间不焊接器件或者直接用焊锡短接；备用跳线电路用于短接测试用。器件插装电路连接单元为与器件插装电路相对应连接的设计电路。
为了保证电路可靠连接，器件插装电路连接单元的尺寸与连接件的尺寸一致。
在本发明实施例中，与器件插装电路相对应连接的设计电路的长度和宽度需与连接件的长度和宽度保持一致，以利于电路连接可靠。
为了便于连接，器件测试电路板包括外部设备连接模块和器件插装电路连接模块。
在本发明实施例中，器件测试电路板由两路电路和连接件组成，一路与器件插装焊盘电路相对应，用于器件插装电路板插入测试用；另外一路为间距2.54mm的常规插装电路，用于与外部测试设备相连接；连接件为上述相同连接件。
为了便于连接，器件插装电路板包括电源插装电路连接模块和器件焊盘电路模 块；电源插装电路连接模块与器件插装电路连接单元通信连接；器件焊盘电路模块与器件插装电路连接模块通信连接。
在本发明实施例中，器件插装电路板由两路电路组成，一路为若干路相同的器件焊盘电路，一路为与电源插装电路相对应连接的设计电路。每个器件焊盘电路的一边均与电源插装电路相对应连接的设计电路相连接。器件焊盘电路与器件的封装规格和尺寸及应用条件相对应进行设计。器件为集成电路类物料，尤为时钟芯片类。
器件焊盘电路相互之间的最小间隔距离为器件的宽度+3mm，最大间隔距离根据器件插装电路板的长度和焊接的器件个数定。与电源插装电路相对应连接的设计电路采用金手指插装形式，以利于与连接件实现快速连接或断开。连接件的内部电路需要电源插装电路和器件插装电路一致，以利于电路连接可靠。连接件为金手指插座总线插槽。连接件的插针端与电源插装电路板焊接固定。连接件的插槽端与器件插装电路板进行插接。器件插装电路板可以根据需要从连接件的插槽端拔出测试用。连接件为插板式金手指插座总线插槽，一般为44芯，各个芯之间的间距均为3.96mm。
本发明实施例提供了一种芯片试验装置、系统及方法，该装置通过电路的巧妙设计和布局，在具体应用时极为方便；可以同时测试多个器件，每一个器件插装电路板可以根据需要焊接多个器件，如一个实施例中具有7个，而每个电源插装电路板上又可以同时连接多个器件插装电路板，如一个实施例中具有8个，一个试验装置可以同时开展56个，可以根据实际情况焊接更多的器件，提高同时试验的样品数量，大大提高了测试效率；电源插装电路板上带有定位孔，可以通过定位柱将多个试验装置按一定的高度垂直连接，节省放入试验箱体内的水平占用空间器件；每个电源插装电路板上连接的器件插装电路板均以并联实现，可以根据器件坏的情况或测试需要，任意抽取器件插装电路板放入器件测试电路板上进行测试，并不影响其他电路板，且操作方便；器件测试电路如与器件插装电路板设计一起，可以实现在试验条件下进行测试；器件插装电路板的器件焊盘电路可以根据采用的集成电路封装进行设计改动，适用其他类型的封装类型，适用性好；另外，整个实验装置，取材容易，且成本较低，而且相比于焊接到成品电路中去测试，大大节约了时间和成本。
本发明实施例还提供了一种芯片试验系统，该系统包括上述任一种芯片试验装置。
本发明实施例中还提供了一种芯片测试方法，如下面的实施例所述。由于该方法 解决问题的原理与芯片测试装置相似，因此该方法的实施可以参见芯片测试装置的实施，重复之处不再赘述。参见图5所示的芯片试验方法流程图，该方法包括如下步骤：
步骤S502，器件插装电路板与待测芯片通信连接，获取待测芯片的测试参数，并将测试参数通过连接件发送至器件测试电路板。
步骤S504，器件测试电路板接收测试参数，并将测试参数发送至测试模块，以使测试模块生成芯片测试结果。
在本发明实施例中，具体执行时，将上述连接件插针端焊接于电源插装电路板上，并将已焊接完成器件的器件插装电路板插入连接件卡槽中，放入试验箱中，试验完成的器件插装电路板可以根据需要任意从卡槽中拔出，插入器件测试电路板的连接件卡槽中，与测试设备连接进行测试。
本发明实施例还提供一种计算机设备，参见图6所示的计算机设备结构示意框图，该计算机设备包括存储器61、处理器62及存储在存储器上并可在处理器上运行的计算机程序，处理器执行计算机程序时实现上述任一种芯片测试方法的步骤。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的计算机设备的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
本发明实施例还提供一种计算机可读存储介质，计算机可读存储介质存储有执行上述任一种芯片测试方法的计算机程序。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
最后应说明的是：以上所述实施例，仅为本发明的具体实施方式，用以说明本发明的技术方案，而非对其限制，本发明的保护范围并不局限于此，尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，其依然可以对前述实施例所记载的技术方案进行修改或可轻易想到变化，或者对其中部分技术特征进行等同替换；而这些修改、变化或者替换，并不使相应技术方案的本质脱离本发明实施例技术方案的精神和范围，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (13)

  1. 一种芯片试验装置，其特征在于，包括：电源插装电路板、器件测试电路板、器件插装电路板和连接件；
    所述电源插装电路板与所述器件测试电路板通信连接；所述器件测试电路板通过多个所述连接件分别和多个所述器件插装电路板通信连接；
    所述器件插装电路板用于与待测芯片通信连接，获取所述待测芯片的测试参数，并将所述测试参数通过所述连接件发送至所述器件测试电路板；
    所述器件测试电路板用于接收所述测试参数，并将所述测试参数发送至测试模块，以使所述测试模块生成芯片测试结果。
  2. 根据权利要求1所述的装置，其特征在于，所述器件测试电路板与所述电源插装电路板为固定连接或活动连接。
  3. 根据权利要求1所述的装置，其特征在于，还包括：至少一个器件插装电路板通过至少一个连接件与所述电源插装电路板通信连接；
    所述至少一个器件插装电路板用于与待测芯片通信连接，获取所述待测芯片的第二测试参数，并将所述第二测试参数通过所述至少一个连接件发送至所述电源插装电路板；
    所述电源插装电路板还用于接收所述第二测试参数，并将所述第二测试参数发送至测试模块，以使所述测试模块生成芯片测试结果。
  4. 根据权利要求1-3任一项所述的装置，其特征在于，所述连接件与所述器件插装电路板为活动连接。
  5. 根据权利要求1所述的装置，其特征在于，所述电源插装电路板上设置有定位孔。
  6. 根据权利要求1所述的装置，其特征在于，所述电源插装电路板包括电源电路模块和插装焊盘电路模块；所述插装焊盘电路模块包括备用跳线单元和器件插装电路连接单元。
  7. 根据权利要求6所述的装置，其特征在于，所述器件插装电路连接单元的尺寸与所述连接件的尺寸一致。
  8. 根据权利要求6所述的装置，其特征在于，所述器件测试电路板包括外部设备 连接模块和器件插装电路连接模块。
  9. 根据权利要求8所述的装置，其特征在于，所述器件插装电路板包括电源插装电路连接模块和器件焊盘电路模块；
    所述电源插装电路连接模块与所述器件插装电路连接单元通信连接；
    所述器件焊盘电路模块与所述器件插装电路连接模块通信连接。
  10. 一种芯片试验系统，其特征在于，包括测试模块以及权利要求1-9任一项所述的芯片试验装置。
  11. 一种芯片试验方法，其特征在于，应用于如权利要求1-9任一项所述的装置，所述方法包括：
    所述器件插装电路板与待测芯片通信连接，获取所述待测芯片的测试参数，并将所述测试参数通过所述连接件发送至所述器件测试电路板；
    所述器件测试电路板接收所述测试参数，并将所述测试参数发送至测试模块，以使所述测试模块生成芯片测试结果。
  12. 一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现权利要求11所述芯片试验方法。
  13. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有执行权利要求11所述芯片试验方法的计算机程序。
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