WO2022057337A1 - 半导体结构的制作方法 - Google Patents

半导体结构的制作方法 Download PDF

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Publication number
WO2022057337A1
WO2022057337A1 PCT/CN2021/100031 CN2021100031W WO2022057337A1 WO 2022057337 A1 WO2022057337 A1 WO 2022057337A1 CN 2021100031 W CN2021100031 W CN 2021100031W WO 2022057337 A1 WO2022057337 A1 WO 2022057337A1
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layer
filling layer
isolation layer
sidewall
etching process
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PCT/CN2021/100031
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English (en)
French (fr)
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宛强
刘涛
李森
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长鑫存储技术有限公司
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Priority to US17/404,222 priority Critical patent/US11915933B2/en
Publication of WO2022057337A1 publication Critical patent/WO2022057337A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Definitions

  • the present application relates to the field of fabrication of semiconductor devices, and in particular, to a fabrication method of a semiconductor structure.
  • the Self-Aligned Double Patterning (SADP) process came into being.
  • the spacer process the principle of which is to form spacers on both sides of the pre-mandrel pattern, then remove the mandrel pattern, and transfer the sidewall pattern to the target material layer to achieve the target pattern.
  • the purpose of the present application is to provide a silicon rod processing equipment and a silicon rod processing method, which can remove the polymer in the etching process and improve the quality of the product.
  • the present application discloses a method for fabricating a semiconductor structure, which is characterized by comprising the following steps:
  • the initial structure comprising a substrate, a mask layer formed on the substrate, and a spacer formed on the mask layer;
  • the filling layer of the first preset thickness is removed by a first etching process, and the remaining filling layer after the first etching process covers the sidewall spacers; in the first etching process, a first etching process is adopted. rate;
  • a second etching process is used to remove the filling layer of the second preset thickness and expose part of the spacer, so as to remove at least part of the carbon-based polymer at the boundary of the filling layer and/or at the boundary between the filling layer and the spacer ; in the second etching process, a second etching rate is used, and the second etching rate is less than the first etching rate; and
  • Patterning is performed on the filling layer and the sidewalls.
  • the parameters of the first etching process include: the etching gas includes oxygen, the flow rate of the oxygen is 12 sccm to 18 sccm, and the etching rate is 0.5 nm/s to 5 nm/s.
  • the parameters of the second etching process include: the etching gas includes nitrogen, the flow rate of the nitrogen is 18 sccm to 22 sccm, and the etching rate is 0.1 nm/s to 0.5 nm/s.
  • the height difference between the filling layer after the second etching process and the top of the spacer is 1 nm to 3 nm.
  • the patterning process on the filling layer and the sidewall includes: forming an isolation layer on the filling layer and the sidewall; and forming a mask structure on the isolation layer.
  • the isolation layer includes a silicon oxynitride layer, a polysilicon layer, an amorphous carbon layer, or an oxide layer.
  • the forming an isolation layer on the filling layer and the sidewall includes: forming a first isolation layer on the filling layer and the sidewall; adopting a spin-on dielectric process, on the first isolation layer.
  • a second isolation layer is formed on an isolation layer; the second isolation layer and the first isolation layer are ground to form an isolation layer.
  • the thickness of the first isolation layer is 35 nm to 45 nm
  • the thickness of the second isolation layer is 25 nm to 35 nm
  • the thickness of the isolation layer is 40 nm to 50 nm.
  • the second isolation layer and the first isolation layer before grinding the second isolation layer and the first isolation layer, it further includes performing an annealing heat treatment on the second isolation layer.
  • the method further includes: etching the mask layer by using the mask structure and the sidewalls as an etch barrier layer to form the first mask layer. a pattern, and continuing to transfer the first pattern to the substrate to obtain the target pattern.
  • the method for fabricating a semiconductor structure disclosed in the present application includes: providing an initial structure; forming a filling layer covering the sidewall spacer on the initial structure; A filling layer with a thickness is set, and then a second etching process is used to remove the filling layer of the second preset thickness at a slower second etching rate and reveal part of the sidewall; patterning is performed on the filling layer and the sidewall .
  • a unique two-step etching process at least part of the carbon-based polymer at the boundary of the filling layer and/or at the boundary between the filling layer and the sidewall can be removed, so as to facilitate the subsequent process. Process stability and improve product quality.
  • FIG. 1 is a schematic diagram showing the presence of polymer residues on the corresponding film layers after an etching process in the related art.
  • FIG. 2 is a schematic flowchart of a method for fabricating a semiconductor structure of the present application.
  • FIG. 3 is a schematic diagram 1 of a structure change of fabricating a semiconductor structure according to the steps of FIG. 2 .
  • FIG. 4 is a schematic diagram showing a second structural variation of fabricating the semiconductor structure according to the steps of FIG. 2 .
  • FIG. 5 is a schematic diagram 3 of the structure change of fabricating the semiconductor structure according to the steps of FIG. 2 .
  • FIG. 6 is a schematic diagram 4 of the structure change of fabricating the semiconductor structure according to the steps of FIG. 2 .
  • FIG. 7 is a schematic diagram 5 of the structure change of fabricating the semiconductor structure according to the steps of FIG. 2 .
  • FIG. 8 is a schematic diagram 6 of a structural variation of fabricating the semiconductor structure according to the steps of FIG. 2 .
  • FIG. 9 is a schematic diagram 7 of a structure change of fabricating the semiconductor structure according to the steps of FIG. 2 .
  • FIG. 10 is a schematic diagram showing eighth structural changes of the semiconductor structure fabricated according to the steps of FIG. 2 .
  • FIG. 11 is a schematic diagram showing nine structural changes of fabricating the semiconductor structure according to the steps of FIG. 2 .
  • FIG. 12 is a schematic view showing a tenth structural variation of the semiconductor structure fabricated according to the steps of FIG. 2 .
  • FIG. 13 is a schematic diagram showing eleven structural changes of the semiconductor structure fabricated according to the steps of FIG. 2 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 is a schematic diagram showing the presence of polymer residues on the corresponding film layers after an etching process in the related art. As shown in FIG.
  • the present application discloses a method for fabricating a semiconductor structure.
  • polymer residues can be eliminated or reduced, so as to facilitate the stability of the subsequent process and improve the quality of the product.
  • the execution body of the present application may be a semiconductor device, which is not limited in the embodiment of the present application.
  • FIG. 2 is a schematic flowchart of a method for fabricating a semiconductor structure of the present application. As shown in FIG. 2 , the fabrication method of the semiconductor structure includes the following steps:
  • step S101 an initial structure is provided, and the initial structure includes a substrate, a mask layer formed on the substrate, and a spacer formed on the mask layer.
  • Step S103 forming a filling layer covering the sidewall on the initial structure.
  • Step S105 the filling layer with the first preset thickness is removed through a first etching process, and the remaining filling layer after the first etching process covers the sidewall spacers.
  • Step S107 removing the filling layer of the second preset thickness and exposing part of the spacer by a second etching process, so as to remove at least part of the carbon-based polymer at the boundary of the filling layer and/or the boundary between the filling layer and the spacer.
  • Step S109 patterning is performed on the filling layer and the sidewall.
  • the semiconductor device performs step S101 to provide an initial structure, where the initial structure includes a substrate, a mask layer formed on the substrate, and a spacer formed on the mask layer.
  • the fabrication process of the semiconductor structure adopts a dual imaging process
  • the dual imaging process may be, for example, a SADP (Self-Aligned Double Patterning, self-aligned dual imaging) process.
  • the substrate has a known patterned layer stack designed for self-aligned double patterning.
  • the substrate may include single crystal silicon, oxide layer, polysilicon layer, silicon germanium, silicon-on-insulator, etc., and the substrate may also include a stacked combination structure of various materials, such as silicon nitride, silicon oxide, carbon A combination of silicon nitride or silicon oxynitride, etc.
  • the base layer 201 is shown as a schematic illustration.
  • a mask layer may be formed on the base layer 201 .
  • the mask layer may be a single-layer structure or a multi-layer structure, and the material of the mask layer may include but not limited to silicon oxynitride (SiON), polysilicon (Poly), and amorphous carbon layer (ACL) , oxide (Oxide) and so on.
  • SiON silicon oxynitride
  • Poly polysilicon
  • ACL amorphous carbon layer
  • Oxide oxide
  • the polishing layer adopts a double-layer structure composed of an amorphous carbon layer (ALC) combined with a silicon oxynitride layer (SiON), that is, an ALC layer is sequentially formed on the base layer 201 202 and a SiON layer 203, wherein the ALC layer 202 can be formed by a chemical vapor deposition process (Chemical Vapor Deposition, CVD) or a spin-on dielectric process (Spin-on Dielectrics, SOD), and the SiON layer 203 can also be used as a follow-up etch stop layer.
  • ALC amorphous carbon layer
  • SiON silicon oxynitride layer
  • spacers 205 are formed on the mask layer, that is, in the embodiment shown in FIG. 3 , the spacers 205 are formed on the SiON layer 203 .
  • the fabrication process of forming the sidewall spacers 205 may include: forming a mandrel layer on the surface of the mask layer; patterning the mandrel layer to form mandrels arranged at intervals, layer and the surface of the mandrel to form a spacer material layer; use a plasma etching process to etch back the spacer material layer until the mask layer and the top of the mandrel are exposed, leaving both sides of the mandrel of sidewall material as sidewalls; remove the mandrels to form sidewalls.
  • the material of the spacers 205 may be oxide materials, dielectric materials, or the like.
  • step S103 the semiconductor device performs step S103 to form a filling layer covering the spacer on the initial structure.
  • a filling layer 207 is formed on the surface of the mask layer (ie, the SiON layer 203 ) until the sidewall spacers 205 are completely covered to form the structure shown in FIG. 4 .
  • the filling layer 207 may be formed by a spin-on-hardmask (SOH) layer, the SOH layer may be formed by a spin-coating process, and the SOH layer may be an insulating layer of a hydrocarbon (CxHy) system, which may include Silicon hard mask materials, carbon hard mask materials, and organic hard mask materials, etc.
  • the filling layer 207 completely covers the sidewall spacer 205, and the thickness of the filling layer 207 may be about 80 nm, for example, within the range of 70 nm to 150 nm. In fact, the thickness of the filling layer 207 is not limited to this, and can be varied according to the height of the sidewalls 205 , which is mainly to completely cover the sidewalls 205 .
  • the filling layer 207 may also be formed of, for example, photoresist or amorphous silicon.
  • the material of the SOH layer has the characteristics of strong viscosity and poor fluidity, so it is easy to aggregate on the surface of the oxide to form C aggregated particles, that is, hard carbon particles (Hard C).
  • Hard C hard carbon particles
  • the filling material will produce hard carbon particles at the interface with the sidewall 205 (the material of the sidewall 205 can be, for example, an oxide material). C).
  • step S105 removing the filling layer of the first predetermined thickness through a first etching process, and the remaining filling layer after the first etching process covers the sidewall spacers.
  • step S105 the semiconductor device performs a first etching process to remove the filling layer of the second preset thickness, wherein the filling layer 207 remaining after the first etching process still covers Adjacent to the side wall 205, the structure shown in FIG. 5 is formed.
  • the step S105 is a preliminary step, which is mainly used to remove the part of the filling layer 207 that covers the side wall 205, that is, the filling layer 207 is higher than the side wall 205. section so that the top of the removed filler layer is as close as possible to the top of the sidewall.
  • the height difference H1 between the sidewall 205 and the filling layer 207 formed in step S103 can be obtained according to the height of the sidewall 205 and the height of the filling layer 207 formed in step S103. According to the height difference H1, a first predetermined thickness of the filling layer to be removed by performing the first etching process is determined.
  • the parameters of the first etching process include: the power is 100W to 300W, and further can be 150W to 250W, the etching gas includes oxygen, and the flow rate of oxygen is 12sccm (standard milliliter/min) to 18sccm (standard ml/min), for example 15 sccm, the etching rate is 0.5 nm/s to 5 nm/s, further 0.6 nm/s to 1.5 nm/s, preferably 0.8 nm/s.
  • the filling layer material of the second predetermined thickness may be removed, and the second predetermined thickness may be, for example, about 15 nm (nanometers), for example, within the range of 12 nm to 18 nm.
  • step S105 the part of the filling layer above the sidewall 205 can be removed as much as possible, which is beneficial to the execution of the subsequent step S105 and improves the efficiency.
  • step S107 removing the filling layer of the second preset thickness and exposing part of the sidewall spacer through a second etching process, so as to remove at least part of the filling layer at the boundary and/or at the boundary between the filling layer and the sidewall spacer.
  • carbon based polymers carbon based polymers.
  • step S107 the semiconductor device performs a second etching process to remove the filling layer of the second preset thickness and expose part of the sidewall spacers to form the structure shown in FIG. 6 .
  • the parameters of the second etching process include: the power is 100W to 300W, and further can be 150W to 250W, the etching gas includes nitrogen, and the flow rate of nitrogen is 18sccm (standard milliliter minute) to 22sccm (standard milliliter /min), for example, 20 sccm, and the etching rate is 0.1 nm/s to 0.5 nm/s.
  • the filling layer material of the second predetermined thickness can be removed and a part of the sidewall spacer is exposed, that is, the filling layer 207 is exposed on the top of the sidewall spacer 205.
  • the sidewall spacer 205 The top of the filling layer 207 is higher than the filling layer 207, for example, about 2 nm (nanometer), for example, within the range of 1 nm to 3 nm, that is, the height difference between the filling layer 207 and the top of the sidewall spacer 205 after the second etching process in step S107 is performed H2 is 1 nm to 3 nm.
  • step S107 the filling layer material of the second preset thickness is removed and part of the sidewall spacers are exposed, so that the carbon-based polymer originally collected at the junction of the filling layer 207 and the top of the sidewall spacers 205 can be removed.
  • the second etching rate used in the second etching process is smaller than the first etching rate used in the first etching process.
  • the filling layer 207 is etched slowly by prolonging the etching time, so that the plasma used in the etching process can be fully reacted and not retained on the surface of the film layer.
  • nitrogen plasma is used to bombard down slowly and vertically, and the filling layer and carbon-based polymer are etched downward at the same time because of their lower hardness than the sidewall material, so as to ensure that the filling layer and carbon-based polymer are etched down at the same time.
  • the carbon-based polymer can also be removed at the same time.
  • the filling layer 207 in this embodiment in the process of performing step S107, in the process of removing the filling layer of the second preset thickness by using the second etching process and exposing part of the sidewall spacer, at least part of the boundary of the filling layer can be removed.
  • the carbon-based polymer at the location is beneficial to ensure the quality of the formed film in the subsequent film manufacturing process.
  • the carbon-based polymer includes carbon-containing polymer (C Polymer) remaining on the surface of the film layer and hard carbon particles (Hard C) remaining at the junction of the film layer and the sidewall. Therefore, at least part of the filling layer is removed.
  • the carbon-based polymer at the boundary and/or at the junction of the filling layer and the sidewall may include: removing or partially removing the carbon-containing polymer (C Polymer) at the boundary of the filling layer, removing or partially removing the carbon-based polymer at the boundary of the filling layer Hard carbon particles (Hard C) remain at the junction with the side wall. Please refer to the schematic diagram of the structural change shown in FIG. 7 .
  • step S109 the semiconductor device executes step S109 to perform patterning processing on the filling layer and the sidewall.
  • the carbon-based polymer at the boundary of the filling layer and/or the boundary between the filling layer and the sidewall may be removed or partially removed, that is, the carbon-containing polymer at the boundary of the filling layer may be removed or partially removed (C Polymer), remove or partially remove the hard carbon particles (Hard C) remaining at the junction of the filling layer and the sidewall, so that the subsequent patterning process can be performed on the filling layer and the sidewall.
  • C Polymer remove or partially remove the hard carbon particles (Hard C) remaining at the junction of the filling layer and the sidewall
  • step S109 there are different implementations for performing the subsequent patterning process.
  • the semiconductor device forms an isolation layer on the filling layer and the sidewall, wherein the isolation layer includes a silicon nitride layer or a silicon oxynitride layer. Therefore, the above steps include: forming an isolation layer 209 on the surfaces of the filling layer 207 and the sidewall spacer 205 to form the structure shown in FIG. 8 .
  • a mask layer 211 and a photoresist layer are formed on the surface of the isolation layer 209, and an etching process is performed to form the structure shown in FIG. 9 .
  • the steps of forming the structure shown in FIG. 9 in the semiconductor device may include: firstly forming a mask layer 211 on the surface of the isolation layer 209 , for example, using a chemical vapor deposition process to form a mask on the surface of the isolation layer 209 Layer 211, the material of the mask layer may include but not limited to silicon oxynitride (SiON), polysilicon (Poly), amorphous carbon layer (ACL), oxide (Oxide), etc.; A patterned photoresist layer is formed on the surface of the film layer 211.
  • a photoresist is spin-coated on the mask layer 211, and the photoresist is patterned through a mask to form a patterned photoresist. and then, using the patterned photoresist layer to etch the mask layer 211 to form a plurality of mask structures on the isolation layer 209, between two adjacent mask structures There is an opening that exposes a partial area of the isolation layer 209 .
  • the mask structure may also be formed on the surface of the isolation layer 209 by an SADP process.
  • the plurality of mask structures constitute the pattern layer.
  • the semiconductor equipment continues the subsequent process, using the mask structure and the sidewall spacers as etch barrier layers to etch the filling layer 207 and the mask layer 202 to form a first pattern, and continue to transfer the first pattern to the substrate, Then the target pattern is obtained.
  • the isolation layer is etched with the mask structure, if the isolation layer is bulged due to the carbon-based polymer or the surface of the isolation layer is uneven, when the layer is transferred downward, a bulged position will be caused Or the position with a high surface is difficult to be etched downward, which eventually leads to the phenomenon of CD unevenness in the obtained target pattern, which affects the product yield.
  • removing the carbon-based polymer and obtaining a flat surface of the isolation layer a target pattern with a uniform CD can be obtained, thereby improving the yield of the product.
  • an isolation layer is formed on the filling layer and the sidewall, wherein the isolation layer includes an oxide layer.
  • the forming process may further include:
  • the semiconductor device forms the first isolation layer 210 on the filling layer 207 and the spacer 205 to form the structure shown in FIG. 10 .
  • the first isolation layer may be formed by chemical vapor deposition (CVD) or spin-on dielectric process (SOD), and the thickness of the first isolation layer is 35 nm to 45 nm, for example, 40 nm.
  • the semiconductor device forms the second isolation layer 212 on the first isolation layer 210 to form the structure shown in FIG. 11 .
  • the second isolation layer may be formed by a spin-on-dielectric process (SOD), and the thickness of the second isolation layer is 25 nm to 35 nm, for example, 30 nm.
  • an annealing heat treatment (Anneal) is further included on the formed second isolation layer 212, and the annealing heat treatment can improve the annealing heat treatment of the second isolation layer 212 formed by the spin-on dielectric process (SOD). roughness and densification of the second isolation layer 212 .
  • the annealing heat treatment process is performed at a high temperature in the range of about 400°C to about 1100°C, which may be a wet annealing process using a gas including water vapor, O2 and H2 or using a gas including N2 and O2 gas dry annealing process.
  • the semiconductor device grinds the second isolation layer and the first isolation layer to form the isolation layer 214 to form the structure shown in FIG. 12 .
  • the second isolation layer 212 formed by the spin-on dielectric process (SOD) in the previous step is mainly ground. After grinding and removing part of the second isolation layer, the remaining second isolation layer and the first isolation layer are The isolation layer constitutes the isolation layer 214, and the thickness of the isolation layer is 40 nm to 50 nm.
  • a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process can be used for the second isolation layer of the grinding removal part, which can obtain a more perfect surface while ensuring the material removal efficiency, and can achieve nanometer
  • CMP Chemical Mechanical Polishing
  • the following process may be continued to form a mask layer 215 on the surface of the isolation layer 214 and perform an etching process to form the structure shown in FIG. 13 .
  • the step of forming the structure shown in FIG. 13 in the semiconductor device may include: firstly forming a mask layer 215 on the surface of the isolation layer 214 , for example, using a chemical vapor deposition process to form a mask on the surface of the isolation layer 214 Layer 215, the material of the mask layer may include but not limited to silicon oxynitride (SiON), polysilicon (Poly), amorphous carbon layer (ACL), oxide (Oxide), etc.; A patterned photoresist layer is formed on the surface of the film layer 215. For example, a photoresist is spin-coated on the mask layer 215, and the photoresist is patterned through a mask to form a patterned photoresist.
  • a photoresist is spin-coated on the mask layer 215, and the photoresist is patterned through a mask to form a patterned photoresist.
  • the patterned photoresist layer to etch the mask layer 215 to form a plurality of mask structures on the isolation layer 214, between two adjacent mask structures There is an opening that exposes a partial area of the isolation layer 214 .
  • the mask structure may also be formed on the surface of the isolation layer 209 through a SADP process.
  • the plurality of mask structures constitute the pattern layer.
  • the semiconductor equipment continues the subsequent process, using the mask structure and the sidewall spacers as etch barrier layers to etch the filling layer 207 and the mask layer 202 to form a first pattern, and continue to transfer the first pattern to the substrate, Then the target pattern is obtained.
  • the isolation layer is etched with the mask structure, if the isolation layer is bulged due to the carbon-based polymer or the surface of the isolation layer is uneven, when the layer is transferred downward, a bulged position will be caused Or the position with a high surface is difficult to be etched downward, which eventually leads to the phenomenon of CD unevenness in the obtained target pattern, which affects the product yield.
  • the target pattern may be a capacitor hole, and in other embodiments, the target pattern may also be other structural patterns.
  • the method for fabricating a semiconductor structure disclosed in the present application includes: providing an initial structure; forming a filling layer covering the sidewall spacer on the initial structure; A filling layer with a thickness is set, and then a second etching process is used to remove the filling layer of the second preset thickness at a slower second etching rate and reveal part of the sidewall; patterning is performed on the filling layer and the sidewall .
  • a unique two-step etching process at least part of the carbon-based polymer at the boundary of the filling layer and/or at the boundary between the filling layer and the sidewall can be removed, so as to facilitate the subsequent process. Process stability and improve product quality.
  • An embodiment of the present application provides a method for fabricating a semiconductor structure.
  • the method includes: providing an initial structure; forming a filling layer covering the sidewall spacer on the initial structure; The filling layer of the first preset thickness is removed by the etching rate, and then the filling layer of the second preset thickness is removed by the second etching process at a slower second etching rate and part of the sidewall is exposed; The wall is patterned.

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Abstract

一种半导体结构的制作方法，包括：提供初始结构；在初始结构上形成覆盖侧墙（205）的填充层（207）；先通过第一刻蚀工艺以较快的第一刻蚀速率去除第一预设厚度的填充层（207），再通过第二刻蚀工艺以较慢的第二刻蚀速率去除第二预设厚度的填充层（207）并显露出部分的侧墙（205）；在填充层（207）和侧墙（205）上进行图案化处理。所述半导体结构的制作方法，通过采用独特的两步刻蚀工艺，可去除至少部分填充层（207）边界处和/或所述填充层（207）与所述侧墙（205）交界处的碳基聚合物，以利于后续制程工艺的稳定性，提高产品的质量。

Description

半导体结构的制作方法
相关申请的交叉引用
本申请基于申请号为202010984443.4、申请日为2020年09月18日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体器件的制造领域，特别是涉及一种半导体结构的制作方法。
背景技术
随着半导体技术节点以及机台的演进，芯片制造商在成本的考量下持续挑战增加器件在晶圆上的密度，集成电路中器件的密集度越来越高，半导体器件的特征关键尺寸(CD)不断减小，已逼近达到光刻的光学物理极限，以现有的光刻工艺形成的掩模图形难以满足半导体器件持续减小的特征关键尺寸的需求，限制了半导体技术的发展。
为了在现有的光刻工艺的基础上，能够进一步缩小半导体器件的尺寸，自对准双重构图(Self-Aligned Double Patterning，SADP)工艺应运而生，自对准双重构图工艺包括芯模(mandrel)和侧墙(spacer)工艺，其原理为将预先芯模图案两侧形成侧墙(spacer)，之后再去除芯模图案，让侧墙图案转移到目标材料层上，进而达到目标的图案。
不过，在半导体工艺中，在对某些膜层进行刻蚀(Etch)时，往往会在膜层表面形成聚合物残留(polymer residue)。例如以干式刻蚀为例，在干式刻蚀时，通常会利用含有氟化碳(Fluorocarbon Plasma)的气体所产生的等离子体进行刻蚀，所使用的气体从四氟化碳(Carbon Tetrafluoride，CF4)到现在的八氟化四碳(C4F8)、八氟化五碳(C5F8)或是六氟化四碳(C4F6)，都可以用来作为提供碳原子及氟原子的反应气体，利用这类气体进行刻蚀，通常刻蚀工艺后会产生以碳(C)元素为主的聚合物，若残留的聚合物不清除的话，会影响后续工艺，例如，造成后续形成的膜层可能产生缺陷，所述缺陷可例如为鼓包(bump)等，影响产品的良率和产率。
发明内容
本申请的目的在于提供一种硅棒加工设备及硅棒加工方法，能够去除刻蚀工艺中的聚合物，提高产品的质量。
本申请公开一种半导体结构的制作方法，其特征在于，包括以下步骤：
提供初始结构，所述初始结构包括基底、形成于所述基底上的掩膜层、以及形成于所述掩膜层上的侧墙；
在所述初始结构上形成覆盖所述侧墙的填充层；
通过第一刻蚀工艺去除第一预设厚度的填充层，经第一刻蚀工艺后剩下的填充层覆盖着所述侧墙；在所述第一刻蚀工艺中，采用第一刻蚀速率；
通过第二刻蚀工艺去除第二预设厚度的填充层并显露出部分的侧墙，以去除至少部分填充层边界处和/或所述填充层与所述侧墙交界处的碳基聚合物；在所述第二刻蚀工艺中，采用第二刻蚀速率，且，所述第二刻蚀速率小于第一刻蚀速率；以及
在所述填充层和所述侧墙上进行图案化处理。
上述方案中，所述第一刻蚀工艺的参数包括：刻蚀气体包括氧气，氧气的流量为12sccm至18sccm，刻蚀速率为0.5nm/s至5nm/s。
上述方案中，所述第二刻蚀工艺的参数包括：刻蚀气体包括氮气，氮气的流量为18sccm至22sccm，刻蚀速率为0.1nm/s至0.5nm/s。
上述方案中，所述第二刻蚀工艺后的填充层与所述侧墙的顶部之间的高度差为1nm至3nm。
上述方案中，所述在所述填充层和所述侧墙上进行图案化处理包括：在所述填充层和所述侧墙上形成隔离层；在所述隔离层上形成掩膜结构。
上述方案中，所述隔离层包括氮氧化硅层、多晶硅层、非晶形碳层、或氧化物层。
上述方案中，所述在所述填充层和所述侧墙上形成隔离层包括：在所述填充层和所述侧墙上形成第一隔离层；采用旋涂式电介质工艺，在所述第一隔离层上形成第二隔离层；对所述第二隔离层和所述第一隔离层进行研磨以形成隔离层。
上述方案中，所述第一隔离层的厚度为35nm至45nm，所述第二隔离层的厚度为25nm至35nm，所述隔离层的厚度为40nm至50nm。
上述方案中，在对所述第二隔离层和所述第一隔离层进行研磨之前还包括对所述第二隔离层进行退火热处理。
上述方案中，在对所述填充层和所述侧墙上进行图案化处理后，还包括：以所述掩膜结构和所述侧墙作为刻蚀阻挡层刻蚀所述掩膜层形成第一图案，继续将所述第一图案转移至基底，获得目标图案。
本申请公开的半导体结构的制作方法，包括：提供初始结构；在初始结构上形成覆盖所述侧墙的填充层；先通过第一刻蚀工艺以较快的第一刻蚀速率去除第一预设厚度的填充层，再通过第二刻蚀工艺以较慢的第二刻蚀速率去除第二预设厚度的填充层并显露出部分的侧墙；在填充层和侧墙上进行图案化处理。本申请半导体结构的制作方法，通过采用独特的两步刻蚀工艺，可去除至少部分填充层边界处和/或所述填充层与所述侧墙交界处的碳基聚合物，以利于后续制程工艺的稳定性，提高产品的质量。
附图说明
本申请所涉及的发明的具体特征如所附权利要求书所显示。通过参考下 文中详细描述的示例性实施方式和附图能够更好地理解本申请所涉及发明的特点和优势。对附图简要说明书如下：
图1显示为相关技术中经刻蚀工艺后相应膜层上存在聚合物残留的示意图。
图2显示为本申请的半导体结构的制作方法的流程示意图。
图3显示为根据图2的步骤制作半导体结构的结构变化示意图一。
图4显示为根据图2的步骤制作半导体结构的结构变化示意图二。
图5显示为根据图2的步骤制作半导体结构的结构变化示意图三。
图6显示为根据图2的步骤制作半导体结构的结构变化示意图四。
图7显示为根据图2的步骤制作半导体结构的结构变化示意图五。
图8显示为根据图2的步骤制作半导体结构的结构变化示意图六。
图9显示为根据图2的步骤制作半导体结构的结构变化示意图七。
图10显示为根据图2的步骤制作半导体结构的结构变化示意图八。
图11显示为根据图2的步骤制作半导体结构的结构变化示意图九。
图12显示为根据图2的步骤制作半导体结构的结构变化示意图十。
图13显示为根据图2的步骤制作半导体结构的结构变化示意图十一。
具体实施方式
以下由特定的实施例说明本申请的实施方式，熟悉此技术的人士可由本说明书所揭露的内容轻易地了解本申请的其他优点及功效。
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本申请将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其 它结构上。
用语“一个”、“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”仅作为标记使用，不是对其对象的数量限制。
在半导体工艺中，在对某些膜层进行刻蚀时，往往会在膜层表面形成聚合物残留。例如在一半导体结构的制作工艺中，在半导体基底上形成有侧墙及覆盖所述侧墙的膜层，之后，对所述膜层进行刻蚀以显露出其原先覆盖着的侧墙，但刻蚀过程中由于提供的反应气体包含碳元素，因此，在刻蚀工艺之后，会存在有相应元素的聚合物残留。请参阅图1，显示为相关技术中经刻蚀工艺后相应膜层上存在聚合物残留的示意图。如图1所示，由于反应气体包含有碳原子，在对膜层进行刻蚀并显露出侧墙的工艺之后，会残留有碳基聚合物，例如，在膜层表面残留有含碳聚合物(C Polymer)以及在膜层与侧墙的交界处残留有硬碳微粒(Hard C)，这些碳基聚合物会造成后续形成的膜层产生缺陷，例如为鼓包(bump)等，影响产品的良率和产率，因此，如何有效消除聚合物残留是业界亟待解决的问题。
有鉴于此，本申请公开一种半导体结构的制作方法，通过对现有刻蚀工艺进行改进，可消除或减少聚合物残留，以利于后续制程工艺的稳定性，提高产品的质量。
本申请的执行主体可以是半导体设备，本申请实施例不做限制。
请参阅图2，显示为本申请的半导体结构的制作方法的流程示意图。如图2所示，所述半导体结构的制作方法包括如下步骤：
步骤S101，提供初始结构，所述初始结构包括基底、形成于所述基底上的掩膜层、以及形成于所述掩膜层上的侧墙。
步骤S103，在初始结构上形成覆盖侧墙的填充层。
步骤S105，通过第一刻蚀工艺去除第一预设厚度的填充层，经第一刻蚀工艺后剩下的填充层覆盖着侧墙。
步骤S107，通过第二刻蚀工艺去除第二预设厚度的填充层并显露出部分 的侧墙，以去除至少部分填充层边界处和/或填充层与侧墙交界处的碳基聚合物。
步骤S109，在填充层和侧墙上进行图案化处理。
下面将结合附图详细说明本申请公开半导体结构的制作方法。
首先，半导体设备执行步骤S101，提供一初始结构，所述初始结构包括基底、形成于基底上的掩膜层、以及形成于掩膜层上的侧墙。
在本申请的一些实施例中，所述半导体结构的制作工艺采用了双重成像工艺，所述双重成像工艺可例如为SADP(Self-Aligned Double Patterning，自对准双重成像)工艺。
以SADP工艺为例，所述基底具有被设计为用于自对准双重图案化的已知图案化层堆叠。在这里，所述基底可包括单晶硅、氧化层、多晶硅层、锗化硅以及绝缘体上硅等，所述基底还可包括多种材料的堆叠组合结构，如氮化硅、氧化硅、碳氮化硅或氮氧化硅等的组合。在图1所示的结构中，作为示意性说明，仅显示了基底层201。
在基底层201上可形成掩膜层。所述掩膜层可以为单层结构或多层结构，所述掩膜层的材料可以包括但不仅限于氮氧化硅(SiON)、多晶硅(Poly)、非晶形碳层(Amorphous Carbon Layer，ACL)、氧化物(Oxide)等。在图3所示的实施例中，所述研磨层采用的是由非晶形碳层(ALC)结合氮氧化硅层(SiON)的双层结构，即，在基底层201上依序形成ALC层202和SiON层203，其中，所述ALC层202可以通过化学气相沉积工艺(Chemical Vapor Deposition，CVD)或者旋涂式电介质工艺(Spin-on Dielectrics，SOD)形成，SiON层203同时也可以作为后续的刻蚀停止层。
此外，在所述掩膜层上形成有侧墙205，即，如图3所示的实施例中，在SiON层203上形成有侧墙205。在本申请一些实施例中，形成侧墙205的制作工艺可包括：在所述掩膜层表面形成心轴层；图案化所述心轴层形成间隔排布的心轴，在所述掩膜层和所述心轴表面形成侧墙材料层；采用等离子体刻蚀工艺回刻蚀所述侧墙材料层直至暴露出所述掩膜层和所述心轴顶部，保留所述心轴两侧的侧墙材料作为侧墙；去除所述心轴，形成侧墙。
所述侧墙205的材料可为氧化物材料、电介质材料等。
通过上述步骤S01之后，形成图3所示的结构。
接着，半导体设备执行步骤S103，在初始结构上形成覆盖侧墙的填充层。
在本申请的一些实施例中，在步骤S103中，在掩膜层(即，SiON层203)的表面形成填充层207直至完全覆盖住侧墙205，形成如图4所示的结构。
其中，填充层207可由旋涂硬掩模(Spin on Hardmask，SOH)层形成，所述SOH层可通过旋转涂布工艺形成，SOH层可以是碳氢(CxHy)体系的绝缘层，其可包括硅硬掩膜材料、碳硬掩膜材料、以及有机硬掩膜材料等。另外，填充层207完全覆盖住侧墙205，填充层207的厚度可为80nm左右，例如70nm至150nm的范围之内。实际上，填充层207的厚度并不以此为限，其可根据侧墙205的高度而作不同的变化，其主要在于可完全覆盖侧墙205。可替换地，填充层207也可例如由光刻胶或非晶硅形成。
仍以SOH层为例，SOH层的材料具有粘性较强、流动性较差等特点，如此，容易在为氧化物表面聚集形成C的聚集颗粒，即，硬碳颗粒(Hard C)。从图4中可以看出，在利用SOD工艺形成填充层207的过程中，填充材料在与侧墙205(侧墙205的材料可例如为氧化物材料)交界处会产生硬碳微粒残留(Hard C)。
接着，半导体设备执行步骤S105，通过第一刻蚀工艺去除第一预设厚度的填充层，经第一刻蚀工艺后剩下的填充层覆盖着侧墙。
在本申请的一些实施例中，在步骤S105中，半导体设备执行第一刻蚀工艺以去除第二预设厚度的填充层，其中，经第一刻蚀工艺后剩下的填充层207仍覆盖着侧墙205，形成如图5所示的结构。
在本申请实施例中，相对于后续中的步骤S107，步骤S105是一个预前步骤，主要是用于去除填充层207中覆盖侧墙205的部分，即，填充层207中高于侧墙205的部分，以使得去除后的填充层的顶部尽可能接近于侧墙的顶部。例如，在实际应用中，可根据侧墙205的高度以及步骤S103中形成的填充层207的高度，可获得侧墙205与步骤S103所形成的填充层207之间的高度差H1，后续，再根据所述高度差H1，确定要执行第一刻蚀工艺去除部分 填充层的第一预设厚度。
在步骤S105中，所述第一刻蚀工艺的参数包括：功率为100W至300W，进一步可以为150W至250W，刻蚀气体包括氧气，氧气的流量为12sccm(标准毫升/分钟)至18sccm(标准毫升/分钟)，例如为15sccm，刻蚀速率为0.5nm/s至5nm/s，进一步为0.6nm/s至1.5nm/s，优选0.8nm/s。通过第一刻蚀工艺，可去除第二预设厚度的填充层材料，所述第二预设厚度可例如为15nm(纳米)左右，例如12nm至18nm的范围之内。
半导体设备执行步骤S105，可尽可能去除侧墙205之上的那部分填充层，有利于后续步骤S105的执行，提高效率。
接着，半导体设备执行步骤S107，通过第二刻蚀工艺去除第二预设厚度的填充层并显露出部分的侧墙，以去除至少部分填充层边界处和/或填充层与侧墙交界处的碳基聚合物。
在本申请的一些实施例中，在步骤S107中，半导体设备执行第二刻蚀工艺去除第二预设厚度的填充层并显露出部分的侧墙，形成如图6所示的结构。
在步骤S107中，所述第二刻蚀工艺的参数包括：功率为100W至300W，进一步可以为150W至250W，刻蚀气体包括氮气，氮气的流量为18sccm(标准毫升分钟)至22sccm(标准毫升/分钟)，例如为20sccm，刻蚀速率为0.1nm/s至0.5nm/s。通过第二刻蚀工艺，可去除第二预设厚度的填充层材料并显露出部分的侧墙，即，侧墙205的顶部露出填充层207，在本申请的一实施例中，侧墙205的顶部高于填充层207例如为2nm(纳米)左右，例如1nm至3nm的范围之内，即，执行步骤S107第二刻蚀工艺后的填充层207与侧墙205的顶部之间的高度差H2为1nm至3nm。
如前所述，由于作为填充层207的SOH层的材料粘性较强、流动性较差，容易在与侧墙205的交界处聚集形成C的聚集颗粒，即，硬碳颗粒(Hard C)，因此，利用步骤S107，去除第二预设厚度的填充层材料并显露出部分的侧墙，从而使得原先在填充层207与侧墙205顶端交界处聚集的碳基聚合物能被去除。
另外，与前述步骤S105相比，执行步骤S107时，第二刻蚀工艺中采用 的第二刻蚀速率是要小于第一刻蚀工艺中采用的第一刻蚀速率，通过降低刻蚀速率，延长刻蚀时间，缓慢刻蚀填充层207，使得刻蚀工艺中使用的等离子体能充分反应且不滞留于膜层的表面。同时利用氮等离子体缓慢垂直往下轰击，且填充层和碳基聚合物因为硬度相比侧墙材料较小，使得填充层和碳基聚合物同时往下刻蚀，从而在保证在刻蚀填充层的同时，碳基聚合物也能同时被去除。以本实施例中填充层207为例，在执行步骤S107中，利用第二刻蚀工艺去除第二预设厚度的填充层并显露出部分的侧墙的过程中，可去除至少部分填充层边界处的碳基聚合物，以利于在后续膜层的制程工艺中确保形成的膜层的质量。
其中，所述碳基聚合物包括在膜层表面残留有含碳聚合物(C Polymer)以及在膜层与侧墙的交界处残留有硬碳微粒(Hard C)，因此，去除至少部分填充层边界处和/或所述填充层与所述侧墙交界处的碳基聚合物，可包括：去除或部分去除填充层边界处的含碳聚合物(C Polymer)，去除或部分去除在填充层与侧墙的交界处残留有硬碳微粒(Hard C)，可参看图7所示的结构变化示意图。
接着，半导体设备执行步骤S109，在填充层和侧墙上进行图案化处理。
通过执行步骤S107之后，可去除或部分去除填充层边界处和/或所述填充层与所述侧墙交界处的碳基聚合物，即，去除或部分去除填充层边界处的含碳聚合物(C Polymer)，去除或部分去除在填充层与侧墙的交界处残留有硬碳微粒(Hard C)，如此，可在填充层和侧墙上进行后续的图案化处理。
针对步骤S109，执行后续图案化处理有不同的实现方式。
在本申请一些实施例中，半导体设备在步骤S109之后，在填充层和侧墙上形成隔离层，其中，所述隔离层包括氮化硅层或氮氧化硅层。因此，上述步骤即包括：在填充层207和侧墙205的表面形成隔离层209，形成如图8所示的结构。
接着，在隔离层209表面形成掩膜层211和光刻胶层，并执行刻蚀工艺，形成如图9所示的结构。
在本申请一些实施例中，半导体设备形成图9所示的结构的步骤可包括： 先在隔离层209表面形成掩膜层211，例如，采用化学气相沉积工艺于隔离层209的表面形成掩膜层211，所述掩膜层的材料可以包括但不仅限于氮氧化硅(SiON)、多晶硅(Poly)、非晶形碳层(Amorphous Carbon Layer，ACL)、氧化物(Oxide)等；接着，在掩膜层211的表面形成图案化的光刻胶层，例如，于所述掩膜层211上旋涂光刻胶，并通过掩膜版对所述光刻胶进行图形化，形成图案化的光刻胶层；接着，利用所述图形化的光刻胶层对掩膜层211进行刻蚀，以形成位于隔离层209上的多个掩膜结构，相邻两个所述掩膜结构之间具有开口，所述开口暴露出所述隔离层209的部分区域。在其它实施例中也可以在所述隔离层209表面通过SADP工艺形成所述掩膜结构。所述多个掩膜结构构成所述图案层。
之后，半导体设备继续后续工艺，以所述掩膜结构和所述侧墙作为刻蚀阻挡层刻蚀填充层207及掩膜层202形成第一图案，继续将所述第一图案转移至基底，进而获得目标图案。在以所述掩膜结构刻蚀隔离层时，若所述隔离层由于碳基聚合物导致出现鼓包或所述隔离层表面不平坦，则将图层往下转移时，会导致有鼓包的位置或表面高的位置难以往下刻蚀，最终导致获得的目标图案中出现CD不均匀的现象，影响产品良率。通过去除碳基聚合物及获得平整的隔离层表面，能得到CD均匀的目标图案，从而提高产品的良率。
在本申请一些实施例中，在步骤S109之后，在填充层和侧墙上形成隔离层，其中，所述隔离层包括氧化物层。
以隔离层包括氧化物层为例，其形成工艺更可包括：
首先，半导体设备在填充层207和侧墙205上形成第一隔离层210，形成如图10所示的结构。其中，所述第一隔离层可通过化学气相沉积工艺(CVD)或者旋涂式电介质工艺(SOD)形成，所述第一隔离层的厚度为35nm至45nm，例如为40nm。
接着，半导体设备在第一隔离层210上形成第二隔离层212，形成如图11所示的结构。其中，所述第二隔离层可通过旋涂式电介质工艺(SOD)形成，所述第二隔离层的厚度为25nm至35nm，例如为30nm。
可以理解的是，基于SOD工艺，即，通过在第一隔离层210表面旋转涂 覆介质层的形成工艺，有利于形成的膜层的平坦化，可有效降低膜层的粗糙度。
其中，在该步骤中，还包括对形成的第二隔离层212进行退火热处理(Anneal)，利用所述退火热处理，可改善通过旋涂式电介质工艺(SOD)所形成的第二隔离层212的粗糙度并致密化第二隔离层212。在一些实施例中，退火热处理工艺是在约400℃至约1100℃的范围内的高温下实施，其可以是使用包括水蒸汽、O2和H2的气体的湿退火工艺或使用包括N2和O2气的气体的干退火工艺。
最后，半导体设备对第二隔离层和第一隔离层进行研磨以形成隔离层214，形成如图12所示的结构。在该步骤中，主要是对前述步骤中通过旋涂式电介质工艺(SOD)所形成的第二隔离层212进行研磨，研磨去除部分的第二隔离层后，剩余的第二隔离层和第一隔离层就构成隔离层214，所述隔离层的厚度为40nm至50nm。
在本申请一些实施例中，所述研磨去除部分的第二隔离层可采用化学机械研磨(Chemical Mechanical Polishing，CMP)工艺，可以在保证材料去除效率的同时，获得较完美的表面，可以实现纳米级到原子级的表面粗糙度，提高隔离层214的平整度。
半导体设备在形成如图12所示的隔离层214之后，即可继续如下工艺，在隔离层214表面形成掩膜层215并执行刻蚀工艺，形成如图13所示的结构。
在本申请一些实施例中，半导体设备形成图13所示的结构的步骤可包括：先在隔离层214表面形成掩膜层215，例如，采用化学气相沉积工艺于隔离层214的表面形成掩膜层215，所述掩膜层的材料可以包括但不仅限于氮氧化硅(SiON)、多晶硅(Poly)、非晶形碳层(Amorphous Carbon Layer，ACL)、氧化物(Oxide)等；接着，在掩膜层215的表面形成图案化的光刻胶层，例如，于所述掩膜层215上旋涂光刻胶，并通过掩膜版对所述光刻胶进行图形化，形成图案化的光刻胶层；接着，利用所述图形化的光刻胶层对掩膜层215进行刻蚀，以形成位于隔离层214上的多个掩膜结构，相邻两个所述掩膜结构之间具有开口，所述开口暴露出所述隔离层214的部分区域。在其它实施 例中也可以在所述隔离层209表面通过SADP工艺形成所述掩膜结构。所述多个掩膜结构构成所述图案层。
之后，半导体设备继续后续工艺，以所述掩膜结构和所述侧墙作为刻蚀阻挡层刻蚀填充层207及掩膜层202形成第一图案，继续将所述第一图案转移至基底，进而获得目标图案。在以所述掩膜结构刻蚀隔离层时，若所述隔离层由于碳基聚合物导致出现鼓包或所述隔离层表面不平坦，则将图层往下转移时，会导致有鼓包的位置或表面高的位置难以往下刻蚀，最终导致获得的目标图案中出现CD不均匀的现象，影响产品良率。通过去除碳基聚合物及获得平整的隔离层表面，能得到CD均匀的目标图案，从而提高产品的良率。在一实施例中，所述目标图案可以是电容孔，在其他实施例中，所述目标图案也可以为其它结构图案。
本申请公开的半导体结构的制作方法，包括：提供初始结构；在初始结构上形成覆盖所述侧墙的填充层；先通过第一刻蚀工艺以较快的第一刻蚀速率去除第一预设厚度的填充层，再通过第二刻蚀工艺以较慢的第二刻蚀速率去除第二预设厚度的填充层并显露出部分的侧墙；在填充层和侧墙上进行图案化处理。本申请半导体结构的制作方法，通过采用独特的两步刻蚀工艺，可去除至少部分填充层边界处和/或所述填充层与所述侧墙交界处的碳基聚合物，以利于后续制程工艺的稳定性，提高产品的质量。
上述实施例仅例示性说明本申请的原理及其功效，而非用于限制本申请。任何熟悉此技术的人士皆可在不违背本申请的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本申请所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本申请的权利要求所涵盖。
工业实用性
本申请实施例提供了一种半导体结构的制作方法，该方法包括：提供初始结构；在初始结构上形成覆盖所述侧墙的填充层；先通过第一刻蚀工艺以较快的第一刻蚀速率去除第一预设厚度的填充层，再通过第二刻蚀工艺以较 慢的第二刻蚀速率去除第二预设厚度的填充层并显露出部分的侧墙；在填充层和侧墙上进行图案化处理。通过上述方法，可以去除至少部分填充层边界处和/或所述填充层与所述侧墙交界处的碳基聚合物，以利于后续制程工艺的稳定性，提高产品的质量。

Claims (10)

  1. 一种半导体结构的制作方法，包括以下步骤：
    提供初始结构，所述初始结构包括基底、形成于所述基底上的掩膜层、以及形成于所述掩膜层上的侧墙；
    在所述初始结构上形成覆盖所述侧墙的填充层；
    通过第一刻蚀工艺去除第一预设厚度的填充层，经第一刻蚀工艺后剩下的填充层覆盖着所述侧墙；在所述第一刻蚀工艺中，采用第一刻蚀速率；
    通过第二刻蚀工艺去除第二预设厚度的填充层并显露出部分的侧墙，以去除至少部分填充层边界处和/或所述填充层与所述侧墙交界处的碳基聚合物；在所述第二刻蚀工艺中，采用第二刻蚀速率，且，所述第二刻蚀速率小于第一刻蚀速率；以及
    在所述填充层和所述侧墙上进行图案化处理。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，所述第一刻蚀工艺的参数包括：
    刻蚀气体包括氧气，氧气的流量为12sccm至18sccm，刻蚀速率为0.5nm/s至5nm/s。
  3. 根据权利要求1或2所述的半导体结构的制作方法，其中，所述第二刻蚀工艺的参数包括：
    刻蚀气体包括氮气，氮气的流量为18sccm至22sccm，刻蚀速率为0.1nm/s至0.5nm/s。
  4. 根据权利要求1所述的半导体结构的制作方法，其中，所述第二刻蚀工艺后的填充层与所述侧墙的顶部之间的高度差为1nm至3nm。
  5. 根据权利要求1所述的半导体结构的制作方法，其中，所述在所述填充层和所述侧墙上进行图案化处理包括：
    在所述填充层和所述侧墙上形成隔离层；以及
    在所述隔离层上形成掩膜结构。
  6. 根据权利要求5所述的半导体结构的制作方法，其中，所述隔离层包括氮氧化硅层、多晶硅层、非晶形碳层、或氧化物层。
  7. 根据权利要求5所述的半导体结构的制作方法，其中，所述在所述填充层和所述侧墙上形成隔离层包括：
    在所述填充层和所述侧墙上形成第一隔离层；
    采用旋转涂布工艺，在所述第一隔离层上形成第二隔离层；以及
    对所述第二隔离层和所述第一隔离层进行研磨以形成隔离层。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，所述第一隔离层的厚度为35nm至45nm，所述第二隔离层的厚度为25nm至35nm，所述隔离层的厚度为40nm至50nm。
  9. 根据权利要求7所述的半导体结构的制作方法，其中，在对所述第二隔离层和所述第一隔离层进行研磨之前还包括对所述第二隔离层进行退火热处理。
  10. 根据权利要求5所述的半导体结构的制作方法，其中，在对所述填充层和所述侧墙上进行图案化处理后，还包括：
    以所述掩膜结构和所述侧墙作为刻蚀阻挡层刻蚀所述掩膜层形成第一图案，继续将所述第一图案转移至基底，获得目标图案。
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