WO2022057333A1 - 存储器装置及其测试方法和使用方法、存储器系统 - Google Patents

存储器装置及其测试方法和使用方法、存储器系统 Download PDF

Info

Publication number
WO2022057333A1
WO2022057333A1 PCT/CN2021/099238 CN2021099238W WO2022057333A1 WO 2022057333 A1 WO2022057333 A1 WO 2022057333A1 CN 2021099238 W CN2021099238 W CN 2021099238W WO 2022057333 A1 WO2022057333 A1 WO 2022057333A1
Authority
WO
WIPO (PCT)
Prior art keywords
cell array
channel
memory
normal
address
Prior art date
Application number
PCT/CN2021/099238
Other languages
English (en)
French (fr)
Inventor
寗树梁
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21868167.4A priority Critical patent/EP4036917B1/en
Priority to US17/446,143 priority patent/US11854640B2/en
Publication of WO2022057333A1 publication Critical patent/WO2022057333A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a memory device, a memory system, a method for testing the memory device, and a method for using the memory device.
  • Volatile memory is widely used in various electronic devices because of its fast read and write speed. As the integration level increases, a volatile memory chip includes more and more normal memory cells. If one of the normal memory cells is unavailable, or even the entire row or column of normal memory cells cannot be used, the entire chip may become unusable. Chips are unavailable, severely reducing the yield of chips.
  • a spare storage unit other than the normal storage unit is usually set in the volatile memory chip to replace the above-mentioned unusable normal storage unit, that is, the normal storage unit means that the test will be preferentially used for data when the test is successful.
  • the read-write storage unit, the spare storage unit refers to the normal storage unit that is used to replace the unavailable normal storage unit when one or some storage units are unavailable.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a memory device, a memory system, a method for testing a memory device, and a method for using the memory device, which can overcome the above-mentioned related art that meets the high-bandwidth requirements, including multiple In the memory device of the channel, how to perform redundant replacement more efficiently.
  • a memory device comprising: a plurality of channels, each channel comprising an array of memory cells, the array of memory cells comprising an array of normal cells, the array of normal cells comprising normal memory cells , the normal storage unit is a volatile memory unit; the test control circuit is used to respond to the test instruction, control and test the normal cell arrays in the multiple channels, and determine that the test fails in the normal cell arrays in the multiple channels
  • the access address of the normal storage unit is the failure address;
  • the non-volatile memory cell array which includes a plurality of non-volatile memory cells, is used for receiving and storing the failure address from the test control circuit.
  • a memory system including: at least one storage layer; and a memory controller configured to control the at least one storage layer.
  • each layer of storage layer includes: a plurality of channels, each channel includes a memory cell array, the memory cell array includes a normal cell array, the normal cell array includes a plurality of normal storage cells, and the normal storage cells are volatile
  • the test control circuit is used for responding to the test instruction, controlling and testing the normal cell arrays in the multiple channels, and determining the access addresses of the normal memory cells that fail the test in the normal cell arrays in the multiple channels as failures address; an array of non-volatile memory cells including a plurality of non-volatile memory cells for receiving and storing the failed address from the test control circuit.
  • the testing method includes: receiving a test instruction; controlling and testing the normal cell arrays in the multiple channels according to the test instruction, and determining the access of the normal memory cells that fail the test in the normal cell arrays in the multiple channels
  • the address is the fail address; the fail address is sent and stored to the array of non-volatile memory cells.
  • a method of using a memory device including a plurality of channels and an array of non-volatile memory cells, each channel including an array of memory cells and a latch block, the array of memory cells including a normal cell array, the normal cell array including normal memory cells, the normal memory cells being volatile memory cells, the non-volatile memory cell array including a plurality of non-volatile memory cells, the non-volatile memory cells A failure address representing an access address of a normal memory cell that fails the test in the normal cell array in the plurality of channels is stored in the volatile memory cell array.
  • the using method includes: when the memory device is powered on, dumping the failed address in the non-volatile memory cell array to a latch block of a corresponding channel.
  • Some embodiments of the present disclosure provide a memory device, a memory system, a method for testing a memory device, and a method for using the memory device.
  • the memory device including multiple channels share the same non-volatile memory cell array, the Satisfying the high bandwidth requirement; on the other hand, by using the non-volatile memory cells in the non-volatile memory cell array to store the access addresses of the unusable normal memory cells in the normal cell array in the plurality of channels that have failed the test
  • the corresponding failure address can still know which or which normal memory cells of the memory cell array in the multiple channels are unavailable after the memory cell array in the multiple channels is powered off. After power-on, there is no need to re-test, which saves test time and cost, improves test efficiency, and at the same time maintains the high-speed read and write performance of the volatile memory cells used in the memory cell array in each channel.
  • FIG. 1 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 2 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 3 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 4 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 5 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 6 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • Figure 7 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • Figure 8 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • FIG. 9 schematically shows a schematic diagram of each interface of a scan host and a latch block of each channel according to an embodiment of the present disclosure.
  • FIG. 10 schematically shows the timing diagram of each signal in FIG. 9 .
  • Figure 11 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • FIG. 12 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 13 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 14 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 15 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 16 schematically shows a schematic diagram of a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • FIG. 17 schematically shows a schematic diagram of a 2.5-dimensional integrated circuit according to an embodiment of the present disclosure.
  • FIG. 18 schematically shows a schematic diagram of a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • FIG. 19 schematically shows a schematic diagram of a memory layer in a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • FIG. 20 schematically shows a schematic diagram of a memory layer in a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • FIG. 21 schematically shows a flowchart of a method for testing a memory device according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • FIG. 1 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • a memory device 100 provided by an embodiment of the present disclosure may include multiple channels, a test control circuit, and a non-volatile memory cell array.
  • the memory device 100 includes channel 1 and channel 2 as an example for illustration, but the present disclosure does not limit the number of channels, as long as it is greater than or equal to 2.
  • Each channel may include an array of memory cells, each array of memory cells may include an array of normal cells, each array of normal cells may include normal memory cells, and each normal memory cell may be a volatile memory cell.
  • the volatile memory unit refers to a memory unit in which data stored therein will be lost after a power failure.
  • channel 1 may include memory cell array 1
  • memory cell array 1 may include normal cell array 1
  • normal cell array 1 may include normal memory cells 1 to 12
  • channel 2 may include memory cell array 2
  • memory cell array 2 may include normal cell array 2
  • normal cell array 2 may also include normal memory cell 1 to normal memory cell 12 .
  • each normal cell array shown in FIG. 1 includes 12 normal memory cells only for illustration, and in fact, the number of normal memory cells included in each normal cell array can be designed according to actual requirements. , which is not limited in the present disclosure.
  • These normal cell arrays may be composed of a plurality of memory blocks (Banks), and normal memory cells in the normal cell arrays may be connected to different word lines and bit lines.
  • the test control circuit may be configured to respond to the test command, control the normal cell arrays in the plurality of channels to test the memory device 100, and determine the normal storage failures in the test in the normal cell arrays in the plurality of channels.
  • the access address of the unit is the failure address.
  • each failure address in the embodiment of the present disclosure may be one or any combination of a row address, a column address, a memory block (Bank) address, etc. of a single normal memory cell.
  • the present disclosure does not limit this, and the meaning referred to by a failure address can be determined as required.
  • the non-volatile memory cell array may include a plurality of non-volatile memory cells.
  • the non-volatile memory unit refers to the memory unit in which the data stored therein will not be lost in the event of a power failure.
  • An array of non-volatile memory cells may be used to receive and store the fail address from the test control circuit.
  • non-volatile memory cells 1 to 5 are included in the non-volatile memory cell array, but the number of non-volatile memory cells here is only for illustration, and in fact non-volatile memory cells
  • the non-volatile memory cells included in the cell array can be designed according to actual requirements, which is not limited in the present disclosure.
  • the non-volatile memory cells may be implemented in any of various forms.
  • fuse fuse
  • electric fuse efuse
  • anti-fuse anti-fuse
  • magnetic memory Magnetic Random Access Memory, MRAM
  • iron memory Feroelectric RAM, FeRAM
  • flash memory Flash etc. to implement non-volatile memory cells.
  • the memory device provided by the present disclosure in a real-time manner can meet the high bandwidth requirement by allowing the memory device including multiple channels to share the same non-volatile memory cell array; on the other hand, by using the non-volatile memory cell
  • the non-volatile memory cells in the array are used to store the failure addresses corresponding to the access addresses of the unusable normal memory cells that have failed the test in the normal cell arrays in the plurality of channels, and the memory cell arrays in the plurality of channels can be After the power is turned off, it is still possible to know which or which normal memory cells in the memory cell array in the multiple channels are unavailable.
  • FIG. 2 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the difference between the memory device 200 provided in the embodiment of FIG. 2 and the memory device 100 provided by the above-mentioned embodiment of FIG. 1 is that the non-volatile memory cell array may include an anti-fuse array, and the corresponding non-volatile memory cells may be Antifuse unit.
  • anti-fuse unit 1 in FIG. 2 may correspond to non-volatile memory unit 1 in FIG. 1
  • anti-fuse unit 2 may correspond to non-volatile memory unit 2 in FIG. 1
  • anti-fuse unit 3 may Corresponding to the non-volatile memory unit 3 in FIG. 1
  • the anti-fuse unit 4 may correspond to the non-volatile memory unit 4 in FIG. 1
  • the anti-fuse unit 5 may correspond to the non-volatile memory unit 5 in FIG. 1 .
  • the non-volatile memory cell array is taken as an example of an anti-fuse array for illustration, but the present disclosure is not limited to this, the non-volatile memory in the non-volatile memory cell array
  • the unit can also be implemented by using any other unit with a non-volatile storage function.
  • FIG. 3 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the anti-fuse array may further include a control block (Control Block).
  • the control block may be used to control the programming of the anti-fuse array, and store the failure address received from the test control circuit in the anti-fuse unit in the anti-fuse array.
  • an anti-fuse array is used as a non-volatile memory cell array, and the anti-fuse cells in the anti-fuse array are used as non-volatile memory cells for storing in a normal cell array. Because the anti-fuse unit is small, it occupies a small chip area, is easy to implement, can resist radiation and interference, and is not affected by electromagnetic radiation.
  • FIG. 4 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the difference between the memory device 400 provided by the embodiment of FIG. 4 and the memory device 300 provided by the above-mentioned embodiment of FIG. 3 is that each channel may further include a latch block.
  • channel 1 may further include latch block 1
  • channel 2 may further include latch block 2 .
  • the anti-fuse array may further include a scan host (Scan Host).
  • the scan host may be configured to dump the failed address stored in the antifuse array to the latch block of the corresponding channel when the memory device 400 is powered on.
  • the failed addresses stored in the antifuse array may be dumped into latch block 1 of channel 1 and/or latch block 2 of channel 2 .
  • each normal memory cell in the normal cell array in the memory cell array of each channel is a volatile memory cell.
  • these failed addresses need to be stored in a non-volatile memory cell array using non-volatile memory cells, such as an anti-fuse array.
  • non-volatile memory cells such as an anti-fuse array.
  • the read failure address in the nonvolatile memory cell array is used, since the read data speed of the nonvolatile memory cell is slower than that of the volatile memory cell, the required failure address cannot be obtained in time.
  • the failed address stored in the non-volatile memory cell array is dumped into the latch block of the corresponding channel, so that the memory device can be read and written. Unusable normal storage units are quickly replaced or not used in the process.
  • FIG. 5 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • each latch block may include a first number of latches
  • each memory cell array may further include a spare Cell arrays
  • each spare cell array may include the first number of spare storage units
  • each spare storage unit is a volatile memory unit.
  • the latch block can also be replaced by a register block, that is, the function of the latch is implemented by using the registers in the register block.
  • each spare storage unit in the embodiment of the present disclosure may include a volatile memory unit (corresponding to the failure address being the access address of a single normal storage unit), or may include a row of volatile memory units on a word line volatile memory cell (corresponding to the failure address is the row address), or a column of volatile memory cells on a bit line (corresponding to the failure address is the column address), or a memory block of volatile memory cells (corresponding to the failure address is the memory block address), etc.
  • a volatile memory unit corresponding to the failure address being the access address of a single normal storage unit
  • a row of volatile memory units on a word line volatile memory cell corresponding to the failure address is the row address
  • a column of volatile memory cells on a bit line corresponding to the failure address is the column address
  • a memory block of volatile memory cells corresponding to the failure address is the memory block address
  • the latch block 1 may include four latches, such as latch 1 to latch 4 . It should be noted that a latch in this embodiment represents a latch capable of storing a failed address.
  • the memory cell array 2 in the channel 2 may include a normal cell array 2 and a spare cell array 2
  • the spare cell array 2 may include four spare memory cells, such as spare memory cells 1 to 4
  • the latch block 2 may include four latches, such as latch 1 to latch 4 .
  • each latch in the latch block in each channel may be set in a one-to-one correspondence with each spare memory cell in the spare cell array in the corresponding channel.
  • the latch 1 in the latch block 1 in the channel 1 corresponds to the spare memory cell 1 in the spare cell array 1 in the channel 1
  • the lock in the latch block 1 in the channel 1 corresponds to
  • the register 2 corresponds to the spare storage unit 2 in the spare cell array 1 in the channel 1
  • the latch 3 in the latch block 1 in the channel 1 corresponds to the spare storage unit 3 in the spare cell array 1 in the channel 1
  • the latch 4 in the latch block 1 in the channel 1 corresponds to the spare storage unit 4 in the spare cell array 1 in the channel 1 .
  • the latch 1 in the latch block 2 in the channel 2 corresponds to the spare memory cell 1 in the spare cell array 2 in the channel 2
  • the latch 2 in the latch block 2 in the channel 2 corresponds to the
  • the spare storage unit 2 in the spare cell array 2 corresponds to the latch 3 in the latch block 2 in the channel 2 corresponding to the spare storage unit 3 in the spare cell array 2 in the channel 2
  • the latch block in the channel 2 corresponds to Latches 4 in 2 correspond to spare memory cells 4 in spare cell array 2 in channel 2.
  • the scan host in the anti-fuse array may be configured to dump the failed address in the anti-fuse array to the corresponding latch in the latch block of the corresponding channel when the memory device 500 is powered on to determine the access address of the target spare storage unit for replacing the failed address as the repair address.
  • the memory cell array 1 in the channel 1 will be The access address of the normal memory cells 1 to 4 in the first row of the normal cell array 1 is stored as a fail address to the anti-fuse cell 1 in the anti-fuse array. Then when the memory device 500 is powered on, the scan host can transfer the failed addresses of the normal memory cells 1 to 4 in the first row of the normal memory cells 1 to 4 in the memory cell array 1 in the channel 1 stored in the anti-fuse unit 1.
  • the access address of the spare memory cell 1 in the spare cell array 1 serves as a repair address to replace the failed addresses of the normal memory cells 1 to 4 of the first row of the normal cell array 1 in the memory cell array 1 in the channel 1 .
  • the normal storage unit represents a single storage unit
  • the spare storage unit represents multiple storage units, which is not limited in this embodiment, and the above description is only for illustrating this embodiment.
  • the memory cell in the channel 1 The access address of the normal memory cell 1, normal memory cell 5 and normal memory cell 9 in the first column of the normal cell array 1 in the cell array 1 is used as a failure address, and is stored in the anti-fuse cell in the anti-fuse array. 2.
  • the scan host can transfer the normal memory cell 1, normal memory cell 5 and normal memory cell 5 of the first column of the normal cell array 1 in the memory cell array 1 stored in the anti-fuse unit 2 to If the failed address of the normal storage unit 9 is transferred to the latch 2 in the latch block 1 of the channel 1, it can be determined to use the spare storage unit in the spare cell array 1 corresponding to the latch 2 in the latch block 1 2 As the target spare storage unit, use the access address of the spare storage unit 2 in the spare cell array 1 as the normal storage unit 1 and the normal storage unit in the first column of the normal cell array 1 in the memory cell array 1 in the replacement channel 1. 5 and the repair address of the failed address of normal memory cell 9.
  • each normal cell array may include a second number of normal memory cells, which may be greater than or equal to the first number.
  • the normal cell array 1 in the channel 1 is assumed to include 12 (that is, the second number is assumed to be 12, but the present disclosure is not limited to this) normal memory cells, and the spare cell array 1 in the channel 1 includes 4
  • a number of spare storage units, that is, the number of spare storage units in the same channel is generally set to be smaller than the number of normal storage units.
  • each latch in the latch block in each channel is set in a one-to-one correspondence with each spare storage unit in the spare cell array in the corresponding channel, and each spare storage unit is not strictly required.
  • the spare storage unit 1 in the spare unit array 1 can also be set.
  • latch 2 in latch block 1 corresponds to latch 2 in latch block 1.
  • the non-volatile memory unit needs to remember which normal memory cells are unavailable, and specify which spare memory cells to replace.
  • These spare memory cells designated for replacement are called target spares.
  • the access address of the target spare storage unit is called the repair address.
  • the embodiment of the present disclosure sets the latch in the latch block of each channel and the spare cell of the corresponding channel by setting the latch in the latch block of each channel
  • the spare storage units in the array are in one-to-one correspondence, so that when the failed address is stored to which latch is determined, it can be determined which spare storage unit is used as the target spare storage unit to replace the normal storage unit corresponding to the failed address, thereby reducing the storage capacity of the latch block.
  • the failed address and its repair address stored in the non-volatile memory cell array can also be transferred to the latches in the latch block of the corresponding channel at the same time.
  • the number of latches will be more than the number of spare storage units in the corresponding channel.
  • FIG. 6 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the read-write circuit may be configured to receive the test command from the test control circuit, and respond to the test command to write the first write data into the target normal storage unit in the memory cell array of the corresponding channel, and compare the The first read data and the first write data read by the target normal storage unit output an indication signal indicating that the target normal storage unit has passed or failed the test based on the comparison result.
  • the read-write control circuit can be used to control the read-write circuit, and when the indication signal indicates that the target normal storage unit fails to test, the access address of the target normal storage unit is used as the failure address, and the A failed address is returned to the test control circuit.
  • the channel 1 may further include a read-write circuit 1 and a read-write control circuit 1 .
  • Channel 2 may also include a read-write circuit 2 and a read-write control circuit 2 .
  • the read-write circuit 1 can receive the test command from the test control circuit, and in response to the received test command, write the first write data into the target normal memory cell in the memory cell array 1 of the channel 1, for example, it is assumed to write in rows , it is assumed that the first write data is first written into the normal memory cells 1 to 4 of the normal cell array 1, and then the first read data is read row by row from the normal memory cells 1 to 4 of the normal cell array 1. If the write data is consistent with the corresponding first read data, it means that the corresponding normal memory cell test passes; if the first write data and the corresponding first read data are inconsistent, it means that the corresponding normal memory cell test fails. By performing the test row by row in sequence, an indication signal of the test pass or test failure of the normal memory cells in each row of the entire normal cell array 1 can be obtained. The access address of the normal memory cell that fails the test is returned to the test control circuit as the failure address.
  • the read-write control circuit may be further configured to control the read-write circuit to write the second write data to be written to the target normal memory cell specified by the failed address by the target spare storage unit specified by the repair address.
  • the normal memory cells in the memory cell array of each channel are tested before the memory device leaves the factory to compare whether the read and write data are consistent, so as to obtain the failure address of the unusable normal memory cell, and then The failed address is stored in the non-volatile memory cell array, so that when subsequent read and write operations are performed on normal storage cells in the memory device, the target spare storage cell represented by the repair address corresponding to the failed address can be used to replace Drop the corresponding unusable normal storage unit to read and write data.
  • FIG. 7 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • each memory cell array may include a plurality of memory blocks.
  • channel 1 is taken as an example, and the memory cell array 1 in channel 1 includes two memory blocks (ie, memory block 1 and memory block 2) as an example for illustration, but in fact, each memory
  • the number of storage blocks included in the cell array can be set according to actual application scenarios, which is not limited in the present disclosure.
  • the memory block 1 includes a normal cell array 11
  • the normal cell array 11 is assumed to include normal memory cells 11 to 18
  • the normal cell array 12 is included in the memory block 2
  • the normal cell array 12 is assumed to include the normal memory cells 21 to 28.
  • the normal cell array 1 in the above embodiment may include the normal cell array 11 and the normal cell array 12 in the embodiment of the present disclosure.
  • the plurality of memory blocks in each channel may share the spare cell array and latch block of the corresponding channel
  • the spare cell array of the corresponding channel may include a first number (assuming equal to 4 in FIG. 7 ) of Spare memory cells (eg, spare memory cells 11, 12, 21, and 22 in FIG. 7)
  • each spare memory cell is a volatile memory cell
  • the latch block of each channel may include the first number of latches (eg, latches 11, 12, 21, and 22 in FIG. 7).
  • the spare cell array 1 in the memory cell array 1 in the channel 1 is assumed to include the spare cell array 11 provided in the memory block 1 and the spare cell array 12 provided in the memory block 2, and the latch block 1 Assume that the latch block 11 provided in the memory block 1 and the latch block 12 provided in the memory block 2 are included. It is assumed that the spare cell array 11 in the storage block 1 includes the spare storage unit 11 and the spare storage unit 12 , and the spare cell array 12 in the storage block 2 includes the spare storage unit 21 and the spare storage unit 22 . It is assumed that latch block 11 in memory block 1 includes latch 11 and latch 12 , and latch block 12 in memory block 2 includes latch 21 and latch 22 .
  • spare cell arrays and the latch blocks in the embodiment of FIG. 7 can be distributed in each storage block, during deployment, multiple storage blocks in the same channel can share all the spare cell arrays and latch blocks in the channel .
  • the spare storage unit 11 may also be set to correspond to the latch 11, the spare storage unit 12 to correspond to the latch 12, the spare storage unit 21 to correspond to the latch 21, and the spare storage unit 22 to correspond to the latch device 22 corresponds.
  • Figure 8 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • the spare cell array and the latch block may not be combined.
  • the latch blocks are distributed in each memory block, and the spare cell array and the latch block of the corresponding channel can be collectively provided outside the plurality of memory blocks.
  • memory block 1 includes normal cell array 11
  • normal cell array 11 is assumed to include normal memory cells 11 to 18
  • memory block 2 includes normal cell array 12
  • normal cell array 12 includes normal memory cells 22 to 28 .
  • a spare cell array 1 is centrally arranged in the memory cell array 1 of the channel 1, and the spare cell array 1 includes spare memory cells 1 to 4.
  • a latch block 1 including latches 1 to 4 is collectively provided in the memory cell array 1 of the channel 1 outside the memory block 1 and the memory block 2 .
  • the spare storage units 1 to 4 may also be set in a one-to-one correspondence with the latches 1 to 4 respectively.
  • a normal storage unit in each channel is divided into a plurality of storage blocks, regardless of whether the latches and spare storage units in each channel are distributed and provided in each storage block , or centrally set in the corresponding channel, by sharing the latch in the latch block in each channel and the spare storage unit in the spare cell array, it can solve the problem in some storage blocks in some cases.
  • the purpose of equalization can be achieved by uniformly scheduling the latches and spare storage units in each channel.
  • FIG. 9 schematically shows a schematic diagram of each interface of a scan host and a latch block of each channel according to an embodiment of the present disclosure.
  • FIG. 10 schematically shows the timing diagram of each signal in FIG. 9 . It can be known from the above embodiments that the non-volatile memory cell array may further include a scan host.
  • the latch block of each channel and the scan host may include a first interface, a second interface, and a third interface.
  • the first interface of the latch block of each channel and the first interface of the scan host can be used to receive the enable signal Se;
  • the second interface of the latch block of each channel and the scan host's first interface can be used to receive the enable signal Se;
  • the second interface may be used to receive the clock signal SC.
  • the third interface of the scan host can be used for the enable signal received at the first interface of the scan host to be a first level (for example, a high level in FIG. 10 , but the present disclosure is not limited to this, it also When the first level can be set as a low level), according to the clock signal SC received by the second interface of the scanning host, the latch block of each channel, such as the latch block 1 of channel 1 and the latch block of channel 2, is sequentially sent to the The third interface from latch block 2 to latch block n of channel n (n is a positive integer greater than or equal to 2) sends the channel address, storage block address and latch block address (transmitted sequentially through the Si signal in Figure 10) , so as to determine the target channel, the target memory block of the target channel and the target latch in the target latch block corresponding to the target channel from the plurality of channels.
  • a first level for example, a high level in FIG. 10 , but the present disclosure is not limited to this, it also When the first level can be set as a low level
  • the third interface of the scanning host After the third interface of the scanning host sends the above-mentioned channel address, storage block address and latch block address to each latch block of each channel through the Si signal, it can then send a command (R/W), for example, if it is a high level , the command is a read command, that is, the data frame is read from the target channel; if it is low, the command is a write command, that is, the data frame is written to the target channel. For example, here is the target of writing the failed address to the target channel. in the latches of the latch block.
  • the third interface of the scanning host first sends a write command to the third interface of each latch block of each channel. After receiving the write command, the third interface of the target latch block of the target channel will send the write command to the scanning host.
  • the third interface of the scanning host returns a response signal (ACK). After the third interface of the scanning host receives the response signal, it can continue to send data to the third interface of each latch block of each channel through the third interface of the scanning host. frame, the failed address is carried in the data frame, so that the failed address is transferred to the target latch.
  • the memory device provided by the embodiment of the present disclosure can correctly transfer the failed address from the non-volatile memory unit to the latch through the above-mentioned first to third interfaces and their corresponding enable signals, clock signals and Si signals In the device, so as to be able to achieve fast reading and writing of the normal cell array of each channel.
  • the latch block of each channel and the scan host further include a fourth interface.
  • the third interface of the scanning host sends a read command to the third interface of the latch block of each channel
  • data is read from the target latch through the fourth interface of the scanning host (through So signal) to compare the written failed address with the read data to verify whether the written failed address is correctly written.
  • the failed address can be correctly transferred from the non-volatile memory unit. into the latches to enable fast reads and writes of the normal cell array for each channel.
  • the failed address dumped into the target latch can also be read out through the fourth interface to verify whether the written failed address is correct, so as to ensure correct reading and writing of the normal cell array of each channel.
  • each latch in each channel and each spare storage unit in the corresponding channel may be mapped one by one in advance. For example, if there are 100 spare storage units in a channel, you can set or use 100 One latch corresponds to one spare storage unit. Assuming that the failed address is stored in the fifth latch, the access address of the fifth spare storage unit can be used as the repair address of the failed address, so that There is no need to use latches to store both a failed address and its repair address.
  • the sending sequence of the channel address, the storage block address and the latched block address can be changed.
  • the scanning host can send the latched block address first, and when a channel monitors the latched block address and its internal When the latch blocks are consistent and the internal latch blocks are available, a response signal can be returned to the scan host. In this way, the scan host can determine in advance whether the target latch block of the target channel is available, so that it can quickly know whether the target channel is available. Continue to send the failed address to this target channel.
  • the scanning host when the start of the write operation of the failed address is enabled by the enable signal, can determine which target channel to write the failed address to by sending the channel address. After the target channel receives the channel address, it can also Reply a response signal to the scanning host to inform the scanning host that it has normally monitored the channel address, so that the scanning host can continue to send the relevant data of the failed address to the target channel; the scanning host then sends the memory block address to inform the current failed address to be stored. Corresponds to the normal storage unit in which target storage block in the target channel, and then sends the latch block address to tell which target latch in the target latch block of the target channel to store the failed address, so as to determine how Dump the failed address into the corresponding latch of the corresponding channel.
  • the fourth interface of the target latch block corresponding to the target channel may be configured to send a response signal to the fourth interface of the scan host after receiving the latch block address, for notifying The scanning host has received the latched block address.
  • the fourth interface of the other latch blocks of the non-target latch block corresponding to the other channels of the non-target channel compares it with its own latch block address, and if it is found inconsistent, it will not send the The fourth interface of the scanning host sends a response signal.
  • Figure 11 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • each channel may further include a read/write circuit and a read/write control circuit, and when each channel includes multiple memory blocks, the read/write control circuit may be used to control the read/write circuit to alternately read Each memory block in the array of memory cells is written.
  • channel 1 is used as an example for illustration. It is assumed that memory cell array 1 of channel 1 includes memory block 1 and memory block 2, and channel 1 also includes read-write circuit 1 And read and write control circuit 1. Then the read-write control circuit 1 can control the read-write circuit 1 to alternately read and write the memory block 1 and the memory block 2 in the memory cell array 1 .
  • the reading and writing in the storage block cannot be completed in real time, and alternately reading and writing each storage block in the same channel can make the operation speed of the same channel faster, From the outside, it seems that data is being read and written in real time, thereby improving the overall read and write speed of each channel.
  • FIG. 12 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the anti-fuse array may further include an analog block.
  • the analog block may be used to provide supply voltages to antifuse cells in an antifuse array.
  • an analog block may be set in the anti-fuse array to provide the required high voltage for the read and write operations of the anti-fuse unit , so that the normal read and write of the anti-fuse unit can be realized.
  • FIG. 13 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the memory device 800 may include vertically stacked multi-layer storage layers, such as the storage layer 110 and the storage layer 120 , which are only used for illustration, and may actually include more than two layers. memory.
  • each storage layer includes at least one channel.
  • each storage layer may include one channel
  • the memory device 800 may have as many storage layers as there are multiple channels, and multiple channels corresponding to the multiple storage layers may share the same antifuse array.
  • the present disclosure is not limited to this.
  • the memory device provided by the embodiments of the present disclosure can accommodate more memory cell arrays in the same memory device through vertically stacked multi-layer storage layers without increasing the area of the memory device, and can meet high bandwidth requirements. And sharing the same anti-fuse array through multiple channels, the anti-fuse array can be uniformly scheduled in these multiple channels to achieve the equalization function, avoiding the large number of unusable normal memory cells in some channels. There are not enough anti-fuse cells to store the failed addresses, and the low number of unusable normal memory cells in some channels leads to the problem that some anti-fuse cells are idle.
  • the anti-fuse array centrally stores the failure addresses of the unusable normal memory cells in the plurality of channels, which saves the area occupied by the anti-fuse array, improves the integration degree of the memory device, and reduces the complexity of the manufacturing process. the complexity.
  • FIG. 14 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • each memory layer may include the plurality of channels, the test control circuit, and the non-volatile memory cell array. That is, multiple channels in each storage layer share the same non-volatile memory cell array, and multiple channels in different storage layers use different non-volatile memory cell arrays.
  • the memory device 900 includes the storage layer 110 and the storage layer 120, and that the storage layer 110 includes the channel 1 and the channel 2, the description of the channel 1 and the channel 2 can refer to the above-mentioned embodiment.
  • the storage layer 120 may also include channel 1 and channel 2 .
  • the memory device provided by the embodiments of the present disclosure can accommodate more memory cell arrays in the same memory device by stacking multiple storage layers vertically, and each layer of the storage layer includes multiple channels.
  • the area of the large memory device further meets the high bandwidth requirements, and through multiple channels in each storage layer sharing the same anti-fuse array, the anti-fuse array can be uniformly scheduled in these multiple channels to achieve the equalization function, It is avoided that the number of unusable normal memory cells in some channels is large, resulting in insufficient anti-fuse cells to store failed addresses, and the number of unusable normal memory cells in some channels is small, resulting in some anti-fuse cells. idle question.
  • the anti-fuse array centrally stores the failure addresses of the unusable normal memory cells in multiple channels in each layer of the storage layer, which saves the area occupied by the anti-fuse array and improves the integration degree of the memory device.
  • the complexity of the manufacturing process is reduced.
  • FIG. 15 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • each storage layer in the memory device 1000 provided by the embodiment of the present disclosure may further include at least one of a charge pump, a temperature sensor, and a chip identification memory.
  • the charge pump may be used to provide power for the plurality of channels of the corresponding storage layer, the test control circuit and/or the non-volatile memory cell array.
  • a temperature sensor may be used to test the temperature of the plurality of channels of the corresponding memory layer, the test control circuit and/or the non-volatile memory cell array.
  • the chip identification memory may be used to store the chip identification information of the corresponding storage layer.
  • each memory layer of the memory device 1000 may also include shared analog circuits and capacitances. That is, multiple channels in each storage layer in the embodiments of the present disclosure may share the same non-volatile memory cell array, charge pump, test control circuit, shared analog circuit and capacitor, temperature sensor and chip identification memory.
  • the memory device is a DRAM (Dynamic Random Access Memory, dynamic random access memory) as an example for illustration, but the present disclosure is not limited to this, and the memory device may be any device capable of realizing a storage function.
  • DRAM Dynamic Random Access Memory, dynamic random access memory
  • FIG. 16 schematically shows a schematic diagram of a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • DRAM core #1 As shown in Figure 16, taking a three-dimensional (3-dimension, 3D) vertically stacked DRAM cube as an example, vertically stack DRAM core #4, DRAM core #3, and DRAM core # on the logic control circuit in sequence 2. DRAM core #1.
  • Three-dimensional stacked DRAM is a new type of memory formed by stacking multiple layers of DRAM through 3D packaging technology, which can provide a large memory capacity and memory bandwidth.
  • FIG. 17 schematically shows a schematic diagram of a 2.5-dimensional (2.5D) integrated circuit according to an embodiment of the present disclosure.
  • DRAM core #4, DRAM core #3, DRAM core #2, and DRAM core #1 are vertically stacked in sequence on an interposer.
  • a logic control circuit is provided on the interposer. .
  • the data communication between the logic control circuit and each DRAM core is realized through the adapter board.
  • FIG. 16 and FIG. 17 take the vertical stacking of four DRAM cores as an example for illustration, but in fact, the present disclosure does not limit the number of vertically stacked DRAM cores.
  • FIG. 18 schematically shows a schematic diagram of a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • each DRAM core includes two channels, for example, DRAM core #4, DRAM core #3, DRAM core #2, and DRAM core #1 each include a channel 1 and channel 2.
  • Each channel can include a single DRAM chip, and multiple DRAM chips in multiple channels can be integrated into one storage layer, and the logic control circuit can control the pins of each channel independently or simultaneously.
  • each channel may include 64 normal data pins, and may also include 8 ECC (Error Correcting Code, error checking and correction) check pins.
  • ECC Error Correcting Code, error checking and correction
  • the ECC check pin can be used to perform error detection and correction on the data supplied from each channel, the data can be detected for errors and the errors can be corrected.
  • FIG. 19 schematically shows a schematic diagram of a memory layer in a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • DRAM core #1 as an example of a storage layer in a memory device, it includes channel 1 and channel 2, and channel 1 and channel 2 share the same non-volatile memory cell array, Charge pumps, test control circuits, shared analog circuits and capacitors, temperature sensors, and chip identification memory.
  • the memory cell array of each channel includes 4 memory blocks.
  • the memory cell array 1 in channel 1 includes memory blocks 1 to 4
  • the memory cell array 2 in channel 2 includes memory blocks 1 to 4 .
  • the memory block 1 in the memory cell array 1 in the channel 1 is provided with a normal cell array 11 (assuming that the normal memory cells 11 to 18 are included), a spare cell array 11 (assuming that the spare memory cell 11 and the spare memory cell 12 are included), and
  • the latch block 11 (assumed to include the latch 11 and the latch 12 )
  • the storage block 2 is provided with a normal cell array 12 (assumed to include the normal storage cells 21 to 28 ), a spare cell array 12 (assumed to include the spare storage cells 21 and 28 ) Spare storage unit 22) and latch block 12 (assumed to include latch 21 and latch 22)
  • storage block 3 is provided with normal cell array 13 (assumed to include normal storage units 31 to 38), spare cell array 13 (assumed to include normal storage units 31 to 38) Including the spare storage unit 31 and the spare storage unit 32) and the latch block 13 (assumed to include the latch 31 and the latch 32),
  • the storage block 4 is provided with a
  • the latch blocks in any other one or more memory blocks in channel 1 can be called The latch is used to store the remaining failed addresses, and the access addresses of the spare memory cells of the spare cell array in any other one or more storage blocks can also be used as the repair addresses of the remaining failed addresses.
  • each spare memory cell in the spare cell array in each memory block can be in one-to-one correspondence with the latches in the latch block in the corresponding memory block.
  • the read-write control circuit 1 in the channel 1 can control the read-write circuit 1 to alternately read and write the memory block 1 to the memory block 4 in turn.
  • channel 2 in FIG. 19 may refer to channel 1 .
  • FIG. 20 schematically shows a schematic diagram of a memory layer in a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • the test control circuit can receive a test command from an external test device or a memory controller in a memory system including DRAM core #1, and respond to the test command, Test normal cell arrays 11 to 14 in memory blocks 1 to 4 in memory cell array 1 of channel 1 and normal cell arrays 11 to 14 in memory blocks 2 to 4 in memory cell array 2 in channel 2 to obtain a test
  • the access address of the failed normal memory cell is taken as the failure address.
  • test control circuit sends the obtained failure address to the control block of the anti-fuse array, and the control block stores it in the anti-fuse unit of the anti-fuse array.
  • the scan host dumps the failed address stored in the anti-fuse unit of the anti-fuse array into the corresponding latch block of the corresponding channel.
  • Embodiments of the present disclosure also provide a memory system, which may include: at least one storage layer and a memory controller.
  • the memory controller may be configured to control the at least one memory layer.
  • the memory controller may provide address, command and control signals to each memory layer to control program (or write) operations and read operations of each memory layer.
  • the command may be a read command or a write command.
  • an address may include a location in each layer of storage tier to which data is written or read from.
  • each storage layer may include: a plurality of channels, a test control circuit and a non-volatile memory cell array.
  • each channel of the plurality of channels may include a memory cell array
  • the memory cell array may include a normal cell array
  • the normal cell array may include a plurality of normal memory cells
  • the normal memory cells may be volatile memory cells.
  • the test control circuit may be used to control and test the normal cell arrays in the multiple channels in response to the test instruction, and determine the access addresses of the normal memory cells that fail the test in the normal cell arrays in the multiple channels as the failure addresses.
  • the array of non-volatile memory cells may include a plurality of non-volatile memory cells, and the array of non-volatile memory cells may be operable to receive and store the fail addresses from the test control circuit.
  • the memory controller may be operable to provide the test instructions to the test control circuit.
  • the memory system may be connected to an external test device, and the test control circuit may receive the test instruction from the external test device.
  • the memory system provided by the present disclosure in a real-time manner, on the one hand, can satisfy high bandwidth requirements by allowing memory devices including multiple channels to share the same non-volatile memory cell array; on the other hand, by using non-volatile memory cells
  • the non-volatile memory cells in the array are used to store the failure addresses corresponding to the access addresses of the unusable normal memory cells that have failed the test in the normal cell arrays in the plurality of channels, and the memory cell arrays in the plurality of channels can be After the power is turned off, it is still possible to know which or which normal memory cells in the memory cell array in the multiple channels are unavailable.
  • FIG. 21 schematically shows a flowchart of a method for testing a memory device according to an embodiment of the present disclosure.
  • the memory device may include a plurality of channels and an array of non-volatile memory cells, each channel may include an array of memory cells, the array of memory cells may include an array of normal cells, the array of normal cells may include normal memory cells, and
  • the normal memory cells may be volatile memory cells, and the non-volatile memory cell array may include a plurality of non-volatile memory cells.
  • the method provided by the embodiment of the present disclosure may include the following steps.
  • step S2110 a test instruction is received.
  • test instruction may be provided to the test control circuit through a memory controller, or the test instruction may be provided to the test control circuit by an external test device connected to the memory device.
  • the source is not limited.
  • step S2120 the normal cell arrays in the multiple channels are controlled to be tested according to the test instruction, and the access addresses of the normal memory cells that fail the test in the normal cell arrays in the multiple channels are determined as failure addresses.
  • step S2130 the failed address is sent and stored to the non-volatile memory cell array.
  • the testing method of the memory device provided by the present disclosure in a real-time manner can meet the high bandwidth requirement by allowing the memory device including multiple channels to share the same non-volatile memory cell array; on the other hand, by using the non-volatile memory
  • the non-volatile memory cells in the non-volatile memory cell array in the plurality of channels are used to store the failure addresses corresponding to the access addresses of the unusable normal memory cells that fail the test in the normal cell array in the plurality of channels, which can be stored in the memory cells in the plurality of channels.
  • After the cell array is powered off it is still possible to know which or which normal memory cells of the memory cell array in the multiple channels are unavailable. In this way, after the next power-on, there is no need to re-test, saving testing time and cost. cost, improve the test efficiency, while maintaining the high-speed read and write performance of the volatile memory cells used in the memory cell array in each channel.
  • Embodiments of the present disclosure also provide a method of using a memory device
  • the memory device may include a plurality of channels and an array of non-volatile memory cells, each channel may include an array of memory cells and a latch block, the memory cells
  • the array may include an array of normal cells, the array of normal cells including normal memory cells, the normal memory cells may be volatile memory cells, the array of non-volatile memory cells may include a plurality of non-volatile memory cells, A failure address representing an access address of a normal memory cell that has failed a test in the normal cell array in the plurality of channels may be stored in the non-volatile memory cell array.
  • the using method may include the following steps: when the memory device is powered on, dumping the failed address in the non-volatile memory cell array to a latch block of a corresponding channel .
  • the latch block may include a first number of latches
  • the memory cell array may further include a spare cell array
  • the spare cell array may include the first number of spare memory cells
  • the spare storage unit may be a volatile memory unit
  • each latch in the latch block in each channel may be in one-to-one correspondence with each spare storage unit in the spare cell array in the corresponding channel.
  • dumping the failed address in the non-volatile memory cell array to the latch block of the corresponding channel may include: when the memory device is powered on, Dumping the failed address in the non-volatile memory cell array to the corresponding latch in the latch block of the corresponding channel to determine the access address of the target spare storage unit for replacing the failed address as Fix the address.
  • the memory cell array may include a plurality of memory blocks, the plurality of memory blocks may share a spare cell array and a latch block, the spare cell array may include a first number of spare memory cells,
  • the spare memory unit may be a volatile memory unit, the latch block may include the first number of latches, and the non-volatile memory cell array may further include a scan master, a lock for each channel.
  • Both the storage block and the scanning host may include a first interface, a second interface and a third interface.
  • transferring the failed address in the non-volatile memory cell array to the latch block of the corresponding channel may include: passing the latch block of each channel and the The first interface of the scan host receives an enable signal; the clock signal is received through the latch block of each channel and the second interface of the scan host; the third interface of the scan host is when the enable signal is the first interface.
  • the channel address, the storage block address and the latch block address are sequentially sent to the third interface of the latch block of each channel through the third interface of the scanning host to determine the target channel respectively , the target storage block of the target channel and the target latch in the target latch block corresponding to the target channel, and send a write command to the third interface of the latch block of each channel to pass the target channel
  • the third interface of the target latch block writes the failed address into the target latch of the target latch block.
  • each channel's latch block and the scan host may further include a fourth interface.
  • the failed addresses tested in the test phase and stored in the non-volatile memory cell array can be dumped to the corresponding latches of the corresponding channels, so that each channel can be used when each channel is used.
  • the normal cell array is formed, the faster read and write speed of the volatile memory cells in the normal cell array can be maintained, and the accuracy of read and write data can be ensured.
  • the exemplary embodiments described herein may be implemented by software, or may be implemented by software combined with necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure may be embodied in the form of software products, and the software products may be stored in a non-volatile storage medium (which may be CD-ROM, U disk, mobile hard disk, etc.) or on the network , which includes several instructions to cause a computing device (which may be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to an embodiment of the present disclosure.
  • a computing device which may be a personal computer, a server, a touch terminal, or a network device, etc.
  • an embodiment of the present disclosure also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs; when the one or more programs are processed by the one or more programs The execution of the one or more processors causes the one or more processors to implement the method described in any of the above embodiments.
  • an embodiment of the present disclosure also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, implements the method described in any of the foregoing embodiments.

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

一种存储器装置及其测试方法和使用方法、存储器系统，属于半导体技术领域。该存储器装置包括：多个通道，每个通道包括存储器单元阵列，所述存储器单元阵列包括正常单元阵列，所述正常单元阵列包括正常存储单元，所述正常存储单元为易失性存储器单元；测试控制电路，用于响应测试指令，控制测试所述多个通道中的正常单元阵列，确定所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址为失败地址；非易失性存储器单元阵列，其包括多个非易失性存储器单元，用于从所述测试控制电路接收并存储所述失败地址。该存储器装置能够使多个通道共享同一个非易失性存储器单元阵列。

Description

存储器装置及其测试方法和使用方法、存储器系统
相关申请的交叉引用
本申请要求于2020年09月15日提交的申请号为202010966642.2、名称为“存储器装置及其测试方法和使用方法、存储器系统”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种存储器装置、存储器系统、存储器装置的测试方法和存储器装置的使用方法。
背景技术
由于易失性存储器具有较快的读写速度，因此被广泛应用于各种电子设备中。随着集成度的增加，一个易失性存储器芯片中包括越来越多的正常存储单元，若其中一个正常存储单元不可用，或者甚至整行或者整列的正常存储单元无法使用，可能导致整颗芯片不可用，严重降低了芯片的良率。
因此，相关技术中，通常会在易失性存储器芯片中设置除正常存储单元以外的备用存储单元用来替换上述不可用的正常存储单元，即正常存储单元是指测试成功时会优先用于数据读写的存储单元，备用存储单元是指某个或某些存储单元不可用时，用来替换不可用的正常存储单元。
同时，随着对高带宽的需求，越来越多的存储器装置中会集成多个通道，如何在这种高带宽应用场景下，合理地用备用存储单元对不可用的正常存储单元进行替换是亟需解决的问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种存储器装置、存储器系统、存储器装置的测试方法和存储器装置的使用方法，可以克服上述相关技术中存在的满足高宽带需求的包括多个通道的存储器装置中，如何更高效地进行冗余替换。
根据本公开的一个方面，提供一种存储器装置，所述存储器装置包括：多个通道，每个通道包括存储器单元阵列，所述存储器单元阵列包括正常单元阵列，所述正常单元阵列包括正常存储单元，所述正常存储单元为易失性存储器单元；测试控制电路，用于响应测试指令，控制测试所述多个通道中的正常单元阵列，确定所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址为失败地址；非易失性存储器单元阵列，其包括多 个非易失性存储器单元，用于从所述测试控制电路接收并存储所述失败地址。
根据本公开的一个方面，提供一种存储器系统，所述存储器系统包括：至少一层存储层；以及存储器控制器，其被构造为控制所述至少一层存储层。其中，每层存储层包括：多个通道，每个通道包括存储器单元阵列，所述存储器单元阵列包括正常单元阵列，所述正常单元阵列包括多个正常存储单元，所述正常存储单元为易失性存储器单元；测试控制电路，用于响应测试指令，控制测试所述多个通道中的正常单元阵列，确定所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址作为失败地址；非易失性存储器单元阵列，其包括多个非易失性存储器单元，用于从所述测试控制电路接收并存储所述失败地址。
根据本公开的一个方面，提供一种存储器装置的测试方法，所述存储器装置包括多个通道和非易失性存储器单元阵列，每个通道包括存储器单元阵列，所述存储器单元阵列包括正常单元阵列，所述正常单元阵列包括正常存储单元，所述正常存储单元为易失性存储器单元，所述非易失性存储器单元阵列包括多个非易失性存储器单元。其中，所述测试方法包括：接收测试指令；根据所述测试指令控制测试所述多个通道中的正常单元阵列，确定所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址为失败地址；将所述失败地址发送并存储至所述非易失性存储器单元阵列。
根据本公开的一个方面，提供一种存储器装置的使用方法，所述存储器装置包括多个通道和非易失性存储器单元阵列，每个通道包括存储器单元阵列和锁存块，所述存储器单元阵列包括正常单元阵列，所述正常单元阵列包括正常存储单元，所述正常存储单元为易失性存储器单元，所述非易失性存储器单元阵列包括多个非易失性存储器单元，所述非易失性存储器单元阵列中存储有用于表示所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址的失败地址。其中，所述使用方法包括：在所述存储器装置上电时，将所述非易失性存储器单元阵列中的所述失败地址转存至对应通道的锁存块中。
本公开某些实施例提供的存储器装置、存储器系统、存储器装置的测试方法和存储器装置的使用方法，一方面，通过让包括多个通道的存储器装置共享同一个非易失性存储器单元阵列，可以满足高带宽需求；另一方面，通过使用非易失性存储器单元阵列中的非易失性存储器单元来存储该多个通道中的正常单元阵列中测试失败的不可用的正常存储单元的访问地址对应的失败地址，可以在该多个通道中的存储器单元阵列在掉电后，仍然能够获知该多个通道中的存储器单元阵列的哪个或者哪些正常存储单元是不可用的，这样，在下次重新上电后，不需要重新测试，节约了测试时间和成本，提高了测试效率，同时还可以保持每个通道中的存储器单元阵列所采用的易失性存储器单元的高速读写性能。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性示出了根据本公开的一实施例的存储器装置的示意图。
图2示意性示出了根据本公开的一实施例的存储器装置的示意图。
图3示意性示出了根据本公开的一实施例的存储器装置的示意图。
图4示意性示出了根据本公开的一实施例的存储器装置的示意图。
图5示意性示出了根据本公开的一实施例的存储器装置的示意图。
图6示意性示出了根据本公开的一实施例的存储器装置的示意图。
图7示意性示出了根据本公开的一实施例的通道的示意图。
图8示意性示出了根据本公开的一实施例的通道的示意图。
图9示意性示出了根据本公开的一实施例的扫描主机和各通道的锁存块的各个接口的示意图。
图10示意性示出了图9中各信号的时序图。
图11示意性示出了根据本公开的一实施例的通道的示意图。
图12示意性示出了根据本公开的一实施例的存储器装置的示意图。
图13示意性示出了根据本公开的一实施例的存储器装置的示意图。
图14示意性示出了根据本公开的一实施例的存储器装置的示意图。
图15示意性示出了根据本公开的一实施例的存储器装置的示意图。
图16示意性示出了根据本公开的一实施例的三维集成电路的示意图。
图17示意性示出了根据本公开的一实施例的2.5维集成电路的示意图。
图18示意性示出了根据本公开的一实施例的三维集成电路的示意图。
图19示意性示出了根据本公开的一实施例的三维集成电路中一层存储层的示意图。
图20示意性示出了根据本公开的一实施例的三维集成电路中一层存储层的示意图。
图21示意性示出了根据本公开的一实施例的存储器装置的测试方法的流程图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知方法、 装置、实现或者操作以避免模糊本公开的各方面。
附图中所示的方框图仅仅是功能实体，不一定必须与物理上独立的实体相对应。即，可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
附图中所示的流程图仅是示例性说明，不是必须包括所有的内容和操作/步骤，也不是必须按所描述的顺序执行。例如，有的操作/步骤还可以分解，而有的操作/步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”仅作为标记使用，不是对其对象的数量限制。
图1示意性示出了根据本公开的一实施例的存储器装置的示意图。如图1所示，本公开实施例提供的存储器装置100可以包括多个通道、测试控制电路和非易失性存储器单元阵列。
图1实施例中，以存储器装置100包括通道1和通道2为例进行举例说明，但本公开并不限定其通道数量，只要大于或者等于2即可。
每个通道可以包括存储器单元阵列，每个存储器单元阵列可以包括正常单元阵列，每个正常单元阵列可以包括正常存储单元，每个正常存储单元可以为易失性存储器单元。其中，易失性存储器单元是指掉电后里面存储的数据会丢失的存储器单元。
例如，图1中，通道1可以包括存储器单元阵列1，存储器单元阵列1可以包括正常单元阵列1，正常单元阵列1可以包括正常存储单元1至正常存储单元12。类似的，通道2可以包括存储器单元阵列2，存储器单元阵列2可以包括正常单元阵列2，正常单元阵列2也可以包括正常存储单元1至正常存储单元12。
需要说明的是，图1中示出的每个正常单元阵列包括12个正常存储单元仅是用于举例说明的，实际上每个正常单元阵列所包括的正常存储单元的数量可以根据实际需求设计，本公开对此不做限定。这些正常单元阵列可由多个存储块(Bank)构成，正常单元阵列中的正常存储单元可连接至不同的字线、位线。
本公开实施例中，测试控制电路可以用于响应测试指令，控制测试存储器装置100的所述多个通道中的正常单元阵列，确定所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址为失败地址。
需要说明的是，本公开实施例中的每个失败地址可能是单个正常存储单元的行地址、列地址、存储块(Bank)地址等中之一或者任意组合。本公开对此不做限定，可以根据需要确定一个失败地址所指代的含义。
本公开实施例中，非易失性存储器单元阵列可以包括多个非易失性存储器单元。其中，非易失性存储器单元是指掉电的情况下，其内存储的数据不会丢失的存储器单元。非易失性存储器单元阵列可以用于从所述测试控制电路接收并存储所述失败地址。
例如，图1中，假设非易失性存储器单元阵列中包括非易失性存储器单元1至5，但这里的非易失性存储器单元的数量仅用于举例说明，实际上非易失性存储器单元阵列中包括的非易失性存储器单元可以根据实际需求进行设计，本公开对此不做限定。
本公开实施例中，可以以任意各种不同的形式来实现非易失性存储器单元。例如，可以利用熔丝(fuse)、电熔丝(efuse)、反熔丝(anti-fuse)、磁存储器(Magnetoresistive Random Access Memory，MRAM)、铁存储器(Ferroelectric RAM，FeRAM)、闪存(Flash)等实现非易失性存储器单元。
本公开实时方式提供的存储器装置，一方面，通过让包括多个通道的存储器装置共享同一个非易失性存储器单元阵列，可以满足高带宽需求；另一方面，通过使用非易失性存储器单元阵列中的非易失性存储器单元来存储该多个通道中的正常单元阵列中测试失败的不可用的正常存储单元的访问地址对应的失败地址，可以在该多个通道中的存储器单元阵列在掉电后，仍然能够获知该多个通道中的存储器单元阵列的哪个或者哪些正常存储单元是不可用的，这样，在下次重新上电后，不需要重新测试，节约了测试时间和成本，提高了测试效率，同时还可以保持每个通道中的存储器单元阵列所采用的易失性存储器单元的高速读写性能。
图2示意性示出了根据本公开的一实施例的存储器装置的示意图。图2实施例提供的存储器装置200与上述图1实施例提供的存储器装置100的区别在于，所述非易失性存储器单元阵列可以包括反熔丝阵列，对应的非易失性存储器单元可以为反熔丝单元。
例如，图2中的反熔丝单元1可以对应图1中的非易失性存储器单元1，反熔丝单元2可以对应图1中的非易失性存储器单元2，反熔丝单元3可以对应图1中的非易失性存储器单元3，反熔丝单元4可以对应图1中的非易失性存储器单元4，反熔丝单元5可以对应图1中的非易失性存储器单元5。
在下面的举例说明中，均以非易失性存储器单元阵列为反熔丝阵列为例进行举例说明，但本公开并不限定于此，非易失性存储器单元阵列中的非易失性存储器单元也可以采用其他任意的具有非易失性存储功能的单元来排布实现。
图3示意性示出了根据本公开的一实施例的存储器装置的示意图。
图3实施例提供的存储器装置300与上述图2实施例提供的存储器装置200的区别之处在于，反熔丝阵列还可以包括控制块(Control Block)。其中控制块可以用于控制反熔丝阵列的编程，将从测试控制电路接收的失败地址存储于反熔丝阵列中的反熔丝单元中。
本公开实施方式提供的存储器装置，采用反熔丝阵列作为非易失性存储器单元阵列，并利用反熔丝阵列中的反熔丝单元来作为非易失性存储器单元用于存储正常单元阵列中的失败地址，由于反熔丝单元较小，因此占用芯片面积小，易于实现，能够抗辐射抗干扰，不受电磁辐射影响。
图4示意性示出了根据本公开的一实施例的存储器装置的示意图。图4实施例提供的存储器装置400与上述图3实施例提供的存储器装置300的区别之处在于，每个通道还可以包括锁存块。
例如，图4中，通道1还可以包括锁存块1，通道2还可以包括锁存块2。
图4实施例中，反熔丝阵列还可以包括扫描主机(Scan Host)。其中，所述扫描主机可以用于在存储器装置400上电时，将反熔丝阵列中存储的所述失败地址转存至对应通道的锁存块中。
例如，图4中，在存储器装置400上电时，可以将存储于反熔丝阵列中的失败地址转存至通道1的锁存块1和/或通道2的锁存块2中。
本公开实施方式提供的存储器装置，为了保证较快的读写速度，因此每个通道的存储器单元阵列中的正常单元阵列中的各个正常存储单元为易失性存储器单元，由于每个存储器单元阵列中包括较多的正常存储单元，为了提高芯片良率，需要在出厂前对每个通道的存储器单元阵列中的正常单元阵列进行测试，获得失败地址。同时，为了掉电后数据不丢失，需要将这些失败地址存储至采用非易失性存储器单元的非易失性存储器单元阵列中例如反熔丝阵列。但在使用该存储器装置时，在对正常单元阵列中的正常存储单元进行快速读写时，也需要快速地获取到哪些正常存储单元是不可用的，若在快速读写时再去非易失性存储器单元阵列中读取失败地址，则由于非易失性存储器单元的读数据速度相比易失性存储器单元较慢，则会导致无法及时获取所需的失败地址。为了进一步解决这个问题，本公开实施例中采用在存储器装置上电时，将非易失性存储器单元阵列中存储的失败地址转存至对应通道的锁存块中，从而能够在存储器装置读写过程中快速替换掉或者不采用不可用的正常存储单元。
图5示意性示出了根据本公开的一实施例的存储器装置的示意图。
图5实施例提供的存储器装置500与上述图4实施例提供的存储器装置400的区别之处在于，每个锁存块可以包括第一数量的锁存器，每个存储器单元阵列还可以包括备用单元阵列，每个备用单元阵列可以包括所述第一数量的备用存储单元，每个备用存储单元为易失性存储器单元。
在其他实施例中，锁存块也可以用寄存块替代，即采用寄存块中的寄存器来实现锁存器的功能。
需要说明的是，本公开实施例中的每个备用存储单元中可以包括一个易失性存储器单元(对应失败地址为单个正常存储单元的访问地址)，也可以包括一条字线上的一行易失性存储器单元(对应失败地址为行地址)，或者一条位线上的一列易失性存储器单元(对 应失败地址为列地址)，或者一个存储块的易失性存储器单元(对应失败地址为存储块地址)等。本领域内技术人员可根据需要自行选择。
例如，图5中，通道1中的存储器单元阵列1可以包括正常单元阵列1和备用单元阵列1，备用单元阵列1中可以包括4个(即假设第一数量＝4，但这里仅用于举例说明，本公开并不限定于此)备用存储单元，如备用存储单元1至备用存储单元4。对应的，锁存块1可以包括4个锁存器，如锁存器1至锁存器4。需要要说明的是，本实施例中的一个锁存器代表能够存储一个失败地址的锁存器。
类似的，通道2中的存储器单元阵列2可以包括正常单元阵列2和备用单元阵列2，备用单元阵列2中可以包括4个备用存储单元，如备用存储单元1至备用存储单元4。对应的，锁存块2可以包括4个锁存器，如锁存器1至锁存器4。
本公开实施例中，可以设置每个通道中的锁存块中的各个锁存器与对应通道中的备用单元阵列中的各个备用存储单元一一对应。
例如，图5实施例中，通道1中的锁存块1中的锁存器1与通道1中的备用单元阵列1中的备用存储单元1对应，通道1中的锁存块1中的锁存器2与通道1中的备用单元阵列1中的备用存储单元2对应，通道1中的锁存块1中的锁存器3与通道1中的备用单元阵列1中的备用存储单元3对应，通道1中的锁存块1中的锁存器4与通道1中的备用单元阵列1中的备用存储单元4对应。
通道2中的锁存块2中的锁存器1与通道2中的备用单元阵列2中的备用存储单元1对应，通道2中的锁存块2中的锁存器2与通道2中的备用单元阵列2中的备用存储单元2对应，通道2中的锁存块2中的锁存器3与通道2中的备用单元阵列2中的备用存储单元3对应，通道2中的锁存块2中的锁存器4与通道2中的备用单元阵列2中的备用存储单元4对应。
本公开实施例中，反熔丝阵列中的扫描主机可以用于在存储器装置500上电时，将反熔丝阵列中的所述失败地址转存至对应通道的锁存块中的对应锁存器，以确定用于替代所述失败地址的目标备用存储单元的访问地址作为修复地址。
例如，图5中，假设测试时发现通道1中的存储器单元阵列1中的正常单元阵列1的第一行的正常存储单元1至4测试失败，则将通道1中的存储器单元阵列1中的正常单元阵列1的第一行的正常存储单元1至4的访问地址作为一个失败地址，将其存储至反熔丝阵列中的反熔丝单元1。则在存储器装置500上电时，扫描主机可以将反熔丝单元1中存储的通道1中的存储器单元阵列1中的正常单元阵列1的第一行的正常存储单元1至4的失败地址转存至通道1的锁存块1中的锁存器1，则可以确定使用与锁存块1中的锁存器1对应的备用单元阵列1中的备用存储单元1作为目标备用存储单元，将备用单元阵列1中的备用存储单元1的访问地址作为替代通道1中的存储器单元阵列1中的正常单元阵列1的第一行的正常存储单元1至4的失败地址的修复地址。
需要注意的是，在上述举例说明中，以假设正常存储单元表示单个存储单元，而备用 存储单元表示多个存储单元为前提，本实施例对此并不限定，上述描述仅仅只是为了示意本实施例对测试失败的正常存储单元的冗余替换过程。
再例如，假设测试时发现通道1中的存储器单元阵列1中的正常单元阵列1的第一列的正常存储单元1、正常存储单元5和正常存储单元9测试失败，则将通道1中的存储器单元阵列1中的正常单元阵列1的第一列的正常存储单元1、正常存储单元5和正常存储单元9的访问地址作为一个失败地址，将其存储至反熔丝阵列中的反熔丝单元2。则在存储器装置500上电时，扫描主机可以将反熔丝单元2中存储的通道1中的存储器单元阵列1中的正常单元阵列1的第一列的正常存储单元1、正常存储单元5和正常存储单元9的失败地址转存至通道1的锁存块1中的锁存器2，则可以确定使用与锁存块1中的锁存器2对应的备用单元阵列1中的备用存储单元2作为目标备用存储单元，将备用单元阵列1中的备用存储单元2的访问地址作为替代通道1中的存储器单元阵列1中的正常单元阵列1的第一列的正常存储单元1、正常存储单元5和正常存储单元9的失败地址的修复地址。
在示例性实施例中，每个正常单元阵列可以包括第二数量的正常存储单元，所述第二数量可以大于或等于所述第一数量。
例如，图5中，通道1中的正常单元阵列1假设包括12(即假设第二数量＝12，但本公开并不限定于此)个正常存储单元，通道1中的备用单元阵列1包括4个备用存储单元，即一般设置同一通道中的备用存储单元数量小于正常存储单元的数量。
需要说明的是，本公开实施例中设置每个通道中的锁存块中的各个锁存器与对应通道中的备用单元阵列中的各个备用存储单元一一对应，并不严格要求每个备用存储单元与锁存器的序号严格一一对应，只要一个锁存器能够确定一个备用存储单元即可，例如在上面图5的举例说明中，也可以设置备用单元阵列1中的备用存储单元1对应锁存块1中的锁存器2。
本公开实施方式提供的存储器装置，为了解决每个通道中的存储器单元阵列中的正常单元阵列，在测试阶段测试出存在不可用的正常存储单元，可以在每个通道中设置一些冗余的备用存储单元用来替换这些不可用的正常存储单元。但为了防止掉电丢失，需要非易失性存储器单元记住哪些正常存储单元是不可用的，并指定用哪些备用存储单元来替换，这些被指定用来替换的备用存储单元称之为目标备用存储单元，目标备用存储单元的访问地址称之为修复地址。在将非易失性存储器单元阵列中存储的失败地址转存至对应通道的锁存块中时，本公开实施例通过设置每个通道的锁存块中的锁存器与对应通道的备用单元阵列中的备用存储单元一一对应，这样当失败地址存储至哪个锁存器确定后，即可确定采用哪个备用存储单元作为替换该失败地址对应的正常存储单元的目标备用存储单元，由此减少了锁存块的存储容量。
在其他实施例中，也可以将非易失性存储器单元阵列中存储的失败地址及其修复地址同时转存至对应通道的锁存块中的锁存器中，此时，锁存器的数量会多与对应通道中的备用存储单元的数量。
图6示意性示出了根据本公开的一实施例的存储器装置的示意图。图6实施例提供的存储器装置600与上述图5实施例提供的存储器装置500的区别之处在于，每个通道还可以包括读写电路和读写控制电路。
其中，读写电路可以用于从所述测试控制电路接收所述测试指令，并响应所述测试指令将第一写数据写入对应通道的存储器单元阵列中的目标正常存储单元中，并比较从所述目标正常存储单元读取的第一读数据与所述第一写数据，基于比较结果输出指示所述目标正常存储单元测试通过或者测试失败的指示信号。
读写控制电路可以用于控制所述读写电路，并在所述指示信号指示所述目标正常存储单元测试失败时，将所述目标正常存储单元的访问地址作为所述失败地址，将所述失败地址返回至所述测试控制电路。
例如，图6实施例中，通道1中还可以包括读写电路1和读写控制电路1。通道2中还可以包括读写电路2和读写控制电路2。
读写电路1可以从测试控制电路接收测试指令，响应接收到的测试指令，将第一写数据写入到通道1的存储器单元阵列1中的目标正常存储单元中，例如假设是按行写入的，则假设首先将第一写数据写入正常单元阵列1的正常存储单元1至4，然后再从正常单元阵列1的正常存储单元1至4中按行读出第一读数据，若第一写数据和对应的第一读数据是一致的，则说明对应的正常存储单元测试通过；若第一写数据和对应的第一读数据不一致，则说明对应的正常存储单元测试失败。依次逐行测试，则可以获得整个正常单元阵列1中每一行中的正常存储单元的测试通过或测试失败的指示信号。将测试失败的正常存储单元的访问地址作为失败地址返回至测试控制电路。
在示例性实施例中，所述读写控制电路可以还用于控制所述读写电路，以将准备写入由所述失败地址指定的所述目标正常存储单元的第二写数据写入由所述修复地址指定的所述目标备用存储单元。
本公开实施方式提供的存储器装置，在存储器装置出厂前对各个通道的存储器单元阵列中的正常存储单元进行测试，比较读写数据是否一致，从而获得不可用的正常存储单元的失败地址，然后将失败地址存储到非易失性存储器单元阵列中，这样，当后续对存储器装置中的正常存储单元进行读写操作时，可以利用与该失败地址对应的修复地址所表示的目标备用存储单元来替换掉对应的不可用的正常存储单元，进行数据的读写。
图7示意性示出了根据本公开的一实施例的通道的示意图。以上述任一实施例中的存储器装置中的任一通道的存储器单元阵列为例，每个存储器单元阵列可以包括多个存储块。
例如，图7中，以通道1为例，且以通道1中的存储器单元阵列1包括两个存储块(即存储块1和存储块2)为例进行举例说明，但实际上，每个存储器单元阵列包括的存储块数量可以根据实际应用场景进行设置，本公开对此不做限定。
图7中假设存储块1中包括正常单元阵列11，正常单元阵列11假设包括正常存储单元11至正常存储单元18。假设存储块2中包括正常单元阵列12，正常单元阵列12假设 包括正常存储单元21至正常存储单元28。上述实施例中的正常单元阵列1可以包括本公开实施例中的正常单元阵列11和正常单元阵列12。
本公开实施例中，每个通道中的所述多个存储块可以共享对应通道的备用单元阵列和锁存块，对应通道的备用单元阵列可以包括第一数量(图7中假设等于4)的备用存储单元(例如图7中的备用存储单元11、12、21和22)，每个备用存储单元为易失性存储器单元，每个通道的锁存块可以包括所述第一数量的锁存器(例如图7中的锁存器11、12、21和22)。
如图7所示，通道1中的存储器单元阵列1中的备用单元阵列1假设包括设置于存储块1中的备用单元阵列11和设置于存储块2中的备用单元阵列12，锁存块1假设包括设置于存储块1中的锁存块11和设置于存储块2中的锁存块12。假设存储块1中的备用单元阵列11包括备用存储单元11和备用存储单元12，存储块2中的备用单元阵列12包括备用存储单元21和备用存储单元22。假设存储块1中的锁存块11包括锁存器11和锁存器12，存储块2中的锁存块12包括锁存器21和锁存器22。
虽然图7实施例中备用单元阵列和锁存块可以分布设置于各个存储块中，但在调配使用时，同一通道内的多个存储块可以共享该通道内的所有备用单元阵列和锁存块。
例如，图7中，若存储块1中有超过2行的正常存储单元测试失败，锁存块11中假设只有2个锁存器，则锁存块1中只能存储对应2行的正常存储单元的访问地址的2个失败地址，对应的，这2个失败地址可以采用备用单元阵列11中的2个备用存储单元的访问地址作为修复地址。则此时可以将剩余的测试失败的存储块1中其他行的正常存储单元的访问地址对应的失败地址存储于存储块2中的锁存块12的锁存器中，对应的，将存储于锁存块12的锁存器中的失败地址采用备用单元阵列12中的备用存储单元的访问地址作为修复地址。
在图7实施例中，还可以设置备用存储单元11与锁存器11对应，备用存储单元12与锁存器12对应，备用存储单元21与锁存器21对应，备用存储单元22与锁存器22对应。
图8示意性示出了根据本公开的一实施例的通道的示意图。
与图7实施例的不同之处在于，图8实施例中，为了实现每个通道中的所述多个存储块共享对应通道的备用单元阵列和锁存块，也可以不将备用单元阵列和锁存块分布设置于各个存储块，而可以在所述多个存储块的外部集中设置该对应通道的备用单元阵列和锁存块。
例如，图8中，存储块1中包括正常单元阵列11，正常单元阵列11假设包括正常存储单元11至18，存储块2中包括正常单元阵列12，正常单元阵列12包括正常存储单元22至28。在存储块1和存储块2外、在通道1的存储器单元阵列1中集中设置备用单元阵列1，备用单元阵列1包括备用存储单元1至4。在存储块1和存储块2外、在通道1的存储器单元阵列1中集中设置锁存块1，锁存块1包括锁存器1至4。
在图8实施例中，还可以设置备用存储单元1至4分别与锁存器1至4一一对应。
本公开实施方式提供的存储器装置，当每个通道内的正常存储单元被划分为多个存储块时，不管每个通道内的锁存器和备用存储单元是分布式设置于每个存储块内，还是集中设置在对应通道内，均可以通过共享每个通道内的锁存块中的锁存器和备用单元阵列中的备用存储单元，可以解决某些情况下，有的存储块中的不可用的正常存储单元较多，其对应设置的锁存器和备用存储单元不够用，而有的存储块中的不可用的正常存储单元较少，其对应设置的锁存器和备用存储单元闲置的问题，通过统一调度每个通道内的锁存器和备用存储单元，可以达到均衡的目的。
图9示意性示出了根据本公开的一实施例的扫描主机和各通道的锁存块的各个接口的示意图。图10示意性示出了图9中各信号的时序图。从上述实施例可知，所述非易失性存储器单元阵列中还可以包括扫描主机。
本公开实施例中，每个通道的锁存块和所述扫描主机均可以包括第一接口、第二接口和第三接口。
例如，图9和10中，每个通道的锁存块的第一接口和扫描主机的第一接口可以用于接收使能信号Se；每个通道的锁存块的第二接口和扫描主机的第二接口可以用于接收时钟信号SC。
其中，扫描主机的第三接口可以用于在扫描主机的第一接口接收到的使能信号为第一电平(例如图10中为高电平，但本公开并不限定于此，其也可以设置第一电平为低电平)时，根据所述扫描主机的第二接口接收到的时钟信号SC，依次向每个通道的锁存块例如通道1的锁存块1、通道2的锁存块2至通道n的锁存块n(n为大于或等于2的正整数)的第三接口发送通道地址、存储块地址和锁存块地址(通过图10中的Si信号依次传输)，以从所述多个通道中确定出目标通道、所述目标通道的目标存储块及所述目标通道对应的目标锁存块中的目标锁存器。
扫描主机的第三接口通过Si信号向各个通道的各个锁存块发送完上述通道地址、存储块地址和锁存块地址之后，接着可以发送一个命令(R/W)，例如若为高电平，则该命令为读命令，即从目标通道读取数据帧；若为低电平，则该命令为写命令，即将数据帧写入目标通道，例如这里是将失败地址写入目标通道的目标锁存块的锁存器中。
这里假设扫描主机的第三接口先向每个通道的各个锁存块的第三接口发送了一个写命令，目标通道的目标锁存块的第三接口接收到该写命令后，会给扫描主机的第三接口返回一个响应信号(ACK)，扫描主机的第三接口接收到该响应信号后，则可以继续通过扫描主机的第三接口向每个通道的各个锁存块的第三接口发送数据帧，在该数据帧中携带了失败地址，则实现了将失败地址转存至目标锁存器中。
本公开实施方式提供的存储器装置，通过上述第一至第三接口及其对应的使能信号、时钟信号和Si信号，可以正确地将失败地址从非易失性存储器单元中转存至锁存器中，以便能够实现每个通道的正常单元阵列的快速读写。
继续参考图9和图10，进一步的，每个通道的锁存块和所述扫描主机均还包括第四接口。其中，当所述扫描主机的第三接口向每个通道的锁存块的第三接口发送读命令时，通过所述扫描主机的第四接口从所述目标锁存器读取数据(通过So信号)，以将写入的所述失败地址与读取的数据进行比较，验证写入的所述失败地址是否正确写入。
本公开实施方式提供的存储器装置，一方面，通过上述第一至第三接口及其对应的使能信号、时钟信号和Si信号，可以正确地将失败地址从非易失性存储器单元中转存至锁存器中，以便能够实现每个通道的正常单元阵列的快速读写。另一方面，还可以通过第四接口将转存至目标锁存器中的失败地址读取出来，验证写入的失败地址是否正确，从而可以保证每个通道的正常单元阵列的正确读写。
本公开实施例中，还可以预先一一映射了每个通道中的各个锁存器与对应通道内的各个备用存储单元，例如一个通道内假设有100个备用存储单元，则可以设置或者采用100个锁存器，一个锁存器对应一个备用存储单元，假设将失败地址存储至第5个锁存器，则可以使用第5个备用存储单元的访问地址作为该失败地址的修复地址，这样就不用同时使用锁存器存储一个失败地址及其修复地址。
需要说明的是，实现失败地址转存的方式并不限于上述图9和图10的举例说明。
在一些实施例中，可以变换通道地址、存储块地址和锁存块地址的发送先后顺序，例如，扫描主机可以先发送锁存块地址，当某个通道监听到该锁存块地址与其内部的锁存块一致，且其内部的锁存块可用时，则可以向扫描主机返回一个响应信号，这样，扫描主机就可以提前确定目标通道的目标锁存块是否可用，从而能够很快获知是否能够继续把失败地址发送给这个目标通道。
在一些实施例中，当通过使能信号使能失败地址的开始写操作，扫描主机可以通过发送通道地址，确定当前要将失败地址写入哪个目标通道，目标通道接收到通道地址之后，也可以给扫描主机回复一个响应信号，告知扫描主机其正常监听到了通道地址，从而使扫描主机可以继续发送失败地址的相关数据给该目标通道；扫描主机然后发送存储块地址，告知当前待存储的失败地址对应的是目标通道内的哪个目标存储块内的正常存储单元，之后发送锁存块地址，告知将失败地址存储至目标通道的目标锁存块中的哪个目标锁存器，从而可以确定出如何将失败地址转存至相应通道的相应锁存器中。
在一些实施例中，所述目标通道对应的目标锁存块的第四接口可以用于在接收到所述锁存块地址之后，向所述扫描主机的第四接口发送响应信号，用于告知扫描主机其接收到了该锁存块地址。而非目标通道的其他通道对应的非目标锁存块的其他锁存块的第四接口在接收到所述锁存块地址后，与其自身锁存块地址比对，发现不一致，则不会向扫描主机的第四接口发送响应信号。
图11示意性示出了根据本公开的一实施例的通道的示意图。
本公开实施例中，每个通道还可以包括读写电路和读写控制电路，当每个通道中包括多个存储块时，所述读写控制电路可以用于控制所述读写电路交替读写所述存储器单元阵 列中的各个存储块。
例如，基于图7的实施例进行举例说明，图11中，以通道1为例进行举例说明，假设通道1的存储器单元阵列1包括存储块1和存储块2，通道1还包括读写电路1和读写控制电路1。则读写控制电路1可以控制读写电路1交替读写存储器单元阵列1中的存储块1和存储块2。
本公开实施方式提供的存储器装置，还考虑到存储块中的读写都不是实时能够完成的，让同一个通道中的各个存储块交替读写，可以使得该同一个通道的操作速度更快，从外部来看，就好像是在实时的读写数据，从而提高了每个通道的整体读写速度。
图12示意性示出了根据本公开的一实施例的存储器装置的示意图。
图12提供的存储器装置700与上述图4提供的存储器装置400的区别在于，所述反熔丝阵列还可以包括模拟块。所述模拟块可以用于为反熔丝阵列中的反熔丝单元提供电源电压。
本公开实施方式提供的存储器装置，考虑到反熔丝单元所需的高电压，可以在反熔丝阵列中设置一个模拟块，用于为反熔丝单元的读写操作提供所需的高电压，从而使得能够实现反熔丝单元的正常读写。
图13示意性示出了根据本公开的一实施例的存储器装置的示意图。
如图13所示，本公开实施例提供的存储器装置800可以包括垂直堆叠的多层存储层，例如存储层110和存储层120，这里仅用于举例说明，实际可以包括比两层更多的存储器。
本公开实施例中，每层存储层包括至少一个通道。
在示例性实施例中，每层存储层可以包括一个通道，则存储器装置800可以有多少层存储层，则有多少个通道，这多层存储层对应的多个通道可以共享同一个反熔丝阵列。但本公开并不限定于此。
本公开实施方式提供的存储器装置，通过垂直堆叠的多层存储层，可以使得在同一个存储器装置中容纳更多的存储器单元阵列，同时不会加大存储器装置的面积，能够满足高带宽需求，并通过多个通道共享同一个反熔丝阵列，能够在这多个通道内统一调度该反熔丝阵列，实现均衡功能，避免了某些通道内的不可用的正常存储单元的数量较多导致没有足够的反熔丝单元存储失败地址，某些通道内的不可用的正常存储单元的数量较少导致有些反熔丝单元空闲的问题。同时，通过该反熔丝阵列集中存储该多个通道内的不可用的正常存储单元的失败地址，节约了反熔丝阵列所占据的面积，提高了存储器装置的集成度，降低了制作工艺的复杂度。
图14示意性示出了根据本公开的一实施例的存储器装置的示意图。
在图14实施例中，每层存储层可以包括所述多个通道、所述测试控制电路和所述非易失性存储器单元阵列。即每层存储层中的多个通道共享同一个非易失性存储器单元阵列，不同存储层的多个通道使用不同的非易失性存储器单元阵列。
例如，图14中，假设存储器装置900中包括存储层110和存储层120，并假设存储 层110中包括通道1和通道2，通道1和通道2的描述可以参照上述实施例。类似的，存储层120中也可以包括通道1和通道2。
本公开实施方式提供的存储器装置，通过垂直堆叠的多层存储层，并且让每层存储层中包括多个通道，可以使得在同一个存储器装置中容纳更多的存储器单元阵列，同时不会加大存储器装置的面积，进一步满足高带宽需求，并通过每层存储层中的多个通道共享同一个反熔丝阵列，能够在这多个通道内统一调度该反熔丝阵列，实现均衡功能，避免了某些通道内的不可用的正常存储单元的数量较多导致没有足够的反熔丝单元存储失败地址，某些通道内的不可用的正常存储单元的数量较少导致有些反熔丝单元空闲的问题。同时，通过该反熔丝阵列集中存储每层存储层中的多个通道内的不可用的正常存储单元的失败地址，节约了反熔丝阵列所占据的面积，提高了存储器装置的集成度，降低了制作工艺的复杂度。
图15示意性示出了根据本公开的一实施例的存储器装置的示意图。
如图15所示，本公开实施例提供的存储器装置1000中的每层存储层还可以包括电荷泵、温度传感器和芯片标识存储器中的至少一个。
其中，电荷泵可以用于为对应存储层的所述多个通道、所述测试控制电路和/或所述非易失性存储器单元阵列提供电源。
温度传感器可以用于测试对应存储层的所述多个通道、所述测试控制电路和/或所述非易失性存储器单元阵列的温度。
芯片标识存储器可以用于存储对应存储层的芯片标识信息。
继续参考图15，存储器装置1000的每层存储层还可以包括共享模拟电路和电容。即本公开实施例中的每层存储层中的多个通道可以共享同一个非易失性存储器单元阵列、电荷泵、测试控制电路、共享模拟电路和电容、温度传感器和芯片标识存储器。
下面以存储器装置为DRAM(Dynamic Random Access Memory，动态随机存储器)为例进行举例说明，但本公开并不限定于此，存储器装置可以是任意一种能够实现存储功能的装置。
图16示意性示出了根据本公开的一实施例的三维集成电路的示意图。
如图16所示，以三维(3-dimension，3D)垂直堆叠的DRAM立方体(cube)为例，在逻辑控制电路上依次垂直堆叠DRAM核(core)#4、DRAM核#3、DRAM核#2、DRAM核#1。
三维堆叠DRAM是通过3D封装技术，将多层DRAM堆叠而成的新型内存，能够提供很大的内存容量和内存带宽。
图17示意性示出了根据本公开的一实施例的2.5维(2.5D)集成电路的示意图。
如图17所示，在转接板(interposer)上依次垂直堆叠DRAM核#4、DRAM核#3、DRAM核#2、DRAM核#1，同时，在该转接板上设置有逻辑控制电路。此时，通过转接板实现逻辑控制电路与各个DRAM核之间的数据通信。
需要说明的是，图16和17以四个DRAM核垂直堆叠为例进行举例说明，但实际上本公开对垂直堆叠的DRAM核的数量并不做限定。
图18示意性示出了根据本公开的一实施例的三维集成电路的示意图。
以上述图16三维集成电路为例，在图18实施例中，假设每个DRAM核包括两个通道，例如DRAM核#4、DRAM核#3、DRAM核#2、DRAM核#1各自包括通道1和通道2。
每个通道中可以包括一个单独的DRAM芯片，可以将多个通道中的多个DRAM芯片集成在一层存储层中，逻辑控制电路可以独立控制每个通道的引脚，也可以同时控制。
每个通道例如可以包括64根正常数据引脚，还可以包括8根ECC(Error Correcting Code，错误检查和校正)校验引脚。ECC校验引脚可以用于对从每个通道提供的数据执行错误检测和校正，可检测数据是否有错误并且可校正错误。
图19示意性示出了根据本公开的一实施例的三维集成电路中一层存储层的示意图。
如图19所示，以DRAM核#1作为存储器装置中的一层存储层为例进行举例说明，其包括通道1和通道2，通道1和通道2共享同一个非易失性存储器单元阵列、电荷泵、测试控制电路、共享模拟电路和电容、温度传感器和芯片标识存储器。
图19中，假设每个通道的存储器单元阵列包括4个存储块。例如通道1中的存储器单元阵列1包括存储块1至存储块4，通道2中的存储器单元阵列2包括存储块1至存储块4。
图19实施例中，假设每个通道的存储器单元阵列中的多个存储块共享备用单元阵列和锁存块，且共享的备用单元阵列和锁存块被分布式设置于各个存储块中，即统一调度同一个通道中的备用单元阵列中的备用存储单元和锁存块中的锁存器。
例如，通道1中的存储器单元阵列1中的存储块1中设置正常单元阵列11(假设包括正常存储单元11至18)、备用单元阵列11(假设包括备用存储单元11和备用存储单元12)和锁存块11(假设包括锁存器11和锁存器12)，存储块2中设置正常单元阵列12(假设包括正常存储单元21至28)、备用单元阵列12(假设包括备用存储单元21和备用存储单元22)和锁存块12(假设包括锁存器21和锁存器22)，存储块3中设置正常单元阵列13(假设包括正常存储单元31至38)、备用单元阵列13(假设包括备用存储单元31和备用存储单元32)和锁存块13(假设包括锁存器31和锁存器32)，存储块4中设置正常单元阵列14(假设包括正常存储单元41至48)、备用单元阵列14(假设包括备用存储单元41和备用存储单元42)和锁存块14(假设包括锁存器41和锁存器42)。
若通道1中的任意一个存储块中的失败地址的数量超过其内设置的锁存块的锁存器的数量，则可以调用通道1中的其他任意一个或者多个存储块中的锁存块的锁存器用于存储剩余的失败地址，也可以使用该其他任意一个或者多个存储块中的备用单元阵列的备用存储单元的访问地址作为剩余的失败地址的修复地址。
图19实施例中，可以将每个存储块中的备用单元阵列中的各个备用存储单元与对应 存储块中的锁存块中的锁存器一一对应。
图19实施例中，通道1中的读写控制电路1可以控制读写电路1交替轮流读写存储块1至存储块4。
图19中的通道2的描述可以参照通道1。
图20示意性示出了根据本公开的一实施例的三维集成电路中一层存储层的示意图。
如图20所示，还是以DRAM核#1为例，在测试阶段，测试控制电路可以从外部测试设备或者包括DRAM核#1的存储器系统中的存储器控制器接收测试指令，响应该测试指令，测试通道1的存储器单元阵列1中的存储块1至4中的正常单元阵列11至14和通道2中的存储器单元阵列2中的存储块2至4中的正常单元阵列11至14，获得测试失败的正常存储单元的访问地址作为失败地址。
然后，测试控制电路将获得的失败地址发送至反熔丝阵列的控制块，通过控制块将其存储至反熔丝阵列的反熔丝单元中。
在使用阶段，当DRAM核#1上电时，扫描主机将存储于反熔丝阵列的反熔丝单元中的失败地址转存至对应通道的对应锁存块中。
本公开实施方式还提供了一种存储器系统，该存储器系统可以包括：至少一层存储层以及存储器控制器。所述存储器控制器可以被构造为控制所述至少一层存储层。
存储器控制器可以将地址、命令和控制信号提供至每层存储层，以控制每层存储层的编程(或写)操作和读操作。例如命令可为读命令或写命令。例如，地址可以包括每层存储层中的向其写数据或从中读数据的位置。
其中，每层存储层可以包括：多个通道、测试控制电路和非易失性存储器单元阵列。
其中，所述多个通道中的每个通道可以包括存储器单元阵列，所述存储器单元阵列可以包括正常单元阵列，所述正常单元阵列可以包括多个正常存储单元，所述正常存储单元可以为易失性存储器单元。
测试控制电路可以用于响应测试指令，控制测试所述多个通道中的正常单元阵列，确定所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址作为失败地址。
非易失性存储器单元阵列可以包括多个非易失性存储器单元，非易失性存储器单元阵列可以用于从所述测试控制电路接收并存储所述失败地址。
在示例性实施例中，所述存储器控制器可以用于向所述测试控制电路提供所述测试指令。
在示例性实施例中，所述存储器系统可以连接外部测试设备，所述测试控制电路可以从所述外部测试设备接收所述测试指令。
本公开实施例提供的存储器系统的其他内容可以参照上述实施例中的存储器装置的描述。
本公开实时方式提供的存储器系统，一方面，通过让包括多个通道的存储器装置共享同一个非易失性存储器单元阵列，可以满足高带宽需求；另一方面，通过使用非易失性存 储器单元阵列中的非易失性存储器单元来存储该多个通道中的正常单元阵列中测试失败的不可用的正常存储单元的访问地址对应的失败地址，可以在该多个通道中的存储器单元阵列在掉电后，仍然能够获知该多个通道中的存储器单元阵列的哪个或者哪些正常存储单元是不可用的，这样，在下次重新上电后，不需要重新测试，节约了测试时间和成本，提高了测试效率，同时还可以保持每个通道中的存储器单元阵列所采用的易失性存储器单元的高速读写性能。
图21示意性示出了根据本公开的一实施例的存储器装置的测试方法的流程图。所述存储器装置可以包括多个通道和非易失性存储器单元阵列，每个通道可以包括存储器单元阵列，所述存储器单元阵列可以包括正常单元阵列，所述正常单元阵列可以包括正常存储单元，所述正常存储单元可以为易失性存储器单元，所述非易失性存储器单元阵列可以包括多个非易失性存储器单元。
如图21所示，本公开实施例提供的方法可以包括以下步骤。
在步骤S2110中，接收测试指令。
例如，可以通过存储器控制器向所述测试控制电路提供所述测试指令，也可以由与存储器装置连接的外部测试设备向所述测试控制电路提供所述测试指令，本公开实施例对测试指令的来源不做限定。
在步骤S2120中，根据所述测试指令控制测试所述多个通道中的正常单元阵列，确定所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址为失败地址。
在步骤S2130中，将所述失败地址发送并存储至所述非易失性存储器单元阵列。
本公开实施例提供的存储器装置的测试方法的其他内容可以参照上述存储器装置和存储器系统实施例的描述。
本公开实时方式提供的存储器装置的测试方法，一方面，通过让包括多个通道的存储器装置共享同一个非易失性存储器单元阵列，可以满足高带宽需求；另一方面，通过使用非易失性存储器单元阵列中的非易失性存储器单元来存储该多个通道中的正常单元阵列中测试失败的不可用的正常存储单元的访问地址对应的失败地址，可以在该多个通道中的存储器单元阵列在掉电后，仍然能够获知该多个通道中的存储器单元阵列的哪个或者哪些正常存储单元是不可用的，这样，在下次重新上电后，不需要重新测试，节约了测试时间和成本，提高了测试效率，同时还可以保持每个通道中的存储器单元阵列所采用的易失性存储器单元的高速读写性能。
本公开实施方式还提供了一种存储器装置的使用方法，所述存储器装置可以包括多个通道和非易失性存储器单元阵列，每个通道可以包括存储器单元阵列和锁存块，所述存储器单元阵列可以包括正常单元阵列，所述正常单元阵列包括正常存储单元，所述正常存储单元可以为易失性存储器单元，所述非易失性存储器单元阵列可以包括多个非易失性存储器单元，所述非易失性存储器单元阵列中可以存储有用于表示所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址的失败地址。
本公开实施例中，所述使用方法可以包括以下步骤：在所述存储器装置上电时，将所述非易失性存储器单元阵列中的所述失败地址转存至对应通道的锁存块中。
在示例性实施例中，所述锁存块可以包括第一数量的锁存器，所述存储器单元阵列还可以包括备用单元阵列，所述备用单元阵列可以包括所述第一数量的备用存储单元，所述备用存储单元可以为易失性存储器单元，每个通道中的锁存块中的各个锁存器可以与对应通道中的备用单元阵列中的各个备用存储单元一一对应。
其中，在所述存储器装置上电时，将所述非易失性存储器单元阵列中的所述失败地址转存至对应通道的锁存块中，可以包括：在所述存储器装置上电时，将所述非易失性存储器单元阵列中的所述失败地址转存至对应通道的锁存块中的对应锁存器，以确定用于替代所述失败地址的目标备用存储单元的访问地址作为修复地址。
在示例性实施例中，所述存储器单元阵列可以包括多个存储块，所述多个存储块可以共享备用单元阵列和锁存块，所述备用单元阵列可以包括第一数量的备用存储单元，所述备用存储单元可以为易失性存储器单元，所述锁存块可以包括所述第一数量的锁存器，所述非易失性存储器单元阵列还可以包括扫描主机，每个通道的锁存块和所述扫描主机均可以包括第一接口、第二接口和第三接口。
其中，在所述存储器装置上电时，将所述非易失性存储器单元阵列中的所述失败地址转存至对应通道的锁存块中，可以包括：通过每个通道的锁存块和所述扫描主机的第一接口接收使能信号；通过每个通道的锁存块和所述扫描主机的第二接口接收时钟信号；所述扫描主机的第三接口在所述使能信号为第一电平时，根据所述时钟信号，通过所述扫描主机的第三接口依次向每个通道的锁存块的第三接口发送通道地址、存储块地址和锁存块地址，以分别确定目标通道、所述目标通道的目标存储块及所述目标通道对应的目标锁存块中的目标锁存器，并向每个通道的锁存块的第三接口发送写命令，以通过所述目标通道的目标锁存块的第三接口将所述失败地址写入所述目标锁存块的目标锁存器中。
在示例性实施例中，每个通道的锁存块和所述扫描主机均还可以包括第四接口。
其中，当所述扫描主机的第三接口向每个通道的锁存块的第三接口发送读命令时，通过所述扫描主机的第四接口从所述目标锁存器读取数据；将写入的所述失败地址与读取的数据进行比较，验证写入的所述失败地址。
本公开实时方式提供的存储器装置的使用方法，可以将测试阶段测试出来并存储到非易失性存储器单元阵列中的失败地址转存至对应通道的对应锁存器中，从而可以在使用各个通道的正常单元阵列时，可以保持正常单元阵列中的易失性存储器单元较快的读写速度，并保证读写数据的准确性。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一 台计算设备(可以是个人计算机、服务器、触控终端、或者网络设备等)执行根据本公开实施方式的方法。
进一步地，本公开实施方式还提供了一种电子设备，包括：一个或多个处理器；存储装置，用于存储一个或多个程序；当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现上述任一实施例中所述的方法。
进一步地，本公开实施方式还提供了一种计算机可读存储介质，其上存储有计算机程序，所述程序被处理器执行时实现上述任一实施例中所述的方法。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (25)

  1. 一种存储器装置，其特征在于，包括：
    多个通道，每个通道包括存储器单元阵列，所述存储器单元阵列包括正常单元阵列，所述正常单元阵列包括正常存储单元，所述正常存储单元为易失性存储器单元；
    测试控制电路，用于响应测试指令，控制测试所述多个通道中的正常单元阵列，确定所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址为失败地址；
    非易失性存储器单元阵列，其包括多个非易失性存储器单元，用于从所述测试控制电路接收并存储所述失败地址。
  2. 根据权利要求1所述的存储器装置，其特征在于，所述非易失性存储器单元阵列包括反熔丝阵列。
  3. 根据权利要求1所述的存储器装置，其特征在于，所述非易失性存储器单元阵列包括：
    控制块，用于控制所述非易失性存储器单元阵列的编程，存储所述失败地址。
  4. 根据权利要求1所述的存储器装置，其特征在于，每个通道还包括锁存块；其中，所述非易失性存储器单元阵列还包括：
    扫描主机，用于在所述存储器装置上电时，将所述非易失性存储器单元阵列中的所述失败地址转存至对应通道的锁存块中。
  5. 根据权利要求4所述的存储器装置，其特征在于，所述锁存块包括第一数量的锁存器，所述存储器单元阵列还包括备用单元阵列，所述备用单元阵列包括所述第一数量的备用存储单元，所述备用存储单元为易失性存储器单元；其中，
    每个通道中的锁存块中的各个锁存器与对应通道中的备用单元阵列中的各个备用存储单元一一对应；
    所述扫描主机用于在所述存储器装置上电时，将所述非易失性存储器单元阵列中的所述失败地址转存至对应通道的锁存块中的对应锁存器，以确定用于替代所述失败地址的目标备用存储单元的访问地址作为修复地址。
  6. 根据权利要求5所述的存储器装置，其特征在于，每个通道还包括：
    读写电路，用于从所述测试控制电路接收所述测试指令，并响应所述测试指令将第一写数据写入对应通道的存储器单元阵列中的目标正常存储单元中，并比较从所述目标正常存储单元读取的第一读数据与所述第一写数据，基于比较结果输出指示所述目标正常存储单元测试通过或者测试失败的指示信号；以及
    读写控制电路，用于控制所述读写电路，并在所述指示信号指示所述目标正常存储单元测试失败时，将所述目标正常存储单元的访问地址作为所述失败地址，将所述失败地址返回至所述测试控制电路。
  7. 根据权利要求6所述的存储器装置，其特征在于，所述读写控制电路还用于控制 所述读写电路，以将准备写入由所述失败地址指定的所述目标正常存储单元的第二写数据写入由所述修复地址指定的所述目标备用存储单元。
  8. 根据权利要求5所述的存储器装置，其特征在于，所述正常单元阵列包括第二数量的正常存储单元，所述第二数量大于或等于所述第一数量。
  9. 根据权利要求1所述的存储器装置，其特征在于，所述存储器单元阵列包括多个存储块，所述多个存储块共享对应通道的备用单元阵列和锁存块，所述备用单元阵列包括第一数量的备用存储单元，所述备用存储单元为易失性存储器单元，所述锁存块包括所述第一数量的锁存器，所述非易失性存储器单元阵列还包括扫描主机；其中，
    每个通道的锁存块和所述扫描主机均包括第一接口、第二接口和第三接口；其中，
    每个通道的锁存块和所述扫描主机的第一接口均用于接收使能信号；
    每个通道的锁存块和所述扫描主机的第二接口均用于接收时钟信号；
    所述扫描主机的第三接口用于在所述使能信号为第一电平时，根据所述时钟信号，依次向每个通道的锁存块的第三接口发送通道地址、存储块地址和锁存块地址，以分别确定目标通道、所述目标通道的目标存储块及所述目标通道对应的目标锁存块中的目标锁存器，并向每个通道的锁存块的第三接口发送写命令，以通过所述目标通道的目标锁存块的第三接口将所述失败地址写入所述目标锁存块的目标锁存器中。
  10. 根据权利要求9所述的存储器装置，其特征在于，每个通道的锁存块和所述扫描主机均还包括第四接口；其中，
    当所述扫描主机的第三接口向每个通道的锁存块的第三接口发送读命令时，通过所述扫描主机的第四接口从所述目标锁存器读取数据，以将写入的所述失败地址与读取的数据进行比较，验证写入的所述失败地址。
  11. 根据权利要求9所述的存储器装置，其特征在于，每个通道还包括读写电路和读写控制电路，所述读写控制电路用于控制所述读写电路交替读写所述存储器单元阵列中的各个存储块。
  12. 根据权利要求1所述的存储器装置，其特征在于，所述非易失性存储器单元阵列还包括：
    模拟块，用于为所述非易失性存储器单元提供电源电压。
  13. 根据权利要求1所述的存储器装置，其特征在于，所述存储器装置包括垂直堆叠的多层存储层，每层存储层包括至少一个通道。
  14. 根据权利要求13所述的存储器装置，其特征在于，每层存储层包括所述多个通道、所述测试控制电路和所述非易失性存储器单元阵列。
  15. 根据权利要求14所述的存储器装置，其特征在于，每层存储层还包括：
    电荷泵，用于为对应存储层的所述多个通道、所述测试控制电路和/或所述非易失性存储器单元阵列提供电源。
  16. 根据权利要求14所述的存储器装置，其特征在于，每层存储层还包括：
    温度传感器，用于测试对应存储层的所述多个通道、所述测试控制电路和/或所述非易失性存储器单元阵列的温度。
  17. 根据权利要求14所述的存储器装置，其特征在于，每层存储层还包括：
    芯片标识存储器，用于存储对应存储层的芯片标识信息。
  18. 一种存储器系统，其特征在于，包括：
    至少一层存储层；以及
    存储器控制器，其被构造为控制所述至少一层存储层，
    其中，每层存储层包括：
    多个通道，每个通道包括存储器单元阵列，所述存储器单元阵列包括正常单元阵列，所述正常单元阵列包括多个正常存储单元，所述正常存储单元为易失性存储器单元；
    测试控制电路，用于响应测试指令，控制测试所述多个通道中的正常单元阵列，确定所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址作为失败地址；
    非易失性存储器单元阵列，其包括多个非易失性存储器单元，用于从所述测试控制电路接收并存储所述失败地址。
  19. 根据权利要求18所述的存储器系统，其特征在于，所述存储器控制器用于向所述测试控制电路提供所述测试指令。
  20. 根据权利要求18所述的存储器系统，其特征在于，所述存储器系统连接外部测试设备，所述测试控制电路从所述外部测试设备接收所述测试指令。
  21. 一种存储器装置的测试方法，其特征在于，所述存储器装置包括多个通道和非易失性存储器单元阵列，每个通道包括存储器单元阵列，所述存储器单元阵列包括正常单元阵列，所述正常单元阵列包括正常存储单元，所述正常存储单元为易失性存储器单元，所述非易失性存储器单元阵列包括多个非易失性存储器单元；其中，所述方法包括：
    接收测试指令；
    根据所述测试指令控制测试所述多个通道中的正常单元阵列，确定所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址为失败地址；
    将所述失败地址发送并存储至所述非易失性存储器单元阵列。
  22. 一种存储器装置的使用方法，其特征在于，所述存储器装置包括多个通道和非易失性存储器单元阵列，每个通道包括存储器单元阵列和锁存块，所述存储器单元阵列包括正常单元阵列，所述正常单元阵列包括正常存储单元，所述正常存储单元为易失性存储器单元，所述非易失性存储器单元阵列包括多个非易失性存储器单元，所述非易失性存储器单元阵列中存储有用于表示所述多个通道中的正常单元阵列中测试失败的正常存储单元的访问地址的失败地址；其中，所述方法包括：
    在所述存储器装置上电时，将所述非易失性存储器单元阵列中的所述失败地址转存至对应通道的锁存块中。
  23. 根据权利要求22所述的方法，其特征在于，所述锁存块包括第一数量的锁存器， 所述存储器单元阵列还包括备用单元阵列，所述备用单元阵列包括所述第一数量的备用存储单元，所述备用存储单元为易失性存储器单元，每个通道中的锁存块中的各个锁存器与对应通道中的备用单元阵列中的各个备用存储单元一一对应；其中，在所述存储器装置上电时，将所述非易失性存储器单元阵列中的所述失败地址转存至对应通道的锁存块中，包括：
    在所述存储器装置上电时，将所述非易失性存储器单元阵列中的所述失败地址转存至对应通道的锁存块中的对应锁存器，以确定用于替代所述失败地址的目标备用存储单元的访问地址作为修复地址。
  24. 根据权利要求22所述的方法，其特征在于，所述存储器单元阵列包括多个存储块，所述多个存储块共享备用单元阵列和锁存块，所述备用单元阵列包括第一数量的备用存储单元，所述备用存储单元为易失性存储器单元，所述锁存块包括所述第一数量的锁存器，所述非易失性存储器单元阵列还包括扫描主机，每个通道的锁存块和所述扫描主机均包括第一接口、第二接口和第三接口；其中，在所述存储器装置上电时，将所述非易失性存储器单元阵列中的所述失败地址转存至对应通道的锁存块中，包括：
    通过每个通道的锁存块和所述扫描主机的第一接口接收使能信号；
    通过每个通道的锁存块和所述扫描主机的第二接口接收时钟信号；
    所述扫描主机的第三接口在所述使能信号为第一电平时，根据所述时钟信号，通过所述扫描主机的第三接口依次向每个通道的锁存块的第三接口发送通道地址、存储块地址和锁存块地址，以分别确定目标通道、所述目标通道的目标存储块及所述目标通道对应的目标锁存块中的目标锁存器，并向每个通道的锁存块的第三接口发送写命令，以通过所述目标通道的目标锁存块的第三接口将所述失败地址写入所述目标锁存块的目标锁存器中。
  25. 根据权利要求24所述的方法，其特征在于，每个通道的锁存块和所述扫描主机均还包括第四接口；其中，
    当所述扫描主机的第三接口向每个通道的锁存块的第三接口发送读命令时，通过所述扫描主机的第四接口从所述目标锁存器读取数据；
    将写入的所述失败地址与读取的数据进行比较，验证写入的所述失败地址。
PCT/CN2021/099238 2020-09-15 2021-06-09 存储器装置及其测试方法和使用方法、存储器系统 WO2022057333A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21868167.4A EP4036917B1 (en) 2020-09-15 2021-06-09 Memory device, testing method therefor and usage method therefor, and memory system
US17/446,143 US11854640B2 (en) 2020-09-15 2021-08-26 Memory device, testing method and using method thereof, and memory system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010966642.2 2020-09-15
CN202010966642.2A CN114187954A (zh) 2020-09-15 2020-09-15 存储器装置及其测试方法和使用方法、存储器系统

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/446,143 Continuation US11854640B2 (en) 2020-09-15 2021-08-26 Memory device, testing method and using method thereof, and memory system

Publications (1)

Publication Number Publication Date
WO2022057333A1 true WO2022057333A1 (zh) 2022-03-24

Family

ID=80601178

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/099238 WO2022057333A1 (zh) 2020-09-15 2021-06-09 存储器装置及其测试方法和使用方法、存储器系统

Country Status (2)

Country Link
CN (1) CN114187954A (zh)
WO (1) WO2022057333A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030107926A1 (en) * 2001-10-12 2003-06-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device provided with memory chips
US20100131812A1 (en) * 2008-11-26 2010-05-27 Qualcomm Incorporated Resizable Cache Memory
CN103295648A (zh) * 2012-02-29 2013-09-11 三星电子株式会社 修复存储器单元的设备和方法及包括该设备的存储器系统
CN103733260A (zh) * 2011-07-25 2014-04-16 高通股份有限公司 非易失性存储器阵列中的保存单元信息的非易失性存储器
CN110021333A (zh) * 2017-11-23 2019-07-16 三星电子株式会社 存储器装置和存储器系统
CN212675921U (zh) * 2020-09-15 2021-03-09 长鑫存储技术有限公司 存储器装置和存储器系统

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101032671B1 (ko) * 2008-03-01 2011-05-06 가부시끼가이샤 도시바 메모리 시스템
US9953725B2 (en) * 2012-02-29 2018-04-24 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods of operating the same
KR20160148347A (ko) * 2015-06-16 2016-12-26 에스케이하이닉스 주식회사 셀프 리페어 장치 및 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030107926A1 (en) * 2001-10-12 2003-06-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device provided with memory chips
US20100131812A1 (en) * 2008-11-26 2010-05-27 Qualcomm Incorporated Resizable Cache Memory
CN103733260A (zh) * 2011-07-25 2014-04-16 高通股份有限公司 非易失性存储器阵列中的保存单元信息的非易失性存储器
CN103295648A (zh) * 2012-02-29 2013-09-11 三星电子株式会社 修复存储器单元的设备和方法及包括该设备的存储器系统
CN110021333A (zh) * 2017-11-23 2019-07-16 三星电子株式会社 存储器装置和存储器系统
CN212675921U (zh) * 2020-09-15 2021-03-09 长鑫存储技术有限公司 存储器装置和存储器系统

Also Published As

Publication number Publication date
CN114187954A (zh) 2022-03-15

Similar Documents

Publication Publication Date Title
CN106548807B (zh) 修复电路、使用它的半导体装置和半导体系统
US8874979B2 (en) Three dimensional(3D) memory device sparing
US11314590B2 (en) Memory device for detecting a defective memory chip
CN212675921U (zh) 存储器装置和存储器系统
US7401270B2 (en) Repair of semiconductor memory device via external command
CN107430558B (zh) 半导体存储装置
US10395748B2 (en) Shared error detection and correction memory
CN102456394A (zh) 执行dram刷新操作的存储电路、系统和模块及其操作方法
CN107919160B (zh) 测试单元阵列的方法及执行其的半导体器件
US11232849B2 (en) Memory device with a repair match mechanism and methods for operating the same
JP2009176384A (ja) 半導体記憶装置
US20130051167A1 (en) Semiconductor memory device and defective cell relieving method
US20190180840A1 (en) Stacked memory device using base die spare cell and method of repairing the same
US10976368B2 (en) Memory apparatus relating to determination of a failed region and test method thereof, memory module and system using the same
WO2022057333A1 (zh) 存储器装置及其测试方法和使用方法、存储器系统
CN116543823A (zh) 存储器装置及其自修复方法、芯片及其测试方法
US10553276B2 (en) Semiconductor memory device
US9236142B2 (en) System method and apparatus for screening a memory system
US11854640B2 (en) Memory device, testing method and using method thereof, and memory system
CN113362883B (zh) 可配置软封装后修复(sppr)方案
US10460769B2 (en) Memory device including error detection circuit
EP4312219A2 (en) Memory system, operating method of the same, and controller of memory device
CN111951845B (zh) 一种分级管理冗余存储的mram芯片

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21868167

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021868167

Country of ref document: EP

Effective date: 20220429

NENP Non-entry into the national phase

Ref country code: DE