WO2022057333A1 - Dispositif de mémoire, procédé de test associé et procédé d'utilisation associé, et système de mémoire - Google Patents

Dispositif de mémoire, procédé de test associé et procédé d'utilisation associé, et système de mémoire Download PDF

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Publication number
WO2022057333A1
WO2022057333A1 PCT/CN2021/099238 CN2021099238W WO2022057333A1 WO 2022057333 A1 WO2022057333 A1 WO 2022057333A1 CN 2021099238 W CN2021099238 W CN 2021099238W WO 2022057333 A1 WO2022057333 A1 WO 2022057333A1
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Prior art keywords
cell array
channel
memory
normal
address
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PCT/CN2021/099238
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English (en)
Chinese (zh)
Inventor
寗树梁
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21868167.4A priority Critical patent/EP4036917B1/fr
Priority to US17/446,143 priority patent/US11854640B2/en
Publication of WO2022057333A1 publication Critical patent/WO2022057333A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a memory device, a memory system, a method for testing the memory device, and a method for using the memory device.
  • Volatile memory is widely used in various electronic devices because of its fast read and write speed. As the integration level increases, a volatile memory chip includes more and more normal memory cells. If one of the normal memory cells is unavailable, or even the entire row or column of normal memory cells cannot be used, the entire chip may become unusable. Chips are unavailable, severely reducing the yield of chips.
  • a spare storage unit other than the normal storage unit is usually set in the volatile memory chip to replace the above-mentioned unusable normal storage unit, that is, the normal storage unit means that the test will be preferentially used for data when the test is successful.
  • the read-write storage unit, the spare storage unit refers to the normal storage unit that is used to replace the unavailable normal storage unit when one or some storage units are unavailable.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a memory device, a memory system, a method for testing a memory device, and a method for using the memory device, which can overcome the above-mentioned related art that meets the high-bandwidth requirements, including multiple In the memory device of the channel, how to perform redundant replacement more efficiently.
  • a memory device comprising: a plurality of channels, each channel comprising an array of memory cells, the array of memory cells comprising an array of normal cells, the array of normal cells comprising normal memory cells , the normal storage unit is a volatile memory unit; the test control circuit is used to respond to the test instruction, control and test the normal cell arrays in the multiple channels, and determine that the test fails in the normal cell arrays in the multiple channels
  • the access address of the normal storage unit is the failure address;
  • the non-volatile memory cell array which includes a plurality of non-volatile memory cells, is used for receiving and storing the failure address from the test control circuit.
  • a memory system including: at least one storage layer; and a memory controller configured to control the at least one storage layer.
  • each layer of storage layer includes: a plurality of channels, each channel includes a memory cell array, the memory cell array includes a normal cell array, the normal cell array includes a plurality of normal storage cells, and the normal storage cells are volatile
  • the test control circuit is used for responding to the test instruction, controlling and testing the normal cell arrays in the multiple channels, and determining the access addresses of the normal memory cells that fail the test in the normal cell arrays in the multiple channels as failures address; an array of non-volatile memory cells including a plurality of non-volatile memory cells for receiving and storing the failed address from the test control circuit.
  • the testing method includes: receiving a test instruction; controlling and testing the normal cell arrays in the multiple channels according to the test instruction, and determining the access of the normal memory cells that fail the test in the normal cell arrays in the multiple channels
  • the address is the fail address; the fail address is sent and stored to the array of non-volatile memory cells.
  • a method of using a memory device including a plurality of channels and an array of non-volatile memory cells, each channel including an array of memory cells and a latch block, the array of memory cells including a normal cell array, the normal cell array including normal memory cells, the normal memory cells being volatile memory cells, the non-volatile memory cell array including a plurality of non-volatile memory cells, the non-volatile memory cells A failure address representing an access address of a normal memory cell that fails the test in the normal cell array in the plurality of channels is stored in the volatile memory cell array.
  • the using method includes: when the memory device is powered on, dumping the failed address in the non-volatile memory cell array to a latch block of a corresponding channel.
  • Some embodiments of the present disclosure provide a memory device, a memory system, a method for testing a memory device, and a method for using the memory device.
  • the memory device including multiple channels share the same non-volatile memory cell array, the Satisfying the high bandwidth requirement; on the other hand, by using the non-volatile memory cells in the non-volatile memory cell array to store the access addresses of the unusable normal memory cells in the normal cell array in the plurality of channels that have failed the test
  • the corresponding failure address can still know which or which normal memory cells of the memory cell array in the multiple channels are unavailable after the memory cell array in the multiple channels is powered off. After power-on, there is no need to re-test, which saves test time and cost, improves test efficiency, and at the same time maintains the high-speed read and write performance of the volatile memory cells used in the memory cell array in each channel.
  • FIG. 1 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 2 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 3 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 4 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 5 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 6 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • Figure 7 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • Figure 8 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • FIG. 9 schematically shows a schematic diagram of each interface of a scan host and a latch block of each channel according to an embodiment of the present disclosure.
  • FIG. 10 schematically shows the timing diagram of each signal in FIG. 9 .
  • Figure 11 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • FIG. 12 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 13 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 14 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 15 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • FIG. 16 schematically shows a schematic diagram of a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • FIG. 17 schematically shows a schematic diagram of a 2.5-dimensional integrated circuit according to an embodiment of the present disclosure.
  • FIG. 18 schematically shows a schematic diagram of a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • FIG. 19 schematically shows a schematic diagram of a memory layer in a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • FIG. 20 schematically shows a schematic diagram of a memory layer in a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • FIG. 21 schematically shows a flowchart of a method for testing a memory device according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • FIG. 1 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • a memory device 100 provided by an embodiment of the present disclosure may include multiple channels, a test control circuit, and a non-volatile memory cell array.
  • the memory device 100 includes channel 1 and channel 2 as an example for illustration, but the present disclosure does not limit the number of channels, as long as it is greater than or equal to 2.
  • Each channel may include an array of memory cells, each array of memory cells may include an array of normal cells, each array of normal cells may include normal memory cells, and each normal memory cell may be a volatile memory cell.
  • the volatile memory unit refers to a memory unit in which data stored therein will be lost after a power failure.
  • channel 1 may include memory cell array 1
  • memory cell array 1 may include normal cell array 1
  • normal cell array 1 may include normal memory cells 1 to 12
  • channel 2 may include memory cell array 2
  • memory cell array 2 may include normal cell array 2
  • normal cell array 2 may also include normal memory cell 1 to normal memory cell 12 .
  • each normal cell array shown in FIG. 1 includes 12 normal memory cells only for illustration, and in fact, the number of normal memory cells included in each normal cell array can be designed according to actual requirements. , which is not limited in the present disclosure.
  • These normal cell arrays may be composed of a plurality of memory blocks (Banks), and normal memory cells in the normal cell arrays may be connected to different word lines and bit lines.
  • the test control circuit may be configured to respond to the test command, control the normal cell arrays in the plurality of channels to test the memory device 100, and determine the normal storage failures in the test in the normal cell arrays in the plurality of channels.
  • the access address of the unit is the failure address.
  • each failure address in the embodiment of the present disclosure may be one or any combination of a row address, a column address, a memory block (Bank) address, etc. of a single normal memory cell.
  • the present disclosure does not limit this, and the meaning referred to by a failure address can be determined as required.
  • the non-volatile memory cell array may include a plurality of non-volatile memory cells.
  • the non-volatile memory unit refers to the memory unit in which the data stored therein will not be lost in the event of a power failure.
  • An array of non-volatile memory cells may be used to receive and store the fail address from the test control circuit.
  • non-volatile memory cells 1 to 5 are included in the non-volatile memory cell array, but the number of non-volatile memory cells here is only for illustration, and in fact non-volatile memory cells
  • the non-volatile memory cells included in the cell array can be designed according to actual requirements, which is not limited in the present disclosure.
  • the non-volatile memory cells may be implemented in any of various forms.
  • fuse fuse
  • electric fuse efuse
  • anti-fuse anti-fuse
  • magnetic memory Magnetic Random Access Memory, MRAM
  • iron memory Feroelectric RAM, FeRAM
  • flash memory Flash etc. to implement non-volatile memory cells.
  • the memory device provided by the present disclosure in a real-time manner can meet the high bandwidth requirement by allowing the memory device including multiple channels to share the same non-volatile memory cell array; on the other hand, by using the non-volatile memory cell
  • the non-volatile memory cells in the array are used to store the failure addresses corresponding to the access addresses of the unusable normal memory cells that have failed the test in the normal cell arrays in the plurality of channels, and the memory cell arrays in the plurality of channels can be After the power is turned off, it is still possible to know which or which normal memory cells in the memory cell array in the multiple channels are unavailable.
  • FIG. 2 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the difference between the memory device 200 provided in the embodiment of FIG. 2 and the memory device 100 provided by the above-mentioned embodiment of FIG. 1 is that the non-volatile memory cell array may include an anti-fuse array, and the corresponding non-volatile memory cells may be Antifuse unit.
  • anti-fuse unit 1 in FIG. 2 may correspond to non-volatile memory unit 1 in FIG. 1
  • anti-fuse unit 2 may correspond to non-volatile memory unit 2 in FIG. 1
  • anti-fuse unit 3 may Corresponding to the non-volatile memory unit 3 in FIG. 1
  • the anti-fuse unit 4 may correspond to the non-volatile memory unit 4 in FIG. 1
  • the anti-fuse unit 5 may correspond to the non-volatile memory unit 5 in FIG. 1 .
  • the non-volatile memory cell array is taken as an example of an anti-fuse array for illustration, but the present disclosure is not limited to this, the non-volatile memory in the non-volatile memory cell array
  • the unit can also be implemented by using any other unit with a non-volatile storage function.
  • FIG. 3 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the anti-fuse array may further include a control block (Control Block).
  • the control block may be used to control the programming of the anti-fuse array, and store the failure address received from the test control circuit in the anti-fuse unit in the anti-fuse array.
  • an anti-fuse array is used as a non-volatile memory cell array, and the anti-fuse cells in the anti-fuse array are used as non-volatile memory cells for storing in a normal cell array. Because the anti-fuse unit is small, it occupies a small chip area, is easy to implement, can resist radiation and interference, and is not affected by electromagnetic radiation.
  • FIG. 4 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the difference between the memory device 400 provided by the embodiment of FIG. 4 and the memory device 300 provided by the above-mentioned embodiment of FIG. 3 is that each channel may further include a latch block.
  • channel 1 may further include latch block 1
  • channel 2 may further include latch block 2 .
  • the anti-fuse array may further include a scan host (Scan Host).
  • the scan host may be configured to dump the failed address stored in the antifuse array to the latch block of the corresponding channel when the memory device 400 is powered on.
  • the failed addresses stored in the antifuse array may be dumped into latch block 1 of channel 1 and/or latch block 2 of channel 2 .
  • each normal memory cell in the normal cell array in the memory cell array of each channel is a volatile memory cell.
  • these failed addresses need to be stored in a non-volatile memory cell array using non-volatile memory cells, such as an anti-fuse array.
  • non-volatile memory cells such as an anti-fuse array.
  • the read failure address in the nonvolatile memory cell array is used, since the read data speed of the nonvolatile memory cell is slower than that of the volatile memory cell, the required failure address cannot be obtained in time.
  • the failed address stored in the non-volatile memory cell array is dumped into the latch block of the corresponding channel, so that the memory device can be read and written. Unusable normal storage units are quickly replaced or not used in the process.
  • FIG. 5 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • each latch block may include a first number of latches
  • each memory cell array may further include a spare Cell arrays
  • each spare cell array may include the first number of spare storage units
  • each spare storage unit is a volatile memory unit.
  • the latch block can also be replaced by a register block, that is, the function of the latch is implemented by using the registers in the register block.
  • each spare storage unit in the embodiment of the present disclosure may include a volatile memory unit (corresponding to the failure address being the access address of a single normal storage unit), or may include a row of volatile memory units on a word line volatile memory cell (corresponding to the failure address is the row address), or a column of volatile memory cells on a bit line (corresponding to the failure address is the column address), or a memory block of volatile memory cells (corresponding to the failure address is the memory block address), etc.
  • a volatile memory unit corresponding to the failure address being the access address of a single normal storage unit
  • a row of volatile memory units on a word line volatile memory cell corresponding to the failure address is the row address
  • a column of volatile memory cells on a bit line corresponding to the failure address is the column address
  • a memory block of volatile memory cells corresponding to the failure address is the memory block address
  • the latch block 1 may include four latches, such as latch 1 to latch 4 . It should be noted that a latch in this embodiment represents a latch capable of storing a failed address.
  • the memory cell array 2 in the channel 2 may include a normal cell array 2 and a spare cell array 2
  • the spare cell array 2 may include four spare memory cells, such as spare memory cells 1 to 4
  • the latch block 2 may include four latches, such as latch 1 to latch 4 .
  • each latch in the latch block in each channel may be set in a one-to-one correspondence with each spare memory cell in the spare cell array in the corresponding channel.
  • the latch 1 in the latch block 1 in the channel 1 corresponds to the spare memory cell 1 in the spare cell array 1 in the channel 1
  • the lock in the latch block 1 in the channel 1 corresponds to
  • the register 2 corresponds to the spare storage unit 2 in the spare cell array 1 in the channel 1
  • the latch 3 in the latch block 1 in the channel 1 corresponds to the spare storage unit 3 in the spare cell array 1 in the channel 1
  • the latch 4 in the latch block 1 in the channel 1 corresponds to the spare storage unit 4 in the spare cell array 1 in the channel 1 .
  • the latch 1 in the latch block 2 in the channel 2 corresponds to the spare memory cell 1 in the spare cell array 2 in the channel 2
  • the latch 2 in the latch block 2 in the channel 2 corresponds to the
  • the spare storage unit 2 in the spare cell array 2 corresponds to the latch 3 in the latch block 2 in the channel 2 corresponding to the spare storage unit 3 in the spare cell array 2 in the channel 2
  • the latch block in the channel 2 corresponds to Latches 4 in 2 correspond to spare memory cells 4 in spare cell array 2 in channel 2.
  • the scan host in the anti-fuse array may be configured to dump the failed address in the anti-fuse array to the corresponding latch in the latch block of the corresponding channel when the memory device 500 is powered on to determine the access address of the target spare storage unit for replacing the failed address as the repair address.
  • the memory cell array 1 in the channel 1 will be The access address of the normal memory cells 1 to 4 in the first row of the normal cell array 1 is stored as a fail address to the anti-fuse cell 1 in the anti-fuse array. Then when the memory device 500 is powered on, the scan host can transfer the failed addresses of the normal memory cells 1 to 4 in the first row of the normal memory cells 1 to 4 in the memory cell array 1 in the channel 1 stored in the anti-fuse unit 1.
  • the access address of the spare memory cell 1 in the spare cell array 1 serves as a repair address to replace the failed addresses of the normal memory cells 1 to 4 of the first row of the normal cell array 1 in the memory cell array 1 in the channel 1 .
  • the normal storage unit represents a single storage unit
  • the spare storage unit represents multiple storage units, which is not limited in this embodiment, and the above description is only for illustrating this embodiment.
  • the memory cell in the channel 1 The access address of the normal memory cell 1, normal memory cell 5 and normal memory cell 9 in the first column of the normal cell array 1 in the cell array 1 is used as a failure address, and is stored in the anti-fuse cell in the anti-fuse array. 2.
  • the scan host can transfer the normal memory cell 1, normal memory cell 5 and normal memory cell 5 of the first column of the normal cell array 1 in the memory cell array 1 stored in the anti-fuse unit 2 to If the failed address of the normal storage unit 9 is transferred to the latch 2 in the latch block 1 of the channel 1, it can be determined to use the spare storage unit in the spare cell array 1 corresponding to the latch 2 in the latch block 1 2 As the target spare storage unit, use the access address of the spare storage unit 2 in the spare cell array 1 as the normal storage unit 1 and the normal storage unit in the first column of the normal cell array 1 in the memory cell array 1 in the replacement channel 1. 5 and the repair address of the failed address of normal memory cell 9.
  • each normal cell array may include a second number of normal memory cells, which may be greater than or equal to the first number.
  • the normal cell array 1 in the channel 1 is assumed to include 12 (that is, the second number is assumed to be 12, but the present disclosure is not limited to this) normal memory cells, and the spare cell array 1 in the channel 1 includes 4
  • a number of spare storage units, that is, the number of spare storage units in the same channel is generally set to be smaller than the number of normal storage units.
  • each latch in the latch block in each channel is set in a one-to-one correspondence with each spare storage unit in the spare cell array in the corresponding channel, and each spare storage unit is not strictly required.
  • the spare storage unit 1 in the spare unit array 1 can also be set.
  • latch 2 in latch block 1 corresponds to latch 2 in latch block 1.
  • the non-volatile memory unit needs to remember which normal memory cells are unavailable, and specify which spare memory cells to replace.
  • These spare memory cells designated for replacement are called target spares.
  • the access address of the target spare storage unit is called the repair address.
  • the embodiment of the present disclosure sets the latch in the latch block of each channel and the spare cell of the corresponding channel by setting the latch in the latch block of each channel
  • the spare storage units in the array are in one-to-one correspondence, so that when the failed address is stored to which latch is determined, it can be determined which spare storage unit is used as the target spare storage unit to replace the normal storage unit corresponding to the failed address, thereby reducing the storage capacity of the latch block.
  • the failed address and its repair address stored in the non-volatile memory cell array can also be transferred to the latches in the latch block of the corresponding channel at the same time.
  • the number of latches will be more than the number of spare storage units in the corresponding channel.
  • FIG. 6 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the read-write circuit may be configured to receive the test command from the test control circuit, and respond to the test command to write the first write data into the target normal storage unit in the memory cell array of the corresponding channel, and compare the The first read data and the first write data read by the target normal storage unit output an indication signal indicating that the target normal storage unit has passed or failed the test based on the comparison result.
  • the read-write control circuit can be used to control the read-write circuit, and when the indication signal indicates that the target normal storage unit fails to test, the access address of the target normal storage unit is used as the failure address, and the A failed address is returned to the test control circuit.
  • the channel 1 may further include a read-write circuit 1 and a read-write control circuit 1 .
  • Channel 2 may also include a read-write circuit 2 and a read-write control circuit 2 .
  • the read-write circuit 1 can receive the test command from the test control circuit, and in response to the received test command, write the first write data into the target normal memory cell in the memory cell array 1 of the channel 1, for example, it is assumed to write in rows , it is assumed that the first write data is first written into the normal memory cells 1 to 4 of the normal cell array 1, and then the first read data is read row by row from the normal memory cells 1 to 4 of the normal cell array 1. If the write data is consistent with the corresponding first read data, it means that the corresponding normal memory cell test passes; if the first write data and the corresponding first read data are inconsistent, it means that the corresponding normal memory cell test fails. By performing the test row by row in sequence, an indication signal of the test pass or test failure of the normal memory cells in each row of the entire normal cell array 1 can be obtained. The access address of the normal memory cell that fails the test is returned to the test control circuit as the failure address.
  • the read-write control circuit may be further configured to control the read-write circuit to write the second write data to be written to the target normal memory cell specified by the failed address by the target spare storage unit specified by the repair address.
  • the normal memory cells in the memory cell array of each channel are tested before the memory device leaves the factory to compare whether the read and write data are consistent, so as to obtain the failure address of the unusable normal memory cell, and then The failed address is stored in the non-volatile memory cell array, so that when subsequent read and write operations are performed on normal storage cells in the memory device, the target spare storage cell represented by the repair address corresponding to the failed address can be used to replace Drop the corresponding unusable normal storage unit to read and write data.
  • FIG. 7 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • each memory cell array may include a plurality of memory blocks.
  • channel 1 is taken as an example, and the memory cell array 1 in channel 1 includes two memory blocks (ie, memory block 1 and memory block 2) as an example for illustration, but in fact, each memory
  • the number of storage blocks included in the cell array can be set according to actual application scenarios, which is not limited in the present disclosure.
  • the memory block 1 includes a normal cell array 11
  • the normal cell array 11 is assumed to include normal memory cells 11 to 18
  • the normal cell array 12 is included in the memory block 2
  • the normal cell array 12 is assumed to include the normal memory cells 21 to 28.
  • the normal cell array 1 in the above embodiment may include the normal cell array 11 and the normal cell array 12 in the embodiment of the present disclosure.
  • the plurality of memory blocks in each channel may share the spare cell array and latch block of the corresponding channel
  • the spare cell array of the corresponding channel may include a first number (assuming equal to 4 in FIG. 7 ) of Spare memory cells (eg, spare memory cells 11, 12, 21, and 22 in FIG. 7)
  • each spare memory cell is a volatile memory cell
  • the latch block of each channel may include the first number of latches (eg, latches 11, 12, 21, and 22 in FIG. 7).
  • the spare cell array 1 in the memory cell array 1 in the channel 1 is assumed to include the spare cell array 11 provided in the memory block 1 and the spare cell array 12 provided in the memory block 2, and the latch block 1 Assume that the latch block 11 provided in the memory block 1 and the latch block 12 provided in the memory block 2 are included. It is assumed that the spare cell array 11 in the storage block 1 includes the spare storage unit 11 and the spare storage unit 12 , and the spare cell array 12 in the storage block 2 includes the spare storage unit 21 and the spare storage unit 22 . It is assumed that latch block 11 in memory block 1 includes latch 11 and latch 12 , and latch block 12 in memory block 2 includes latch 21 and latch 22 .
  • spare cell arrays and the latch blocks in the embodiment of FIG. 7 can be distributed in each storage block, during deployment, multiple storage blocks in the same channel can share all the spare cell arrays and latch blocks in the channel .
  • the spare storage unit 11 may also be set to correspond to the latch 11, the spare storage unit 12 to correspond to the latch 12, the spare storage unit 21 to correspond to the latch 21, and the spare storage unit 22 to correspond to the latch device 22 corresponds.
  • Figure 8 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • the spare cell array and the latch block may not be combined.
  • the latch blocks are distributed in each memory block, and the spare cell array and the latch block of the corresponding channel can be collectively provided outside the plurality of memory blocks.
  • memory block 1 includes normal cell array 11
  • normal cell array 11 is assumed to include normal memory cells 11 to 18
  • memory block 2 includes normal cell array 12
  • normal cell array 12 includes normal memory cells 22 to 28 .
  • a spare cell array 1 is centrally arranged in the memory cell array 1 of the channel 1, and the spare cell array 1 includes spare memory cells 1 to 4.
  • a latch block 1 including latches 1 to 4 is collectively provided in the memory cell array 1 of the channel 1 outside the memory block 1 and the memory block 2 .
  • the spare storage units 1 to 4 may also be set in a one-to-one correspondence with the latches 1 to 4 respectively.
  • a normal storage unit in each channel is divided into a plurality of storage blocks, regardless of whether the latches and spare storage units in each channel are distributed and provided in each storage block , or centrally set in the corresponding channel, by sharing the latch in the latch block in each channel and the spare storage unit in the spare cell array, it can solve the problem in some storage blocks in some cases.
  • the purpose of equalization can be achieved by uniformly scheduling the latches and spare storage units in each channel.
  • FIG. 9 schematically shows a schematic diagram of each interface of a scan host and a latch block of each channel according to an embodiment of the present disclosure.
  • FIG. 10 schematically shows the timing diagram of each signal in FIG. 9 . It can be known from the above embodiments that the non-volatile memory cell array may further include a scan host.
  • the latch block of each channel and the scan host may include a first interface, a second interface, and a third interface.
  • the first interface of the latch block of each channel and the first interface of the scan host can be used to receive the enable signal Se;
  • the second interface of the latch block of each channel and the scan host's first interface can be used to receive the enable signal Se;
  • the second interface may be used to receive the clock signal SC.
  • the third interface of the scan host can be used for the enable signal received at the first interface of the scan host to be a first level (for example, a high level in FIG. 10 , but the present disclosure is not limited to this, it also When the first level can be set as a low level), according to the clock signal SC received by the second interface of the scanning host, the latch block of each channel, such as the latch block 1 of channel 1 and the latch block of channel 2, is sequentially sent to the The third interface from latch block 2 to latch block n of channel n (n is a positive integer greater than or equal to 2) sends the channel address, storage block address and latch block address (transmitted sequentially through the Si signal in Figure 10) , so as to determine the target channel, the target memory block of the target channel and the target latch in the target latch block corresponding to the target channel from the plurality of channels.
  • a first level for example, a high level in FIG. 10 , but the present disclosure is not limited to this, it also When the first level can be set as a low level
  • the third interface of the scanning host After the third interface of the scanning host sends the above-mentioned channel address, storage block address and latch block address to each latch block of each channel through the Si signal, it can then send a command (R/W), for example, if it is a high level , the command is a read command, that is, the data frame is read from the target channel; if it is low, the command is a write command, that is, the data frame is written to the target channel. For example, here is the target of writing the failed address to the target channel. in the latches of the latch block.
  • the third interface of the scanning host first sends a write command to the third interface of each latch block of each channel. After receiving the write command, the third interface of the target latch block of the target channel will send the write command to the scanning host.
  • the third interface of the scanning host returns a response signal (ACK). After the third interface of the scanning host receives the response signal, it can continue to send data to the third interface of each latch block of each channel through the third interface of the scanning host. frame, the failed address is carried in the data frame, so that the failed address is transferred to the target latch.
  • the memory device provided by the embodiment of the present disclosure can correctly transfer the failed address from the non-volatile memory unit to the latch through the above-mentioned first to third interfaces and their corresponding enable signals, clock signals and Si signals In the device, so as to be able to achieve fast reading and writing of the normal cell array of each channel.
  • the latch block of each channel and the scan host further include a fourth interface.
  • the third interface of the scanning host sends a read command to the third interface of the latch block of each channel
  • data is read from the target latch through the fourth interface of the scanning host (through So signal) to compare the written failed address with the read data to verify whether the written failed address is correctly written.
  • the failed address can be correctly transferred from the non-volatile memory unit. into the latches to enable fast reads and writes of the normal cell array for each channel.
  • the failed address dumped into the target latch can also be read out through the fourth interface to verify whether the written failed address is correct, so as to ensure correct reading and writing of the normal cell array of each channel.
  • each latch in each channel and each spare storage unit in the corresponding channel may be mapped one by one in advance. For example, if there are 100 spare storage units in a channel, you can set or use 100 One latch corresponds to one spare storage unit. Assuming that the failed address is stored in the fifth latch, the access address of the fifth spare storage unit can be used as the repair address of the failed address, so that There is no need to use latches to store both a failed address and its repair address.
  • the sending sequence of the channel address, the storage block address and the latched block address can be changed.
  • the scanning host can send the latched block address first, and when a channel monitors the latched block address and its internal When the latch blocks are consistent and the internal latch blocks are available, a response signal can be returned to the scan host. In this way, the scan host can determine in advance whether the target latch block of the target channel is available, so that it can quickly know whether the target channel is available. Continue to send the failed address to this target channel.
  • the scanning host when the start of the write operation of the failed address is enabled by the enable signal, can determine which target channel to write the failed address to by sending the channel address. After the target channel receives the channel address, it can also Reply a response signal to the scanning host to inform the scanning host that it has normally monitored the channel address, so that the scanning host can continue to send the relevant data of the failed address to the target channel; the scanning host then sends the memory block address to inform the current failed address to be stored. Corresponds to the normal storage unit in which target storage block in the target channel, and then sends the latch block address to tell which target latch in the target latch block of the target channel to store the failed address, so as to determine how Dump the failed address into the corresponding latch of the corresponding channel.
  • the fourth interface of the target latch block corresponding to the target channel may be configured to send a response signal to the fourth interface of the scan host after receiving the latch block address, for notifying The scanning host has received the latched block address.
  • the fourth interface of the other latch blocks of the non-target latch block corresponding to the other channels of the non-target channel compares it with its own latch block address, and if it is found inconsistent, it will not send the The fourth interface of the scanning host sends a response signal.
  • Figure 11 schematically shows a schematic diagram of a channel according to an embodiment of the present disclosure.
  • each channel may further include a read/write circuit and a read/write control circuit, and when each channel includes multiple memory blocks, the read/write control circuit may be used to control the read/write circuit to alternately read Each memory block in the array of memory cells is written.
  • channel 1 is used as an example for illustration. It is assumed that memory cell array 1 of channel 1 includes memory block 1 and memory block 2, and channel 1 also includes read-write circuit 1 And read and write control circuit 1. Then the read-write control circuit 1 can control the read-write circuit 1 to alternately read and write the memory block 1 and the memory block 2 in the memory cell array 1 .
  • the reading and writing in the storage block cannot be completed in real time, and alternately reading and writing each storage block in the same channel can make the operation speed of the same channel faster, From the outside, it seems that data is being read and written in real time, thereby improving the overall read and write speed of each channel.
  • FIG. 12 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the anti-fuse array may further include an analog block.
  • the analog block may be used to provide supply voltages to antifuse cells in an antifuse array.
  • an analog block may be set in the anti-fuse array to provide the required high voltage for the read and write operations of the anti-fuse unit , so that the normal read and write of the anti-fuse unit can be realized.
  • FIG. 13 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • the memory device 800 may include vertically stacked multi-layer storage layers, such as the storage layer 110 and the storage layer 120 , which are only used for illustration, and may actually include more than two layers. memory.
  • each storage layer includes at least one channel.
  • each storage layer may include one channel
  • the memory device 800 may have as many storage layers as there are multiple channels, and multiple channels corresponding to the multiple storage layers may share the same antifuse array.
  • the present disclosure is not limited to this.
  • the memory device provided by the embodiments of the present disclosure can accommodate more memory cell arrays in the same memory device through vertically stacked multi-layer storage layers without increasing the area of the memory device, and can meet high bandwidth requirements. And sharing the same anti-fuse array through multiple channels, the anti-fuse array can be uniformly scheduled in these multiple channels to achieve the equalization function, avoiding the large number of unusable normal memory cells in some channels. There are not enough anti-fuse cells to store the failed addresses, and the low number of unusable normal memory cells in some channels leads to the problem that some anti-fuse cells are idle.
  • the anti-fuse array centrally stores the failure addresses of the unusable normal memory cells in the plurality of channels, which saves the area occupied by the anti-fuse array, improves the integration degree of the memory device, and reduces the complexity of the manufacturing process. the complexity.
  • FIG. 14 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • each memory layer may include the plurality of channels, the test control circuit, and the non-volatile memory cell array. That is, multiple channels in each storage layer share the same non-volatile memory cell array, and multiple channels in different storage layers use different non-volatile memory cell arrays.
  • the memory device 900 includes the storage layer 110 and the storage layer 120, and that the storage layer 110 includes the channel 1 and the channel 2, the description of the channel 1 and the channel 2 can refer to the above-mentioned embodiment.
  • the storage layer 120 may also include channel 1 and channel 2 .
  • the memory device provided by the embodiments of the present disclosure can accommodate more memory cell arrays in the same memory device by stacking multiple storage layers vertically, and each layer of the storage layer includes multiple channels.
  • the area of the large memory device further meets the high bandwidth requirements, and through multiple channels in each storage layer sharing the same anti-fuse array, the anti-fuse array can be uniformly scheduled in these multiple channels to achieve the equalization function, It is avoided that the number of unusable normal memory cells in some channels is large, resulting in insufficient anti-fuse cells to store failed addresses, and the number of unusable normal memory cells in some channels is small, resulting in some anti-fuse cells. idle question.
  • the anti-fuse array centrally stores the failure addresses of the unusable normal memory cells in multiple channels in each layer of the storage layer, which saves the area occupied by the anti-fuse array and improves the integration degree of the memory device.
  • the complexity of the manufacturing process is reduced.
  • FIG. 15 schematically shows a schematic diagram of a memory device according to an embodiment of the present disclosure.
  • each storage layer in the memory device 1000 provided by the embodiment of the present disclosure may further include at least one of a charge pump, a temperature sensor, and a chip identification memory.
  • the charge pump may be used to provide power for the plurality of channels of the corresponding storage layer, the test control circuit and/or the non-volatile memory cell array.
  • a temperature sensor may be used to test the temperature of the plurality of channels of the corresponding memory layer, the test control circuit and/or the non-volatile memory cell array.
  • the chip identification memory may be used to store the chip identification information of the corresponding storage layer.
  • each memory layer of the memory device 1000 may also include shared analog circuits and capacitances. That is, multiple channels in each storage layer in the embodiments of the present disclosure may share the same non-volatile memory cell array, charge pump, test control circuit, shared analog circuit and capacitor, temperature sensor and chip identification memory.
  • the memory device is a DRAM (Dynamic Random Access Memory, dynamic random access memory) as an example for illustration, but the present disclosure is not limited to this, and the memory device may be any device capable of realizing a storage function.
  • DRAM Dynamic Random Access Memory, dynamic random access memory
  • FIG. 16 schematically shows a schematic diagram of a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • DRAM core #1 As shown in Figure 16, taking a three-dimensional (3-dimension, 3D) vertically stacked DRAM cube as an example, vertically stack DRAM core #4, DRAM core #3, and DRAM core # on the logic control circuit in sequence 2. DRAM core #1.
  • Three-dimensional stacked DRAM is a new type of memory formed by stacking multiple layers of DRAM through 3D packaging technology, which can provide a large memory capacity and memory bandwidth.
  • FIG. 17 schematically shows a schematic diagram of a 2.5-dimensional (2.5D) integrated circuit according to an embodiment of the present disclosure.
  • DRAM core #4, DRAM core #3, DRAM core #2, and DRAM core #1 are vertically stacked in sequence on an interposer.
  • a logic control circuit is provided on the interposer. .
  • the data communication between the logic control circuit and each DRAM core is realized through the adapter board.
  • FIG. 16 and FIG. 17 take the vertical stacking of four DRAM cores as an example for illustration, but in fact, the present disclosure does not limit the number of vertically stacked DRAM cores.
  • FIG. 18 schematically shows a schematic diagram of a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • each DRAM core includes two channels, for example, DRAM core #4, DRAM core #3, DRAM core #2, and DRAM core #1 each include a channel 1 and channel 2.
  • Each channel can include a single DRAM chip, and multiple DRAM chips in multiple channels can be integrated into one storage layer, and the logic control circuit can control the pins of each channel independently or simultaneously.
  • each channel may include 64 normal data pins, and may also include 8 ECC (Error Correcting Code, error checking and correction) check pins.
  • ECC Error Correcting Code, error checking and correction
  • the ECC check pin can be used to perform error detection and correction on the data supplied from each channel, the data can be detected for errors and the errors can be corrected.
  • FIG. 19 schematically shows a schematic diagram of a memory layer in a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • DRAM core #1 as an example of a storage layer in a memory device, it includes channel 1 and channel 2, and channel 1 and channel 2 share the same non-volatile memory cell array, Charge pumps, test control circuits, shared analog circuits and capacitors, temperature sensors, and chip identification memory.
  • the memory cell array of each channel includes 4 memory blocks.
  • the memory cell array 1 in channel 1 includes memory blocks 1 to 4
  • the memory cell array 2 in channel 2 includes memory blocks 1 to 4 .
  • the memory block 1 in the memory cell array 1 in the channel 1 is provided with a normal cell array 11 (assuming that the normal memory cells 11 to 18 are included), a spare cell array 11 (assuming that the spare memory cell 11 and the spare memory cell 12 are included), and
  • the latch block 11 (assumed to include the latch 11 and the latch 12 )
  • the storage block 2 is provided with a normal cell array 12 (assumed to include the normal storage cells 21 to 28 ), a spare cell array 12 (assumed to include the spare storage cells 21 and 28 ) Spare storage unit 22) and latch block 12 (assumed to include latch 21 and latch 22)
  • storage block 3 is provided with normal cell array 13 (assumed to include normal storage units 31 to 38), spare cell array 13 (assumed to include normal storage units 31 to 38) Including the spare storage unit 31 and the spare storage unit 32) and the latch block 13 (assumed to include the latch 31 and the latch 32),
  • the storage block 4 is provided with a
  • the latch blocks in any other one or more memory blocks in channel 1 can be called The latch is used to store the remaining failed addresses, and the access addresses of the spare memory cells of the spare cell array in any other one or more storage blocks can also be used as the repair addresses of the remaining failed addresses.
  • each spare memory cell in the spare cell array in each memory block can be in one-to-one correspondence with the latches in the latch block in the corresponding memory block.
  • the read-write control circuit 1 in the channel 1 can control the read-write circuit 1 to alternately read and write the memory block 1 to the memory block 4 in turn.
  • channel 2 in FIG. 19 may refer to channel 1 .
  • FIG. 20 schematically shows a schematic diagram of a memory layer in a three-dimensional integrated circuit according to an embodiment of the present disclosure.
  • the test control circuit can receive a test command from an external test device or a memory controller in a memory system including DRAM core #1, and respond to the test command, Test normal cell arrays 11 to 14 in memory blocks 1 to 4 in memory cell array 1 of channel 1 and normal cell arrays 11 to 14 in memory blocks 2 to 4 in memory cell array 2 in channel 2 to obtain a test
  • the access address of the failed normal memory cell is taken as the failure address.
  • test control circuit sends the obtained failure address to the control block of the anti-fuse array, and the control block stores it in the anti-fuse unit of the anti-fuse array.
  • the scan host dumps the failed address stored in the anti-fuse unit of the anti-fuse array into the corresponding latch block of the corresponding channel.
  • Embodiments of the present disclosure also provide a memory system, which may include: at least one storage layer and a memory controller.
  • the memory controller may be configured to control the at least one memory layer.
  • the memory controller may provide address, command and control signals to each memory layer to control program (or write) operations and read operations of each memory layer.
  • the command may be a read command or a write command.
  • an address may include a location in each layer of storage tier to which data is written or read from.
  • each storage layer may include: a plurality of channels, a test control circuit and a non-volatile memory cell array.
  • each channel of the plurality of channels may include a memory cell array
  • the memory cell array may include a normal cell array
  • the normal cell array may include a plurality of normal memory cells
  • the normal memory cells may be volatile memory cells.
  • the test control circuit may be used to control and test the normal cell arrays in the multiple channels in response to the test instruction, and determine the access addresses of the normal memory cells that fail the test in the normal cell arrays in the multiple channels as the failure addresses.
  • the array of non-volatile memory cells may include a plurality of non-volatile memory cells, and the array of non-volatile memory cells may be operable to receive and store the fail addresses from the test control circuit.
  • the memory controller may be operable to provide the test instructions to the test control circuit.
  • the memory system may be connected to an external test device, and the test control circuit may receive the test instruction from the external test device.
  • the memory system provided by the present disclosure in a real-time manner, on the one hand, can satisfy high bandwidth requirements by allowing memory devices including multiple channels to share the same non-volatile memory cell array; on the other hand, by using non-volatile memory cells
  • the non-volatile memory cells in the array are used to store the failure addresses corresponding to the access addresses of the unusable normal memory cells that have failed the test in the normal cell arrays in the plurality of channels, and the memory cell arrays in the plurality of channels can be After the power is turned off, it is still possible to know which or which normal memory cells in the memory cell array in the multiple channels are unavailable.
  • FIG. 21 schematically shows a flowchart of a method for testing a memory device according to an embodiment of the present disclosure.
  • the memory device may include a plurality of channels and an array of non-volatile memory cells, each channel may include an array of memory cells, the array of memory cells may include an array of normal cells, the array of normal cells may include normal memory cells, and
  • the normal memory cells may be volatile memory cells, and the non-volatile memory cell array may include a plurality of non-volatile memory cells.
  • the method provided by the embodiment of the present disclosure may include the following steps.
  • step S2110 a test instruction is received.
  • test instruction may be provided to the test control circuit through a memory controller, or the test instruction may be provided to the test control circuit by an external test device connected to the memory device.
  • the source is not limited.
  • step S2120 the normal cell arrays in the multiple channels are controlled to be tested according to the test instruction, and the access addresses of the normal memory cells that fail the test in the normal cell arrays in the multiple channels are determined as failure addresses.
  • step S2130 the failed address is sent and stored to the non-volatile memory cell array.
  • the testing method of the memory device provided by the present disclosure in a real-time manner can meet the high bandwidth requirement by allowing the memory device including multiple channels to share the same non-volatile memory cell array; on the other hand, by using the non-volatile memory
  • the non-volatile memory cells in the non-volatile memory cell array in the plurality of channels are used to store the failure addresses corresponding to the access addresses of the unusable normal memory cells that fail the test in the normal cell array in the plurality of channels, which can be stored in the memory cells in the plurality of channels.
  • After the cell array is powered off it is still possible to know which or which normal memory cells of the memory cell array in the multiple channels are unavailable. In this way, after the next power-on, there is no need to re-test, saving testing time and cost. cost, improve the test efficiency, while maintaining the high-speed read and write performance of the volatile memory cells used in the memory cell array in each channel.
  • Embodiments of the present disclosure also provide a method of using a memory device
  • the memory device may include a plurality of channels and an array of non-volatile memory cells, each channel may include an array of memory cells and a latch block, the memory cells
  • the array may include an array of normal cells, the array of normal cells including normal memory cells, the normal memory cells may be volatile memory cells, the array of non-volatile memory cells may include a plurality of non-volatile memory cells, A failure address representing an access address of a normal memory cell that has failed a test in the normal cell array in the plurality of channels may be stored in the non-volatile memory cell array.
  • the using method may include the following steps: when the memory device is powered on, dumping the failed address in the non-volatile memory cell array to a latch block of a corresponding channel .
  • the latch block may include a first number of latches
  • the memory cell array may further include a spare cell array
  • the spare cell array may include the first number of spare memory cells
  • the spare storage unit may be a volatile memory unit
  • each latch in the latch block in each channel may be in one-to-one correspondence with each spare storage unit in the spare cell array in the corresponding channel.
  • dumping the failed address in the non-volatile memory cell array to the latch block of the corresponding channel may include: when the memory device is powered on, Dumping the failed address in the non-volatile memory cell array to the corresponding latch in the latch block of the corresponding channel to determine the access address of the target spare storage unit for replacing the failed address as Fix the address.
  • the memory cell array may include a plurality of memory blocks, the plurality of memory blocks may share a spare cell array and a latch block, the spare cell array may include a first number of spare memory cells,
  • the spare memory unit may be a volatile memory unit, the latch block may include the first number of latches, and the non-volatile memory cell array may further include a scan master, a lock for each channel.
  • Both the storage block and the scanning host may include a first interface, a second interface and a third interface.
  • transferring the failed address in the non-volatile memory cell array to the latch block of the corresponding channel may include: passing the latch block of each channel and the The first interface of the scan host receives an enable signal; the clock signal is received through the latch block of each channel and the second interface of the scan host; the third interface of the scan host is when the enable signal is the first interface.
  • the channel address, the storage block address and the latch block address are sequentially sent to the third interface of the latch block of each channel through the third interface of the scanning host to determine the target channel respectively , the target storage block of the target channel and the target latch in the target latch block corresponding to the target channel, and send a write command to the third interface of the latch block of each channel to pass the target channel
  • the third interface of the target latch block writes the failed address into the target latch of the target latch block.
  • each channel's latch block and the scan host may further include a fourth interface.
  • the failed addresses tested in the test phase and stored in the non-volatile memory cell array can be dumped to the corresponding latches of the corresponding channels, so that each channel can be used when each channel is used.
  • the normal cell array is formed, the faster read and write speed of the volatile memory cells in the normal cell array can be maintained, and the accuracy of read and write data can be ensured.
  • the exemplary embodiments described herein may be implemented by software, or may be implemented by software combined with necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure may be embodied in the form of software products, and the software products may be stored in a non-volatile storage medium (which may be CD-ROM, U disk, mobile hard disk, etc.) or on the network , which includes several instructions to cause a computing device (which may be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to an embodiment of the present disclosure.
  • a computing device which may be a personal computer, a server, a touch terminal, or a network device, etc.
  • an embodiment of the present disclosure also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs; when the one or more programs are processed by the one or more programs The execution of the one or more processors causes the one or more processors to implement the method described in any of the above embodiments.
  • an embodiment of the present disclosure also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, implements the method described in any of the foregoing embodiments.

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

Dispositif de mémoire, procédé de test associé et procédé d'utilisation associé, et système de mémoire, appartenant au domaine technique des semi-conducteurs. Le dispositif de mémoire comprend : de multiples canaux, chaque canal comprenant un réseau de cellules de mémoire, le réseau de cellules de mémoire comprenant un réseau de cellules normales, le réseau de cellules normales comprenant des cellules de mémoire normales, et les cellules de mémoire normales étant des cellules de mémoire volatile ; un circuit de contrôle de test, configuré pour contrôler, en réponse à une instruction de test, un test des réseaux de cellules normales dans les multiples canaux, et configuré pour déterminer que les adresses d'accès de cellules de mémoire normales qui n'ont pas été testées dans les réseaux de cellules normales des multiples canaux, sont des adresses de défaillance ; et un réseau de cellules de mémoire non volatile, comprenant de multiples cellules de mémoire non volatile, et configuré pour recevoir les adresses de défaillance provenant du circuit de contrôle de test et les stocker. Le dispositif de mémoire peut permettre à de multiples canaux de partager le même réseau de cellules de mémoire non volatile.
PCT/CN2021/099238 2020-09-15 2021-06-09 Dispositif de mémoire, procédé de test associé et procédé d'utilisation associé, et système de mémoire WO2022057333A1 (fr)

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