WO2022052216A1 - 显示装置及其制备方法 - Google Patents

显示装置及其制备方法 Download PDF

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Publication number
WO2022052216A1
WO2022052216A1 PCT/CN2020/122072 CN2020122072W WO2022052216A1 WO 2022052216 A1 WO2022052216 A1 WO 2022052216A1 CN 2020122072 W CN2020122072 W CN 2020122072W WO 2022052216 A1 WO2022052216 A1 WO 2022052216A1
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WO
WIPO (PCT)
Prior art keywords
layer
display device
pixel definition
area
flat
Prior art date
Application number
PCT/CN2020/122072
Other languages
English (en)
French (fr)
Inventor
陈永胜
蒋谦
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/267,901 priority Critical patent/US20230189571A1/en
Publication of WO2022052216A1 publication Critical patent/WO2022052216A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • the present application relates to the field of display technology, and in particular, to a display device and a preparation method thereof.
  • the present application provides a display device and a manufacturing method thereof, so as to solve the problem of scratching the substrate in the prior art.
  • the present application relates to a display device, wherein the display device includes a display area and a non-display area, and the display device includes:
  • the flat layer is disposed on the array substrate
  • the passivation layer covers the flat layer
  • the pixel definition layer is located in the display area, the pixel definition layer is disposed on the passivation layer;
  • the protective layer is located in the non-display area, and the protective layer is arranged on the flat layer.
  • the material of the protective layer is diamond-like carbon.
  • the thickness of the protective layer is 3 nanometers to 980 nanometers.
  • the display device further includes a support structure, and the support structure is disposed on the pixel definition layer.
  • the display device further includes a blocking wall
  • the non-display area includes a first area and a second area
  • the first area is located on a side close to the pixel definition layer, so the non-display area includes a first area and a second area.
  • the second area is located on a side away from the pixel definition layer
  • the blocking wall is arranged on a flat layer on the second area
  • the protective layer covers the blocking wall
  • the height of the blocking wall is the same as the height of the blocking wall.
  • the sum of the thicknesses of the protective layers is greater than the height of the support structure.
  • the display device further includes a cathode contact layer, and the cathode contact layer is disposed on the flat layer of the first region.
  • the present application also provides a display device, wherein the display device includes a display area and a non-display area, and the display device includes:
  • the flat layer is disposed on the array substrate
  • the pixel definition layer is located in the display area, the pixel definition layer is disposed on the flat layer;
  • the protective layer is located in the non-display area, and the protective layer is arranged on the flat layer.
  • the material of the protective layer is diamond-like carbon.
  • the thickness of the protective layer is 3 nanometers to 980 nanometers.
  • the display device further includes a support structure, and the support structure is disposed on the pixel definition layer.
  • the display device further includes a blocking wall
  • the non-display area includes a first area and a second area
  • the first area is located on a side close to the pixel definition layer, so the non-display area includes a first area and a second area.
  • the second area is located on a side away from the pixel definition layer
  • the blocking wall is arranged on a flat layer on the second area
  • the protective layer covers the blocking wall
  • the height of the blocking wall is the same as the height of the blocking wall.
  • the sum of the thicknesses of the protective layers is greater than the height of the support structure.
  • the display device further includes a cathode contact layer, and the cathode contact layer is disposed on the flat layer of the first region.
  • the display device further includes an isolation layer, and the isolation layer is disposed on the cathode contact layer.
  • the display device further includes a dam, and the dam is disposed on the flat layer on the second region.
  • the display device further includes a crack blocking dam, and the crack blocking dam is disposed on the flat layer on the second region.
  • the present application also provides a preparation method of a display device, the display device includes a display area and a non-display area, and the preparation method of the display device includes:
  • a planarization layer and a pixel definition layer are formed in sequence on the array substrate, and the pixel definition layer is located in the display area;
  • a protective layer is formed on the flat layer.
  • the step of forming a protective layer on the flat layer in the non-display area before including:
  • a protective layer is formed on the pixel definition layer and the flat layer.
  • the material of the protective layer is one or a combination of polyester, SiOx or SiNx.
  • the protective layer is a metal mask.
  • the step of forming a flat layer and a pixel definition layer on the array substrate in sequence after the step of forming a flat layer and a pixel definition layer on the array substrate in sequence, and the pixel definition layer is located in the display area, in the non- The display area, before the step of forming the protective layer on the flat layer, further includes:
  • a support structure material is provided on the pixel definition layer, and the support structure is formed by etching.
  • the present application provides a display device and a manufacturing method thereof, the display device includes a display area and a non-display area, the display device includes an array substrate, a flat layer, a pixel definition layer and a protective layer, the flat layer is disposed on the On the array substrate, the pixel definition layer is located in the display area, the pixel definition layer is disposed on the flat layer, the protective layer is located in the non-display area, and the protective layer is disposed on the flat layer .
  • a protective layer on the flat layer located in the non-display area, water and oxygen are prevented from invading the display device, and the structures in the display device are prevented from being scratched and subsequent processes are not affected, thereby improving the reliability of the display device. .
  • FIG. 1 is a top view of a display device provided by the present application.
  • FIG. 2 is a cross-sectional view of the display device provided by the present application along line AB.
  • FIG. 3 is a flowchart of a method for manufacturing a display device provided by the present application.
  • FIG. 1 is a top view of the display device provided by the present application.
  • the present application provides a display device 10 .
  • the display device 10 includes a display area 11 and a non-display area 12 .
  • the non-display area 12 surrounds the display area 11 .
  • the display device 10 includes a cathode film layer 20 , a driving chip 30 , a chip on film 40 , a flexible circuit board binding area 50 and a protective layer 60 .
  • the cathode film layer 20 , the driving chip 30 , the chip on film 40 , the flexible circuit board binding area 50 and the protective layer 60 are located in the non-display area 12 .
  • the cathode film layer 20 is disposed around the display area 11 .
  • the chip on film 40 is connected to the cathode film layer 20 .
  • the driving chip 30 is bound on the chip on film 40 .
  • the flexible circuit board binding area 50 is disposed on the side of the chip on film 40 away from the cathode film layer 20 .
  • the driver chip 30 is provided.
  • the protective layer 60 is disposed around the cathode film layer 20 , the chip on film 40 and the flexible circuit board binding area 50 .
  • FIG. 2 is a cross-sectional view of the display device provided by the present application along line AB.
  • the display device 10 includes an array substrate 100 , a planarization layer 200 , a pixel definition layer 300 and a protection layer 60 .
  • the non-display area 12 includes a first area 13 and a second area 14 .
  • the first region 13 is located on a side close to the pixel definition layer 300 .
  • the second region 14 is located on a side away from the pixel definition layer 300 .
  • the array substrate 100 includes a substrate 110 , a light shielding layer 120 , a buffer layer 130 and a transistor 140 .
  • the substrate 110 may be polyimide, glass, or the like.
  • the light shielding layer 120 and the buffer layer 130 are sequentially stacked on the substrate 110 .
  • the transistor 140 is located in the display area 11 .
  • the transistor 140 is disposed on the buffer layer 130 .
  • the transistor 140 includes a gate electrode 141 , a gate insulating layer 142 , an active layer 143 , a source electrode 144 and a drain electrode 145 .
  • the gate 141 is disposed on the buffer layer 120 .
  • the gate insulating layer 142 covers the gate 141 .
  • the active layer 143 is disposed on the gate insulating layer 142 .
  • the source electrode 144 is disposed on one side of the active layer 143 and is electrically connected to the active layer 143 .
  • the drain 145 is disposed on the other side of the active layer 143
  • the flat layer 200 is disposed on the array substrate 110 . Specifically, the flat layer 200 covers the gate insulating layer 142 and the active layer 143 . In the display area 11 , the flat layer 200 includes a first through hole 201 and a second through hole 202 .
  • the first through hole 201 penetrates through the flat layer 200 to expose one side of the active layer 143 .
  • the second through hole 202 penetrates through the flat layer 200 to expose the other side of the active layer 143 .
  • the source electrode 144 is filled in the first through hole 201 and is electrically connected to the active layer 143 through the first through hole 201 .
  • the drain 145 is filled in the second through hole 202 and is electrically connected to the active layer 143 through the second through hole 202 .
  • the display device 10 further includes a passivation layer 400 .
  • the passivation layer 400 covers the flat layer 200 , the source electrode 144 and the drain electrode 145 .
  • the passivation layer 400 includes a third through hole 401 .
  • the third through hole 401 penetrates through the passivation layer 400 to expose the drain electrode 145 .
  • the display device 10 further includes an anode 500 .
  • the anode 500 is disposed in the third through hole 401 and on the passivation layer 400 .
  • the anode 500 is electrically connected to the drain 145 .
  • the display device 10 further includes a cathode contact layer 600 .
  • the second cathode contact layer 600 is disposed on the flat layer 200 of the first region 13 .
  • the cathode contact layer 600 includes a first part 610 and a second part 620 .
  • the first portion 610 is disposed in the same layer as the active layer 143 and disposed on the gate insulating layer 142 .
  • the passivation layer 400 further includes a first via hole 402 and a second via hole 403 .
  • the first via hole 402 penetrates through the passivation layer 400 and the planarization layer 200 to expose one side of the first portion 610 .
  • the second via hole 403 penetrates the passivation layer 400 and the planarization layer 200 to expose the other side of the first portion 610 .
  • the second portion 620 is disposed in the first via hole 402 , the second via hole 403 and on the passivation layer 400 .
  • the second portion 620 is electrically connected to the first portion 610 through the first via hole 402 and the second via hole 403 .
  • the pixel definition layer 300 is located in the display area 11 .
  • the pixel definition layer 300 is disposed on the flat layer 200 .
  • the pixel definition layer 300 is disposed on the passivation layer 400 of the display area 11 .
  • the pixel definition layer 300 includes fourth through holes 301 .
  • the fourth through hole 301 penetrates through the pixel definition layer 300 to expose the anode 500 .
  • the display device 10 further includes an isolation layer 700 .
  • the isolation layer 700 is disposed on the cathode contact layer 600 .
  • the isolation layer 700 has a plurality of fifth through holes 701 .
  • the fifth through hole 701 penetrates the isolation layer 700 to expose the cathode contact layer 600 .
  • the cathode contact layer is divided into a plurality of regions by the isolation layer, which avoids scratches or foreign matter in a certain region of the cathode contact layer during the preparation of the display device, so that other regions can still be used. normal use, thereby improving the yield of the display device and reducing the production cost.
  • the display device 10 further includes a retaining wall 800 .
  • the retaining wall 800 is disposed on the flat layer 200 on the second area 14 .
  • the retaining wall is used to prevent the mobile phase from overflowing before the structure of the display device is solidified.
  • the display device 10 further includes a dam 900 .
  • the dam 900 is disposed on the flat layer 200 on the second region 14 .
  • the dam 900 is disposed on the same layer as the retaining wall 800 and is located between the retaining wall 800 and the isolation layer 700 .
  • the height h of the embankment 900 is smaller than the height H of the retaining wall 800 .
  • the display device 10 further includes a support structure 1000 .
  • the support structure 1000 is disposed on the pixel definition layer 300 .
  • the support structure 1000 is used for supporting the structure of the display device to crush or scratch other structures in subsequent manufacturing processes.
  • the display device 10 further includes a crack blocking dam 1100 .
  • the crack barrier dam 1100 is disposed on the flat layer 200 on the second region 14 .
  • the crack blocking dam 1100 is located on the side of the retaining wall 800 away from the dam 900 .
  • Crack barrier dams are used to prevent other structures from developing cracks in subsequent processes.
  • the protective layer 60 is located in the non-display area 11 .
  • the protective layer 60 is disposed on the flat layer 200 .
  • the protection layer 60 covers the passivation layer 400 , the retaining wall 800 , the dam 900 and the crack blocking dam 1100 .
  • the sum D of the height of the retaining wall 800 and the thickness of the protective layer 60 is greater than the height d of the support structure 1000 .
  • the material of the protective layer 60 is diamond-like carbon.
  • the thickness L of the protective layer 60 is 3 nanometers to 980 nanometers. Specifically, in some embodiments, the thickness L of the protective layer 60 may be 4 nanometers, 6 nanometers, 8 nanometers, 10 nanometers, 206 nanometers, 700 nanometers, and 920 nanometers. When the thickness L of the protective layer 60 is between 3 and 10 nanometers, the display device can be bent.
  • the sum of the height of the retaining wall and the thickness of the protective layer is set to be greater than the height of the support structure, so as to avoid scratches or pressure injuries caused by the support structure in the subsequent manufacturing process or use process, and ensure the subsequent manufacturing process. or use it normally;
  • the protective layer is formed of diamond-like carbon, so that the protective layer has a thin hard film with waterproof and oxygen permeation effect, so as to prevent other structures of the display device from waiting too long and inhaling water vapor in the subsequent process, which will lead to the subsequent process. peel off the film
  • the protective layer is formed of diamond-like carbon, so that the protective layer has a thin anti-scratch hard film, which can reduce the encapsulation failure in the subsequent thin-film encapsulation process caused by the metal mask being crushed or scratched by foreign objects after scratching the retaining walls and dams. , thereby avoiding the invasion of water and oxygen, thereby improving the reliability and service life of the display device.
  • the protective layer is formed of diamond-like carbon and is arranged in the non-display area, which can reduce the increase of metal oxidation value caused by foreign matter pressure damage in the module process or high temperature and high humidity environment on the peripheral metal lines of the display device, thereby improving the yield of the display device.
  • the display device 10 further includes a light-emitting layer 1200 .
  • the light emitting layer 1200 is disposed in the fourth through hole 301 .
  • the light-emitting layer 1200 includes one of a red light-emitting layer, a green light-emitting layer and a blue light-emitting layer.
  • the display device 10 further includes a cathode 1300 .
  • the cathode 1300 covers the light emitting layer 1200 , the pixel definition layer 300 , the support structure 1000 , the isolation layer 700 and the fifth through hole 701 .
  • the cathode 1300 is electrically connected to the cathode contact layer 600 through the fifth through hole 701 .
  • the cathode contact layer 600 and the light emitting layer 1200 are electrically connected through the cathode 1300 .
  • the cathode contact layer 600 and the cathode 1300 form the cathode film layer 20 in FIG. 1 .
  • the anode 500 , the light emitting layer 1200 and the cathode 1300 constitute an organic light emitting diode.
  • FIG. 3 is a flowchart of a method for manufacturing a display device provided by the present application.
  • the present application also provides a method for manufacturing a display device.
  • the display device 10 includes a display area 11 and a non-display area 12 .
  • the preparation method of the display device includes:
  • the array substrate 100 includes a substrate 110 , a light shielding layer 120 , a buffer layer 130 and a transistor 140 .
  • the substrate 110 may be polyimide, glass, or the like.
  • the light shielding layer 120 and the buffer layer 130 are sequentially stacked on the substrate 110 .
  • the transistor 140 is located in the display area 11 .
  • the transistor 140 is disposed on the buffer layer 130 .
  • the transistor 140 includes a gate electrode 141 , a gate insulating layer 142 , an active layer 143 , a source electrode 144 and a drain electrode 145 .
  • the gate 141 is disposed on the buffer layer 120 .
  • the gate insulating layer 142 covers the gate 141 .
  • the active layer 143 is disposed on the gate insulating layer 142 .
  • the source electrode 144 is disposed on one side of the active layer 143 and is electrically connected to the active layer 143 .
  • the drain 145 is disposed on the other side of the active layer 143 and is electrically connected to the active layer 143 .
  • the first portion 610 of the cathode contact layer 600 is disposed on the gate insulating layer 142 of the first region 13 .
  • the first portion 610 is disposed in the same layer as the active layer 143 .
  • the planarization layer 200 and the pixel definition layer 300 in sequence on the array substrate 100 .
  • the pixel definition layer 300 is located in the display area 11 .
  • the material of the flat layer 200 is disposed on the gate insulating layer 142 and the active layer 143 , and the material of the flat layer 200 is etched to form the flat layer 200 .
  • the flat layer 200 includes a first through hole 201 and a second through hole 202 .
  • the first through hole 201 penetrates through the flat layer 200 to expose one side of the active layer 143 .
  • the second through hole 202 penetrates through the flat layer 200 to expose the other side of the active layer 143 .
  • the source electrode 144 is filled in the first through hole 201 and is electrically connected to the active layer 143 through the first through hole 201 .
  • the drain 145 is filled in the second through hole 202 and is electrically connected to the active layer 143 through the second through hole 202 .
  • the method further includes:
  • a passivation layer 400 material is disposed on the flat layer 200 , the source electrode 144 and the drain electrode 145 , and the passivation layer 400 material is etched to form the passivation layer 400 .
  • the passivation layer 400 includes a third via hole 401 , a first via hole 402 and a second via hole 403 .
  • the third through hole 401 is located in the display area 11 .
  • the third through hole 401 penetrates through the passivation layer 400 to expose the drain electrode 145 .
  • the first via hole 402 and the second via hole 403 are located in the first region 13 , and the first via hole 402 penetrates through the passivation layer 400 and the planarization layer 20 to expose one side of the first portion 610 .
  • the second via hole 403 penetrates through the passivation layer 400 and the planarization layer 20 to expose the other side of the first portion 610 .
  • the method further includes:
  • An anode 500 is formed in the third through hole 401 and on the passivation layer 400 .
  • the anode 500 is electrically connected to the drain 145 .
  • the method further includes:
  • a second portion 620 of the second cathode contact layer 600 is disposed on the passivation layer 400 in the first region 13 , in the first via hole 402 and the second via hole 403 .
  • the second portion 620 is electrically connected to the first portion 610 through the first via hole 402 and the second via hole 403 .
  • the first portion 610 and the second portion 620 are the cathode contact layer 600 .
  • the method includes:
  • a pixel definition layer 300 is provided on the flat layer 200 of the display area 11 .
  • the material of the pixel definition layer 300 , the material of the isolation layer 700 and the material of the dam 900 are arranged on the passivation layer 400 and the cathode contact layer 600 .
  • the material of the pixel definition layer 300 , the material of the isolation layer 700 and the material of the bank 900 are etched to form the pixel definition layer 300 , the isolation layer 700 and the bank 900 .
  • the pixel definition layer 300 is located on the passivation layer 400 of the display area 11 .
  • the pixel definition layer 300 includes fourth through holes 301 .
  • the fourth through hole 301 penetrates through the pixel definition layer 300 to expose the anode 500 .
  • the isolation layer 700 is located on the cathode contact layer 600 .
  • the isolation layer 700 has a plurality of fifth through holes 701 .
  • the fifth through hole 701 penetrates the isolation layer 700 to expose the cathode contact layer 600 .
  • the dam 900 is located on the flat layer 200 on the second region 14 .
  • the cathode contact layer is divided into a plurality of regions by the isolation layer, which avoids scratches or foreign matter in a certain region of the cathode contact layer during the preparation of the display device, so that other regions can still be used. normal use, thereby improving the yield of the display device.
  • the method further includes:
  • the material of the retaining wall 800 and the material of the supporting structure 1000 are arranged on the pixel defining layer 300 and the passivation layer 400 , and the retaining wall 800 and the supporting structure 1000 are formed by etching.
  • the retaining wall 800 is located on the flat layer 200 on the second area 14 .
  • the retaining wall is used to prevent the mobile phase from overflowing before the structure of the display device is solidified.
  • the support structure 1000 is located on the pixel definition layer 300 .
  • the support structure 1000 is used for supporting the structure of the display device to crush or scratch other structures in subsequent manufacturing processes.
  • the method further includes:
  • the crack barrier dam 1100 material is provided on the flat layer 200 on the second region 14 , and the crack barrier dam 1100 is formed by etching the crack barrier dam 1100 material.
  • the crack blocking dam 1100 is located on the side of the retaining wall 800 away from the dam 900 . Crack barrier dams are used to prevent other structures from developing cracks in subsequent processes.
  • a protective layer 60 is formed on the flat layer 200.
  • the array substrate 100 , the flat layer 200 and the pixel definition layer 300 are transferred to an oven for baking to remove moisture adsorbed in the organic photoresist.
  • the baking temperature is 120 degrees Celsius - 250 degrees Celsius. Specifically, the baking temperature may be 125 degrees Celsius, 146 degrees Celsius, 181 degrees Celsius, and 238 degrees Celsius.
  • Baking time is 10 minutes - 590 minutes. Specifically, the baking time is 17 minutes, 90 minutes, 260 minutes, 372 minutes, and 570 minutes. The time will decrease as the temperature increases.
  • a protective layer is formed on the array substrate 100 , the pixel definition layer 300 , the isolation layer 700 , the cathode contact layer 600 and the support structure 1000 .
  • the material of the protective layer is one or a combination of polyester, SiOx or SiNx.
  • the material of the protective layer is polyester. Then, it is transferred to a plasma-enhanced chemical method equipment.
  • a protective layer 60 is formed on the passivation layer 400 , the retaining wall 800 , the dam 900 and the crack blocking dam 1100 .
  • the material of the protective layer 60 is diamond-like carbon.
  • the thickness L of the protective layer 60 is 3 nanometers to 980 nanometers. Specifically, in some embodiments, the thickness L of the protective layer 60 may be 4 nanometers, 6 nanometers, 8 nanometers, 10 nanometers, 206 nanometers, 700 nanometers, and 920 nanometers.
  • the display device can be bent.
  • the protective layer 60 is formed, the array substrate 100 , the planarization layer 200 , the pixel definition layer 300 and the protective layer 60 are transferred out of the plasma-enhanced chemical method equipment, and the polyester protective film is removed.
  • steps include:
  • the material of the light emitting layer 1200 is filled in the fourth through hole 301 to form the light emitting layer 1200 .
  • the light-emitting layer 1200 includes one of a red light-emitting layer, a green light-emitting layer and a blue light-emitting layer.
  • a cathode 1300 is formed on the light emitting layer 1200 , the pixel definition layer 300 , the support structure 1000 , the isolation layer 700 and in the fifth through hole 701 .
  • the cathode 1300 is electrically connected to the cathode contact layer 600 through the fifth through hole 701 .
  • the cathode contact layer 600 and the light emitting layer 1200 are electrically connected through the cathode 1300 .
  • the cathode contact layer 600 and the cathode 1300 form the cathode film layer 20 in FIG. 1 .
  • the anode 500 , the light emitting layer 1200 and the cathode 1300 constitute an organic light emitting diode.
  • the array substrate 100 , the pixel definition layer 300 , the isolation layer 700 , the cathode contact layer 600 and the support structure 1000 may not be first A polyester protective layer is formed. It is first conveyed to the plasma-enhanced chemical method equipment. The patterned metal mask protection layer in the cavity is aligned with the array substrate 100 , the pixel definition layer 300 , the isolation layer 700 , and the cathode contact layer 600 .
  • the protective layer is a metal mask in a plasma-enhanced chemical method equipment.
  • a protective layer 60 is formed on the passivation layer 400 , the retaining wall 800 , the dam 900 and the crack blocking dam 1100 . Then, the plasma-enhanced chemical method equipment is sent out, and then the subsequent processes of the light-emitting layer 1200 and the cathode 1300 are performed.
  • the sum of the height of the retaining wall and the thickness of the protective layer is set to be greater than the height of the support structure, so as to avoid scratches or pressure injuries caused by the support structure in the subsequent manufacturing process or use process, and ensure the subsequent manufacturing process.
  • the protective layer is formed of diamond-like carbon, so that the protective layer has a thin hard film with waterproof and oxygen permeation effect, so as to prevent other structures of the display device from waiting too long and inhaling water vapor in the subsequent manufacturing process, which will lead to the subsequent manufacturing process.
  • the film layer is peeled off due to the release of water vapor; the protective layer is formed of diamond-like carbon, so that the protective layer has a thin hard film that is scratch-resistant, which can reduce the occurrence of metal mask pressure or scratches on retaining walls and dams.
  • the foreign matter caused by the film will cause packaging failure, thereby avoiding the invasion of water and oxygen, thereby improving the reliability and service life of the display device.
  • the metal oxidation value increases due to the foreign body crushing of the module process or the high temperature and high humidity environment, thereby improving the yield of the display device.
  • the present application provides a display device and a manufacturing method thereof, the display device includes a display area and a non-display area, the display device includes an array substrate, a flat layer, a pixel definition layer and a protective layer, the flat layer is disposed on the On the array substrate, the pixel definition layer is located in the display area, the pixel definition layer is disposed on the flat layer, the protective layer is located in the non-display area, and the protective layer is disposed on the flat layer .
  • a protective layer on the flat layer located in the non-display area, water and oxygen are prevented from invading the display device, and the structures in the display device are prevented from being scratched and subsequent processes are not affected, thereby improving the reliability of the display device. .

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Abstract

一种显示装置（10）及其制备方法，显示装置（10）包括显示区（11）和非显示区（12），显示装置（10）包括阵列基板（100）、平坦层（200）、像素定义层（300）和防护层（60），平坦层（200）设置于阵列基板（100）上，像素定义层（300）位于显示区（11），像素定义层（300）设置于平坦层（200）上，防护层（60）位于非显示区（12），防护层（60）设置于平坦层（200）上。

Description

显示装置及其制备方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示装置及其制备方法。
 背景技术
近年来，有机发光二极管显示装置以其独有的优势正吸引着业内绝大多数从业者注意，在中小尺寸显示领域更有取代液晶显示面板的趋势，现阶段中的有机发光二极管面板大多依赖蒸镀制程，其中，在蒸镀制程中用于图形定义的治具为金属掩模版，但是因为金属掩膜板在使用刻蚀制程后形成开口，且开口与基板直接接触，进而会对基板造成划伤，因划伤产生的异物可能会对后续的制程产品信赖性不良的结果，并且半刻蚀设计会造成边缘膜厚不均区域增加，不利于实现窄边框。
 技术问题
本申请提供一种显示装置及其制备方法，以解决现有技术中对基板划伤的问题。
 技术解决方案
本申请一种显示装置，其中，所述显示装置包括显示区和非显示区，所述显示装置包括：
一阵列基板；
平坦层，所述平坦层设置于所述阵列基板上；
钝化层，所述钝化层覆盖于所述平坦层；
像素定义层，所述像素定义层位于所述显示区，所述像素定义层设置于所述钝化层上；以及
防护层，所述防护层位于所述非显示区，所述防护层设置于所述平坦层上。
在本申请所提供的显示装置中，所述防护层的材料为类金刚石。
在本申请所提供的显示装置中，所述防护层的厚度为3纳米-980纳米。
在本申请所提供的显示装置中，所述显示装置还包括支撑结构，所述支撑结构设置于所述像素定义层上。
在本申请所提供的显示装置中，所述显示装置还包括挡墙，所述非显示区包括第一区域和第二区域，所述第一区域位于靠近所述像素定义层的一侧，所述第二区域位于远离所述像素定义层的一侧，所述挡墙设置于所述第二区域上的平坦层，所述防护层覆盖所述挡墙，所述挡墙的高度与所述防护层的厚度之和大于所述支撑结构的高度。
在本申请所提供的显示装置中，所述显示装置还包括阴极接触层，所述阴极接触层设置于所述第一区域的平坦层上。
本申请还提供一种显示装置，其中，所述显示装置包括显示区和非显示区，所述显示装置包括：
一阵列基板；
平坦层，所述平坦层设置于所述阵列基板上；
像素定义层，所述像素定义层位于所述显示区，所述像素定义层设置于所述平坦层上；以及
防护层，所述防护层位于所述非显示区，所述防护层设置于所述平坦层上。
在本申请所提供的显示装置中，所述防护层的材料为类金刚石。
在本申请所提供的显示装置中，所述防护层的厚度为3纳米-980纳米。
在本申请所提供的显示装置中，所述显示装置还包括支撑结构，所述支撑结构设置于所述像素定义层上。
在本申请所提供的显示装置中，所述显示装置还包括挡墙，所述非显示区包括第一区域和第二区域，所述第一区域位于靠近所述像素定义层的一侧，所述第二区域位于远离所述像素定义层的一侧，所述挡墙设置于所述第二区域上的平坦层，所述防护层覆盖所述挡墙，所述挡墙的高度与所述防护层的厚度之和大于所述支撑结构的高度。
在本申请所提供的显示装置中，所述显示装置还包括阴极接触层，所述阴极接触层设置于所述第一区域的平坦层上。
在本申请所提供的显示装置中，所述显示装置还包括隔离层，所述隔离层设置于所述阴极接触层上。
在本申请所提供的显示装置中，所述显示装置还包括堤坝，所述堤坝设置于所述第二区域上的平坦层上。
在本申请所提供的显示装置中，所述显示装置还包括裂痕阻挡坝，所述裂痕阻挡坝设置于所述第二区域上的平坦层上。
本申请还提供一种显示装置的制备方法，所述显示装置包括显示区和非显示区，所述显示装置的制备方法包括：
提供一阵列基板；
在所述阵列基板上依次层叠形成平坦层以及像素定义层，所述像素定义层位于所述显示区；以及
在所述非显示区，在所述平坦层上形成防护层。
在本申请所提供的显示装置的制备方法中，所述在所述阵列基板上形成平坦层以及像素定义层的步骤之后，在所述非显示区，在所述平坦层上形成防护层的步骤之前，包括：
在所述显示区，在所述像素定义层及所述平坦层上形成保护层。
在本申请所提供的显示装置的制备方法中，所述保护层的材料为聚酯、SiOx或SiNx中的一种或几种组合。
在本申请所提供的显示装置的制备方法中，所述保护层为金属掩膜版。
在本申请所提供的显示装置的制备方法中，所述在在所述阵列基板上依次层叠形成平坦层以及像素定义层，所述像素定义层位于所述显示区的步骤之后，在所述非显示区，在所述平坦层上形成防护层的步骤之前，还包括：
在所述像素定义层上设置支撑结构材料，蚀刻形成支撑结构。
 有益效果
本申请提供一种显示装置及其制备方法，所述显示装置包括显示区和非显示区，所述显示装置包括阵列基板、平坦层、像素定义层和防护层，所述平坦层设置于所述阵列基板上，所述像素定义层位于所述显示区，所述像素定义层设置于所述平坦层上，所述防护层位于所述非显示区，所述防护层设置于所述平坦层上。在本申请中，通过在位于非显示区的平坦层上设置防护层，进而防止水氧入侵显示装置，并防止显示装置中的结构受到划伤以及不影响后续制程，进而提高显示装置的信赖性。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施方式描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请提供的显示装置的俯视图。
图2为本申请提供的显示装置沿AB线的截面图。
图3为本申请提供的显示装置的制备方法的流程图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，图1为本申请提供的显示装置的俯视图。本申请提供一种显示装置10。所述显示装置10包括显示区11和非显示区12。所述非显示区12围绕所述显示区11。所述显示装置10包括阴极膜层20、驱动芯片30、覆晶薄膜40、柔性电路板绑定区50和防护层60。所述阴极膜层20、所述驱动芯片30、所述覆晶薄膜40、所述柔性电路板绑定区50和所述防护层60位于所述非显示区12。所述阴极膜层20围绕所述显示区11设置。所述覆晶薄膜40与所述阴极膜层20连接。所述驱动芯片30绑定于所述覆晶薄膜40上。所述柔性电路板绑定区50设置于所述覆晶薄膜40远离所述阴极膜层20的一侧。设置有所述驱动芯片30。所述防护层60围绕所述阴极膜层20、所述覆晶薄膜40以及所述柔性电路板绑定区50设置。
请参阅图2，图2为本申请提供的显示装置沿AB线的截面图。所述显示装置10包括阵列基板100、平坦层200、像素定义层300和防护层60。所述非显示区12包括第一区域13和第二区域14。所述第一区域13位于靠近所述像素定义层300的一侧。所述第二区域14位于远离所述像素定义层300的一侧。
所述阵列基板100包括基板110、遮光层120、缓冲层130和晶体管140。所述基板110可以为聚酰亚胺或玻璃等。所述遮光层120和所述缓冲层130依次层叠设置于所述基板110上。所述晶体管140位于所述显示区11。所述晶体管140设置于所述缓冲层130上。所述晶体管140包括栅极141、栅极绝缘层142、有源层143、源极144和漏极145。所述栅极141设置于所述缓冲层120上。所述栅极绝缘层142覆盖所述栅极141。所述有源层143设置于所述栅极绝缘层142上。所述源极144设置于所述有源层143的一侧，并与所述有源层143电连接。所述漏极145设置于所述有源层143的另一侧，并与所述有源层143电连接。
所述平坦层200设置于所述阵列基板110上。具体的，所述平坦层200覆盖所述栅极绝缘层142以及所述有源层143。在所述显示区11，所述平坦层200包括第一通孔201和第二通孔202。所述第一通孔201贯穿所述平坦层200以暴露所述有源层143的一侧。所述第二通孔202贯穿所述平坦层200以暴露所述有源层143的另一侧。所述源极144填充于所述第一通孔201中，并通过所述第一通孔201与有源层143电连接。所述漏极145填充于所述第二通孔202中，并通过第二通孔202与所述有源层143电连接。
在另一实施例中，所述显示装置10还包括钝化层400。所述钝化层400覆盖所述平坦层200、所述源极144以及所述漏极145。在所述显示区11，所述钝化层400包括第三通孔401。所述第三通孔401贯穿所述钝化层400以暴露所述漏极145。
在另一实施例中，所述显示装置10还包括阳极500。所述阳极500设置于所述第三通孔401中以及所述钝化层400上。所述阳极500与所述漏极145电连接。
在另一实施例中，所述显示装置10还包括阴极接触层600。所述第二所述阴极接触层600设置于所述第一区域13的平坦层200上。具体的，所述阴极接触层600包括第一部分610和第二部分620。所述第一部分610与所述有源层143同层设置，设置于所述栅极绝缘层142上。在所述第一区域13，所述钝化层400还包括第一过孔402和第二过孔403。所述第一过孔402贯穿所述钝化层400及所述平坦层200以暴露所述第一部分610的一侧。所述第二过孔403贯穿所述钝化层400及所述平坦层200以暴露所述第一部分610的另一侧。所述第二部分620设置于所述第一过孔402中、所述第二过孔403以及所述钝化层400上。所述第二部分620通过所述第一过孔402以及所述第二过孔403与所述第一部分610电连接。
所述像素定义层300位于所述显示区11。所述像素定义层300设置于所述平坦层200上。具体的，所述像素定义层300设置于所述显示区11的钝化层400上。所述像素定义层300包括第四通孔301。所述第四通孔301贯穿所述像素定义层300以暴露所述阳极500。
在另一实施例中，所述显示装置10还包括隔离层700。所述隔离层700设置于所述阴极接触层600上。所述隔离层700具有若干第五通孔701。所述第五通孔701贯穿所述隔离层700以暴露所述阴极接触层600。
在本申请中，用隔离层将阴极接触层划分为多个区域，避免了在显示装置制备的过程中造成阴极接触层中的某个区域划伤或者存有异物，进而使得另外的区域仍然可以正常使用，进而提高显示装置的良率，并降低生产成本。
在另一实施例中，所述显示装10置还包括挡墙800。所述挡墙800设置于所述第二区域14上的平坦层200上。所述挡墙用于防止显示装置的结构固化之前的流动相溢出。
在另一实施例中，所述显示装10置还包括堤坝900。所述堤坝900设置于所述第二区域14上的平坦层200上。所述堤坝900与所述挡墙800同层设置，并位于所述挡墙800与所述隔离层700之间。所述堤坝900的高度h  小于所述挡墙800的高度H。
在另一实施例中，所述显示装置10还包括支撑结构1000。所述支撑结构1000设置于所述像素定义层300上。所述支撑结构1000用于支撑显示装置的结构在后续制程中对其他结构的压伤或划伤。
在另一实施例中，所述显示装10置还包括裂痕阻挡坝1100。所述裂痕阻挡坝1100设置于所述第二区域14上的平坦层200上。所述裂痕阻挡坝1100位于所述挡墙800远离所述堤坝900的一侧。裂痕阻挡坝用于防止其他结构在后续制程中产生裂痕。
所述防护层60位于所述非显示区11。所述防护层60设置于所述平坦层200上。具体的，所述防护层60覆盖所述钝化层400、所述挡墙800、所述堤坝900以及所述裂痕阻挡坝1100。所述挡墙800的高度与所述防护层60的厚度之和D大于所述支撑结构1000的高度d。所述防护层60的材料为类金刚石。所述防护层60的厚度L为3纳米-980纳米。具体的，在一些实施例中，所述防护层60的厚度L可以为4纳米、6纳米、8纳米、10纳米、206纳米、700纳米和920纳米等。当所述防护层60的厚度L在3至10 纳米之间时，所述显示装置可以弯折。
在本申请中，将挡墙的高度与所述防护层的厚度之和设置为大于所述支撑结构的高度，可以避免支撑结构在后续制程或使用过程中造成划伤或压伤，保证后续制程或使用正常进行；
防护层采用类金刚石形成，使得防护层具有防水氧渗透作用的薄硬膜，避免显示装置的其它结构在后续制程中，等待时间过长而吸入水汽，进而导致在后续制程中，水汽因受热释出而使得膜层剥离
防护层采用类金刚石形成，使得防护层具有防划伤的薄硬膜，可以减少因为金属掩膜版压伤或是划伤挡墙以及堤坝后产生的异物在后续的薄膜封装制程中造成封装失效，进而避免水氧入侵，进而提高显示装置的信赖性以及使用寿命。
防护层采用类金刚石形成，并设置在非显示区，可以减少显示装置外围金属线路因为模组制程异物压伤或是高温高湿环境造成金属氧化值上升，进而提高显示装置的良率。
在另一实施例中，所述显示装置10还包括发光层1200。所述发光层1200设置于所述第四通孔301中。所述发光层1200包括红色发光层、绿色发光层和蓝色发光层中的一种。
在另一实施例中，所述显示装置10还包括阴极1300。所述阴极1300覆盖所述发光层1200、所述像素定义层300、所述支撑结构1000、所述隔离层700以及所述第五通孔701。所述阴极1300通过所述第五通孔701与所述阴极接触层600电连接。所述阴极接触层600与所述发光层1200通过所述阴极1300电连接。所述阴极接触层600和所述阴极1300形成图1中的阴极膜层20。所述阳极500、所述发光层1200以及所述阴极1300组成有机发光二极管。
图3为本申请提供的显示装置的制备方法的流程图。本申请还提供一种显示装置的制备方法，所述显示装置10包括显示区11和非显示区12。所述显示装置的制备方法包括：
71、提供一阵列基板100。
所述阵列基板100包括基板110、遮光层120、缓冲层130和晶体管140。所述基板110可以为聚酰亚胺或玻璃等。所述遮光层120和所述缓冲层130依次层叠设置于所述基板110上。所述晶体管140位于所述显示区11。所述晶体管140设置于所述缓冲层130上。所述晶体管140包括栅极141、栅极绝缘层142、有源层143、源极144和漏极145。所述栅极141设置于所述缓冲层120上。所述栅极绝缘层142覆盖所述栅极141。所述有源层143设置于所述栅极绝缘层142上。所述源极144设置于所述有源层143的一侧，并与所述有源层143电连接。所述漏极145设置于所述有源层143的另一侧，并与所述有源层143电连接。所述有源层143形成后，所述阴极接触层600的第一部分610设置于所述第一区域13的栅极绝缘层142上。所述第一部分610与所述有源层143同层设置。
72、在所述阵列基板100上依次层叠形成平坦层200以及像素定义层300。所述像素定义层300位于所述显示区11。
具体的，在所述栅极绝缘层142以及所述有源层143上设置平坦层200材料，对所述平坦层200材料进行蚀刻，形成平坦层200。在所述显示区11，所述平坦层200包括第一通孔201和第二通孔202。所述第一通孔201贯穿所述平坦层200以暴露所述有源层143的一侧。所述第二通孔202贯穿所述平坦层200以暴露所述有源层143的另一侧。所述源极144填充于所述第一通孔201中，并通过所述第一通孔201与有源层143电连接。所述漏极145填充于所述第二通孔202中，并通过第二通孔202与所述有源层143电连接。
在一实施例中，在所述阵列基板100上形成平坦层200的步骤之后，还包括：
在所述平坦层200、所述源极144以及所述漏极145上设置钝化层400材料，对所述钝化层400材料进行蚀刻，形成钝化层400。所述钝化层400包括第三通孔401、第一过孔402和第二过孔403。所述第三通孔401位于在所述显示区11。所述第三通孔401贯穿所述钝化层400以暴露所述漏极145。第一过孔402和第二过孔403位于所述第一区域13，所述第一过孔402贯穿所述钝化层400及所述平坦层20以暴露所述第一部分610的一侧。所述第二过孔403贯穿所述钝化层400及所述平坦层20以暴露所述第一部分610的另一侧。
在一实施例中，在所述平坦层200、所述源极144以及所述漏极145上形成钝化层400的步骤之后，还包括：
在所述第三通孔401中以及所述钝化层400上形成阳极500。所述阳极500与所述漏极145电连接。
在一实施例中，在所述第三通孔401中以及所述钝化层400上形成阳极500的步骤之后，还包括：
在所述第一区域13的钝化层400上、所述第一过孔402和所述第二过孔403中设置第二所述阴极接触层600的第二部分620。所述第二部分620通过所述第一过孔402以及所述第二过孔403与所述第一部分610电连接。所述第一部分610和所述第二部分620为所述阴极接触层600。
在所述第一区域13的钝化层400上、所述第一过孔402和所述第二过孔403中设置第二所述阴极接触层600的第二部分620的步骤之后，包括：
在所述显示区11的平坦层200上设置像素定义层300。具体的，在钝化层400以及所述阴极接触层600上设置像素定义层300材料、隔离层700材料以及堤坝900材料。对所述像素定义层300材料、所述隔离层700材料以及所述堤坝900材料蚀刻形成像素定义层300、隔离层700以及堤坝900。所述像素定义层300位于所述显示区11的钝化层400上。所述像素定义层300包括第四通孔301。所述第四通孔301贯穿所述像素定义层300以暴露所述阳极500。所述隔离层700位于所述阴极接触层600上。所述隔离层700具有若干第五通孔701。所述第五通孔701贯穿所述隔离层700以暴露所述阴极接触层600。所述堤坝900位于所述第二区域14上的平坦层200上。
在本申请中，用隔离层将阴极接触层划分为多个区域，避免了在显示装置制备的过程中造成阴极接触层中的某个区域划伤或者存有异物，进而使得另外的区域仍然可以正常使用，进而提高显示装置的良率。
在一实施例中，在钝化层400以及所述阴极接触层600上设置像素定义层300、隔离层700以及堤坝900的步骤之后，还包括：
在所述像素定义层300以及所述钝化层400上设置挡墙800材料以及所述支撑结构1000材料，蚀刻形成挡墙800以及支撑结构1000。所述挡墙800位于所述第二区域14上的平坦层200上。所述挡墙用于防止显示装置的结构固化之前的流动相溢出。所述支撑结构1000位于所述像素定义层300上。所述支撑结构1000用于支撑显示装置的结构在后续制程中对其他结构的压伤或划伤。
在一实施例中，在所述像素定义层300以及所述钝化层400上形成挡墙800以及所述支撑结构1000的步骤之后，还包括：
所述第二区域14上的平坦层200上设置裂痕阻挡坝1100材料，蚀刻所述裂痕阻挡坝1100材料形成裂痕阻挡坝1100。所述裂痕阻挡坝1100位于所述挡墙800远离所述堤坝900的一侧。裂痕阻挡坝用于防止其他结构在后续制程中产生裂痕。
73、在所述非显示区12，在所述平坦层200上形成防护层60。
将所述阵列基板100、所述平坦层200以及所述像素定义层300传送至烤箱中，进行烘烤去除有机光阻中吸附的水汽。烘烤的温度为120摄氏度-250摄氏度。具体的，烘烤的温度可以为125摄氏度、146摄氏度、181摄氏度和238摄氏度等。烘烤时间为10分钟-590分钟。具体的，烘烤时间为17分钟、90分钟、260分钟、372分钟和570分钟等。时间会随着温度的升高而缩短。在烤箱中去除水汽后，在所述阵列基板100、所述像素定义层300、所述隔离层700、所述阴极接触层600以及所述支撑结构1000上形成保护层。所述保护层的材料为聚酯、SiOx或SiNx中的一种或几种组合。在本实施例中，所述保护层的材料为聚酯。然后，传送至等离子体增强化学法设备中。在所述非显示区12，在所述钝化层400、所述挡墙800、所述堤坝900以及所述裂痕阻挡坝1100上形成防护层60。所述防护层60的材料为类金刚石。所述防护层60的厚度L为3纳米-980纳米。具体的，在一些实施例中，所述防护层60的厚度L可以为4纳米、6纳米、8纳米、10纳米、206纳米、700纳米和920纳米等。当所述防护层60的厚度L在3至10 纳米之间时，所述显示装置可以弯折。形成防护层60之后，将所述阵列基板100、所述平坦层200、所述像素定义层300以及防护层60传送出等离子体增强化学法设备，并去除聚酯保护膜。
去除保护层后的步骤之后，包括:
在所述第四通孔301中填充发光层1200材料形成发光层1200。所述发光层1200包括红色发光层、绿色发光层和蓝色发光层中的一种。
在所述第四通孔301中填充发光层1200的步骤之后，包括：
在所述发光层1200、所述像素定义层300上、所述支撑结构1000上、所述隔离层700上以及所述第五通孔701中形成阴极1300。所述阴极1300通过所述第五通孔701与所述阴极接触层600电连接。所述阴极接触层600与所述发光层1200通过所述阴极1300电连接。所述阴极接触层600和所述阴极1300形成图1中的阴极膜层20。所述阳极500、所述发光层1200以及所述阴极1300组成有机发光二极管。
在另一实施例中，在烤箱中去除水汽后，可以不先在所述阵列基板100、所述像素定义层300、所述隔离层700、所述阴极接触层600以及所述支撑结构1000上形成聚酯保护层。先将其传送至等离子体增强化学法设备中。将腔体内图形化的金属掩膜版保护层与所述阵列基板100、所述像素定义层300、所述隔离层700、所述阴极接触层600经过对位贴合。所述保护层为等离子体增强化学法设备中的金属掩膜版。然后，在所述非显示区12，在所述钝化层400、所述挡墙800、所述堤坝900以及所述裂痕阻挡坝1100上形成防护层60。然后，传送出等离子体增强化学法设备，然后，在进行后续的发光层1200和阴极1300的制程。
在本申请中，将挡墙的高度与所述防护层的厚度之和设置为大于所述支撑结构的高度，可以避免支撑结构在后续制程或使用过程中造成划伤或压伤，保证后续制程或使用正常进行；防护层采用类金刚石形成，使得防护层具有防水氧渗透作用的薄硬膜，避免显示装置的其它结构在后续制程中，等待时间过长而吸入水汽，进而导致在后续制程中，水汽因受热释出而使得膜层剥离；防护层采用类金刚石形成，使得防护层具有防划伤的薄硬膜，可以减少因为金属掩膜版压伤或是划伤挡墙以及堤坝后产生的异物在后续的薄膜封装制程中造成封装失效，进而避免水氧入侵，进而提高显示装置的信赖性以及使用寿命；防护层采用类金刚石形成，并设置在非显示区，可以减少显示装置外围金属线路因为模组制程异物压伤或是高温高湿环境造成金属氧化值上升，进而提高显示装置的良率。
本申请提供一种显示装置及其制备方法，所述显示装置包括显示区和非显示区，所述显示装置包括阵列基板、平坦层、像素定义层和防护层，所述平坦层设置于所述阵列基板上，所述像素定义层位于所述显示区，所述像素定义层设置于所述平坦层上，所述防护层位于所述非显示区，所述防护层设置于所述平坦层上。在本申请中，通过在位于非显示区的平坦层上设置防护层，进而防止水氧入侵显示装置，并防止显示装置中的结构受到划伤以及不影响后续制程，进而提高显示装置的信赖性。

Claims (20)

  1. 一种显示装置，其中，所述显示装置包括显示区和非显示区，所述显示装置包括：
    一阵列基板；
    平坦层，所述平坦层设置于所述阵列基板上；
    钝化层，所述钝化层覆盖于所述平坦层；
    像素定义层，所述像素定义层位于所述显示区，所述像素定义层设置于所述钝化层上；以及
    防护层，所述防护层位于所述非显示区，所述防护层设置于所述平坦层上。
  2. 如权利要求1所述的显示装置，其中，所述防护层的材料为类金刚石。
  3. 如权利要求1所述的显示装置，其中，所述防护层的厚度为3纳米-980纳米。
  4. 如权利要求1所述的显示装置，其中，所述显示装置还包括支撑结构，所述支撑结构设置于所述像素定义层上。
  5. 如权利要求4所述的显示装置，其中，所述显示装置还包括挡墙，所述非显示区包括第一区域和第二区域，所述第一区域位于靠近所述像素定义层的一侧，所述第二区域位于远离所述像素定义层的一侧，所述挡墙设置于所述第二区域上的平坦层，所述防护层覆盖所述挡墙，所述挡墙的高度与所述防护层的厚度之和大于所述支撑结构的高度。
  6. 如权利要求4所述的显示装置，其中，所述显示装置还包括阴极接触层，所述阴极接触层设置于所述第一区域的平坦层上。
  7. 一种显示装置，其中，所述显示装置包括显示区和非显示区，所述显示装置包括：
    一阵列基板；
    平坦层，所述平坦层设置于所述阵列基板上；
    像素定义层，所述像素定义层位于所述显示区，所述像素定义层设置于所述平坦层上；以及
    防护层，所述防护层位于所述非显示区，所述防护层设置于所述平坦层上。
  8. 如权利要求7所述的显示装置，其中，所述防护层的材料为类金刚石。
  9. 如权利要求7所述的显示装置，其中，所述防护层的厚度为3纳米-980纳米。
  10. 如权利要求7所述的显示装置，其中，所述显示装置还包括支撑结构，所述支撑结构设置于所述像素定义层上。
  11. 如权利要求10所述的显示装置，其中，所述显示装置还包括挡墙，所述非显示区包括第一区域和第二区域，所述第一区域位于靠近所述像素定义层的一侧，所述第二区域位于远离所述像素定义层的一侧，所述挡墙设置于所述第二区域上的平坦层，所述防护层覆盖所述挡墙，所述挡墙的高度与所述防护层的厚度之和大于所述支撑结构的高度。
  12. 如权利要求11所述的显示装置，其中，所述显示装置还包括阴极接触层，所述阴极接触层设置于所述第一区域的平坦层上。
  13. 如权利要求12所述的显示装置，其中，所述显示装置还包括隔离层，所述隔离层设置于所述阴极接触层上。
  14. 如权利要11所述的显示装置，其中，所述显示装置还包括堤坝，所述堤坝设置于所述第二区域上的平坦层上。
  15. 如权利要11所述的显示装置，其中，所述显示装置还包括裂痕阻挡坝，所述裂痕阻挡坝设置于所述第二区域上的平坦层上。
  16. 一种显示装置的制备方法，其中，所述显示装置包括显示区和非显示区，所述显示装置的制备方法包括：
    提供一阵列基板；
    在所述阵列基板上依次层叠形成平坦层以及像素定义层，所述像素定义层位于所述显示区；以及
    在所述非显示区，在所述平坦层上形成防护层。
  17. 如权利要求16所述的显示装置的制备方法，其中，所述在所述阵列基板上形成平坦层以及像素定义层的步骤之后，在所述非显示区，在所述平坦层上形成防护层的步骤之前，包括：
    在所述显示区，在所述像素定义层及所述平坦层上形成保护层。
  18. 如权利要求17所述的显示装置的制备方法，其中，所述保护层的材料为聚酯、SiOx或SiNx中的一种或几种组合。
  19. 如权利要求16所述的显示装置的制备方法，其中，所述保护层为金属掩膜版。
  20. 如权利要求16所述的显示装置的制备方法，其中，所述在在所述阵列基板上依次层叠形成平坦层以及像素定义层，所述像素定义层位于所述显示区的步骤之后，在所述非显示区，在所述平坦层上形成防护层的步骤之前，还包括：
    在所述像素定义层上设置支撑结构材料，蚀刻形成支撑结构。
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