WO2022052045A1 - 负电容无结纳米线场效应晶体管及其制造方法 - Google Patents

负电容无结纳米线场效应晶体管及其制造方法 Download PDF

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WO2022052045A1
WO2022052045A1 PCT/CN2020/114818 CN2020114818W WO2022052045A1 WO 2022052045 A1 WO2022052045 A1 WO 2022052045A1 CN 2020114818 W CN2020114818 W CN 2020114818W WO 2022052045 A1 WO2022052045 A1 WO 2022052045A1
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dielectric layer
region
drain
source
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李龙飞
林信南
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/701—IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0415—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having ferroelectric gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/689—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having ferroelectric layers

Definitions

  • the invention relates to the field of semiconductor integrated circuit application devices, in particular to a negative capacitance junctionless nanowire field effect transistor and a manufacturing method thereof.
  • MOS devices follow "Moore's Law", and the feature size continues to shrink proportionally.
  • the disadvantages of MOS field effect transistor devices based on PN junctions are becoming more and more obvious: for example, in order to reduce the size of the device, the source-drain distance of the device is continuously shortened, resulting in source-drainage.
  • junctionless nanowire field effect transistor To overcome the insurmountable obstacles faced by junction field effect transistor devices in the nanoscale range, a junctionless nanowire field effect transistor is proposed.
  • junctionless nanowire field effect transistor structures There are two commonly used junctionless nanowire field effect transistor structures, one is a traditional doped junctionless device; the other is a junctionless device based on a charge-plasma structure.
  • the first is the traditional junctionless device, which relies on heavy doping inside the source and drain regions, and uses the gate bias voltage to change the electric field strength perpendicular to the conductive channel, so that the majority carriers in the channel are accumulated or depleted. Thereby modulating the channel conductance to control the channel current.
  • the working principle of traditional doped junctionless devices is closely related to the doping concentration, and the doping concentration is very easily affected by the fluctuation of the doping process, resulting in inconsistent doping concentration, which affects the stability of the electrical performance of the device with this structure. , and thus limit the application of this structural device in the circuit.
  • the second is a junctionless device based on a charge-plasma structure.
  • the structure of a junctionless device based on a charge-plasma structure includes a junctionless nanowire, which is defined as a source region, a channel region and a drain along the axis of the junctionless nanowire.
  • the outer surfaces of the source and drain regions are fully covered with a source-drain metal layer, and there is a source-drain dielectric layer between the source and drain regions and the source-drain metal.
  • the working principle of this device is: by controlling the source and drain
  • the work function of the metal layer and the gate metal layer adjusts the type of transistor, and induces carriers in the source and drain regions through the source-drain metal layer, and the metal layer responsible for inducing carriers is related to bulk silicon (that is, junction-free nanometers).
  • the lines) are separated by a source-drain dielectric, and a carrier path is formed on the part of the surface of the source-drain region that is not covered by the source-drain dielectric layer, so that the device works. Since the working principle of the device is independent of the doping in the source and drain regions, the device not only gets rid of the influence of the doping process, but also achieves the required functions. Therefore, the junctionless device based on the charge-plasma structure becomes a The mainstream structure of junction nanowire field effect transistors.
  • the junctionless device with charge-plasma structure in the prior art when the junctionless device with charge-plasma structure in the prior art is applied, the on-state current is small, the turn-on speed is slow, and the power consumption is high. Therefore, the junctionless device with charge-plasma structure in the prior art has The electrical performance needs to be improved.
  • the purpose of the present invention is to provide a negative capacitance junctionless nanowire field effect transistor and a manufacturing method thereof, so that its electrical properties can be improved.
  • an embodiment provides a negative capacitance junctionless nanowire field effect transistor, comprising: a junctionless nanowire, wherein the junctionless nanowire includes a source region and a channel region sequentially defined along its axis direction and drain region; the outer surface of the source region is covered with a source electrode layer, wherein an active dielectric layer is between the source electrode layer and part of the surface of the source region; the outer surface of the drain region is covered with a drain electrode There is a drain dielectric layer between the drain electrode layer and the surface of the part of the drain region; the outer peripheral surface of the channel region has a gate dielectric layer, a ferroelectric material layer and a gate electrode layer in sequence, wherein all the The gate dielectric layer covers the outer peripheral surface of the channel region, the ferroelectric material layer is located on the outer circumference of the gate dielectric layer, and the gate electrode layer is located on the outer circumference of the ferroelectric material layer.
  • the capacitance characteristic of the ferroelectric material layer is smaller than the capacitance characteristic of the gate dielectric layer; the thickness of the ferroelectric material layer is greater than the thickness of the gate dielectric layer.
  • the source and drain regions have doped regions of the same doping type as the channel region, and the doped regions of the source and drain regions are heavily doped regions, and the channel region is a lightly doped region.
  • a spacer isolation layer is provided between the gate electrode layer and the ferroelectric material layer and the source electrode layer, and a spacer is provided between the gate electrode layer and the ferroelectric material layer and the drain electrode layer Isolation layer.
  • the source, channel and drain regions are axisymmetric.
  • an embodiment provides a method for manufacturing a negative capacitance junctionless nanowire field effect transistor, the method comprising:
  • junctionless nanowire forming a junctionless nanowire, and defining an active region, a channel region and a drain region in sequence along the axis direction of the junctionless nanowire;
  • a dielectric layer including a gate dielectric layer, a source dielectric layer, and a drain dielectric layer, wherein the gate dielectric layer covers a peripheral surface surrounding the channel region, the source dielectric layer is formed in the source region part of the outer surface of the drain region, the drain dielectric layer is formed on a part of the outer surface of the drain region;
  • a gate electrode layer, a source electrode layer and a drain electrode layer are formed, the gate electrode layer is formed on the outer peripheral surface of the ferroelectric material layer; the source electrode layer is formed on the surface of the source dielectric layer and does not cover the source dielectric On the outer surface of the source region of the layer, the drain electrode layer is formed on the surface of the drain dielectric layer and the outer surface of the drain region not covering the drain dielectric layer.
  • junctionless nanowires before the forming of the junctionless nanowires, further comprising:
  • a silicon substrate is provided, and a preliminary doping process and an annealing process are performed on the silicon substrate, and the preliminary doping concentration is light doping less than or equal to 1 ⁇ 10 19 cm -3 ;
  • junctionless nanowires The silicon substrate with a certain thickness is etched to form junctionless nanowires, and the junctionless nanowires are axially symmetric.
  • the method before forming the gate electrode layer, the source electrode layer and the drain electrode layer, the method further includes:
  • Spacer isolation layers are formed on both sides of the gate dielectric layer.
  • the method further includes:
  • Parts and all of the source and drain regions are heavily doped using a doping process.
  • the method of forming a layer of ferroelectric material includes:
  • a layer of ferroelectric material is deposited on the peripheral surface surrounding the gate dielectric layer.
  • the material of the source dielectric layer and the drain dielectric layer is hafnium dioxide, and the material of the gate dielectric layer is silicon dioxide.
  • the ferroelectric material layer is a mixture of hafnium dioxide and metallic gadolinium.
  • the method further includes: forming a metal protection layer between the gate dielectric layer and the negative charge protection layer.
  • the ferroelectric material since the ferroelectric material has the characteristics of spontaneous polarization, when the ferroelectric material is placed in the electric field in different directions, the polarization of the ferroelectric material shows different When the device works in the accumulation region, the gate voltage is positive, and the polarization charge of the ferroelectric material is positive.
  • the positive polarization charge and the gate voltage work together to increase the surface potential of the semiconductor, making The drive current is larger, which improves the turn-on speed of the device; when the device works in the depletion region, the gate voltage is 0V, and the polarization charge of the ferroelectric material is negative at this time, and the negative polarization charge will make the semiconductor surface potential is negative, thereby reducing the leakage current, so that the power consumption of the device is reduced; thus, the electrical performance of the device is improved.
  • FIG. 1 is a schematic structural diagram of a negative capacitance junctionless nanowire field effect transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a negative capacitance junctionless nanowire field effect transistor according to another embodiment of the present invention.
  • FIG. 3 is a flowchart of a method for manufacturing a negative capacitance junctionless nanowire field effect transistor according to an embodiment of the present invention
  • FIGS. 4 to 9 are schematic diagrams of a manufacturing process flow diagram of a negative capacitance junctionless nanowire field effect transistor according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a negative capacitance junctionless nanowire field effect transistor according to another embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a negative capacitance junctionless nanowire field effect transistor according to still another embodiment of the present invention.
  • FIG. 12 is a flowchart of a method for manufacturing a negative capacitance junctionless nanowire field effect transistor according to another embodiment of the present invention.
  • 13A is a comparison diagram of transfer characteristic curves of a negative capacitance accumulation dual-gate charge-plasma nanowire field effect transistor and a conventional dual-gate charge-plasma nanowire field effect transistor according to an embodiment of the present invention
  • FIG. 13B is a comparison diagram of transfer characteristic curves of a negative capacitance accumulation dual-gate charge-plasma nanowire field effect transistor and a conventional accumulation dual-gate charge-plasma nanowire field effect transistor according to an embodiment of the present invention
  • 14A is a schematic diagram of the channel potential distribution of a negative capacitance accumulation dual-gate charge-plasma nanowire field effect transistor and a conventional accumulation dual-gate charge-plasma nanowire field effect transistor;
  • FIG. 14B is a schematic diagram of the channel carrier distribution of the negative capacitance accumulation type double-gate charge-plasma nanowire field effect transistor and the conventional accumulation type double gate charge-plasma nanowire field effect transistor.
  • connection and “connection” mentioned in this application, unless otherwise specified, include both direct and indirect connections (connections).
  • the analysis shows that when the charge-plasma structure junctionless device works in the accumulation region, if the surface potential of the semiconductor device can be increased, its driving current can be greatly improved; when the junctionless device works in the depletion region, The leakage current can be effectively reduced if the surface potential of the semiconductor device can be lowered.
  • the voltage node becomes smaller and smaller, and it becomes more important to ensure that the semiconductor device can be turned on and off normally at a small supply voltage.
  • the factor that determines this key issue is the subthreshold slope. (SS), however, the subthreshold slope of semiconductor devices based on electron thermal emission theory will have a minimum limit—Boltzmann limit (60mV/dec), which is also faced by traditional charge-plasma devices.
  • the sub-threshold slope becomes larger and larger. How to obtain a steeper sub-threshold slope has also become an important challenge.
  • a negative capacitance junctionless nanowire field effect transistor and a manufacturing method thereof including a source region, a channel region and a drain region; a gate dielectric layer, a gate dielectric layer, a gate dielectric layer, a A ferroelectric material layer and a gate electrode layer, wherein the gate dielectric layer covers the outer peripheral surface of the channel region, the ferroelectric material layer is located on the outer peripheral surface of the gate dielectric layer, and the gate electrode layer is located in the The outer peripheral surface of the ferroelectric material layer.
  • the polarization charge of the ferroelectric material is positive, and its positive polarization
  • the combined action of the charge and the gate voltage increases the surface potential of the semiconductor, making the drive current larger and improving the turn-on speed of the device; when the device works in the depletion region, the gate voltage is 0V, and the polarization of the ferroelectric material is at this time.
  • the charge is negative, and the negative polarized charge will make the surface potential of the semiconductor negative, thereby reducing leakage current and reducing power consumption of the device. Therefore, the electrical performance of the device is greatly improved.
  • FIG. 1 is a schematic structural diagram of a negative capacitance junctionless nanowire field effect transistor provided in this embodiment.
  • the junctionless nanowire field effect transistor includes: a junctionless nanowire 10 , and the junctionless nanowire 10 It includes a source region 12 , a channel region 11 and a drain region 13 which are sequentially defined along its axis direction.
  • the junctionless nanowire 10 is a horizontal monocrystalline silicon pillar, the two ends of the pillar are a source region 12 and a drain region 13 respectively, and the middle is a channel region 11 (shown in cross-section in FIG. 1 );
  • the junctionless nanowire 10 can also be understood as a strip-shaped single crystal silicon rod body of a transistor on an SOI substrate, and the single crystal silicon rod body includes a source region 12 , a channel region 11 and a drain region 13 .
  • the source region 12 , the channel region 11 and the drain region 13 are axially symmetric.
  • the single crystal silicon rod can be doped or lightly doped. If it is lightly doped, the doping types of the source region 12 , the channel region 11 and the drain region 13 are the same.
  • An outer surface of the source region 12 is covered with a source electrode layer 32 , wherein an active dielectric layer 22 is located between the source electrode layer 32 and a part of the surface of the source region 12 .
  • the source dielectric layer 22 covers the outer peripheral surface of the source region 12 .
  • the source dielectric layer 22 may also be located on a part of the peripheral surface of the source region 12 , or may be located on the end surface (end surface) of the source region 12 .
  • the outer surface of the drain region 13 is covered with a drain electrode layer 33 , wherein there is a drain dielectric layer 23 between the drain electrode layer 33 and a part of the surface of the drain region 13 .
  • the drain dielectric layer 23 covers the outer peripheral surface of the drain region 13 .
  • the drain dielectric layer 23 may also be located on part of the outer peripheral surface of the drain region 13 , or may be located on the end surface (end surface) of the drain region 13 .
  • the source dielectric layer 22 and the drain dielectric layer 23 are oxides. In this embodiment, the source dielectric layer 22 and the drain dielectric layer 23 are hafnium dioxide.
  • the outer peripheral surface of the channel region 11 has a gate dielectric layer 21, a ferroelectric material layer 50 and a gate electrode layer 31 in sequence, wherein the gate dielectric layer 21 covers the outer peripheral surface of the channel region 11, and the The ferroelectric material layer 50 is located on the outer peripheral surface of the gate dielectric layer 21 , and the gate electrode layer 31 is located on the outer circumference of the ferroelectric material layer 50 .
  • the gate dielectric layer 21 is a metal oxide, specifically silicon dioxide; the silicon dioxide deposition has a high degree of lattice matching with single crystal silicon, so as to avoid the crystal lattice when the single crystal silicon is in contact with other materials. device damage due to mismatch.
  • the gate electrode layer 21 is a metal conductive layer, which may be copper, aluminum or platinum.
  • the ferroelectric material has spontaneous polarization characteristics, and the capacitance characteristic of the ferroelectric material layer 50 is smaller than that of the gate dielectric layer 21 , the ferroelectric material layer 50 is disposed on the gate dielectric layer 21 and the gate electrode. Between layers 31, the entire junctionless nanowire FET device exhibits negative capacitance characteristics, that is, when the device operates in the accumulation region, the drive current is larger; when the device operates in the depletion region, the leakage current decrease.
  • the thickness of the ferroelectric material layer and the thickness of the gate dielectric layer 21 can be controlled so as to control the ferroelectric material. Capacitance properties of layer 50 and capacitance properties of the gate dielectric layer 21 .
  • a suitable thickness of the ferroelectric material layer 50 and a suitable thickness of the gate dielectric layer 21 are selected, the negative capacitance characteristic of the entire junctionless nanowire field effect transistor device will be more obvious, and the whole device can also have more excellent electrical properties. performance.
  • the thickness of the ferroelectric material layer 50 is greater than the thickness of the gate dielectric layer 21 .
  • the gate dielectric layer 21 is 0.4 nm silicon dioxide
  • the ferroelectric material layer 50 is 10 nm HZO (metal doped hafnium dioxide material), specifically, gadolinium metal doped oxide Hafnium material.
  • the metal protective layer 51 between the gate dielectric layer 21 and the ferroelectric material layer 50 ; the metal protective layer 51 is an equipotential body and will not affect the iron
  • the electrical material layer 50 plays a negative capacitance role in the whole device.
  • the metal layer 51 can increase capacitance matching to obtain better sub-threshold slope.
  • the effect of negative capacitance is achieved, and the degree of lattice mismatch between the ferroelectric material layer 50 and the gate electrode layer 31 can be reduced, and the internal defects of the device can be reduced.
  • a spacer isolation region is defined on the outer periphery of the junctionless nanowire 10 , and a spacer isolation layer 40 is formed on the sidewall isolation region, so that the gate electrode layer 31 and the ferroelectric material layer 50 are formed. It is insulated from the source electrode layer 32 and the drain electrode layer 33 on both sides. That is, there is a spacer isolation layer 40 between the gate electrode layer 31 and the ferroelectric material layer 50 and the source electrode layer 32 ; There is a sidewall isolation layer 40 between.
  • FIG. 3 is a flowchart of the manufacturing method of the junctionless nanowire field effect transistor provided by this embodiment. The method includes:
  • step S1 a junctionless nanowire 10 is formed, and a source region 12 , a channel region 11 and a drain region 13 of the junctionless nanowire 10 are sequentially defined along the axis direction of the junctionless nanowire 10 .
  • the steps of forming the junctionless nanowire 10 are:
  • a silicon substrate 11 is provided.
  • the silicon substrate 11 may be subjected to a preliminary doping process and annealed, or may not be subjected to a doping process.
  • the silicon substrate 11 with a predetermined thickness is etched to form the junctionless nanowire 10 (refer to FIG. 6 , which is a cross-sectional schematic view of the junctionless nanowire 10 in the direction of the tangent line CC1 in FIG. 5 . ).
  • the source region 12 , the channel region 11 and the drain region 13 defined by the junctionless nanowire 10 are axisymmetric.
  • step S2 a gate dielectric layer 21, a source dielectric layer 22 and a drain dielectric layer 23 are formed.
  • the gate dielectric layer 21 covers the peripheral surface of the channel region 11
  • the source dielectric layer 22 covers the peripheral surface of the source region 12
  • the drain dielectric layer 23 covers the peripheral surface of the source region 12 .
  • the outer peripheral surface of the drain region 13 is described.
  • the source dielectric layer 22 may also be formed on the end surface (end surface) of the source region 12 ; the drain dielectric layer 23 may also be formed on the end surface (end surface) of the drain region 13 .
  • the gate dielectric layer 21 , the source dielectric layer 22 and the drain dielectric layer 23 are formed by chemical vapor deposition or physical vapor deposition.
  • the gate dielectric layer 21, the source dielectric layer 22 and the drain dielectric layer 23 are oxides.
  • the dielectric constants of the materials of the source dielectric layer 22 and the drain dielectric layer 23 are selected as high oxide materials as possible;
  • the source dielectric layer 22 and the drain dielectric layer 23 are made of hafnium dioxide;
  • the gate dielectric layer 21 is made of silicon dioxide, and the gate dielectric layer 21 in this embodiment can be oxidized by dry oxygen.
  • the thickness of the source dielectric layer 22 and the drain dielectric layer 23 is thinner than that of the gate dielectric layer 21.
  • step S3 the ferroelectric material layer 50 is formed.
  • the ferroelectric material layer 50 is formed on the outer peripheral surface surrounding the gate dielectric layer 21 .
  • the ferroelectric material layer 50 is formed on the outer peripheral surface of the gate dielectric layer 21 by physical vapor deposition or chemical vapor deposition, and the ferroelectric material layer 50 is hafnium dioxide and metal gadolinium mixture.
  • a metal protection layer 51 (as shown in FIG. 2) may be deposited on the outer peripheral surface of the gate dielectric layer 21, and the The metal protection layer 51 is an equipotential body and will not affect the negative capacitance effect of the ferroelectric material layer 50 in the entire device, and the metal protection layer 51 can increase capacitance matching and obtain better sub-threshold slope.
  • other dielectric layers may be formed around the outer peripheral surface of the ferroelectric material layer 50, and the other dielectric layers at least do not affect the ferroelectric material layer 50 plays the role of negative capacitance in the whole device, and can reduce the degree of lattice mismatch between the ferroelectric material layer 50 and the gate electrode layer 31, and reduce the internal defects of the device.
  • step S4 the gate electrode layer 31, the source electrode layer 32 and the drain electrode layer 33 are formed.
  • the gate electrode layer 31 is formed on the outer peripheral surface of the ferroelectric material layer 50; the source electrode layer 32 is formed on the surface of the source dielectric layer 22 and the source region 12 not covered with the source dielectric layer On the outer surface, the drain electrode layer 33 is formed on the surface of the drain dielectric layer 23 and the outer surface of the drain region 13 not covered by the drain dielectric layer.
  • the gate electrode layer 31, the source electrode layer 32 and the drain electrode layer 33 are made of metal materials, which may be copper, aluminum, platinum, or the like.
  • spacer isolation regions may be defined before the gate dielectric layer 21 , the source dielectric layer 22 and the drain dielectric layer 23 are formed, and spacer isolation regions may be formed in the roll isolation regions Layer 40.
  • the spacer isolation layer 40 insulates and isolates the gate electrode layer 31 and the ferroelectric material layer 50 to be subsequently formed from the source electrode layer 32 and the drain electrode layer 33 on both sides.
  • the gate dielectric layer 21 may be formed first, the ferroelectric material layer 50 may be formed around the outer surface of the gate dielectric layer 21 , and the gate electrode may be formed around the outer surface of the ferroelectric material layer 50 After layer 31, spacer isolation layers 40 are formed on both sides of gate dielectric layer 21, ferroelectric material layer 50 and gate electrode layer 31.
  • the spacer isolation layers 40 make gate electrode layer 31 and ferroelectric material layer 50 and two The source electrode layer 32 and the drain electrode layer 33 on the side are insulated and isolated.
  • this embodiment will further describe the different parts in detail with reference to the accompanying drawings. In order to avoid redundant articles, the repeated parts with the first embodiment will not be repeated.
  • FIG. 10 is a schematic structural diagram of a junctionless nanowire field effect transistor provided in this embodiment.
  • the junctionless nanowire field effect transistor includes: A source region 101 , a channel region 103 and a drain region 102 are sequentially defined in the axial direction.
  • the channel region 103 is lightly doped, the source region 101 and the drain region 102 have the same doping type as the channel region 103, including the source region doped region A and the drain region doped region B , and the source doped region A and the drain doped region B are heavily doped regions.
  • light doping refers to doping with a doping concentration less than or equal to 1 ⁇ 10 19 cm -3 ;
  • heavy doping refers to doping with a doping concentration ranging from 1 ⁇ 10 19 cm -3 to 1 ⁇ 10 21 cm -3 doping.
  • the doping type is N-type doping or P-type doping.
  • the junctionless nanowire 100 can be understood as a horizontal monocrystalline silicon pillar, the two ends of the pillar are the source region 101 and the drain region 102 respectively, and the channel region 103 is in the middle; It is understood as a strip-shaped single crystal silicon rod body of a transistor on an SOI substrate, and the single crystal silicon rod body may include a channel region 103 , a source region 101 and a drain region 102 .
  • the single crystal silicon rod is undoped or lightly doped. If it is lightly doped, the doping types of the channel region 103 , the source region 101 and the drain region 102 are the same.
  • the doping types of the channel region 103 , the source region 101 and the drain region 102 are P-type doping or N-type doping.
  • the doping material can be boron or indium; when the channel region 103 , the source region 101 and the drain region 102
  • the doping material can be phosphorus, arsenic or antimony.
  • Part or all of the source region 101 and the drain region 102 are doped regions, for example, a part or all of the source region 101 is a doped region A. Part or all of the drain region 102 is the doped region B. As shown in FIG.
  • the outer surface of the source region 101 is covered with a source electrode layer 301, wherein an active dielectric layer 201 is between the source electrode layer 301 and a part of the surface of the source region 101; for example, the source dielectric layer 201 covers the the peripheral surface of the source region 101 .
  • the outer surface of the drain region 102 is covered with a drain electrode layer 302, wherein there is a leakage dielectric layer 202 between the drain electrode layer 302 and a part of the surface of the drain region 102; for example, the leakage dielectric layer 302 covers all the surfaces. the outer peripheral surface of the drain region 102 .
  • the outer peripheral surface surrounding the channel region 103 has a gate dielectric layer 203, a ferroelectric material layer 500 and a gate electrode layer 303 in sequence, wherein the gate dielectric layer 203 covers the outer peripheral surface of the channel region 103, and the The ferroelectric material layer 500 is located on the outer circumference of the gate dielectric layer 203 , and the gate electrode layer 203 is located on the outer circumference of the ferroelectric material layer 500 .
  • the source dielectric layer 201 , the drain dielectric layer 202 and the gate dielectric layer 203 are all oxides.
  • the source dielectric layer 22 and the drain dielectric layer 23 are hafnium dioxide, and the gate dielectric layer is Silica.
  • the source electrode layer 301 , the drain electrode layer 302 and the gate electrode layer 303 are metal conductive layers, which may be copper, aluminum, platinum, or the like.
  • the ferroelectric material Since the ferroelectric material has spontaneous polarization characteristics, and the capacitance characteristic of the ferroelectric material layer 500 is smaller than that of the gate dielectric layer 203 , the ferroelectric material layer 500 is disposed on the gate dielectric layer 203 and the gate electrode. Between layers 303, the entire junctionless nanowire field effect transistor device exhibits negative capacitance characteristics, that is, when the device operates in the accumulation region, the drive current is larger; when the device operates in the depletion region, the leakage current decrease.
  • the thickness of the ferroelectric material layer 500 is greater than the thickness of the gate dielectric layer 203 .
  • the gate dielectric layer 203 is 0.4 nm hafnium dioxide
  • the ferroelectric material layer 500 is 10 nm HZO (metal doped hafnium dioxide material), specifically, gadolinium metal doped oxide hafnium.
  • a metal protection layer 501 may be further provided between the gate dielectric layer 203 and the ferroelectric material layer 500 ; the metal protection layer 501 is an equipotential body and will not affect the The ferroelectric material layer 500 plays the role of negative capacitance in the whole device.
  • the metal protection layer 501 can reduce the degree of lattice mismatch and avoid internal defects of the device.
  • the negative capacitance effect is obtained, and the degree of lattice mismatch between the ferroelectric material layer 500 and the gate electrode layer 303 can be reduced, and the internal defects of the device can be reduced.
  • a spacer isolation region is defined on the outer periphery of the junctionless nanowire 100 , and a spacer isolation layer 400 is formed on the sidewall isolation region, so that the gate electrode layer 303 and the ferroelectric material layer 500 are formed. It is insulated from the source electrode layer 301 and the drain electrode layer 302 on both sides. That is, there is a spacer isolation layer 400 between the gate electrode layer 303 and the ferroelectric material layer 500 and the source electrode layer 301 ; There is a sidewall isolation layer 400 between.
  • This embodiment also provides a method for manufacturing the above-mentioned medium-negative capacitance junctionless nanowire field effect transistor.
  • the difference between the method provided in this embodiment and the first embodiment is that before step S2 in the first embodiment, the method further includes: step 1A, using a doping process to perform doping on the source region 101 and the drain region 102 with the same doping type as the doping type of the channel region 103, and the The doping concentration of the source region 101 and the drain region 102 is greater than that of the channel region 103 .
  • FIG. 12 is a flowchart of a method for manufacturing a negative capacitance junctionless nanowire field effect transistor provided in this embodiment, and the method includes:
  • step S1 a junctionless nanowire 100 is formed, and a source region 101, a drain region 102 and a channel region 103 of the junctionless nanowire 100 are sequentially defined along the axis of the junctionless nanowire 100.
  • the source region 101, The channel region 103 and the drain region 102 are axially symmetrical.
  • the method for forming the junctionless nanowire 100 includes: first, a silicon substrate 11 is provided, and a preliminary doping process and an annealing process are performed on the silicon substrate.
  • the concentration of the preliminary doping determines the doping concentration of the channel region 103 of the device.
  • the preliminary doping concentration may be light doping less than or equal to 1 ⁇ 10 19 cm ⁇ 3 .
  • the resistivity of the whole device is reduced, and the electrical performance of the device is improved.
  • a certain thickness of the silicon substrate 11 is etched to form junctionless nanowires 100 .
  • the silicon substrate 11 may not be doped, so that the channel region 103 is not doped.
  • step S1A the source region 101 and the drain region 102 are heavily doped using a doping process.
  • the doping type is P-type doping or N-type doping.
  • the doping types of the channel region 103 , the source region 101 and the drain region 102 are P-type doping or N-type doping.
  • the doping material can be boron or indium; when the channel region 103 , the source region 101 and the drain region 102
  • the doping material can be phosphorus, arsenic or antimony.
  • the source region 101 and the drain region 102 are doped by means of ion implantation, and the source region 101 and the drain region 102 are doped at a concentration of 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 21 cm -3 of heavy doping.
  • step S2 a source dielectric layer 201, a drain dielectric layer 202 and the gate dielectric layer 203 are formed.
  • step S3 a ferroelectric material layer 500 is formed.
  • the ferroelectric material layer 500 is formed on the peripheral surface surrounding the gate dielectric layer 203 .
  • the ferroelectric material layer 500 is formed on the outer peripheral surface of the gate dielectric layer 203 by physical vapor deposition or chemical vapor deposition, and the ferroelectric material layer 500 is hafnium dioxide and metal gadolinium mixture.
  • a metal protection layer 501 may be deposited on the outer peripheral surface of the gate dielectric layer 203, and the metal protection layer 501 is equipotential It will not affect the negative capacitance effect of the ferroelectric material layer 500 in the whole device, and the metal protection layer 501 is equivalent to a transition layer, which can reduce the lattice of the ferroelectric material layer 500 and the gate dielectric layer 203 The degree of mismatch reduces the internal defects of the device.
  • ferroelectric material layer 500 after the ferroelectric material layer 500 is formed, other dielectric layers may also be formed around the outer peripheral surface of the ferroelectric material layer 500, and the other dielectric layers at least do not affect the ferroelectric material layer
  • the negative capacitance played by 500 in the whole device can reduce the degree of lattice mismatch between the ferroelectric material layer 500 and the gate electrode layer 303 and reduce the internal defects of the device.
  • step S4 a source electrode layer 301, a drain electrode layer 302 and the gate electrode layer 303 are formed.
  • the inventor found that the driving current of the junctionless nanowire field effect transistor was greatly increased, the leakage current was greatly reduced, and the subthreshold slope of the device could be reduced. Below the limit value of 60mV/dec of traditional devices, the electrical performance of the junctionless nanowire field effect transistor device is greatly improved. Based on the above-mentioned junctionless nanowire field effect transistor and its manufacturing method, a comparison diagram of the electrical properties of the junctionless nanowire field effect transistor of the present application and the Charge-plasma junctionless nanowire field effect transistor in the prior art is also provided.
  • the negative capacitance junctionless nanowire field effect transistor of the present application may be referred to as a negative capacitance accumulation type double-gate Charge-plasma nanowire field effect transistor, and the fixed parameters of the device include: the junctionless nanowire 100 is made of silicon The material (may be referred to as a silicon body), wherein the doping types of the source region 101, the drain region 102 and the channel region 103 are all N-type, and the doping concentration of the channel region 103 is 1 ⁇ 10 16 cm ⁇ 3 .
  • the doping concentration of the doped region A and the doped region B is 1 ⁇ 10 20 cm ⁇ 3 ; the width and diameter of the device are 10 nm, and the thickness of the ferroelectric material layer 500 is 10 nm; the source dielectric layer 201 and the drain dielectric layer 202 are The thickness is hafnium dioxide of 0.4 nm.
  • the work function of the gate electrode layer 303 is 4.8 eV, and the work function of the source electrode layer 301 and the drain electrode layer 302 is 3.9 eV.
  • the performance comparison chart of this embodiment is obtained based on the simulation research of the two-dimensional Sentaurus TCAD software.
  • FIG. 13A is a comparison diagram of the transfer characteristic curves of the negative capacitance accumulation type dual-gate charge-plasma nanowire field effect transistor provided by this embodiment and a conventional dual-gate charge-plasma nanowire field effect transistor;
  • FIG. 13B Comparison of transfer characteristic curves of capacitive accumulation dual-gate Charge-plasma nanowire field effect transistor and accumulation dual-gate charge-plasma nanowire field effect transistor.
  • the negative capacitance accumulation type double-gate Charge-plasma structure can be more than 2 times higher than the accumulation type double-gate Charge-plasma structure, and compared with the traditional Charge-plasma nanowire junctionless device, this
  • the negative capacitance transistor provided by the invention increases the driving current by about 90 times, and the large driving current can ensure fast fast turn-off speed, so the negative capacitance accumulation type double-gate Charge-plasma structure provided by the invention has a very good high-speed switching. application prospects.
  • the negative capacitance accumulation type double gate Charge-plasma structure can reduce the leakage current by more than 5 orders of magnitude, which proves that the negative capacitance accumulation type double gate Charge-plasma structure provided by the present invention has a good low power consumption circuit application prospects.
  • the negative capacitance accumulation type double-gate Charge-plasma structure provided by the present invention can make the sub-threshold slope of the device break through the Boltzmann limit (60mV/dec) of the traditional device, so that the sub-threshold slope is reduced by 76mV/dec is reduced to 54mV/dec, an optimization of about 41%, which ensures the application of this type of device in low-voltage and low-power circuits.
  • the current switching ratio of the negative capacitance accumulation type double-gate Charge-plasma structure in the present invention can reach 1.5 ⁇ 10 14 , which is compared with 2.9 ⁇ 10 of the traditional accumulation type Charge-plasma nanowire junctionless device. 8 improves over 6 orders of magnitude.
  • 14A and 14B are schematic diagrams of channel potential distribution and carrier distribution of a negative capacitance accumulation dual-gate charge-plasma nanowire field effect transistor and a conventional accumulation dual-gate charge-plasma nanowire field effect transistor, respectively;
  • the negative capacitance accumulation dual-gate Charge-plasma nanowire FET When the device is in the off state, the negative capacitance accumulation dual-gate Charge-plasma nanowire FET has a lower surface potential than the traditional accumulation dual-gate Charge-plasma structure, so there will be a lower leakage current; and When the device is in the on state, the negative capacitance accumulation type double-gate Charge-plasma nanowire field effect transistor has a higher surface potential than the traditional accumulation type double-gate Charge-plasma structure, so it will have a higher drive current.
  • Carrier concentration distribution due to the potential distribution in Fig. 14A It can be seen that when the device is turned on, due to the higher surface potential of the negative capacitance accumulation type double-gate Charge-plasma nanowire field effect transistor, the carrier concentration will be relatively high, and the on-state current will also increase; when the device is turned on. When turned off, the carrier concentration is relatively lower and the leakage current becomes smaller due to the lower surface potential of the negative-capacitance accumulation dual-gate Charge-plasma nanowire FET.
  • the negative capacitance accumulation type dual-gate Charge-plasma nanowire field effect transistor proposed by the present invention can greatly improve the driving current, transconductance and current switching ratio of the transistor, and can effectively reduce the leakage current and subthreshold slope of the device. . That is to say, the negative capacitance device in the present invention has better application prospects for circuits such as high-speed switching, low power consumption, and high gain.
  • the term “comprising” and any other variations thereof are non-exclusive inclusion, such that a process, method, article or device including a list of elements includes not only those elements, but also not expressly listed or included in the process , method, system, article or other elements of a device.
  • the term “coupled” and any other variations thereof refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and/or any other connection.

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Abstract

一种负电容无结纳米线场效应晶体管及其制造方法，包括无结纳米线（10），源区（12）的外表面覆盖有源电极层（32），其中，源电极层（32）和源区（12）的部分表面之间有源电介质层（22）；漏区（13）的外表面覆盖有漏电极层（33），其中，漏电极层（33）和漏区（13）部分表面之间有漏电介质层（23）；环沟道区（11）的外周表面依次覆盖具有栅电介质层（21）、铁电材料层（50）以及栅电极层（31）。由于基于铁电材料的无结晶体管的负电容特性，当器件工作在积累区的时候，使得器件的驱动电流更大，提高了器件的开启速度；当器件工作在耗尽区时，使得器件的亚阈值斜率和泄漏电流减小，器件的功耗减小，极大地提高了器件的电学性能。

Description

负电容无结纳米线场效应晶体管及其制造方法 技术领域
本发明涉及半导体集成电路应用器件领域，具体涉及一种负电容无结纳米线场效应晶体管及其制造方法。
背景技术
MOS器件遵循“摩尔定律”，特征尺寸持续按比例微缩，基于PN结的MOS场效应晶体管器件弊端越来越明显：例如，为了减小器件尺寸，使器件的源漏距离不断缩短，造成源漏穿通，产生短沟道效应，使得器件的栅控能力变差，器件性能及可靠性严重退化；现有技术中提出制作超陡PN结的方法防止源漏穿通，以避免短沟道效应，但是，由于掺杂原子难以统计分布且掺杂原子易扩散等原因，在纳米尺度范围内制作超陡PN结异常困难，使得该方法造价高、实用性低。
为克服结型场效应晶体管器件在纳米尺度范围所面临的难以逾越的障碍，提出了无结的纳米线场效应晶体管。目前常用的无结的纳米线场效应晶体管结构有两种，一种是传统的掺杂型无结器件；另一种是基于charge-plasma结构的无结器件。
第一种是传统的无结器件，其依靠源漏区内部重掺杂，利用栅极偏置电压来改变垂直于导电沟道的电场强度，使沟道内的多数载流子累计或者耗尽，从而调制沟道电导以控制沟道电流。传统的掺杂型无结器件的工作原理与掺杂浓度密切相关，而掺杂浓度非常容易受到掺杂工艺波动的影响，导致掺杂浓度不一致，从而影响到该结构器件的电学性能的稳定性，并由此限制了该结构器件在电路中的应用。
第二种是基于charge-plasma结构的无结器件，基于charge-plasma结构的无结器件的结构包括无结纳米线，沿所述无结纳米线轴线上定义为源区、沟道区和漏区；所述源区和漏区的外表面全覆盖有源漏金属层，并且源区和漏区与源漏金属之间部分具有源漏介质层，该种器件工作原理是：通过控制源漏金属层与栅极金属层的功函数来调节晶体管的类型，并且通过源漏金属层在源漏区域内部诱导载流子，负责诱导出载流子的金属层与体硅(也就是无结纳米线)之间由源漏电介质隔开，在源漏区表面没有覆盖源漏电介质层的部分形成载流子通路，使得器件工作。由 于使该种器件工作原理与源漏区中的掺杂无关，因此，该器件不仅摆脱了掺杂工艺的影响，而且能达到所需功能，因此，基于charge-plasma结构的无结器件成为无结的纳米线场效应晶体管的主流结构。
但是，现有技术中的charge-plasma结构的无结器件在应用时，开态电流小，开启速度较慢，并且功耗高，因此，现有技术中的charge-plasma结构的无结器件的电学性能有待提高。
发明内容
本发明目的在于提供一种负电容无结纳米线场效应晶体管及其制造方法，使其电学性得以提升。
根据第一方面，一种实施例中提供一种负电容无结纳米线场效应晶体管，包括：无结纳米线，所述无结纳米线包括沿其轴线方向依次定义的源区、沟道区和漏区；所述源区的外表面覆盖有源电极层，其中，所述源电极层和所述源区的部分表面之间有源电介质层；所述漏区的外表面覆盖有漏电极层，其中，所述漏电极层和所述漏区部分表面之间有漏电介质层；环所述沟道区的外周表面依次具有栅电介质层、铁电材料层以及栅电极层，其中，所述栅电介质层覆盖在所述沟道区的外周表面，所述铁电材料层位于所述栅电介质层外周，所述栅电极层位于所述铁电材料层外周。
一些实施例中，所述铁电材料层的电容特性小于所述栅电介质层的电容特性；所述铁电材料层的厚度大于所述栅电介质层的厚度。
一些实施例中，所述源区和漏区具有与所述沟道区掺杂类型相同的掺杂区，且所述源区和漏区的掺杂区为重掺杂区，所述沟道区为轻掺杂区。
一些实施例中，所述栅电极层以及铁电材料层与所述源电极层之间具有侧墙隔离层，所述栅电极层以及铁电材料层与所述漏电极层之间具有侧墙隔离层。
一些实施例中，所述源区、沟道区和漏区为轴对称形。
一些实施例中，所述栅电介质层与所述铁电材料层之间具有金属保护层。
根据第二方面，一种实施例中提供一种负电容无结纳米线场效应晶 体管的制造方法，所述方法包括：
形成无结纳米线，沿所述无结纳米线的轴线方向依次定义有源区、沟道区和漏区；
形成电介质层，所述电介质层包括栅电介质层、源电介质层和漏电介质层，其中，栅电介质层覆盖在环所述沟道区的外周表面上，所述源电介质层形成在所述源区的部分外表面，所述漏电介质层形成在所述漏区的部分外表面；
形成铁电材料层，所述铁电材料层覆盖在环所述栅电介质层的外周表面上；
形成栅电极层、源电极层和漏电极层，所述栅电极层形成于环所述铁电材料层的外周表面上；所述源电极层形成于所述源电介质层表面和未覆盖源电介质层的源区外表面上，所述漏电极层形成于所述漏电介质层表面和未覆盖漏电介质层的漏区外表面上。
一些实施例中，所述形成无结纳米线之前，还包括：
提供硅衬底，对所述硅衬底进行初步掺杂工艺和退火工艺，所述初步掺杂浓度为小于或等于1×10 19cm -3的轻掺杂；
刻蚀一定厚度的所述硅衬底，形成无结纳米线，所述无结纳米线为轴对称形。
一些实施例中，形成栅电极层、源电极层和漏电极层之前，还包括：
在所述栅电介质层的两侧形成侧墙隔离层。
一些实施例中，所述形成无结纳米线之后，还包括：
使用掺杂工艺对所述源区和所述漏区的部分区域和全部区域进行重掺杂。
一些实施例中，形成铁电材料层的方法包括：
在环所述栅电介质层的外周表面上沉积铁电材料层。
一些实施例中，所述源电介质层和所述漏电介质层的材料为二氧化铪，所述栅电介质层的材料为二氧化硅。
一些实施例中，所述铁电材料层为二氧化铪与金属钆的混合物。
一些实施例中，还包括：在所述栅电介质层与所述负电保护层之间形成金属保护层。
依据上述实施例中提供的无结纳米线场效应晶体管及其制造方法，由于铁电材料具有自发极化的特性，当铁电材料置于不同方向的电场中， 铁电材料极化表现出不同的电势，当器件工作在积累区的时候，栅极电压为正，此时铁电材料的极化电荷为正，其正的极化电荷与栅极电压共同作用使得半导体表面电势增大，使得驱动电流更大，提高了器件的开启速度；当器件工作在耗尽区时，栅极电压为0V，此时铁电材料的极化电荷为负，该负的极化电荷会使半导体表面电势为负，从而降低泄漏电流，使得器件的功耗降低；从而该器件的电学性能提高。
附图说明
图1为本发明一实施例提供的一种负电容无结纳米线场效应晶体管结构示意图；
图2为本发明另一实施例提供的一种负电容无结纳米线场效应晶体管结构示意图；
图3为本发明一实施例提供的负电容无结纳米线场效应晶体管制造方法流程图；
图4至图9为本发明一实施例提供的负电容无结纳米线场效应晶体管制造工艺流程示意图；
图10为本发明又一实施例提供的一种负电容无结纳米线场效应晶体管结构示意图；
图11为本发明再一实施例提供的一种负电容无结纳米线场效应晶体管结构示意图；
图12为本发明又一实施例提供的负电容无结纳米线场效应晶体管的制造方法流程图；
图13A为本发明一实施例提供的负电容积累型双栅Charge-plasma纳米线场效应晶体管与传统双栅charge-plasma纳米线场效应晶体管的转移特性曲线对比图；
图13B为本发明一实施例提供的负电容积累型双栅Charge-plasma纳米线场效应晶体管与传统积累型双栅charge-plasma纳米线场效应晶体管的转移特性曲线对比图；
图14A为负电容积累型双栅Charge-plasma纳米线场效应晶体管与传统积累型双栅charge-plasma纳米线场效应晶体管沟道电势分布示意图；
图14B为负电容积累型双栅Charge-plasma纳米线场效应晶体管与 传统积累型双栅charge-plasma纳米线场效应晶体管沟道载流子分布示意图。
具体实施方式
下面通过具体实施方式结合附图对本发明作进一步详细说明。其中不同实施方式中类似元件采用了相关联的类似的元件标号。在以下的实施方式中，很多细节描述是为了使得本申请能被更好的理解。然而，本领域技术人员可以毫不费力的认识到，其中部分特征在不同情况下是可以省略的，或者可以由其他元件、材料、方法所替代。在某些情况下，本申请相关的一些操作并没有在说明书中显示或者描述，这是为了避免本申请的核心部分被过多的描述所淹没，而对于本领域技术人员而言，详细描述这些相关操作并不是必要的，他们根据说明书中的描述以及本领域的一般技术知识即可完整了解相关操作。
另外，说明书中所描述的特点、操作或者特征可以以任意适当的方式结合形成各种实施方式。同时，方法描述中的各步骤或者动作也可以按照本领域技术人员所能显而易见的方式进行顺序调换或调整。因此，说明书和附图中的各种顺序只是为了清楚描述某一个实施例，并不意味着是必须的顺序，除非另有说明其中某个顺序是必须遵循的。
本文中为部件所编序号本身，例如“第一”、“第二”等，仅用于区分所描述的对象，不具有任何顺序或技术含义。而本申请所说“连接”、“联接”，如无特别说明，均包括直接和间接连接(联接)。
由背景技术可知，随着工艺节点走向更小，对场效应晶体管也提出了很多苛刻的要求，比如能够在较小的节点电压下迅速地开启以及具备极低的泄漏电流从而满足低功耗方面的应用。但是现有技术中的charge-plasma结构的无结器件在应用时，开启速度较慢，功耗较高，电学性能还有待提高。
经分析可知，charge-plasma结构的无结器件工作在积累区的时候，如果能够提高该半导体器件的表面电势就可以大幅度的提高其驱动电流；当无结器件工作在耗尽区的时候，如果能够降低该半导体器件的表面电势就可以有效地减小泄漏电流。
并且，随着特征尺寸的减小，电压节点也越来越小，保证半导体器件在较小的供给电压下能够正常的开启和关闭变得更加重要，决定这一 关键问题的因素就是亚阈值斜率(SS)，然而，基于电子热发射理论的半导体器件的亚阈值斜率会存在一个最小极限——玻尔兹曼极限(60mV/dec)，传统charge-plasma器件也同样面临这个极限。而且随着尺寸越来越小，短沟道效应越来越严重，亚阈值斜率也会越来越大，如何获得较陡的亚阈值斜率也成为一个重要挑战。
在本实施例中，提供一种负电容无结纳米线场效应晶体管及其制造方法，包括源区、沟道区和漏区；环所述沟道区的外周表面依次设有栅电介质层、铁电材料层以及栅电极层，其中，所述栅电介质层覆盖在所述沟道区的外周表面，所述铁电材料层位于所述栅电介质层外周表面，所述栅电极层位于所述铁电材料层外周表面。通过利用铁电材料的自发极化特性，当器件工作在积累区的时候，栅极电压加正电，栅极电压为正，此时铁电材料的极化电荷为正，其正的极化电荷与栅极电压共同作用使得半导体表面电势增大，使得驱动电流更大，提高了器件的开启速度；当器件工作在耗尽区时，栅极电压为0V，此时铁电材料的极化电荷为负，该负的极化电荷会使半导体表面电势为负，从而降低泄漏电流，使得器件的功耗降低。因此，极大的提高了该器件的电学性能。
为使本申请的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本申请进一步详细说明。
实施例一
图1为本实施例提供的一种负电容无结纳米线场效应晶体管结构示意图，参考图1，所述无结纳米线场效应晶体管包括：无结纳米线10，所述无结纳米线10包括沿其轴线方向依次定义的源区12、沟道区11和漏区13。
本实施例中，所述无结纳米线10为横置的单晶硅柱体，该柱体两端分别源区12和漏区13，中间为沟道区11(图1为剖面展示)；所述无结纳米线10还可以理解为SOI衬底上晶体管的一个条状的单晶硅棒体，该单晶硅棒体包括源区12、沟道区11和漏区13。其中，所述源区12、沟道区11和漏区13为轴对称形。
需要说明的是，该单晶硅棒可以掺杂或者轻掺杂，若是轻掺杂时，则源区12、沟道区11和漏区13的掺杂类型相同。
所述源区12的外表面覆盖有源电极层32，其中，所述源电极层32和所述源区12的部分表面之间有源电介质层22。
本实施例中，所述源电介质层22覆盖在所述源区12的外周表面。
在一些实施例中，所述源电介质层22还可以位于部分所述源区12的外周表面，也可以位于所述源区12的端部表面(端面)。
所述漏区13的外表面覆盖有漏电极层33，其中，所述漏电极层33和所述漏区13部分表面之间有漏电介质层23。
本实施例中，所述漏电介质层23覆盖在所述漏区13外周表面。
在一些实施例中，所述漏电介质层23还可以位于部分所述漏区13的外周表面，也可以位于所述漏区13端部表面(端面)。
所述源电介质层22以及所述漏电介质层23为氧化物，本实施例中，所述源电介质层22以及所述漏电介质层23是二氧化铪。
环所述沟道区11的外周表面依次具有栅电介质层21、铁电材料层50以及栅电极层31，其中，所述栅电介质层21覆盖在所述沟道区11的外周表面，所述铁电材料层50位于所述栅电介质层21的外周表面，所述栅电极层31位于所述铁电材料层50外周。
本实施例中，所述栅电介质层21为金属氧化物，具体可以是二氧化硅；二氧化硅沉积与单晶硅的晶格匹配度高，避免单晶硅与其它材料接触时因晶格不匹配而造成器件损坏。所述栅电极层21为金属导电层，可以是铜、铝或铂。
由于铁电材料具有自发极化特性，并且所述铁电材料层50的电容特性小于所述栅电介质层21的电容特性，所述铁电材料层50设置于栅电介质层21以及所述栅电极层31之间时，整个无结纳米线场效应晶体管器件表现出负电容特性，也就是，当该器件工作在积累区的时候，驱动电流更大；当器件工作在耗尽区时，泄漏电流减小。
由于某种铁电材料和某种栅电介质层21的相对介电常数分别是一定的，因此，通常，可以通过控制铁电材料层的厚度以及栅电介质层21的厚度，来使得控制铁电材料层50的电容特性和所述栅电介质层21的电容特性。当选择合适厚度的铁电材料层50和合适厚度的栅电介质层21时，整个无结纳米线场效应晶体管器件表现出负电容特性就会越明显，也就能够使得整个器件具有更加优秀的电学性能。
本实施例中，所述铁电材料层50的厚度大于所述栅电介质层21的厚度。例如，所述栅电介质层21为0.4nm的二氧化硅，所述铁电材料层50为10nm的HZO(掺杂了金属的二氧化铪材料)，具体可以是掺杂 了钆金属的二氧化铪材料。
参考图2，在一些实施例中，所述栅电介质层21与所述铁电材料层50之间还具有金属保护层51；所述金属保护层51为等势体，不会影响所述铁电材料层50在整个器件中起到的负电容作用。并且所述金属层51可以增加电容匹配，获得更好的亚阈值斜率。
在其他一些实施例中，所述铁电材料层50和所述栅电极层31之间也可以具有其他介质层，所述其它介质层至少不影响所述铁电材料层50在整个器件中起到的负电容作用，并可以降低铁电材料层50和所述栅电极层31之间的晶格不匹配的程度，减少器件内部缺陷。
需要说明的是，在所述无结纳米线10外周上会定义出侧墙隔离区，并在侧墙隔离区上形成侧墙隔离层40，用以使栅电极层31以及铁电材料层50与两侧的源电极层32、漏电极层33之间绝缘隔离。也就是所述栅电极层31以及铁电材料层50与所述源电极层32之间具有侧墙隔离层40；所述栅电极层31以及铁电材料层50与所述漏电极层33之间具有侧墙隔离层40。
本实施例还提供上述中无结纳米线场效应晶体管的制造方法，请结合参考图3，图3为本实施例提供的无结纳米线场效应晶体管的制造方法流程图，所述方法包括：
步骤S1，形成无结纳米线10，沿所述无结纳米线的轴线方向依次定义有所述无结纳米线10的源区12、沟道区11和漏区13。
本实施例中，形成所述无结纳米线10的步骤为：
参考图4，提供硅衬底11。可以对所述硅衬底11进行初步掺杂工艺并进行退火，也可以不进行掺杂工艺。
参考图5，刻蚀预设厚度的所述硅衬底11，形成无结纳米线10(参考图6，图6为图5中沿切线CC1方向上的无结纳米线10的切面剖视示意图)。所述无结纳米线10所定义出的源区12、沟道区11和漏区13轴对称。
步骤S2，形成栅电介质层21、源电介质层22和漏电介质层23。
参考图7，所述栅电介质层21覆盖在环所述沟道区11的外周表面上，所述源电介质层22覆盖在所述源区12的外周表面，所述漏电介质层23覆盖在所述漏区13外周表面。
在一些实施例中，所述源电介质层22还可以形成于所述源区12的 端部表面(端面)；所述漏电介质层23还可以形成于所述漏区13端部表面(端面)。
本实施例中，使用化学气相沉积或物理气相沉积的方式形成栅电介质层21、源电介质层22和漏电介质层23。所述栅电介质层21、源电介质层22和漏电介质层23为氧化物，本实施例中，源电介质层22和漏电介质层23的材料的介电常数尽量选用较高的氧化材料；本实施例中，所述源电介质层22以及所述漏电介质层23的材料是二氧化铪；所述栅电介质层21的材料是二氧化硅，本实施例中的栅电介质层21可以通过干氧氧化的方法制成，沉积所述源电介质层22和漏电介质层23厚度较沉积栅电介质层21的厚度薄。
步骤S3，形成铁电材料层50。
参考图8，在环所述栅电介质层21的外周表面上形成所述铁电材料层50。
本实施例中，通过物理气相沉积或化学气相沉积的方式在环所述栅电介质层21的外周表面上形成所述铁电材料层50，所述铁电材料层50为二氧化铪与金属钆的混合物。
在其它一些实施例中，在形成所述铁电材料层50之前，还可以在所述栅电介质层21的外周表面上先沉积一层金属保护层51(如图2所示)，并且所述金属保护层51为等势体，不会影响所述铁电材料层50在整个器件中起到的负电容作用，并且所述金属保护层51可以增加电容匹配，获得更好的亚阈值斜率。
在其它一些实施例中，在形成所述铁电材料层50之后，还可以在环所述铁电材料层50外周表面形成其他介质层，所述其它介质层至少不影响所述铁电材料层50在整个器件中起到的负电容作用，并可以降低铁电材料层50和所述栅电极层31之间的晶格不匹配的程度，减少器件内部缺陷。
步骤S4，形成栅电极层31、源电极层32和漏电极层33。
参考图9，所述栅电极层31形成于环所述铁电材料层50的外周表面上；所述源电极层32形成于所述源电介质层22表面和未覆盖源电介质层的源区12外表面上，所述漏电极层33形成于所述漏电介质层23表面和未覆盖漏电介质层的漏区13外表面上。
本实施例中，所述栅电极层31、源电极层32和漏电极层33为金属 材料，可以是铜、铝和铂等。
需要说明的是，在其它一些实施例中，可以在形成栅电介质层21、源电介质层22和漏电介质层23之前，定义出侧墙隔离区，并在所述侧倾隔离区形成侧墙隔离层40。所述侧墙隔离层40使得后续形成的栅电极层31以及铁电材料层50与两侧的源电极层32、漏电极层33之间绝缘隔离。
在其它一些实施例中，可以先形成栅电介质层21，并在环所述栅电介质层21外表面形成所述铁电材料层50，环所述铁电材料层50外表面形成所述栅电极层31之后，在栅电介质层21、铁电材料层50以及栅电极层31的两侧形成侧墙隔离层40，所述侧墙隔离层40使得栅电极层31以及铁电材料层50与两侧的源电极层32、漏电极层33之间绝缘隔离。
实施例二
本实施例与实施例一的区别仅在于，所述无结纳米线场效应晶体管中的源区和漏区具有与所述沟道区掺杂类型相同的掺杂区，且所述源区和漏区的掺杂区为重掺杂区，所述沟道区为轻掺杂区。下面，本实施例将结合附图，对区别部分进一步详细说明，为避免文章冗余，与实施例一重复部分将不再赘述。
图10为本实施例提供的一种无结纳米线场效应晶体管结构示意图，参考图10，所述无结纳米线场效应晶体管包括：无结纳米线100，所述无结纳米线100沿其轴线方向依次定义的源区101、沟道区103和漏区102。所述沟道区103轻掺杂，所述源区101和漏区102具有与所述沟道区103掺杂类型相同的掺杂区，包括源区掺杂区A和漏区掺杂区B，且所述源区掺杂区A和漏区掺杂区B为重掺杂区。
本领域人员可知，轻掺杂为掺杂浓度小于或等于1×10 19cm -3的掺杂；重掺杂为掺杂浓度为1×10 19cm -3至1×10 21cm -3的掺杂。所述掺杂类型为N型掺杂或P型掺杂。
与实施例一中相同，所述无结纳米线100可以理解为一个横置的单晶硅柱体，该柱体两端分别源区101和漏区102，中间为沟道区103；还可以理解为SOI衬底上晶体管的一个条状的单晶硅棒体，该单晶硅棒体可以包括沟道区103、源区101和漏区102。该单晶硅棒为不掺杂或者轻掺杂，若是轻掺杂时，则沟道区103、源区101和漏区102的掺杂类型相同。
例如，所述沟道区103、源区101和漏区102的掺杂类型为P型掺杂或者N型掺杂。当所述沟道区103、源区101和漏区102的掺杂类型为P型掺杂时，掺杂材料可以是硼或铟；当所述沟道区103、源区101和漏区102的掺杂类型为N型掺杂时，掺杂材料可以是磷、砷或锑等。
所述源区101和漏区102的部分区域或全部区域为掺杂区，例如，所述源区101部分区域或全部区域为掺杂区A。所述漏区102的部分区域或全部区域为掺杂区B。
所述源区101的外表面覆盖有源电极层301，其中，所述源电极层301和所述源区101的部分表面之间有源电介质层201；例如，所述源电介质层201覆盖在所述源区101的外周表面。
所述漏区102的外表面覆盖有漏电极层302，其中，所述漏电极层302和所述漏区102部分表面之间有漏电介质层202；例如，所述漏电介质层302覆盖在所述漏区102的外周表面。
环所述沟道区103的外周表面依次具有栅电介质层203、铁电材料层500以及栅电极层303，其中，所述栅电介质层203覆盖在所述沟道区103的外周表面，所述铁电材料层500位于所述栅电介质层203外周，所述栅电极层203位于所述铁电材料层500外周。
所述源电介质层201、漏电介质层202和所述栅电介质层203都为氧化物，本实施例中，所述源电介质层22以及所述漏电介质层23是二氧化铪，栅电介质层为二氧化硅。
所述源电极层301、漏电极层302和所述栅电极层303、为金属导电层，可以是铜、铝或铂等。
由于铁电材料具有自发极化特性，并且所述铁电材料层500的电容特性小于所述栅电介质层203的电容特性，所述铁电材料层500设置于栅电介质层203以及所述栅电极层303之间时，整个无结纳米线场效应晶体管器件表现出负电容特性，也就是，当该器件工作在积累区的时候，驱动电流更大；当器件工作在耗尽区时，泄漏电流减小。
本实施例中，所述铁电材料层500的厚度大于所述栅电介质层203的厚度。例如，所述栅电介质层203为0.4nm的二氧化铪，所述铁电材料层500为10nm的HZO(掺杂了金属的二氧化铪材料)，具体可以是掺杂了钆金属的二氧化铪。
参考图11，在一些实施例中，所述栅电介质层203与所述铁电材料 层500之间还可以具有金属保护层501；所述金属保护层501为等势体，不会影响所述铁电材料层500在整个器件中起到的负电容作用。并且所述金属保护层501可以降低晶格不匹配的程度，避免器件内部缺陷。
在其他一些实施例中，所述铁电材料层500和所述栅电极层303之间还可以具有其他介质层，所述其它介质层至少不影响所述铁电材料层500在整个器件中起到的负电容作用，并可以降低铁电材料层500和所述栅电极层303之间的晶格不匹配的程度，减少器件内部缺陷。
需要说明的是，在所述无结纳米线100外周上会定义出侧墙隔离区，并在侧墙隔离区上形成侧墙隔离层400，用以使栅电极层303以及铁电材料层500与两侧的源电极层301、漏电极层302之间绝缘隔离。也就是所述栅电极层303以及铁电材料层500与所述源电极层301之间具有侧墙隔离层400；所述栅电极层303以及铁电材料层500与所述漏电极层302之间具有侧墙隔离层400。
本实施例还提供一种上述中负电容无结纳米线场效应晶体管的制造方法，本实施例中所提供的方法与实施例一中的区别仅在于，在实施例一中的步骤S2之前，步骤S1形成无结纳米线之后，还包括：步骤1A，使用掺杂工艺对所述源区101和所述漏区102进行与沟道区103的掺杂类型相同的掺杂，且，所述源区101和所述漏区102掺杂浓度大于所述沟道区103的掺杂浓度。下面，本实施例将结合附图，对区别部分步骤进一步详细说明，为避免文章冗余，与实施例一方法步骤重复部分将不再详细赘述。
参考图12，图12为本实施例提供的负电容无结纳米线场效应晶体管的制造方法流程图，所述方法包括：
步骤S1，形成无结纳米线100，沿所述无结纳米线的轴线方向依次定义有所述无结纳米线100的源区101、漏区102和沟道区103，所述源区101、沟道区103和漏区102为轴对称形。
本实施例中，形成所述无结纳米线100的方法包括：首先，提供硅衬底11，对所述硅衬底进行初步掺杂工艺和退火工艺。初步掺杂的浓度决定了该器件沟道区103的掺杂浓度，进行初步掺杂时，所述初步掺杂浓度可以为小于或等于1×10 19cm -3的轻掺杂。经过初步掺杂工艺之后，整体器件的电阻率降低，器件的电学性能提高。然后，刻蚀一定厚度的所述硅衬底11，形成无结纳米线100。
在其他实施例中，也可以对所述硅衬底11不进行掺杂，使得所述沟道区103中未掺杂。
步骤S1A，使用掺杂工艺对所述源区101和所述漏区102进行重掺杂。
在掺杂的过程中，需要控制注入剂量和能量，以便在源漏区域形成合适的掺杂区域。
需要说明的是，所述掺杂类型为P型掺杂或者N型掺杂。
例如，所述沟道区103、源区101和漏区102的掺杂类型为P型掺杂或者N型掺杂。当所述沟道区103、源区101和漏区102的掺杂类型为P型掺杂时，掺杂材料可以是硼或铟；当所述沟道区103、源区101和漏区102的掺杂类型为N型掺杂时，掺杂材料可以是磷、砷或锑等。
本实施例中，通过离子注入的方法对所述源区101和所述漏区102进行掺杂，所述源区101和漏区102为掺杂浓度为1×10 19cm -3至1×10 21cm -3的重掺杂。
步骤S2，形成源电介质层201、漏电介质层202和所述栅电介质层203。
步骤S3，形成铁电材料层500。
在环所述栅电介质层203的外周表面上形成所述铁电材料层500。
本实施例中，通过物理气相沉积或化学气相沉积的方式在环所述栅电介质层203的外周表面上形成所述铁电材料层500，所述铁电材料层500为二氧化铪与金属钆的混合物。
在其它一些实施例中，在形成所述铁电材料层500之前，还可以在所述栅电介质层203的外周表面上先沉积一层金属保护层501，并且所述金属保护层501为等势体，不会影响所述铁电材料层500在整个器件中起到的负电容作用，并且所述金属保护层501相当于过渡层，可以降低铁电材料层500与栅电介质层203的晶格不匹配的程度，减少器件内部缺陷。
在其它一些实施例中，在形成所述铁电材料层500之后，还可以在环所述铁电材料层500外周表面形成其他介质层，所述其它介质层至少不影响所述铁电材料层500在整个器件中起到的负电容作用，并可以降低铁电材料层500和所述栅电极层303之间的晶格不匹配的程度，减少器件内部缺陷。
步骤S4，形成源电极层301、漏电极层302和所述栅电极层303。
上述步骤S1、S2以及S4与实施例一中的细节相同，在此不再赘述。
在采用上述结构的无结纳米线场效应晶体管后，经过测试，发明人发现该无结纳米线场效应晶体管的驱动电流大幅度提高、泄漏电流大幅度减小，并且能够降低器件的亚阈值斜率到传统器件的极限值60mV/dec以下，使得该无结纳米线场效应晶体管器件的电学性能大幅度的提高。基于上述的无结纳米线场效应晶体管及其制造方法，还提供本申请的无结纳米线场效应晶体管与现有技术中Charge-plasma无结型纳米线场效应晶体管的电学性能的对比图。
在本实施例中，本申请的负电容无结纳米线场效应晶体管可以称为负电容积累型双栅Charge-plasma纳米线场效应晶体管，该器件固定的参数包括：无结纳米线100为硅材料(可称为硅体)，其中源区101、漏区102和沟道区103的掺杂类型均为N型，沟道区103的掺杂浓度为1×10 16cm -3。掺杂区A和掺杂区B的掺杂浓度为1×10 20cm -3；该器件宽度直径为10nm，铁电材料层500的厚度为10纳米；源电介质层201和漏电介质层202为厚度是0.4nm的二氧化铪。栅电极层303的功函数为4.8eV，源电极层301、漏电极层302的功函数为3.9eV。本实施例性能对比图基于二维Sentaurus TCAD软件仿真模拟研究得到。
图13A为本实施例提供的负电容积累型双栅Charge-plasma纳米线场效应晶体管与传统双栅charge-plasma纳米线场效应晶体管的转移特性曲线对比图；图13B为本实施例提供的负电容积累型双栅Charge-plasma纳米线场效应晶体管与积累型双栅charge-plasma纳米线场效应晶体管的转移特性曲线对比图。
如图13A和13B所示：
1)对于驱动电流来说，负电容积累型双栅Charge-plasma结构相比于积累型双栅Charge-plasma结构能够提高超过2倍，而相比于传统Charge-plasma纳米线无结器件，本发明提供的负电容晶体管更是将驱动电流提高了约90倍，大的驱动电流能够保证快的快关速度，从而本发明提供的负电容积累型双栅Charge-plasma结构有着很好的高速开关应用前景。
2)对于泄漏电流，负电容积累型双栅Charge-plasma结构能够将泄漏电流减小5个数量级以上，从而证明本发明提供的负电容积累型双栅 Charge-plasma结构有着良好的低功耗电路应用前景。
3)对于亚阈值斜率(SS)，本发明提供的负电容积累型双栅Charge-plasma结构能够使器件的亚阈值斜率突破传统器件玻尔兹曼极限(60mV/dec)，使亚阈值斜率由76mV/dec降到54mV/dec，优化了约41％，保证了该类型器件在低压低功耗电路中的应用。
4)对于电流开关比，本发明中的负电容积累型双栅Charge-plasma结构的电流开关比能够达到1.5×10 14，相比于传统积累型Charge-plasma纳米线无结器件的2.9×10 8提升了超过了6个数量级。
图14A和图14B分别为负电容积累型双栅Charge-plasma纳米线场效应晶体管与传统积累型双栅charge-plasma纳米线场效应晶体管沟道电势分布和载流子分布示意图；
如图14A所示：
当器件处于关态时，负电容积累型双栅Charge-plasma纳米线场效应晶体管有着相比于传统积累型双栅Charge-plasma结构更低的表面电势，所以会有更低的泄漏电流；而在器件处于开态时，负电容积累型双栅Charge-plasma纳米线场效应晶体管有着相比于传统积累型双栅Charge-plasma结构更高的表面电势，所以会有更高的驱动电流。
如14B所示：
由于图14A中的电势分布引起的载流子浓度分布。可以看到器件开启的时候，由于负电容积累型双栅Charge-plasma纳米线场效应晶体管有更高的表面电势，所以载流子浓度会相对较高，开态电流也随之提高；当器件关闭的时候，由于负电容积累型双栅Charge-plasma纳米线场效应晶体管有更低的表面电势，所以载流子浓度会相对较低，泄露电流也变得更小。
由上述结果可知，本发明提出的负电容积累型双栅Charge-plasma纳米线场效应晶体管可以大幅提高晶体管的驱动电流、跨导和电流开关比；可以有效地降低器件的泄漏电流和亚阈值斜率。也就是说本发明中的负电容器件有更好的高速开关、低功耗、高增益等电路应用前景。
本文参照了各种示范实施例进行说明。然而，本领域的技术人员将认识到，在不脱离本文范围的情况下，可以对示范性实施例做出改变和修正。例如，各种操作步骤以及用于执行操作步骤的组件，可以根据特定的应用或考虑与系统的操作相关联的任何数量的成本函数以不同的方 式实现(例如一个或多个步骤可以被删除、修改或结合到其他步骤中)。
虽然在各种实施例中已经示出了本文的原理，但是许多特别适用于特定环境和操作要求的结构、布置、比例、元件、材料和部件的修改可以在不脱离本披露的原则和范围内使用。以上修改和其他改变或修正将被包含在本文的范围之内。
前述具体说明已参照各种实施例进行了描述。然而，本领域技术人员将认识到，可以在不脱离本披露的范围的情况下进行各种修正和改变。因此，对于本披露的考虑将是说明性的而非限制性的意义上的，并且所有这些修改都将被包含在其范围内。同样，有关于各种实施例的优点、其他优点和问题的解决方案已如上所述。然而，益处、优点、问题的解决方案以及任何能产生这些的要素，或使其变得更明确的解决方案都不应被解释为关键的、必需的或必要的。本文中所用的术语“包括”和其任何其他变体，皆属于非排他性包含，这样包括要素列表的过程、方法、文章或设备不仅包括这些要素，还包括未明确列出的或不属于该过程、方法、系统、文章或设备的其他要素。此外，本文中所使用的术语“耦合”和其任何其他变体都是指物理连接、电连接、磁连接、光连接、通信连接、功能连接和/或任何其他连接。
具有本领域技术的人将认识到，在不脱离本发明的基本原理的情况下，可以对上述实施例的细节进行许多改变。因此，本发明的范围应根据以下权利要求确定。

Claims (14)

  1. 一种负电容无结纳米线场效应晶体管，其特征在于，包括：无结纳米线，所述无结纳米线包括沿其轴线方向依次定义的源区、沟道区和漏区；
    所述源区的外表面覆盖有源电极层，其中，所述源电极层和所述源区的部分表面之间有源电介质层；
    所述漏区的外表面覆盖有漏电极层，其中，所述漏电极层和所述漏区部分表面之间有漏电介质层；
    环所述沟道区的外周表面依次具有栅电介质层、铁电材料层以及栅电极层，其中，所述栅电介质层覆盖在所述沟道区的外周表面，所述铁电材料层位于所述栅电介质层外周，所述栅电极层位于所述铁电材料层外周。
  2. 如权利要求1所述的晶体管，其特征在于，所述铁电材料层的电容特性小于所述栅电介质层的电容特性；所述铁电材料层的厚度大于所述栅电介质层的厚度。
  3. 如权利要求1所述的晶体管，其特征在于，所述源区和漏区具有与所述沟道区掺杂类型相同的掺杂区，且所述源区和漏区的掺杂区为重掺杂区，所述沟道区为轻掺杂区。
  4. 如权利要求1所述的晶体管，其特征在于，所述栅电极层以及铁电材料层与所述源电极层之间具有侧墙隔离层，所述栅电极层以及铁电材料层与所述漏电极层之间具有侧墙隔离层。
  5. 如权利要求1所述的晶体管，其特征在于，所述源区、沟道区和漏区为轴对称形。
  6. 如权利要求1-5中任一项所述的晶体管，其特征在于，所述栅电介质层与所述铁电材料层之间具有金属保护层。
  7. 一种负电容无结纳米线场效应晶体管的制造方法，其特征在于，所述方法包括：
    形成无结纳米线，沿所述无结纳米线的轴线方向依次定义有源区、沟道区和漏区；
    形成电介质层，所述电介质层包括栅电介质层、源电介质层和漏电介质层，其中，栅电介质层覆盖在环所述沟道区的外周表面上，所述源电介质层形成在所述源区的部分外表面，所述漏电介质层形成在所述漏 区的部分外表面；
    形成铁电材料层，所述铁电材料层覆盖在环所述栅电介质层的外周表面上；
    形成栅电极层、源电极层和漏电极层，所述栅电极层形成于环所述铁电材料层的外周表面上；所述源电极层形成于所述源电介质层表面和未覆盖源电介质层的源区外表面上，所述漏电极层形成于所述漏电介质层表面和未覆盖漏电介质层的漏区外表面上。
  8. 如权利要求7所述的制造方法，其特征在于，所述形成无结纳米线之前，还包括：
    提供硅衬底，对所述硅衬底进行初步掺杂工艺和退火工艺，所述初步掺杂浓度为小于或等于1×10 19cm -3的轻掺杂；
    刻蚀一定厚度的所述硅衬底，形成无结纳米线，所述无结纳米线为轴对称形。
  9. 如权利要求7所述的制造方法，其特征在于，形成栅电极层、源电极层和漏电极层之前，还包括：
    在所述栅电介质层的两侧形成侧墙隔离层。
  10. 如权利要求7所述的制造方法，其特征在于，所述形成无结纳米线之后，还包括：
    使用掺杂工艺对所述源区和所述漏区的部分区域和全部区域进行重掺杂。
  11. 如权利要求7所述的制造方法，其特征在于，形成铁电材料层的方法包括：
    在环所述栅电介质层的外周表面上沉积铁电材料层。
  12. 如权利要求7所述的制造方法，其特征在于，所述源电介质层和所述漏电介质层的材料为二氧化铪，所述栅电介质层的材料为二氧化硅。
  13. 如权利要求7所述的制造方法，其特征在于，所述铁电材料层为二氧化铪与金属钆的混合物。
  14. 如权利要求7-13所述的制造方法，其特征在于，还包括：在所述栅电介质层与所述负电保护层之间形成金属保护层。
PCT/CN2020/114818 2020-09-11 2020-09-11 负电容无结纳米线场效应晶体管及其制造方法 Ceased WO2022052045A1 (zh)

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