WO2019205537A1 - 一种双栅mosfet结构 - Google Patents

一种双栅mosfet结构 Download PDF

Info

Publication number
WO2019205537A1
WO2019205537A1 PCT/CN2018/111908 CN2018111908W WO2019205537A1 WO 2019205537 A1 WO2019205537 A1 WO 2019205537A1 CN 2018111908 W CN2018111908 W CN 2018111908W WO 2019205537 A1 WO2019205537 A1 WO 2019205537A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
region
channel
channel region
oxide layer
Prior art date
Application number
PCT/CN2018/111908
Other languages
English (en)
French (fr)
Inventor
郭宇锋
张茂林
童祎
陈静
李曼
Original Assignee
南京邮电大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南京邮电大学 filed Critical 南京邮电大学
Publication of WO2019205537A1 publication Critical patent/WO2019205537A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Definitions

  • the invention belongs to the technical field of semiconductor devices, and in particular relates to a dual gate MOSFET structure.
  • the performance and density of chips are increasing, which requires the device to shrink in size.
  • short channel effects are caused.
  • the short channel effect will cause the control capability of the device gate to drop, causing the threshold voltage drift and the drain-induced barrier reduction effect, resulting in an increase in the static power consumption of the device.
  • the reduced device size will result in an increase in the electric field inside the device, increasing the generation of hot carriers and reducing the reliability of the device.
  • Document 1 such as Long W, Ou H, Kuo J M, et al. Dual-material gate (DMG) field effect transistor [J].
  • IEEE Transactions on Electron Devices, 1999, 46 (5): 865-870 A MOSFET having a two-segment gate structure. As shown in Figure 1, 1 is the first segment of the gate metal, 2 is the second segment of the gate metal, 3 is the gate oxide layer, 4 is the source, 5 is the source region, 6 is the substrate, 7 is the drain region, 8 is The drain, 9 is the substrate electrode.
  • the structure improves the controllability of the gate and enhances the transport characteristics of the electron by utilizing the characteristics of two materials having different work functions.
  • the manufacturing process of the double-segment gate is very cumbersome, the cost is high and it is not suitable for use in a very large scale integrated circuit.
  • Document 2 such as Zhang Zhecheng, Chinese Patent, 201710288728.2, proposes a FinFET structure MOS transistor.
  • 1 is a gate
  • 2 is a gate oxide layer
  • 3 is a source region
  • 4 is a channel region
  • 5 is a drain region
  • 6 is a substrate.
  • the device increases the number of gates and three-dimensionalizes the channel, which increases the effective channel width of the device while improving the control capability of the gate, thereby increasing the current driving capability and effectively suppressing the short channel. effect.
  • the electric field strength inside the device is increased, thereby reducing the reliability of the device.
  • Document 3 for example, US Patent Colinge JP. Junctionless metal-oxide-semiconductor transistor: U.S. Patent 8,178,862 [P].
  • 2012-5-15 proposes a junctionless field effect transistor. As shown in FIG. 3, 1 is the first gate, 2 is the first gate oxide layer, 3 is the source, 4 is the source region, 5 is the channel region, 6 is the drain region, 7 is the drain, and 8 is the first The second gate oxide layer, 9 is the second gate.
  • the invention utilizes the characteristics of the depletion region to control the turn-on and turn-off of the device. Since there is no PN junction, the manufacturing process is relatively simple. The channel and source and drain regions of the structure are doped with impurities of the same type and high concentration. However, the carrier fluctuation effect makes the internal carrier concentration distribution of the device inconsistent, which limits the large-scale application of the device.
  • the purpose of the utility model is to provide a double-gate MOSFET structure, which can effectively control the short channel effect, improve the driving ability of the current, and can reduce the electric field peak inside the device and improve the reliability of the device.
  • a dual gate MOSFET structure includes: a channel region having a gradual thickness, a source region having a small thickness of the channel region, and a drain region on a side having a large thickness, the source region being far away
  • the side of the channel region is provided with a source
  • the drain region is provided with a drain away from the side of the channel region; the upper and lower surfaces of the connected channel region, the source region and the drain region respectively cover the first gate oxide layer and the first a second gate oxide layer, a first gate is disposed on an upper surface of a portion of the first gate oxide layer covering the channel region, and a second gate is disposed on a lower surface of a portion of the second gate oxide layer covering the channel region, the first gate
  • the pole and the second gate form a double gate structure.
  • a preferred embodiment of the present invention is that the extended faces of the upper and lower surfaces of the channel region must intersect.
  • the material of the channel region, the source region and the drain region is silicon or germanium, germanium silicon, gallium arsenide, gallium nitride.
  • the doping type of the channel region, the source region and the drain region is P-type or N-type.
  • the material of the first gate oxide layer and the second gate oxide layer is an insulating material of an oxide or a nitride.
  • the material of the source, the drain, the first gate and the second gate is polysilicon or metal.
  • the utility model has the beneficial effects that: the channel with a small thickness near the source region in the structure can effectively provide the gate control capability, thereby reducing the short channel effect; and the channel having a larger thickness near the drain region can be effectively reduced.
  • the electric field strength, and the oblique PN junction due to the change of the channel thickness can reduce the electric field strength, so the electric field peak of the drain region is reduced.
  • the scattering inside the device is improved, and the device structure is improved. It can effectively enhance the current drive capability.
  • FIG. 1 is a schematic view of a two-segment grid structure used in Document 1 in the background art
  • FIG. 2 is a schematic diagram of a FinFET structure employed in Document 1 in the background art
  • FIG. 3 is a schematic diagram of a junctionless MOSFET structure adopted in Document 1 in the background art
  • FIG. 4 is a schematic cross-sectional view showing the structure of a dual gate MOSFET of the present invention.
  • FIG. 5 is a three-dimensional schematic diagram of a dual gate MOSFET structure according to Embodiment 1 of the present invention.
  • FIG. 6 is a three-dimensional schematic diagram of a dual gate MOSFET structure according to a second embodiment of the present invention.
  • Figure 7 is a schematic view showing the improvement of the channel potential distribution of the present invention.
  • Figure 8 is a schematic view showing the improvement of surface distribution of the present invention.
  • Figure 9 is a schematic illustration of the improved transconductance of the present invention.
  • a dual-gate MOSFET structure includes: a channel region 5 having a gradual thickness; a side of the channel region 5 having a small thickness is provided with a source region 4, and a side having a large thickness is provided with a drain region. 6.
  • the source region 4 is provided with a source 3 away from the side of the channel region, and the drain region 6 is provided with a drain 7 away from the side of the channel region; the upper channel region 5, the source region 4 and the drain region 6 are connected
  • the lower surface respectively covers the first gate oxide layer 2 and the second gate oxide layer 8.
  • the upper surface of the portion of the first gate oxide layer 2 covering the channel region is provided with the first gate electrode 1, and the second gate oxide layer 8 covers the trench
  • the lower surface of the portion of the track region is provided with a second gate electrode 9, and the first gate electrode 1 and the second gate electrode 9 constitute a double gate structure.
  • the material of the channel region 5, the source region 4 and the drain region 6 is silicon or germanium, germanium silicon, gallium arsenide, gallium nitride.
  • the doping type of the channel region 5, the source region 4, and the drain region 6 is P-type or N-type.
  • the material of the first gate oxide layer 2 and the second gate oxide layer 8 is an insulating material of an oxide or a nitride.
  • the material of the source 3, the drain 7, the first gate 1 and the second gate 9 is polysilicon or metal.
  • the channel thickness of a conventional dual gate MOSFET is set to 10 nm.
  • FIG. 7 is a comparison of the channel potential of the conventional double gate structure and the gradient channel thickness double gate structure proposed by the present invention.
  • Figure 8 is a comparison of the surface electric field of a conventional double gate structure with a graded channel thickness double gate structure proposed by the present invention.
  • Figure 9 is a transconductance comparison of a conventional double gate structure with a graded channel thickness double gate structure proposed by the present invention.
  • the channel potential distribution of the conventional double gate structure and the graded channel thickness double gate structure proposed by the present invention is compared in FIG.
  • the potential of the drain region 6 will affect the potential distribution of the channel region 5.
  • the channel potential will rise, so the threshold required for the device to be turned on The voltage will decrease.
  • the rise of the potential will cause a decrease in the barrier between the source region 4 and the channel region 5, thereby affecting the subthreshold characteristics of the device, increasing the leakage of the device, and thus increasing the static power consumption.
  • the channel potential of the graded channel thickness double gate structure is lower than that of the conventional double gate structure. This means that the gradient channel thickness double gate structure can effectively suppress the short channel effect, making the device threshold voltage more stable, reducing leakage current and reducing static power consumption.
  • the surface electric field distribution of the conventional double gate structure and the gradient channel thickness double gate structure proposed by the present invention is compared in FIG. As the device size shrinks, the internal electric field strength gradually increases, resulting in a decrease in device reliability. As can be seen from FIG. 8, the peak value of the drain region of the double-gate structure of the gradation channel thickness is lower than the peak value of the drain region of the conventional double gate structure. This means that the gradient channel thickness double gate structure can effectively reduce the peak value of the electric field in the drain region, thereby reducing the breakdown voltage of the device, suppressing the generation of hot carriers, and improving the reliability of the device.
  • Transconductance is a key parameter of the device. The larger the transconductance, the faster the device works. It is not difficult to find from Fig. 9 that the transconductance of the double-gate structure of the graded channel thickness is higher than that of the conventional double-gate structure, so the operating speed of the double-gate structure of the graded channel thickness is higher than that of the conventional double-gate structure. . This is because the double-gate structure of the gradient channel thickness can reduce the electron scattering effect of the inversion layer, thereby increasing the mobility of the electrons, thereby improving the transconductance of the device.
  • the XY plane is defined to be parallel to the wafer surface, and the Z direction is defined as the normal direction of the wafer surface.
  • the channel region 5 is arranged in a gradient thickness in the Z direction, the lower surface thereof is horizontal, the upper surface is in a sloped state, the source region 4 is provided on the side having a small thickness, and the drain region 6 is provided on the side having a large thickness.
  • a source 3 is disposed on a side away from the channel region, and a drain 7 is disposed on a side of the drain region 6 away from the channel region; upper and lower surfaces of the connected channel region 5, source region 4, and drain region 6 are respectively Covering the first gate oxide layer 2 and the second gate oxide layer 8, the upper surface of the portion of the first gate oxide layer 2 covering the channel region is provided with the first gate electrode 1, and the second gate oxide layer 8 covers the portion of the channel region
  • the lower surface is provided with a second gate electrode 9, and the first gate electrode 1 and the second gate electrode 9 form a double gate structure.
  • the thickness of the channel region 5 on the side of the source region 4 is smaller than the thickness on the side of the drain region 6.
  • a channel having a small thickness close to the source region 4 can effectively provide a gate.
  • the pole control ability reduces the short channel effect; the thicker channel near the drain region 6 can effectively reduce the electric field strength, and the oblique PN junction due to the change of the channel thickness can reduce the electric field strength, thus the drain region The electric field peak of 6 is reduced; finally, due to the gradual change of the channel thickness, the scattering inside the device is improved, and the structure of the device can effectively enhance the current driving capability.
  • the XY plane is defined as being parallel to the wafer surface, and the Z direction is defined as the normal direction of the wafer surface, in which the channel region 5 is set to a gradual thickness on the XY plane;
  • the source region 4 and the drain region 6 are respectively disposed on both sides of the track region 5;
  • the gate oxide layer 2 covers the front and rear surfaces and the upper surface of the channel region 5;
  • the gate electrode 1 is disposed on the surface of the gate oxide layer 2;
  • the thickness above the channel region 5 is set to be much larger than the thickness of the front and rear surfaces of the channel region 5. With this arrangement, the portion of the gate 1 above the channel will not provide control, so that the front and back portions of the gate 1 form a double gate structure.
  • the thickness of the channel region 5 on the side of the source region 4 is smaller than the thickness on the side of the drain region 6.
  • a channel having a small thickness close to the source region 4 can effectively provide a gate.
  • the pole control ability reduces the short channel effect; the thicker channel near the drain region 6 can effectively reduce the electric field strength, and the oblique PN junction due to the change of the channel thickness can reduce the electric field strength, thus the drain region The electric field peak of 6 is reduced; finally, due to the gradual change of the channel thickness, the scattering inside the device is improved, and the structure of the device can effectively enhance the current driving capability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种双栅MOSFET结构，包括：呈渐变厚度的沟道区，沟道区的厚度小的一侧设有源区，其厚度大的一侧设有漏区，源区远离沟道区的侧边设有源极，漏区远离沟道区的侧边设有漏极；相连的沟道区、源区和漏区的上、下表面分别覆盖第一栅氧层和第二栅氧层，第一栅氧层覆盖沟道区的部分的上表面设有第一栅极，第二栅氧层覆盖沟道区的部分的下表面设有第二栅极，第一栅极和第二栅极构成双栅结构。本发明所提供的器件结构既能有效地抑制短沟道效应，又能提高电流驱动能力，减小漏区的电场峰值；且工艺步骤相对简单，可与现有CMOS工艺相兼容。

Description

一种双栅MOSFET结构 技术领域
本发明属于半导体器件技术领域，具体涉及一种双栅MOSFET结构。
背景技术
随着集成电路的快速发展，芯片的性能和密度随之不断增加，这要求器件尺寸不断缩小，然而当器件的尺寸缩小到一定程度时将引发短沟道效应。短沟道效应将会导致器件栅极的控制能力下降，从而引起阈值电压的漂移和漏致势垒降低效应，从而导致器件的静态功耗增加。与此同时，缩小的器件尺寸将导致器件内部的电场升高，增加了热载流子的生成，降低器件的可靠性。
据申请人了解，为了改善MOSFET的短沟道效应，研究人员提出了各种措施。文献1，如Long W,Ou H,Kuo J M,et al.Dual-material gate(DMG)field effect transistor[J].IEEE Transactions on Electron Devices,1999,46(5):865-870提出了一种具有双段栅结构的MOSFET。如图1所示，1是第一段栅金属，2是第二段栅金属，3是栅氧层，4是源极，5是源区，6是衬底，7是漏区，8是漏极，9是衬底电极。该结构通过利用了两种具有不同功函数的材料的特性，提高了栅极的控制能力，并且增强了电子的运输特性。但是由于双段栅的制造工艺十分繁琐，因此其成本较高，不适合应用于超大规模集成电路中。
文献2，如张哲诚，中国专利，201710288728.2，提出了一种FinFET结 构的MOS晶体管。如图2所示，1是栅极，2是栅氧层，3是源区，4是沟道区，5是漏区，6是衬底。该器件增加了栅极的数量，并且将沟道三维化，使得器件的有效沟道宽度增加的同时提高了栅极的控制能力，因此增大了电流驱动能力，并且有效地抑制了短沟道效应。然而由于沟道尺寸的下降，增加了器件内部的电场强度，从而降低器件的可靠性。
文献3，如美国专利Colinge JP.Junctionless metal-oxide-semiconductor transistor:U.S.Patent8,178,862[P].2012-5-15提出了一种无结型场效应晶体管。如图3所示，1是第一栅极，2是第一栅氧层，3是源极，4是源区，5是沟道区，6是漏区，7是漏极，8是第二栅氧层，9是第二栅极。该发明利用了耗尽区的特性来控制器件的开启和关断。由于不存在PN结，其制造工艺较为简单。该结构的沟道和源漏区都需掺杂相同类型且浓度很高的杂质，然而载流子涨落效应，使得器件内部载流子浓度分布不一致，限制了该器件的大规模应用。
实用新型内容
本实用新型的目的在于：一种双栅MOSFET结构，可以有效控制短沟道效应，提高电流的驱动能力，并能降低器件内部的电场峰值，提高器件的可靠性。
为了达到以上目的，一种双栅MOSFET结构，包括：呈渐变厚度的沟道区，沟道区的厚度小的一侧设有源区，其厚度大的一侧设有漏区，源区远离沟道区的侧边设有源极，漏区远离沟道区的侧边设有漏极；相连的沟道区、源区和漏 区的上、下表面分别覆盖第一栅氧层和第二栅氧层，第一栅氧层覆盖沟道区的部分的上表面设有第一栅极，第二栅氧层覆盖沟道区的部分的下表面设有第二栅极，第一栅极和第二栅极构成双栅结构。
本实用新型的优选方案是：沟道区的上、下两表面的延长面必会相交。
优选地，沟道区、源区和漏区的材料为硅或锗、锗硅、砷化镓、氮化镓。
优选地，沟道区、源区和漏区的掺杂类型为P型或N型。
优选地，第一栅氧层和第二栅氧层的材料为氧化物或氮化物的绝缘材料。
优选地，源极、漏极、第一栅极和第二栅极的材料为多晶硅或金属。
本实用新型有益效果为：该结构中靠近源区的厚度较小的沟道可以有效地提供栅极控制能力，从而降低短沟道效应；而靠近漏区的厚度较大的沟道可以有效降低电场强度，同时由于沟道厚度的变化而产生的斜PN结可以降低电场强度，因此漏区的电场峰值得以降低；最后由于沟道厚度的渐变，器件内部的散射作用得以改善，使该器件结构能够有效地增强电流驱动能力。
附图说明
下面结合附图对本实用新型作进一步的说明。
图1为背景技术中文献1采用的双段栅结构的示意图；
图2为背景技术中文献1采用的FinFET结构的示意图；
图3为背景技术中文献1采用的无结MOSFET结构的示意图；
图4为本发明的双栅MOSFET结构的截面示意图；
图5是本发明实施例一的双栅MOSFET结构三维示意图；
图6是本发明实施例二的双栅MOSFET结构三维示意图；
图7是本发明对沟道电势分布改善的示意图；
图8是本发明对表面分布改善的示意图；
图9是本发明对跨导改善的示意图。
具体实施方式
如图4所示，一种双栅MOSFET结构，包括：呈渐变厚度的沟道区5，沟道区5的厚度小的一侧设有源区4，其厚度大的一侧设有漏区6，源区4远离沟道区的侧边设有源极3，漏区6远离沟道区的侧边设有漏极7；相连的沟道区5、源区4和漏区6的上、下表面分别覆盖第一栅氧层2和第二栅氧层8，第一栅氧层2覆盖沟道区的部分的上表面设有第一栅极1，第二栅氧层8覆盖沟道区的部分的下表面设有第二栅极9，第一栅极1和第二栅极9构成双栅结构。
沟道区5的上、下两表面的延长面必会相交。
沟道区5、源区4和漏区6的材料为硅或锗、锗硅、砷化镓、氮化镓。
沟道区5、源区4和漏区6的掺杂类型为P型或N型。
第一栅氧层2和第二栅氧层8的材料为氧化物或氮化物的绝缘材料。
源极3、漏极7、第一栅极1和第二栅极9的材料为多晶硅或金属。
如图7-图9所示，选取三种渐变沟道厚度双栅结构与常规双栅MOSFET进行性能对比，分别为(t源＝5nm，t漏＝10nm)，(t源＝5nm，t漏＝15nm) 和(t源＝10nm，t漏＝15nm)，其中t源表示靠近源区4的沟道厚度，t漏表示靠近漏区6的沟道厚度。常规双栅MOSFET的沟道厚度设置为10nm。
其中，图7是常规双栅结构与本发明所提出的渐变沟道厚度双栅结构的沟道电势对比。图8是常规双栅结构与本发明所提出的渐变沟道厚度双栅结构的表面电场对比。图9是常规双栅结构与本发明所提出的渐变沟道厚度双栅结构的跨导对比。
在图7中比较了常规双栅结构与本发明所提出的渐变沟道厚度双栅结构的沟道电势分布。当器件沟道长度缩短时，漏区6的电势将会影响沟道区5的电势分布，通常来说，随着沟道长度的缩短，沟道电势将会抬升，因此器件开启所需的阈值电压将会降低。并且电势的升高将会导致源区4和沟道区5之间的势垒的降低，从而影响器件的亚阈值特性，器件漏电增加，进而静态功耗增加。由图7可知，渐变沟道厚度双栅结构的沟道电势比常规双栅结构的沟道电势更低。这就意味着渐变沟道厚度双栅结构可以有效抑制短沟道效应，使得器件阈值电压更加稳定，降低漏电流，减小静态功耗。
在图8中比较了常规双栅结构与本发明所提出的渐变沟道厚度双栅结构的表面电场分布。随着器件尺寸的缩小，其内部的电场强度逐渐升高，导致器件可靠性下降。从图8中可知，渐变沟道厚度双栅结构的漏区电场峰值比常规双栅结构的漏区电场峰值更低。这意味着渐变沟道厚度双栅结构可以有效降低漏区电场峰值，从而降低器件的击穿电压，抑制热载流子的生成，提高器件的可 靠性。
在图9中比较了常规双栅结构与本发明所提出的渐变沟道厚度双栅结构的跨导随着栅电压的变化情况。跨导是器件的一个关键参数，跨导越大，意味着器件的工作速度越快。从图9中不难发现，渐变沟道厚度双栅结构的跨导比常规双栅结构的跨导更高，因此渐变沟道厚度双栅结构的工作速度比常规双栅结构的工作速度更高。这是由于渐变沟道厚度双栅结构可以降低反型层的电子散射作用，从而提高电子的迁移率，进而提高器件的跨导。
实施例一
如图5所示，在本实施例中XY面定义为与晶圆表面平行，Z方向定义为晶圆表面的法线方向，
沟道区5在Z方向上设置为渐变厚度，其下表面为水平，上表面呈斜面状态，厚度小的一侧设有源区4，其厚度大的一侧设有漏区6，源区4远离沟道区的侧边设有源极3，漏区6远离沟道区的侧边设有漏极7；相连的沟道区5、源区4和漏区6的上、下表面分别覆盖第一栅氧层2和第二栅氧层8，第一栅氧层2覆盖沟道区的部分的上表面设有第一栅极1，第二栅氧层8覆盖沟道区的部分的下表面设有第二栅极9，第一栅极1和第二栅极9构成双栅结构。
在该结构中，沟道区5在源区4一侧的厚度要比在漏区6一侧的厚度小，通过这种设置，靠近源区4的厚度较小的沟道可以有效地提供栅极控制能力，从而降低短沟道效应；而靠近漏区6的厚度较大的沟道可以有效降低电场强度， 同时由于沟道厚度的变化而产生的斜PN结可以降低电场强度，因此漏区6的电场峰值得以降低；最后由于沟道厚度的渐变，器件内部的散射作用得以改善，导致该器件结构能够有效地增强电流驱动能力。
实施例二
如图6所示，在本实施例中XY面定义为与晶圆表面平行，Z方向定义为晶圆表面的法线方向，该结构中沟道区5在XY面上设置为渐变厚度；沟道区5的两侧分别设置源区4和漏区6；栅氧层2覆盖于沟道区5的前后表面和上表面；栅极1设置于覆盖在栅氧层2表面；栅氧层2在沟道区5的上方的厚度设置为远大于在沟道区5前后表面的厚度。通过这种设置，栅极1在沟道上方的部分将不提供控制能力，从而栅极1的前后部分构成双栅结构.
在该结构中，沟道区5在源区4一侧的厚度要比在漏区6一侧的厚度小，通过这种设置，靠近源区4的厚度较小的沟道可以有效地提供栅极控制能力，从而降低短沟道效应；而靠近漏区6的厚度较大的沟道可以有效降低电场强度，同时由于沟道厚度的变化而产生的斜PN结可以降低电场强度，因此漏区6的电场峰值得以降低；最后由于沟道厚度的渐变，器件内部的散射作用得以改善，导致该器件结构能够有效地增强电流驱动能力。
除上述实施例外，本实用新型还可以有其他实施方式。凡采用等同替换或等效变换形成的技术方案，均落在本实用新型要求的保护范围。

Claims (6)

  1. 一种双栅MOSFET结构，其特征在于，包括：呈渐变厚度的沟道区，所述沟道区的厚度小的一侧设有源区，其厚度大的一侧设有漏区，所述源区远离沟道区的侧边设有源极，所述漏区远离沟道区的侧边设有漏极；相连的所述沟道区、所述源区和所述漏区的上、下表面分别覆盖第一栅氧层和第二栅氧层，所述第一栅氧层覆盖所述沟道区的部分的上表面设有第一栅极，所述第二栅氧层覆盖所述沟道区的部分的下表面设有第二栅极，所述第一栅极和所述第二栅极构成双栅结构。
  2. 根据权利要求1所述的一种双栅MOSFET结构，其特征在于，所述沟道区的上、下两表面的延长面必会相交。
  3. 根据权利要求1所述的一种双栅MOSFET结构，其特征在于，所述沟道区、所述源区和所述漏区的材料为硅或锗、锗硅、砷化镓、氮化镓。
  4. 根据权利要求1所述的一种双栅MOSFET结构，其特征在于，所述沟道区、所述源区和所述漏区的掺杂类型为P型或N型。
  5. 根据权利要求1所述的一种双栅MOSFET结构，其特征在于，所述第一栅氧层和所述第二栅氧层的材料为氧化物或氮化物的绝缘材料。
  6. 根据权利要求1所述的一种双栅MOSFET结构，其特征在于，所述源极、所述漏极、所述第一栅极和所述第二栅极的材料为多晶硅或金属。
PCT/CN2018/111908 2018-04-28 2018-10-25 一种双栅mosfet结构 WO2019205537A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810398766.8 2018-04-28
CN201810398766.8A CN108767011A (zh) 2018-04-28 2018-04-28 一种双栅mosfet结构

Publications (1)

Publication Number Publication Date
WO2019205537A1 true WO2019205537A1 (zh) 2019-10-31

Family

ID=64012201

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/111908 WO2019205537A1 (zh) 2018-04-28 2018-10-25 一种双栅mosfet结构

Country Status (2)

Country Link
CN (1) CN108767011A (zh)
WO (1) WO2019205537A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110416288A (zh) * 2019-08-01 2019-11-05 南京邮电大学 一种双栅隧穿晶体管结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008192819A (ja) * 2007-02-05 2008-08-21 Toshiba Corp 半導体装置
CN101501861A (zh) * 2006-08-04 2009-08-05 Nxp股份有限公司 制造双栅晶体管的方法
KR20120066150A (ko) * 2010-12-14 2012-06-22 서강대학교산학협력단 비대칭 활성영역을 갖는 터널링 전계효과 트랜지스터
US20130001589A1 (en) * 2011-01-03 2013-01-03 International Business Machines Corporation Lateral extended drain metal oxide semiconductor field effect transistor (ledmosfet) with tapered dielectric plates to achieve a high drain-to-body breakdown voltage, a method of forming the transistor and a program storage device for designing the transistor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461250A (en) * 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
CN105826391B (zh) * 2016-05-19 2018-12-25 杭州电子科技大学 一种非对称双栅无结场效应晶体管

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101501861A (zh) * 2006-08-04 2009-08-05 Nxp股份有限公司 制造双栅晶体管的方法
JP2008192819A (ja) * 2007-02-05 2008-08-21 Toshiba Corp 半導体装置
KR20120066150A (ko) * 2010-12-14 2012-06-22 서강대학교산학협력단 비대칭 활성영역을 갖는 터널링 전계효과 트랜지스터
US20130001589A1 (en) * 2011-01-03 2013-01-03 International Business Machines Corporation Lateral extended drain metal oxide semiconductor field effect transistor (ledmosfet) with tapered dielectric plates to achieve a high drain-to-body breakdown voltage, a method of forming the transistor and a program storage device for designing the transistor

Also Published As

Publication number Publication date
CN108767011A (zh) 2018-11-06

Similar Documents

Publication Publication Date Title
Imenabadi et al. A novel PNPN-like Z-shaped tunnel field-effect transistor with improved ambipolar behavior and RF performance
Chen et al. Symmetric U-shaped gate tunnel field-effect transistor
Chattopadhyay et al. Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor
Chaudhry et al. Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review
US8860140B2 (en) Tunneling field effect transistor and method for forming the same
Biswas et al. Fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs
KR101286707B1 (ko) 독립된 듀얼 게이트의 핀펫 구조를 갖는 터널링 전계효과 트랜지스터 및 그 제조방법
Yamada et al. Suppression of drain-induced barrier lowering in silicon-on-insulator MOSFETs through source/drain engineering for low-operating-power system-on-chip applications
Goswami et al. Optimization of electrical parameters of pocket doped soi tfet with l shaped gate
Ramezani et al. An asymmetric nanoscale SOI MOSFET by means of a PN structure as virtual Hole’s well at the source side
Kumar et al. Dual-material gate-drain overlapped DG-TFET device for low leakage current design
CN105118858B (zh) 纵向隧穿场效应晶体管
WO2019205537A1 (zh) 一种双栅mosfet结构
CN107611170B (zh) 开态电流增强的纵向隧穿场效应晶体管
CN110729355B (zh) 一种改善亚阈值摆幅的纵向隧穿场效应晶体管
KR102273935B1 (ko) 음성 트랜스 컨덕턴스 기반의 터널링 트랜지스터
KR102131902B1 (ko) 터널링 전계효과 트랜지스터 및 이의 제조방법
WO2013063975A1 (zh) 隧穿场效应晶体管结构及其形成方法
Mishra et al. Induction of buried oxide layer in substrate FD-SOI MOSFET for improving the digital and analog performance
US9012963B2 (en) Semiconductor device
US20120223361A1 (en) Low-power consumption tunneling field-effect transistor with finger-shaped gate structure
Juyal et al. TCAD simulation of Ge-GaAs hetrojunction dopingless tunnel field effect transistor
Panda et al. Ambipolarity suppression in SiGe/Si-TFET using hetero-dielectric BOX engineering
Patel et al. Performance enhancement of the tunnel field effect transistor using a SiGe source
US20240063256A1 (en) Semiconductor device and method for fabricating same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18915817

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18915817

Country of ref document: EP

Kind code of ref document: A1