WO2022051903A1 - 基于相位的分频器及相关锁相环、芯片、电子装置及时钟产生方法 - Google Patents

基于相位的分频器及相关锁相环、芯片、电子装置及时钟产生方法 Download PDF

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WO2022051903A1
WO2022051903A1 PCT/CN2020/114014 CN2020114014W WO2022051903A1 WO 2022051903 A1 WO2022051903 A1 WO 2022051903A1 CN 2020114014 W CN2020114014 W CN 2020114014W WO 2022051903 A1 WO2022051903 A1 WO 2022051903A1
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variable
clock
phase
frequency
clocks
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PCT/CN2020/114014
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English (en)
French (fr)
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张孟文
易律凡
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2020/114014 priority Critical patent/WO2022051903A1/zh
Publication of WO2022051903A1 publication Critical patent/WO2022051903A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth

Definitions

  • the present application relates to a phase-based frequency divider, and more particularly, to a phase-based frequency divider capable of simultaneously outputting integer and fractional multiple frequencies, a related phase-locked loop, a chip, an electronic device and a clock generation method.
  • some audio formats have a sampling rate of 48kHz and multiples of 48kHz.
  • a clock that is an integer multiple of 48kHz is also required.
  • the source of these clocks is usually provided by a phase-locked loop, but the reference clock of the phase-locked loop on the market is usually not a simple proportional relationship with 48KHz, such as the common 32.762KHz, 2MHz and so on. If a custom reference clock is used, the system cost will increase.
  • a common method is to use a fractional frequency division phase-locked loop to obtain the expected clock frequency, but the problem brought by the fractional frequency division phase-locked loop is that it will introduce many fractional spurs, thereby reducing the performance of the system. Therefore, how to overcome the above-mentioned problems is one of the key projects to be improved urgently in this field.
  • One of the objectives of the present application is to disclose a phase-based frequency divider capable of simultaneously outputting integer and fractional multiple frequencies, a related phase-locked loop, a chip, an electronic device and a clock generation method to solve the above problems.
  • An embodiment of the present application discloses a phase-locked loop for generating a first variable clock and a second variable clock according to a reference clock
  • the phase-locked loop includes: a phase error generator for generating a first variable clock according to a frequency division ratio , the reference clock and the second variable clock generate phase errors, wherein the ratio of the frequency of the second variable clock to the frequency of the reference clock is the frequency division ratio;
  • the phase error is filtered to generate a frequency control signal;
  • an n-stage ring oscillator is used to generate n variable clocks according to the frequency control signal, and the n variable clocks have the same frequency and different phases, wherein one of the n variable clocks is used as the first variable clock, wherein n is greater than 1; and a phase-based frequency divider for according to the n variable clocks and a preset offset
  • the second variable clock is generated; the ratio of the period of the second variable clock to the period of the first variable clock is (a+n)/n, where a is the prese
  • An embodiment of the present application discloses a phase-based frequency divider, which is used to generate a frequency-divided clock according to n variable clocks, and the phase-based frequency divider includes: a first multiplexer for receiving all The n variable clocks are outputted according to the first selected value, wherein the n variable clocks have the same frequency and different phases, and n is greater than 1; the second multiplexer uses to receive the n variable clocks and output the second selected variable clock according to the second selected value; the first flip-flop is used to output the first selected value, wherein the first flip-flop is used to output the first selected value according to the divided The rising edge of the frequency clock causes the first selected value to perform data switching according to the selected value after the modulo; an addition unit is used to perform an addition operation on the first selected value and the preset offset to generate a preset offset an accumulated value; a modulo unit for performing modulo operation on the preset offset accumulated value with n to generate the modulo post-selected value; a second flip-flop
  • An embodiment of the present application discloses a chip including the above-mentioned phase-locked loop or phase-based frequency divider.
  • An embodiment of the present application discloses an electronic device including the above-mentioned chip.
  • An embodiment of the present application discloses a clock generation method for generating a first variable clock and a second variable clock according to a reference clock, and the clock generation method includes: according to a frequency division ratio, the reference clock and all The second variable clock generates a phase error, wherein the ratio of the frequency of the second variable clock to the frequency of the reference clock is the frequency division ratio; filtering the phase error to generate a frequency control signal; generating n variable clocks according to the frequency control signal, the n variable clocks have the same frequency and different phases, and one of the n variable clocks is used as the first variable clock , wherein n is greater than 1; and the second variable clock is generated according to the n variable clocks and a preset offset, wherein the period of the second variable clock is the same as the period of the first variable clock
  • the ratio of is (a+n)/n, where a is the preset offset.
  • the present application realizes the characteristic of fractional frequency division on the premise that the whole phase-locked loop works on the premise of integer frequency division, so the influence of fractional spurs can be eliminated.
  • FIG. 1 is a circuit block diagram of an embodiment of a phase-locked loop of the present application.
  • FIG. 2 is a circuit block diagram of an embodiment of the phase-based frequency divider of the present application.
  • phase-based frequency divider of the present application is a timing diagram of a first operational embodiment of the phase-based frequency divider of the present application
  • phase-based frequency divider 4 is a timing diagram of a second operational embodiment of the phase-based frequency divider of the present application
  • FIG. 5 is a circuit block diagram of an embodiment of the phase-locked loop of the present application implemented by an analog circuit.
  • FIG. 6 is a circuit block diagram of an embodiment of the phase-locked loop of the present application implemented by a digital circuit.
  • first and second features are in direct contact with each other; and may also include Certain embodiments may have additional components formed between the first and second features described above, such that the first and second features may not be in direct contact.
  • present disclosure may reuse reference numerals and/or reference numerals in various embodiments. Such reuse is for brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.
  • spatially relative terms such as “below”, “below”, “below”, “above”, “above” and the like, may be used to facilitate the description of the drawings. relationship between one component or feature shown with respect to another component or feature.
  • These spatially relative terms are intended to encompass many different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be positioned in other orientations (eg, rotated 90 degrees or at other orientations) and these spatially relative descriptors should be interpreted accordingly.
  • the oscillator in the phase-locked loop usually uses a ring oscillator, and the ring oscillator can generate clocks with multiple phases. Therefore, this application designs a frequency divider based on multi-phase clocks to achieve fractional frequency division. However, the entire phase-locked loop still works in the mode of integer frequency division, so the influence of fractional spurs can be eliminated, and the integer clock and the fractional frequency division clock can be output at the same time for use, the details of which will be explained later.
  • FIG. 1 is a circuit block diagram of an embodiment of a phase-locked loop 100 of the present application.
  • the phase-locked loop 100 can generate the first variable clock CLK VF and the second variable clock CLK V according to the reference clock CLK R , the frequency division ratio N and the preset offset a, so that the frequency of the second variable clock CLK V is The ratio to the frequency of the reference clock CLK R is the frequency division ratio N, and the ratio of the frequency of the second variable clock CLK V to the frequency of the first variable clock CLK VF is determined by the preset offset a.
  • the reference clock CLK R can be provided by a crystal oscillator outside the chip where the phase-locked loop 100 is located, or by other circuits in the chip; the frequency division ratio N and the preset offset a are based on the lock It is determined by the application of the system in which the phase ring 100 is located, and is preset in the wafer. where a and N are integers.
  • the phase-locked loop 100 includes a phase error generator 102 , a filter 104 , an n-stage ring oscillator 106 and a phase-based frequency divider 108 .
  • the phase error generator 102 is used for generating the phase error ⁇ E according to the frequency division ratio N, the reference clock CLK R and the second variable clock CLK V .
  • the filter 104 is used for filtering the phase error ⁇ E to generate the frequency control signal SC.
  • the n-stage ring oscillator 106 is used for generating n variable clocks CLK V1 ⁇ CLK Vn according to the frequency control signal SC, the n variable clocks CLK V1 ⁇ CLK Vn have the same frequency and different phases, and the n variable clocks One of CLK V1 ⁇ CLK Vn is used as the first variable clock CLK VF , for example, the variable clock CLK V1 is used as the first variable clock CLK VF in FIG. 1 .
  • the phase-based frequency divider 108 is used for generating the second variable clock CLK V according to the n variable clocks CLK V1 ⁇ CLK Vn and the preset offset a.
  • the frequency of the second variable clock CLK V and The ratio of the frequency of the first variable clock CLK VF is determined by the preset offset a and the stage number n of the n-stage ring oscillator 106 , where n is an integer greater than 1.
  • phase error generator 102 the filter 104 and the n-stage ring oscillator 106
  • the phase error generator 102 , the filter 104 and the n-stage ring oscillator 106 106 can be implemented by means of an analog circuit, as shown in FIG. 5; in some embodiments, the phase error generator 102, the filter 104 and the n-stage ring oscillator 106 can be implemented by means of a digital circuit, as shown in FIG. 6 shown. It will be explained later.
  • the phase-based frequency divider 108 includes a first multiplexer 202 , a second multiplexer 204 , a first flip-flop 206 , a second flip-flop 208 , an OR gate 210 , an addition unit 212 and a modulo unit 214 .
  • the data input terminal D of the first flip-flop 206 is used to receive the modulo-selected value SM by the modulo unit 214, the data output terminal Q is used to output the first selected value S1; the data input terminal D of the second flip-flop 208 is used to After receiving the modulo selection value SM, the data output terminal Q is used to output the second selection value S2.
  • the first flip-flop 206 in FIG. 2 is only for illustration. In fact, since the number of bits of the selected value SM after the modulo is usually greater than 1 bit, multiple first flip-flops 206 are needed to temporarily store the received After the modulo is taken, the value SM is selected and output as the first selected value S1; similarly, the second flip-flop 208 in FIG. 2 is only for illustration. The plurality of second flip-flops 208 temporarily store the received modulo selection value SM and output it as the first selection value S2.
  • the first flip-flop 206 outputs the first selected value S1 according to the rising edge of the second variable clock CLKV and the modulo-selected value SM; the second flip-flop 208 outputs the first selected value S1 according to the falling edge of the second variable clock CLKV And after the modulo is taken, the value SM is selected to output the second selected value S2.
  • the addition unit 212 is used to perform an addition operation on the first selection value S1 and the preset offset a to generate a preset offset accumulation value SA, and the preset offset accumulation value SA is then passed through the modulo unit 214 to n pairs of the preset value.
  • the accumulated offset value SA is subjected to a modulo operation to generate a modulo post-selection value SM.
  • SM modulo post-selection value
  • the overflow of the first flip-flop 206 is substantially equivalent to the function of taking the modulo.
  • n is 2 to the mth power
  • m first flip-flops are used.
  • the device 206 is equivalent to combining the modulo unit 214 at the same time.
  • the addition unit 212 with fixed-point operation (m bits) can also be used, which can also achieve the function of taking the modulo, which is equivalent to combining the modulo unit 214 at the same time.
  • the first multiplexer 202 is used for outputting one of the n variable clocks CLK V1 to CLK Vn as the first selected variable clock CLK S1 according to the first selection value S1 ; the second multiplexer 204 is used for The second value S2 is selected to output one of the n variable clocks CLK V1 ⁇ CLK Vn as the second selected variable clock CLK S2 .
  • the OR gate 210 is used to perform an "OR" logic operation on the first selected variable clock CLK S1 and the second selected variable clock CLK S2 to generate the second variable clock CLK V .
  • the second variable clock CLK V is input to the first flip-flop 206 and the second flip-flop 208 again.
  • FIG. 3 is a timing diagram of the first operation embodiment of the phase-based frequency divider of the present application. In the embodiment of FIG.
  • the preset offset a is 1, and the schematic Only two of the n variable clocks CLK V1 to CLK Vn are drawn on the ground, that is, the variable clock CLK V1 and the variable clock CLK V2 . Since the data switching time of the first selection value S1 is determined by the rising edge of the second variable clock CLK V ; the data switching time of the second selection value S2 is determined by the falling edge of the second variable clock CLK V , so it can be seen that the first Both the first selection value S1 and the second selection value S2 are accumulated by 1 at the frequency of the second variable clock CLK V , but the switching time of the second selection value S2 lags behind the switching time of the first selection value S1.
  • the timing state of the first selection variable clock CLK S1 output by the first multiplexer 202 can be obtained according to the first selection value S1
  • the second selection output by the second multiplexer 204 can be obtained according to the second selection value S2
  • the timing state of the variable clock CLK S2 and then by performing an "OR" logic operation on the first selected variable clock CLK S1 and the second selected variable clock CLK S2 , the second variable clock CLK in Figure 3 can be obtained.
  • the preset offset a is greater than 0 (the preset offset a is 1 in the embodiment of FIG.
  • the clock period of the second variable clock CLK V is greater than that of the variable clock CLK V1 and the clock period of the variable clock CLK V2 . That is to say, the frequency of the second variable clock CLK V is lower than the clock period of the variable clock CLK V1 and the variable clock CLK V2 , and because the first variable clock CLK VF is n variable clocks CLK V1 ⁇ CLK Vn One of them, so the frequency of the second variable clock CLK V is lower than the clock period of the first variable clock CLK VF .
  • the difference between the clock period of the second variable clock CLK V and the clock period of the variable clock CLK V1 (or the variable clock CLK V2 ) is the phase difference between the variable clock CLK V1 and the variable clock CLK V2 , namely a*T/n (the preset offset a is 1 in the embodiment of FIG. 3 ), therefore, the ratio of the clock period of the second variable clock CLK V to the clock period of the first variable clock CLK VF is (T+a*T/n)/T, ie (a+n)/n, that is, the ratio of the frequency of the second variable clock CLK V to the frequency of the first variable clock CLK VF is n/( a+n).
  • the duty cycles of the n variable clocks CLK V1 to CLK Vn are all 50%, but when the preset offset a is greater than 0, the duty cycle of the second variable clock CLK V is not 50%, but In one clock cycle of the second variable clock CLK V , the time length of the high level is greater than the time length of the low level.
  • the time length of the low level in one clock cycle of the second variable clock CLK V is equal to the time length of the low level in the clock cycles of any one of the n variable clocks CLK V1 to CLK Vn
  • the time length of the high level in one clock cycle of the second variable clock CLK V is equal to the time length of the high level in the clock cycles of any one of the n variable clocks CLK V1 to CLK Vn plus a*T/ n.
  • n/(a+n) can be set to 128/122.8. Since 128/122.8 is approximately 25/24, so when designing , the stage number n of the n-stage ring oscillator 106 is designed to be 24, the frequency is designed to be 128MHz, and the preset offset a is set to -1, the frequency of the first variable clock CLK VF can be obtained as 122.8MHz and The frequency of the second variable clock CLK V is 128 MHz.
  • the reference frequency is 2MHz, so the frequency division ratio N is an integer of 64, and two frequencies of 128MHz and 122.8MHz can be generated at the same time. Since there is no need to use complex fractional frequency division to generate the frequency of 122.8MHz, the overall phase lock Ring 100 actually operates in integer division mode, thus eliminating the effects of fractional spurs.
  • the phases of the n variable clocks CLK V1 to CLK Vn of the n-stage ring oscillator 106 are ideally staggered by the phase difference of T/n.
  • the phases of the variable clocks CLK V1 ⁇ CLK Vn may not be perfectly staggered at equal distances, resulting in jitter of the second variable clock CLK V.
  • the n variable clocks CLK V1 ⁇ CLK Vn of the n-stage ring oscillator 106 are The closer the phase difference is equidistantly staggered, the smaller the jitter of the second variable clock CLK V is.
  • FIG. 4 is a timing diagram of the second operation embodiment of the phase-based frequency divider of the present application.
  • the preset offset a is -1
  • the schematic Only two of the n variable clocks CLK V1 to CLK Vn that is, the variable clock CLK V4 and the variable clock CLK V5 , are schematically drawn. It can be found that when the preset offset a is smaller than 0, the clock period of the second variable clock CLK V is smaller than the clock periods of the variable clock CLK V4 and the variable clock CLK V5 .
  • the frequency of the second variable clock CLK V is higher than the clock period of the variable clock CLK V4 and the variable clock CLK V5 , that is, the frequency of the second variable clock CLK V is higher than that of the first variable clock CLK VF clock cycle.
  • the difference between the clock period of the second variable clock CLK V and the clock period of the variable clock CLK V4 (or the variable clock CLK V5 ) is the phase difference between the variable clock CLK V4 and the variable clock CLK V5 , namely a*T/n, therefore, the ratio of the clock period of the second variable clock CLK V to the clock period of the first variable clock CLK VF is (T+a*T/n)/T, that is, (a+ n)/n, that is to say, the ratio of the frequency of the second variable clock CLK V to the frequency of the first variable clock CLK VF is n/(a+n), since the preset offset in the embodiment of FIG. 4
  • the quantity a is -1, so in practice the ratio of the frequency of the second variable clock CLK V to the frequency of the first variable clock CLK VF is n/(n-1).
  • the second variable clock CLK V the duty cycle is not 50%, but in one clock cycle of the second variable clock CLK V , the time length of the high level is greater than the time length of the low level.
  • the time length of the low level in one clock cycle of the second variable clock CLK V is equal to the time length of the low level in the clock cycles of any one of the n variable clocks CLK V1 to CLK Vn plus a*T/n, since the preset offset a is -1 in the embodiment of FIG.
  • the time length of the low level in one clock cycle of the second variable clock CLK V is longer than n possible times.
  • the time length of the low level in any one of the clock cycles of the variable clocks CLK V1 to CLK Vn is short by T/n.
  • the time length of the high level in one clock cycle of the second variable clock CLK V is equal to the time length of the high level in the clock cycle of any one of the n variable clocks CLK V1 to CLK Vn .
  • the frequency of the second variable clock CLK V is equal to the frequency of the n variable clocks CLK V1 ⁇ CLK Vn , that is, the frequency of the first variable clock CLK VF , and the The duty cycle of the two variable clocks CLK V is 50%.
  • FIG. 5 is a circuit block diagram of an embodiment of the phase-locked loop of the present application implemented by an analog circuit.
  • the phase error generator 102 , the filter 104 and the n-stage ring oscillator 106 in the phase-locked loop 500 are implemented by means of analog circuits.
  • the filter 104 may be a low-pass filter implemented in an analog circuit with a first order or more; the n-stage ring oscillator 106 may be a ring oscillator implemented in an analog circuit.
  • the phase error generator 102 includes a frequency dividing unit 502 for dividing the frequency of the second variable clock CLK V according to the frequency dividing ratio N to generate the frequency-divided second variable clock CLK VD , and the phase detector 504 is used for dividing the frequency according to the reference
  • the clock CLK R and the frequency-divided second variable clock CLK VD generate phase error information, and convert them into voltage signals to output the phase error ⁇ E . Since there are many ways to implement the phase error generator 102 , the filter 104 and the n-stage ring oscillator 106 in an analog manner, they will not be described in detail in this application.
  • FIG. 6 is a circuit block diagram of an embodiment of the phase-locked loop of the present application implemented by an analog circuit.
  • the phase error generator 102, the filter 104 and the n-stage ring oscillator 106 in the phase-locked loop 600 are realized by means of digital circuits.
  • the filter 104 may be a low-pass filter of a first order or more implemented by a digital circuit; the n-stage ring oscillator 106 may be a ring oscillator implemented by a digital circuit.
  • the phase error generator 102 includes a reference phase accumulator 602 , a variable phase accumulator 604 and a phase detector 606 .
  • the reference phase accumulator 602 is used for accumulating the frequency division ratio N according to the reference clock CLK R to generate the reference phase ⁇ R , and the reference phase ⁇ R represents the phase information of the reference clock CLK R .
  • the variable phase accumulator 604 is used to accumulate 1 according to the variable clock CLK V to generate the variable phase ⁇ V , and the variable phase ⁇ V represents the phase information of the variable clock CLK V.
  • the phase detector 606 is used for generating the phase error ⁇ E according to the reference phase ⁇ R and the variable phase ⁇ V . Since there are many ways to digitally implement the phase error generator 102 , the filter 104 and the n-stage ring oscillator 106 , they will not be described in detail in this application.
  • the present application also provides a chip, which includes a phase-based frequency divider 108 or a phase-locked loop 100/500/600, and the chip can be installed in an electronic device, such as a smart phone. , personal digital assistants, handheld computer systems, or any electronic device such as a tablet computer.

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Abstract

本申请公开了一种基于相位的分频器及相关锁相环(100)、芯片、电子装置及时钟产生方法。锁相环包括：相位误差产生器(102)，用以依据分频比(N)、参考时钟(CLKR)以及第二可变时钟(CLKV)产生相位误差(φE)，其中第二可变时钟的频率和参考时钟的频率的比例为分频比；滤波器(104)，用以对相位误差进行滤波处理以产生频率控制信号(SC)；n级环形振荡器(106)，用以依据频率控制信号产生n个可变时钟(CLKV1～CLKVn)，n个可变时钟彼此频率皆相同且相位皆不同，其中n个可变时钟的其中之一被作为第一可变时钟(CLKVF)，其中n大于1；以及基于相位的分频器(108)，用以依据n个可变时钟以及预设偏移量(a)产生第二可变时钟；第二可变时钟的周期与第一可变时钟的周期的比例为(a+n)/n，其中a为预设偏移量。

Description

基于相位的分频器及相关锁相环、芯片、电子装置及时钟产生方法 技术领域
本申请涉及一种基于相位的分频器，尤其涉及一种能够同时输出整数与小数倍频率的基于相位的分频器以及相关锁相环、芯片、电子装置及时钟产生方法。
背景技术
在音频应用中，有些音频格式的采样率为48kHz及48kHz整数倍。此外，音频前端若采用过采样技术，为了方便数字滤波器的设计，也需要一个48kHz整数倍的时钟。这些时钟的源头通常由一个锁相环提供，但是市面上锁相环的参考时钟通常与48KHz不为简单的比例关系，例如常见的32.762KHz、2MHz等等。若采用定制的参考时钟，系统成本将会升高。一种常用的方法是，采用小数分频锁相环，以获得预期的时钟频率，但是小数分频锁相环带来的问题是会引入诸多的小数杂散，从而降低系统的性能。因此，如何克服上述问题，乃是本领域亟待改进的重点项目之一。
发明内容
本申请的目的之一在于公开一种能够同时输出整数与小数倍频率的基于相位的分频器以及相关锁相环、芯片、电子装置及时钟产生方法，来解决上述问题。
本申请的一实施例公开了一种锁相环，用以依据参考时钟产生第一可变时钟与第二可变时钟，所述锁相环包括：相位误差产生器，用以依据分频比、所述参考时钟以及所述第二可变时钟产生相位误差， 其中所述第二可变时钟的频率和所述参考时钟的频率的比例为所述分频比；滤波器，用以对所述相位误差进行滤波处理以产生频率控制信号；n级环形振荡器，用以依据所述频率控制信号产生n个可变时钟，所述n个可变时钟彼此频率皆相同且相位皆不同，其中所述n个可变时钟的其中之一被作为所述第一可变时钟，其中n大于1；以及基于相位的分频器，用以依据所述n个可变时钟以及预设偏移量产生所述第二可变时钟；所述第二可变时钟的周期与所述第一可变时钟的周期的比例为(a+n)/n，其中a为所述预设偏移量。
本申请的一实施例公开了一种基于相位的分频器，用来依据n个可变时钟产生分频时钟，所述基于相位的分频器包括：第一复用器，用来接收所述n个可变时钟，并依据第一选值输出第一选取可变时钟，其中所述n个可变时钟彼此频率皆相同且相位皆不同，其中n大于1；第二复用器，用来接收所述n个可变时钟，并依据第二选值输出第二选取可变时钟；第一触发器，用来输出所述第一选值，其中所述第一触发器依据所述分频时钟的上升沿使所述第一选值依据取模后选值进行数据切换；加法单元，用来对所述第一选值以及预设偏移量进行加法运算以产生预设偏移量累加值；取模单元，以n对所述预设偏移量累加值进行取模运算以产生所述取模后选值；第二触发器，用来输出所述第二选值，其中所述第二触发器依据所述分频时钟的下降沿使所述第二选值依据取模后选值进行数据切换；以及或门，用来依据所述第一选取可变时钟和所述第二选取可变时钟输出所述分频时钟；所述分频时钟的周期与所述可变时钟的周期的比例为(a+n)/n，其中a为所述预设偏移量。
本申请的一实施例公开了一种芯片，包括上述的锁相环或基于相位的分频器。
本申请的一实施例公开了一种电子装置，包括上述的芯片。
本申请的一实施例公开了一种时钟产生方法，用以依据参考时钟产生第一可变时钟与第二可变时钟，所述时钟产生方法包括：依据分频比、所述参考时钟以及所述第二可变时钟产生相位误差，其中所述 第二可变时钟的频率和所述参考时钟的频率的比例为所述分频比；对所述相位误差进行滤波处理以产生频率控制信号；依据所述频率控制信号产生n个可变时钟，所述n个可变时钟彼此频率皆相同且相位皆不同，其中所述n个可变时钟的其中之一被作为所述第一可变时钟，其中n大于1；以及依据所述n个可变时钟以及预设偏移量产生所述第二可变时钟，其中所述第二可变时钟的周期与所述第一可变时钟的周期的比例为(a+n)/n，其中a为所述预设偏移量。
本申请在整个锁相环工作在整数分频的前提下实现小数分频的特性，因此可消除了小数杂散的影响。
附图说明
图1为本申请的锁相环的实施例的电路模块图。
图2为本申请的基于相位的分频器的实施例的电路模块图。
图3为本申请的基于相位的分频器的第一操作实施例的时序图
图4为本申请的基于相位的分频器的第二操作实施例的时序图
图5为本申请的锁相环以模拟电路实现的实施例的电路模块图。
图6为本申请的锁相环以数字电路实现的实施例的电路模块图。
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见，这些叙述仅为例示，其本意并非用于限制本揭示内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外， 本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
再者，在此处使用空间上相对的词汇，譬如「之下」、「下方」、「低于」、「之上」、「上方」及与其相似者，可能是为了方便说明图中所绘示的一组件或特征相对于另一或多个组件或特征之间的关系。这些空间上相对的词汇其本意除了图中所绘示的方位之外，还涵盖了装置在使用或操作中所处的多种不同方位。可能将所述设备放置于其他方位(如，旋转90度或处于其他方位)，而这些空间上相对的描述词汇就应该做相应的解释。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
锁相环中的振荡器通常会采用环形振荡器，而环形振荡器可以产生多个相位的时钟，因此本申请在此基础上设计了基于多相位时钟的分频器，从而实现小数分频的特性，但是整个锁相环仍然工作在整数分频的模式，因此可消除了小数杂散的影响，还可以同时输出整数时钟和小数分频时钟供使用，其细节说明于后。
请参考图1，图1为本申请的锁相环100的实施例的电路模块图。锁相环100能够依据参考时钟CLK R、分频比N和预设偏移量a来产生第一可变时钟CLK VF和第二可变时钟CLK V，使第二可变时钟CLK V的频率和参考时钟CLK R的频率的比例为分频比N，且第二可变时钟CLK V的频率和第一可变时钟CLK VF的频率的比例由预设偏移量a决定。其中参考时钟CLK R可以是由锁相环100所在的晶片之外的晶体振荡器提供，或是由所述晶片中的其他电路提供；分频比N和预设偏移量a则是依据锁相环100所在的系统的应用来决定，并预先设置于所述晶片中。其中a、N为整数。
锁相环100包括相位误差产生器102、滤波器104、n级环形振荡器106及基于相位的分频器108。相位误差产生器102用以依据分频比N、参考时钟CLK R以及第二可变时钟CLK V产生相位误差φ E。滤波器104用以对相位误差φ E进行滤波处理以产生频率控制信号SC。n级环形振荡器106用以依据频率控制信号SC产生n个可变时钟CLK V1～CLK Vn，n个可变时钟CLK V1～CLK Vn彼此频率皆相同且相位皆不同，而n个可变时钟CLK V1～CLK Vn的其中之一被作为第一可变时钟CLK VF，例如图1中使用可变时钟CLK V1作为第一可变时钟CLK VF。基于相位的分频器108用以依据n个可变时钟CLK V1～CLK Vn以及预设偏移量a产生第二可变时钟CLK V，具体来说，第二可变时钟CLK V的频率和第一可变时钟CLK VF的频率的比例由预设偏移量a以及n级环形振荡器106的级数n决定，其中n为大于1的整数。
本申请并不对相位误差产生器102、滤波器104及n级环形振荡器106的实施方式作进一步的限定，在某些实施例中，相位误差产生器102、滤波器104及n级环形振荡器106可以由模拟电路的方式来实现，如图5所示；在某些实施例中，相位误差产生器102、滤波器104及n级环形振荡器106可以由数字电路的方式来实现，如图6所示。将说明于后。
请参考图2，图2为本申请的基于相位的分频器的实施例的电路模块图。基于相位的分频器108包括第一复用器202、第二复用器204、 第一触发器206、第二触发器208、或门210、加法单元212及取模单元214。其中第一触发器206的数据输入端D用来接收取模单元214取模后选值SM，数据输出端Q用来输出第一选值S1；第二触发器208的数据输入端D用来接收取模后选值SM，数据输出端Q用来输出第二选值S2。应注意的是，图2中的第一触发器206仅为示意，实际上由于取模后选值SM的比特数通常大于1比特，因此需要多个第一触发器206以暂存接收到的取模后选值SM并输出为第一选值S1；相似地，图2中的第二触发器208仅为示意，实际上由于取模后选值SM的比特数通常大于1比特，因此需要多个第二触发器208以暂存接收到的取模后选值SM并输出为第一选值S2。
具体而言，第一触发器206依据第二可变时钟CLK V的上升沿以及取模后选值SM来输出第一选值S1；第二触发器208依据第二可变时钟CLKV的下降沿以及取模后选值SM来输出使第二选值S2。
加法单元212用来对第一选值S1以及预设偏移量a进行加法运算以产生预设偏移量累加值SA，预设偏移量累加值SA再经过取模单元214以n对预设偏移量累加值SA进行取模运算以产生取模后选值SM。例如当n级环形振荡器106为16级环形振荡器时，n为16，则当预设偏移量累加值SA为18时，经过取模单元214后会得到取模后选值SM为2。应注意的是，图2中加法单元212和取模单元214的作法仅为示意，实际上不限于此。例如在某些实施例中，n为2的整数次幂的情况，第一触发器206的溢出即实质等同于取模的作用，例如n为2的m次方时，使用m个第一触发器206即相当于同时结合了取模单元214。又或是可以使用定点运算(m比特)的加法单元212，同樣可以達到取模的作用，即相当于同时结合了取模单元214。
第一复用器202用来依据第一选值S1来将n个可变时钟CLK V1～CLK Vn的其中之一输出为第一选取可变时钟CLK S1；第二复用器204用来依据第二选值S2来将n个可变时钟CLK V1～CLK Vn的其中之一输出为第二选取可变时钟CLK S2。或门210用来对第一选取可变时钟CLK S1和第二选取可变时钟CLK S2进行“或”的逻辑运算以产生第 二可变时钟CLK V。且第二可变时钟CLK V又输入至第一触发器206和第二触发器208。
假设n级环形振荡器106的时钟周期为T，即n个可变时钟CLK V1～CLK Vn的时钟周期皆为T，则n个可变时钟CLK V1～CLK Vn的相位以T/n的相位差等距错开，换句话说，n个可变时钟CLK V1～CLK Vn的相邻相位之间的时钟时间差为T/n。请同时参考图2和图3，图3为本申请的基于相位的分频器的第一操作实施例的时序图，图3的实施例中，预设偏移量a为1，且示意性地仅绘出了n个可变时钟CLK V1～CLK Vn的其中之二，即可变时钟CLK V1和可变时钟CLK V2。由于第一选值S1的数据切换时间是由第二可变时钟CLK V上升沿决定；第二选值S2的数据切换时间是由第二可变时钟CLK V下降沿决定，因此可以看到第一选值S1和第二选值S2都会以第二可变时钟CLK V的频率累加1，但第二选值S2的切换时间落后第一选值S1的切换时间。
因此可以依据第一选值S1得知第一复用器202输出的第一选取可变时钟CLK S1的时序状态，以及依据第二选值S2来得到第二复用器204输出的第二选取可变时钟CLK S2的时序状态，再通过对第一选取可变时钟CLK S1和第二选取可变时钟CLK S2进行“或”的逻辑运算，便可得到图3中的第二可变时钟CLK V。图3的实施例中，预设偏移量a大于0(图3的实施例中预设偏移量a为1)，可以发现第二可变时钟CLK V的时钟周期大于可变时钟CLK V1和可变时钟CLK V2的时钟周期。也就是说，第二可变时钟CLK V的频率低于可变时钟CLK V1和可变时钟CLK V2的时钟周期，又因为第一可变时钟CLK VF为n个可变时钟CLK V1～CLK Vn的其中之一，因此第二可变时钟CLK V的频率低于第一可变时钟CLK VF的时钟周期。
如图3所示，第二可变时钟CLK V的时钟周期和可变时钟CLK V1(或可变时钟CLK V2)的时钟周期的差距为可变时钟CLK V1和可变时钟CLK V2的相位差，即a*T/n(图3的实施例中预设偏移量a为1)，因此，第二可变时钟CLK V的时钟周期和第一可变时钟CLK VF的时钟 周期的比例为(T+a*T/n)/T，即(a+n)/n，也就是说，第二可变时钟CLK V的频率和第一可变时钟CLK VF的频率的比例为n/(a+n)。
此外，由图3还可以看到，若要能够依照图2的逻辑来产生图3及图4的效果，由于n个可变时钟CLK V1～CLK Vn的上升沿及下降沿都会被使用到，因此，n个可变时钟CLK V1～CLK Vn的占空比需为50％，否则会造成第二可变时钟CLK V的抖动(jitter)，换句话说，n个可变时钟CLK V1～CLK Vn的占空比越接近50％，第二可变时钟CLK V的抖动越小。若n个可变时钟CLK V1～CLK Vn的占空比皆为50％，但当预设偏移量a大于0时，第二可变时钟CLK V的占空比不为50％，而是在第二可变时钟CLK V的一个时钟周期中，高电平的时间长度大于低电平的时间长度。具体来说，第二可变时钟CLK V的一个时钟周期中的低电平的时间长度等于n个可变时钟CLK V1～CLK Vn中任一个的时钟周期中的低电平的时间长度，而第二可变时钟CLK V的一个时钟周期中的高电平的时间长度等于n个可变时钟CLK V1～CLK Vn中任一个的时钟周期中的高电平的时间长度加上a*T/n。
举例来说，若在音频系统中同时需要128MHz和122.8MHz两个分频输出，那么可以将n/(a+n)设为128/122.8，由于128/122.8近似25/24，因此在设计时，将n级环形振荡器106的级数n设计为24，频率设计为128MHz，以及将预设偏移量a设为-1，则可以得到第一可变时钟CLK VF的频率为122.8MHz以及第二可变时钟CLK V的频率为128MHz。举例来说，参考频率为2MHz，因此分频比N为整数64即可同时产生128MHz和122.8MHz两个频率，由于不需特别为了产生122.8MHz的频率而使用复杂的小数分频，整体锁相环100实际上是工作在整数分频的模式，因此可消除了小数杂散的影响。
应注意的是，n级环形振荡器106的n个可变时钟CLK V1～CLK Vn的相位以T/n的相位差等距错开为理想状况，实际上n级环形振荡器106的n个可变时钟CLK V1～CLK Vn的相位可能并非完美的等距错开，造成第二可变时钟CLK V的抖动，换句话说，n级环形振荡器106的n个可变时钟CLK V1～CLK Vn之间的相位差越接近等距错开，第二可 变时钟CLK V的抖动越小。
请同时参考图2和图4，图4为本申请的基于相位的分频器的第二操作实施例的时序图，图4的实施例中，预设偏移量a为-1，且示意性地仅绘出了n个可变时钟CLK V1～CLK Vn的其中之二，即可变时钟CLK V4和可变时钟CLK V5。可以发现在预设偏移量a小于0的情况下，第二可变时钟CLK V的时钟周期小于可变时钟CLK V4和可变时钟CLK V5的时钟周期。也就是说，第二可变时钟CLK V的频率高于可变时钟CLK V4和可变时钟CLK V5的时钟周期，即第二可变时钟CLK V的频率高于第一可变时钟CLK VF的时钟周期。
如图4所示，第二可变时钟CLK V的时钟周期和可变时钟CLK V4(或可变时钟CLK V5)的时钟周期的差距为可变时钟CLK V4和可变时钟CLK V5的相位差，即a*T/n，因此，第二可变时钟CLK V的时钟周期和第一可变时钟CLK VF的时钟周期的比例为(T+a*T/n)/T，即(a+n)/n，也就是说，第二可变时钟CLK V的频率和第一可变时钟CLK VF的频率的比例为n/(a+n)，由于图4的实施例中预设偏移量a为-1，因此实际上第二可变时钟CLK V的频率和第一可变时钟CLK VF的频率的比例为n/(n-1)。
此外，由图4还可以看到，若n个可变时钟CLK V1～CLK Vn的占空比皆为50％，但当预设偏移量a小于0时，第二可变时钟CLK V的占空比不为50％，而是在第二可变时钟CLK V的一个时钟周期中，高电平的时间长度大于低电平的时间长度。具体来说，第二可变时钟CLK V的一个时钟周期中的低电平的时间长度等于n个可变时钟CLK V1～CLK Vn中任一个的时钟周期中的低电平的时间长度加上a*T/n，由于图4的实施例中预设偏移量a为-1，因此,实际上第二可变时钟CLK V的一个时钟周期中的低电平的时间长度较n个可变时钟CLK V1～CLK Vn中任一个的时钟周期中的低电平的时间长度短T/n。而第二可变时钟CLK V的一个时钟周期中的高电平的时间长度等于n个可变时钟CLK V1～CLK Vn中任一个的时钟周期中的高电平的时间长度。
因此，当预设偏移量a等于0时，第二可变时钟CLK V的频率等 于n个可变时钟CLK V1～CLK Vn的频率，即等于第一可变时钟CLK VF的频率，且第二可变时钟CLK V的占空比为50％。
如前所述，本申请的基于相位的分频器108可搭配应用于模拟锁相环和数字锁相环中。图5为本申请的锁相环以模拟电路实现的实施例的电路模块图。锁相环500中的相位误差产生器102、滤波器104及n级环形振荡器106由模拟电路的方式来实现。例如滤波器104可以为一阶以上以模拟电路实现的低通滤波器；n级环形振荡器106可以为以模拟电路实现的环形振荡器。相位误差产生器102包括分频单元502，用来依据分频比N对第二可变时钟CLK V进行分频以产生分频后第二可变时钟CLK VD，鉴相器504用来依据参考时钟CLK R以及分频后第二可变时钟CLK VD产生相位误差信息，并转换成电压信号输出相位误差φ E。由于以模拟方式实现相位误差产生器102、滤波器104及n级环形振荡器106的方式很多，本申请中便不一一赘述。
图6为本申请的锁相环以模拟电路实现的实施例的电路模块图。锁相环600中的相位误差产生器102、滤波器104及n级环形振荡器106由数字电路的方式来实现。例如滤波器104可以为一阶以上以数字电路实现的低通滤波器；n级环形振荡器106可以为以数字电路实现的环形振荡器。相位误差产生器102包括参考相位累加器602、可变相位累加器604以及鉴相器606。参考相位累加器602用来依据参考时钟CLK R累加分频比N以产生参考相位φ R，参考相位φ R代表参考时钟CLK R的相位信息。可变相位累加器604用来依据可变时钟CLK V累加1以产生可变相位φ V，可变相位φ V代表可变时钟CLK V的相位信息。鉴相器606用以依据参考相位φ R以及可变相位φ V产生相位误差φ E。由于以数字方式实现相位误差产生器102、滤波器104及n级环形振荡器106的方式很多，本申请中便不一一赘述。
本申请还提供了一种芯片，其包括基于相位的分频器108或锁相环100/500/600，且所述芯片可以设置于电子装置中，例如所述电子装置可为例如智能型手机、个人数字助理、手持式计算机系统或平板计算机等任何电子装置。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本揭示内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本揭示内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本揭示内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本揭示内容之精神与范围。

Claims (19)

  1. 一种锁相环，其特征在于，用以依据参考时钟产生第一可变时钟与第二可变时钟，所述锁相环包括：
    相位误差产生器，用以依据分频比、所述参考时钟以及所述第二可变时钟产生相位误差，其中所述第二可变时钟的频率和所述参考时钟的频率的比例为所述分频比；
    滤波器，用以对所述相位误差进行滤波处理以产生频率控制信号；
    n级环形振荡器，用以依据所述频率控制信号产生n个可变时钟，所述n个可变时钟彼此频率皆相同且相位皆不同，其中所述n个可变时钟的其中之一被作为所述第一可变时钟，其中n大于1；以及
    基于相位的分频器，用以依据所述n个可变时钟以及预设偏移量产生所述第二可变时钟；
    所述第二可变时钟的周期与所述第一可变时钟的周期的比例为(a+n)/n，其中a为所述预设偏移量。
  2. 如权利要求1所述的锁相环，其特征在于，所述基于相位的分频器包括：
    第一触发器，用来输出第一选值，其中所述第一触发器依据所述第二可变时钟的上升沿以及取模后选值来产生所述第一选值；
    加法单元，用来对所述第一选值以及所述预设偏移量进行加法运算以产生预设偏移量累加值；
    取模单元，以n对所述预设偏移量累加值进行取模运算以产生所述取模后选值；
    第二触发器，用来输出第二选值，其中所述第二触发器依据所述第二可变时钟的下降沿以及取模后选值来产生所述第二选值；
    第一复用器，用来依据所述第一选值将所述n个可变时钟的其中之一输出为第一选取可变时钟；
    第二复用器，用来依据所述第二选值将所述n个可变时钟的其中之一输出为第二选取可变时钟；以及
    或门，用来依据所述第一选取可变时钟和所述第二选取可变时钟进行或处理以输出所述第二可变时钟。
  3. 如权利要求1所述的锁相环，其特征在于，所述相位误差产生器包括：
    分频单元，用来依据所述分频比对所述第二可变时钟进行分频以产生分频后第二可变时钟；以及
    鉴相器，用以依据所述参考时钟以及所述分频后第二可变时钟产生所述相位误差。
  4. 如权利要求1所述的锁相环，其特征在于，所述相位误差产生器包括：
    参考相位累加器，用来依据所述参考时钟累加所述分频比以产生参考相位，所述参考相位代表所述参考时钟的相位信息；
    可变相位累加器，用来依据所述第二可变时钟累加1以产生可变相位，所述可变相位代表所述第二可变时钟的相位信息；以及
    鉴相器，用以依据所述参考相位以及所述可变相位产生所述相位误差。
  5. 如权利要求1所述的锁相环，其特征在于，所述n个可变时钟的时钟周期为T，且所述n个可变时钟的相位以T/n的相位差等距错开。
  6. 如权利要求5所述的锁相环，其特征在于，当所述预设偏移量大于0时，所述第二可变时钟的频率高于所述第一可变时钟的频率；当所述预设偏移量小于0时，所述第二可变时钟的频率低于所述第一可变时钟的频率。
  7. 如权利要求5所述的锁相环，其特征在于，当所述n个可变时钟的占空比皆为50％时，所述第二可变时钟的占空比不为50％。
  8. 如权利要求5所述的锁相环，其特征在于，当所述n个可变时钟的占空比皆为50％时，所述第二可变时钟的时钟周期中，高电平和低电平的时间长度差为a*(T/n)。
  9. 如权利要求5所述的锁相环，其特征在于，当所述n个可变时钟的占空比皆为50％且所述预设偏移量大于0时，所述第二可变时 钟的时钟周期中的低电平的时间长度等于所述n个可变时钟中任一个的时钟周期中的低电平的时间长度；当所述n个可变时钟的占空比皆为50％且所述预设偏移量小于0时，所述第二可变时钟的时钟周期中的高电平的时间长度等于所述n个可变时钟中任一个的时钟周期中的高电平的时间长度。
  10. 一种基于相位的分频器，其特征在于，用来依据n个可变时钟产生分频时钟，所述基于相位的分频器包括：
    第一复用器，用来接收所述n个可变时钟，并依据第一选值输出第一选取可变时钟，其中所述n个可变时钟彼此频率皆相同且相位皆不同，其中n大于1；
    第二复用器，用来接收所述n个可变时钟，并依据第二选值输出第二选取可变时钟；
    第一触发器，用来输出所述第一选值，其中所述第一触发器依据所述分频时钟的上升沿使所述第一选值依据取模后选值进行数据切换；
    加法单元，用来对所述第一选值以及预设偏移量进行加法运算以产生预设偏移量累加值；
    取模单元，以n对所述预设偏移量累加值进行取模运算以产生所述取模后选值；
    第二触发器，用来输出所述第二选值，其中所述第二触发器依据所述分频时钟的下降沿使所述第二选值依据取模后选值进行数据切换；以及
    或门，用来依据所述第一选取可变时钟和所述第二选取可变时钟输出所述分频时钟；
    所述分频时钟的周期与所述可变时钟的周期的比例为(a+n)/n，其中a为所述预设偏移量。
  11. 如权利要求10所述的基于相位的分频器，其特征在于，所述n个可变时钟的时钟周期为T，且所述n个可变时钟的相位以T/n的相位差等距错开。
  12. 一种芯片，其特征在于，包括：
    如权利要求1至9中任一项所述的锁相环或权利要求10至11中任一项所述的基于相位的分频器。
  13. 一种电子装置，其特征在于，包括：
    如权利要求12所述的芯片。
  14. 一种时钟产生方法，其特征在于，用以依据参考时钟产生第一可变时钟与第二可变时钟，所述时钟产生方法包括：
    依据分频比、所述参考时钟以及所述第二可变时钟产生相位误差，其中所述第二可变时钟的频率和所述参考时钟的频率的比例为所述分频比；
    对所述相位误差进行滤波处理以产生频率控制信号；
    依据所述频率控制信号产生n个可变时钟，所述n个可变时钟彼此频率皆相同且相位皆不同，其中所述n个可变时钟的其中之一被作为所述第一可变时钟，其中n大于1；以及
    依据所述n个可变时钟以及预设偏移量产生所述第二可变时钟，其中所述第二可变时钟的周期与所述第一可变时钟的周期的比例为(a+n)/n，其中a为所述预设偏移量。
  15. 如权利要求14所述的时钟产生方法，其特征在于，所述n个可变时钟的时钟周期为T，且所述n个可变时钟的相位以T/n的相位差等距错开。
  16. 如权利要求15所述的时钟产生方法，其特征在于，当所述预设偏移量大于0时，所述第二可变时钟的频率高于所述第一可变时钟的频率；当所述预设偏移量小于0时，所述第二可变时钟的频率低于所述第一可变时钟的频率。
  17. 如权利要求15所述的时钟产生方法，其特征在于，当所述n个可变时钟的占空比皆为50％且所述预设偏移量不等于0时，所述第二可变时钟的占空比不为50％。
  18. 如权利要求15所述的时钟产生方法，其特征在于，当所述n个 可变时钟的占空比皆为50％且所述预设偏移量不等于0时，所述第二可变时钟的时钟周期中，高电平和低电平的时间长度差为a*(T/n)。
  19. 如权利要求15所述的时钟产生方法，其特征在于，当所述n个可变时钟的占空比皆为50％且所述预设偏移量大于0时，所述第二可变时钟的时钟周期中的低电平的时间长度等于所述n个可变时钟中任一个的时钟周期中的低电平的时间长度；当所述n个可变时钟的占空比皆为50％且所述预设偏移量小于0时，所述第二可变时钟的时钟周期中的高电平的时间长度等于所述n个可变时钟中任一个的时钟周期中的高电平的时间长度。
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CN101814914A (zh) * 2009-12-31 2010-08-25 海能达通信股份有限公司 一种优化小数杂散的方法及系统
CN102843134A (zh) * 2011-06-20 2012-12-26 英特尔移动通信有限责任公司 具有自动时钟对准的数字pll
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