WO2022048044A1 - Oled 面板的制作方法、 oled 面板 - Google Patents

Oled 面板的制作方法、 oled 面板 Download PDF

Info

Publication number
WO2022048044A1
WO2022048044A1 PCT/CN2020/131386 CN2020131386W WO2022048044A1 WO 2022048044 A1 WO2022048044 A1 WO 2022048044A1 CN 2020131386 W CN2020131386 W CN 2020131386W WO 2022048044 A1 WO2022048044 A1 WO 2022048044A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
oled panel
insulating layer
conductor
thickness
Prior art date
Application number
PCT/CN2020/131386
Other languages
English (en)
French (fr)
Inventor
周星宇
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/973,012 priority Critical patent/US12022686B2/en
Publication of WO2022048044A1 publication Critical patent/WO2022048044A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/102—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising tin oxides, e.g. fluorine-doped SnO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO

Definitions

  • the invention relates to the field of display, in particular to a manufacturing method of an OLED panel and an OLED panel.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal display
  • FIG. 1 is a structural diagram of a conventional OLED panel.
  • the panel includes a substrate 101, a light shielding layer 102, a first conductor layer 103, a buffer layer 104, an active layer 105, a second conductor layer 106, a gate insulating layer 107, a gate 108, a second insulating layer Layer 109 , source electrode 110 , drain electrode 111 , passivation layer 112 , planarization layer 113 , pixel electrode 114 and pixel definition layer 115 .
  • the first semiconductor layer 103, the buffer layer 104 and the second semiconductor layer 106 are used as transparent capacitor structures in bottom-emission OLEDs. Since the transparent capacitor structures do not affect the capacitor area, the aperture ratio increases, but the storage capacity of the capacitors increases. Ability is limited.
  • Embodiments of the present invention provide a method for fabricating an OLED panel.
  • the existing OLED panels have the problems of low aperture ratio and poor capacitance storage capacity.
  • the first conductor layer is overlapped with the light-shielding layer, the pixel electrode is connected with the source electrode, the flat layer and the passivation layer in the capacitor area are removed, the aperture ratio of the OLED panel is improved, the storage capacity of the capacitor is greatly improved, and the degree of freedom of design is improved. Higher, can be applied to larger size OLED panels, improving capacitance retention.
  • embodiments of the present invention provide a method for fabricating an OLED panel and an OLED panel, so as to solve the problems of low aperture ratio and low capacitance storage capacity of the existing OLED panel.
  • a first aspect of the present invention provides a method for manufacturing an OLED panel, comprising the following steps:
  • a transparent metal oxide is coated on the substrate and the light-shielding layer, and the transparent metal oxide is patterned to form a first conductor layer, and one end of the first conductor layer is overlapped with the light-shielding layer ;
  • a buffer layer, a semiconductor layer, a first insulating layer and a first metal layer are sequentially deposited on the substrate, and the semiconductor layer, the first insulating layer and the first metal layer are patterned to form a first a semiconductor layer, a second semiconductor layer, a gate insulating layer and a gate, the first semiconductor layer and the second semiconductor layer are spaced apart;
  • the first semiconductor layer and the second semiconductor layer are subjected to plasma treatment to obtain an active layer and a second conductor spaced from the active layer Floor;
  • a second insulating layer covering the buffer layer, the active layer, the second conductor layer, the gate insulating layer and the gate, and patterning the second insulating layer and the buffer layer to form exposed a first via hole in the source layer, a second via hole exposing the active layer, and a third via hole exposing the light shielding layer;
  • a second metal layer is formed on the second insulating layer, and the second metal layer is patterned to form a source electrode and a drain electrode, and the drain electrode is connected to the active layer through the first via hole connection, the source electrode is connected to the active layer through the second via hole, and the source electrode is connected to the light shielding layer through the third via hole;
  • a transparent metal oxide is coated on the flat layer and the opening, and the transparent metal oxide is patterned to form a pixel electrode, and the pixel electrode is connected to the source electrode through the fourth via hole ;
  • a pixel definition layer covering the planarization layer and the pixel electrode is formed, and the pixel definition layer is patterned to expose the pixel electrode over the opening.
  • first conductor layer, the buffer layer, the second conductor layer, the second insulating layer and the pixel electrode form a three-layer sandwich transparent capacitor structure.
  • the material of the light-shielding layer is one or more of Mo, Al, Cu, and Ti;
  • the thickness of the light-shielding layer is 2000-10000 ⁇ ;
  • the thickness of the first conductor layer is 200-2000 ⁇ .
  • the fourth via hole is prepared by yellow light.
  • the thickness of the semiconductor layer is 100-1000 ⁇ ;
  • the material of the semiconductor layer is one of IGZO, IZTO, and IGZTO;
  • the thickness of the gate insulating layer is 1000-3000 ⁇ ;
  • the material of the second metal layer is one or more of Mo, Al, Cu, and Ti, and the thickness is 2000-8000 ⁇ .
  • the material of the second insulating layer is one or a combination of SiOx and SiNx;
  • the thickness of the second insulating layer is 2000-10000 ⁇ .
  • the material of the passivation layer is one or a combination of SiOx and SiNx;
  • the thickness of the passivation layer is 1000-5000 ⁇ ;
  • the material of the pixel electrode is ITO or IZO;
  • the thickness of the pixel electrode is 200-2000 ⁇ .
  • the active layer is located above the light shielding layer
  • the second conductor layer is located above the first conductor layer
  • the opening is located above the second conductor layer.
  • the width of the active layer is smaller than the width of the light shielding layer
  • the width of the gate insulating layer is smaller than the width of the active layer
  • the width of the gate is smaller than the width of the gate insulating layer.
  • the thickness of the buffer layer is 1000-5000 ⁇ ;
  • the material of the buffer layer is one or a combination of two of SiOx and SiNx.
  • a second aspect of the present invention provides an OLED panel, comprising:
  • a light-shielding layer prepared on the surface of the substrate
  • the first conductor layer is prepared on the surface of the substrate, and one end of the first conductor layer is overlapped with the light shielding layer;
  • a buffer layer covering the light shielding layer, the first conductor layer and the substrate
  • the second conductor layer is prepared on the surface of the buffer layer, and the second conductor layer is spaced from the active layer;
  • a gate insulating layer prepared on the surface of the active layer
  • a gate prepared on the surface of the gate insulating layer
  • a second insulating layer covering the buffer layer, the active layer, the second conductor layer, the gate insulating layer and the gate;
  • a drain prepared on the surface of the second insulating layer, and connected to the active layer through a first via hole penetrating the second insulating layer;
  • the source electrode prepared on the surface of the second insulating layer, is connected to the active layer through a second via hole penetrating the second insulating layer, and is connected to the active layer through a second via hole penetrating the second insulating layer and the buffer layer.
  • the via hole is connected with the light shielding layer;
  • a pixel electrode is prepared on the surface of the flat layer, the pixel electrode is connected to the source electrode through a fourth via hole passing through the flat layer and the passivation layer, and the pixel electrode passes through the flat layer and the passivation layer.
  • the opening of the passivation layer is in contact with the second insulating layer;
  • the pixel definition layer is prepared on the surface of the flat layer and the pixel electrode, and exposes the pixel electrode above the opening.
  • the active layer is located above the light shielding layer
  • the second conductor layer is located above the first conductor layer
  • the opening is located above the second conductor layer.
  • the width of the active layer is smaller than the width of the light shielding layer
  • the width of the gate insulating layer is smaller than the width of the active layer
  • the width of the gate is smaller than the width of the gate insulating layer.
  • first conductor layer, the buffer layer, the second conductor layer, the second insulating layer and the pixel electrode form a three-layer sandwich transparent capacitor structure.
  • the material of the light-shielding layer is one or more of Mo, Al, Cu, and Ti;
  • the thickness of the light-shielding layer is 2000-10000 ⁇ ;
  • the thickness of the first conductor layer is 200-2000 ⁇ .
  • the fourth via hole is prepared by yellow light.
  • the thickness of the semiconductor layer is 100-1000 ⁇ ;
  • the material of the semiconductor layer is one of IGZO, IZTO, and IGZTO;
  • the thickness of the second metal layer is 1000-3000 ⁇ ;
  • the material of the source electrode and the drain electrode is one or more of Mo, Al, Cu, and Ti, and the thickness is 2000-8000 ⁇ .
  • the material of the second insulating layer is one or a combination of SiOx and SiNx;
  • the thickness of the second insulating layer is 2000-10000 ⁇ .
  • the material of the passivation layer is one or a combination of SiOx and SiNx;
  • the thickness of the passivation layer is 1000-5000 ⁇ ;
  • the material of the pixel electrode is ITO or IZO;
  • the thickness of the pixel electrode is 200-2000 ⁇ .
  • the thickness of the buffer layer is 1000-5000 ⁇ ;
  • the material of the buffer layer is one or a combination of two of SiOx and SiNx.
  • FIG. 1 is a structural diagram of a conventional OLED panel.
  • FIG. 2 is a flowchart of a method for fabricating an OLED panel according to an embodiment of the present invention.
  • FIG. 3 is a structural diagram of a first graphic layer according to an embodiment of the present invention.
  • FIG. 4 is a structural diagram of a second graphics layer according to an embodiment of the present invention.
  • FIG. 5 is a structural diagram of a third graphics layer according to an embodiment of the present invention.
  • FIG. 6 is a structural diagram of an OLED panel according to an embodiment of the present invention.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • FIG. 2 is a flowchart of a method for fabricating an OLED panel according to an embodiment of the present invention. As shown in FIG. 2, the present invention discloses a manufacturing method of an OLED panel, comprising the following steps:
  • S202 coating a transparent metal oxide on the substrate and the light-shielding layer, and patterning the transparent metal oxide to form a first conductor layer, and one end of the first conductor layer is overlapped with the light-shielding layer;
  • S203 Deposit a buffer layer, a semiconductor layer, a first insulating layer and a first metal layer in sequence on the substrate, and pattern the semiconductor layer, the first insulating layer and the first metal layer to form a first semiconductor layer and a second semiconductor layer layer, a gate insulating layer and a gate, the first semiconductor layer and the second semiconductor layer are spaced apart;
  • S205 forming a second insulating layer covering the buffer layer, the active layer, the second conductor layer, the gate insulating layer and the gate, and patterning the second insulating layer and the buffer layer to form a second insulating layer exposing the active layer a via hole, a second via hole exposing the active layer, and a third via hole exposing the light shielding layer;
  • S206 forming a second metal layer on the second insulating layer, and patterning the second metal layer to form a source electrode and a drain electrode, the drain electrode is connected to the active layer through a first via hole, and the source electrode is connected to the active layer through a second via hole The hole is connected to the active layer, and the source is connected to the light shielding layer through the third via hole;
  • S207 forming a passivation layer covering the second insulating layer, the source electrode and the drain electrode;
  • S208 forming a flat layer covering the passivation layer, and patterning the passivation layer and the flat layer to form a fourth via hole exposing the source electrode and an opening exposing the second insulating layer;
  • S209 coating a transparent metal oxide on the flat layer and the opening, and patterning the transparent metal oxide to form a pixel electrode, and the pixel electrode is connected to the source electrode through a fourth via hole;
  • FIG. 3 is a structural diagram of a first graphic layer according to an embodiment of the present invention.
  • a light shielding layer 302 and a first conductor layer 303 are prepared on the substrate 301 to form a first pattern layer.
  • the substrate 301 is cleaned first, and then a layer of metal is deposited on the substrate 301 .
  • a layer of conductive transparent metal oxide such as ITO or IZO is deposited on the substrate 301 with a thickness of 200-2000 ⁇ , and a pattern is formed by photolithography as the first conductor layer 303 .
  • the first conductor layer 303 serves as a pole plate of the capacitor, and the first conductor layer 303 is directly overlapped with the light shielding layer 302, and the signals are connected.
  • FIG. 4 is a structural diagram of a second graphics layer according to an embodiment of the present invention.
  • a buffer layer 304, a second conductor layer 306, an active layer 305, a gate insulating layer 307, a gate 308 and a second insulating layer 309 are prepared on the first pattern layer to form a second pattern layer.
  • the buffer layer 304 can optionally be a one-layer or multi-layer structure.
  • the metal oxide semiconductor material is etched into a pattern to form a first semiconductor layer and a second semiconductor layer.
  • first insulating layer Deposit a layer of SiOx or SiNx or a multilayer structure film as the first insulating layer with a thickness of 1000-3000 ⁇ .
  • a layer of metal is deposited as the first metal layer, which can be Mo, Al, Cu, Ti, etc., or an alloy, with a thickness of 2000-8000 ⁇ .
  • the gate 308 is first etched, and then the pattern of the gate 308 is used as self-alignment to etch the first insulating layer. Only under the film layer with the gate 308, the first insulating layer exists, and the rest Where the first insulating layer is etched away, a gate insulating layer 307 is formed.
  • Plasma treatment is performed on the entire surface, and for the second semiconductor layer that is not protected by the gate 308 and the gate insulating layer 307 above, the resistance is significantly reduced after the treatment, and an N+ conductor layer is formed, and a part of the first semiconductor layer is also conductive. In the resistance region, the part of the first semiconductor layer below the gate electrode 308 is not processed, and the semiconductor characteristics are maintained, serving as the TFT channel.
  • a second insulating layer 309 is deposited, and the material of the second insulating layer 309 is ILD, SiOx or SiNx or a multilayer structure film, and the thickness is 2000-10000 ⁇ .
  • Yellow light and etching are performed on the second insulating layer 309 to form a first via hole 3091 exposing the active layer 305 , a second via hole 3092 exposing the active layer 305 and a third via hole 3093 exposing the light shielding layer 302 .
  • FIG. 5 is a structural diagram of a third graphics layer according to an embodiment of the present invention.
  • a source electrode 310 , a drain electrode 311 , a passivation layer 312 and a flat layer 313 are prepared on the second pattern layer to form a third pattern layer.
  • a layer of metal as the second metal layer, which can be Mo, Al, Cu, Ti, etc., or an alloy, with a thickness of 2000-8000 ⁇ , and then define a pattern
  • the source electrode 310 is connected to the lower light shielding layer 302 and the capacitor lower substrate .
  • SiOx or SiNx or a multilayer structure film is deposited as the passivation layer 312, and the thickness of the passivation layer 312 is 1000-5000 ⁇ .
  • a layer of photoresist material with a thickness of 0.5-4um is made as the flat layer 313, a fourth via hole 3131 is made on the flat layer 313 by yellow light, and the flat layer 313 and the passivation layer 312 in the capacitor area are etched to form an opening 3132.
  • a pixel electrode and a pixel definition layer are prepared on the third graphic layer to complete the fabrication of the OLED panel.
  • the pixel electrode is made of ITO or IZO and other similar conductive transparent metal oxides.
  • the thickness of the pixel electrode is 200-2000 ⁇ , and a pattern is made by a photolithography.
  • the pixel electrode as the anode of the OLED is directly signal-connected to the source electrode 310 of the TFT.
  • the fabrication of the OLED material, and the deposition and packaging of the cathode are completed, the fabrication of the OLED panel is completed.
  • the first conductor layer 303 , the buffer layer 304 , the second conductor layer 306 , the second insulating layer 309 and the pixel electrode 314 form a three-layer sandwich transparent capacitor structure.
  • the first conductor layer 303 is overlapped with the light-shielding layer 302, the pixel electrode is connected with the source electrode 310, the flat layer 313 and the passivation layer 312 in the capacitor area are removed, and the OLED panel is improved.
  • the aperture ratio and capacitor storage capacity are greatly improved, and the design freedom is higher. It can be applied to larger-sized OLED panels and improves the capacity of capacitor retention.
  • FIG. 6 is a structural diagram of an OLED panel according to an embodiment of the present invention.
  • the panel includes: a substrate 301; a light-shielding layer 302, which is prepared on the surface of the substrate 301; layer 304, covering the light-shielding layer 302, the first conductor layer 303 and the substrate 301; the active layer 305, prepared on the surface of the buffer layer 304; the second conductor layer 306, prepared on the surface of the buffer layer 304, the second conductor layer 306 and the active layer 306
  • the layers 305 are arranged at intervals; the gate insulating layer 307 is prepared on the surface of the active layer 305; the gate 308 is prepared on the surface of the gate insulating layer 307; the second insulating layer 309 covers the buffer layer 304, the active layer 305, the second The conductor layer 306, the gate insulating layer 307 and the gate 308; the drain electrode 311, prepared on the surface of the second insulating layer 309 and connected to the active
  • the active layer 305 is located above the light shielding layer 302 .
  • the second conductor layer 306 is located above the first conductor layer 303 .
  • the opening 3132 is located above the second conductor layer 306 .
  • the width of the active layer 305 is smaller than that of the light shielding layer 302 .
  • the width of the gate insulating layer 307 is smaller than that of the active layer 305 .
  • the width of the gate electrode 308 is smaller than the width of the gate insulating layer 307 .
  • the first conductor layer 303 is overlapped with the light shielding layer 302, the pixel electrode 314 is connected with the source electrode 310, the flat layer 313 and the passivation layer 312 in the capacitor area are removed, and the OLED panel is improved.
  • the aperture ratio is greatly improved, the capacitance storage capacity is greatly improved, and the design freedom is higher. It can be applied to larger-sized OLED panels and improves the capacitance retention capacity.
  • the embodiments of the present invention can simultaneously improve the aperture ratio and the capacitance storage capacity of the OLED panel, have a high degree of design freedom, and can be applied to a larger size OLED panel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种OLED面板的制作方法、OLED面板。通过将第一导体层（303）与遮光层（302）搭接，将像素电极（314）与源极（310）连接，去除电容区域的平坦层（313）和钝化层（312），提高了OLED面板的开口率，电容存储能力大幅提升，设计自由度更高，可应用于更大尺寸的OLED面板，提高了电容保持能力。克服了现有的OLED面板存在的开口率低、电容存储能力差的问题。

Description

OLED面板的制作方法、OLED面板 技术领域
本发明涉及显示领域，具体涉及一种OLED面板的制作方法、OLED面板。
 背景技术
有机发光器件OLED(Organic Light Emitting Diode)相对于液晶显示器(LCD)，具有自发光、反应快、视角广、亮度高、色彩艳、轻薄等优点，被认为是下一代显示技术。其中，对于底发射型显示面板而言，开口率和电容的存储能力是衡量其优劣的重要参数之一。
图1为一种现有OLED面板的结构图。如图1所示，该面板包括基板101、遮光层102、第一导体层103、缓冲层104、有源层105、第二导体层106、栅极绝缘层107、栅极108、第二绝缘层109、源极110、漏极111、钝化层112、平坦层113、像素电极114和像素定义层115。现有技术中，将第一半导体层103、缓冲层104和第二半导体层106作为透明电容结构应用于底发射OLED，由于透明电容结构不会影响电容区域，开口率增大，但是电容的存储能力受限。
因此，如何同时提高OLED面板的开口率和电容存储能力成为了本领域技术人员亟待解决的技术问题和始终研究的重点。
 技术问题
本发明实施例提供了一种OLED面板的制作方法。现有的OLED面板存在开口率低、电容存储能力差的问题。本发明通过将第一导体层与遮光层搭接，将像素电极与源极连接，去除电容区域的平坦层和钝化层，提高了OLED面板的开口率，电容存储能力大幅提升，设计自由度更高，可应用于更大尺寸的OLED面板，提高了电容保持能力。
 技术解决方案
有鉴于此，本发明实施例提供了一种OLED面板的制作方法、OLED面板，以解决现有的OLED面板的开口率低、电容存储能力低的问题。
为此，本发明实施例提供了如下技术方案：
本发明第一方面提供了一种OLED面板的制作方法，包括如下步骤：
在基板上形成遮光层；
在所述基板和所述遮光层上涂布透明金属氧化物，并对所述透明金属氧化物进行图案化，形成第一导体层，所述第一导体层的一端与所述遮光层搭接；
在所述基板上依次沉积缓冲层、半导体层、第一绝缘层和第一金属层，并对所述半导体层、所述第一绝缘层和所述第一金属层进行图案化，形成第一半导体层、第二半导体层、栅极绝缘层和栅极，所述第一半导体层与所述第二半导体层间隔设置；
以所述栅极及所述栅极绝缘层为遮挡，对所述第一半导体层与所述第二半导体层进行等离子处理，得到有源层以及与所述有源层间隔设置的第二导体层；
形成覆盖所述缓冲层、有源层、第二导体层、栅极绝缘层和栅极的第二绝缘层，并对所述第二绝缘层和所述缓冲层进行图案化，形成暴露出有源层的第一过孔、暴露出有源层的第二过孔和暴露出遮光层的第三过孔；
在所述第二绝缘层上形成第二金属层，并对所述第二金属层进行图案化，形成源极和漏极，所述漏极通过所述第一过孔与所述有源层连接，所述源极通过所述第二过孔与所述有源层连接，所述源极通过所述第三过孔与所述遮光层连接；
形成覆盖所述第二绝缘层、所述源极和所述漏极的钝化层；
形成覆盖所述钝化层的平坦层，并对所述钝化层和所述平坦层进行图案化，形成暴露出源极的第四过孔和暴露出所述第二绝缘层的开口；
在所述平坦层和所述开口上涂布透明金属氧化物，并对所述透明金属氧化物进行图案化，形成像素电极，所述像素电极通过所述第四过孔与所述源极连接；
形成覆盖所述平坦层和所述像素电极的像素定义层，并对所述像素定义层进行图案化暴露出位于所述开口上方的像素电极。
进一步地，所述第一导体层、所述缓冲层、所述第二导体层、所述第二绝缘层与所述像素电极形成三层夹心透明电容结构。
进一步地，所述遮光层的材质为Mo，Al，Cu，Ti中的一种或几种；
所述遮光层的厚度为2000-10000Å；
所述第一导体层的厚度为200-2000Å。
进一步地，所述第四过孔通过黄光置备。
进一步地，所述半导体层的厚度为100-1000Å；
所述半导体层的材质为IGZO，IZTO，IGZTO中的一种；
所述栅极绝缘层的厚度为1000-3000Å；
所述第二金属层的材质为Mo，Al，Cu，Ti中的一种或几种，厚度为2000-8000Å。
进一步地，所述第二绝缘层的材质为SiOx和SiNx中的一种或两种的组合；
所述第二绝缘层的厚度为2000-10000Å。
进一步地，所述钝化层的材质为SiOx和SiNx中的一种或两种的组合；
所述钝化层的厚度为1000-5000Å；
所述像素电极的材质为ITO或IZO；
所述像素电极的厚度为200-2000Å。
进一步地，所述有源层位于所述遮光层上方；
所述第二导体层位于所述第一导体层上方；
所述开口位于所述第二导体层上方。
进一步地，所述有源层的宽度小于所述遮光层的宽度；
所述栅极绝缘层的宽度小于所述有源层的宽度；
所述栅极的宽度小于所述栅极绝缘层的宽度。
进一步地，所述缓冲层的厚度为1000-5000Å；
所述缓冲层的材质为SiOx和SiNx中的一种或两种的组合。
本发明第二方面提供了一种OLED面板，包括：
基板；
遮光层，制备于所述基板表面；
第一导体层，制备于所述基板表面，所述第一导体层的一端与所述遮光层搭接；
缓冲层，覆盖所述遮光层、所述第一导体层和所述基板；
有源层，制备于所述缓冲层表面；
第二导体层，制备于所述缓冲层表面，所述第二导体层与所述有源层间隔设置；
栅极绝缘层，制备于所述有源层表面；
栅极，制备于所述栅极绝缘层表面；
第二绝缘层，覆盖所述缓冲层、有源层、第二导体层、栅极绝缘层和栅极；
漏极，制备于所述第二绝缘层表面，通过贯穿所述第二绝缘层的第一过孔与所述有源层连接；
源极，制备于所述第二绝缘层表面，通过贯穿所述第二绝缘层的第二过孔与所述有源层连接，通过贯穿所述第二绝缘层和所述缓冲层的第三过孔与所述遮光层连接；
钝化层，覆盖所述第二绝缘层、所述源极和所述漏极；
平坦层，制备于所述钝化层表面；
像素电极，制备于所述平坦层表面，所述像素电极通过贯穿所述平坦层和所述钝化层的第四过孔与所述源极连接，所述像素电极通过贯穿所述平坦层和所述钝化层的开口与所述第二绝缘层接触；
像素定义层，制备于所述平坦层和所述像素电极表面，并暴露出位于所述开口上方的像素电极。
进一步地，所述有源层位于所述遮光层上方；
所述第二导体层位于所述第一导体层上方；
所述开口位于所述第二导体层上方。
进一步地，所述有源层的宽度小于所述遮光层的宽度；
所述栅极绝缘层的宽度小于所述有源层的宽度；
所述栅极的宽度小于所述栅极绝缘层的宽度。
进一步地，所述第一导体层、缓冲层、第二导体层、第二绝缘层与所述像素电极形成三层夹心透明电容结构。
进一步地，所述遮光层的材质为Mo，Al，Cu，Ti中的一种或几种；
所述遮光层的厚度为2000-10000Å；
所述第一导体层的厚度为200-2000Å。
进一步地，所述第四过孔通过黄光置备。
进一步地，所述半导体层的厚度为100-1000Å；
所述半导体层的材质为IGZO，IZTO，IGZTO中的一种；
所述第二金属层的厚度为1000-3000Å；
所述源极和漏极的材质为Mo，Al，Cu，Ti中的一种或几种，厚度为2000-8000Å。
进一步地，所述第二绝缘层的材质为SiOx和SiNx中的一种或两种的组合；
所述第二绝缘层的厚度为2000-10000Å。
进一步地，所述钝化层的材质为SiOx和SiNx中的一种或两种的组合；
所述钝化层的厚度为1000-5000Å；
所述像素电极的材质为ITO或IZO；
所述像素电极的厚度为200-2000Å。
进一步地，所述缓冲层的厚度为1000-5000Å；
所述缓冲层的材质为SiOx和SiNx中的一种或两种的组合。
 附图说明
为了更清楚地说明本发明具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种现有OLED面板的结构图。
图2为本发明实施例的OLED面板制作方法流程图。
图3为本发明实施例的第一图形层结构图。
图4为本发明实施例的第二图形层结构图。
图5为本发明实施例的第三图形层结构图。
图6为本发明实施例的OLED面板结构图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中一种OLED面板的制作方法、OLED面板的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，“示例性”一词用来表示“用作例子、例证或说明”。本申请中被描述为“示例性”的任何实施例不一定被解释为比其它实施例更优选或更具优势。为了使本领域任何技术人员能够实现和使用本申请，给出了以下描述。在以下描述中，为了解释的目的而列出了细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本申请。在其它实例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本申请的描述变得晦涩。因此，本申请并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。
图2为本发明实施例的OLED面板制作方法流程图。如图2所示，本发明公开了一种OLED面板的制作方法，包括如下步骤：
S201：在基板上形成遮光层；
S202: 在基板和遮光层上涂布透明金属氧化物，并对透明金属氧化物进行图案化，形成第一导体层，第一导体层的一端与遮光层搭接；
S203: 在基板上依次沉积缓冲层、半导体层、第一绝缘层和第一金属层，并对半导体层、第一绝缘层和第一金属层进行图案化，形成第一半导体层、第二半导体层、栅极绝缘层和栅极，第一半导体层与第二半导体层间隔设置；
S204: 以栅极及栅极绝缘层为遮挡，对第一半导体层与第二半导体层进行等离子处理，得到有源层以及与有源层间隔设置的第二导体层；
S205: 形成覆盖缓冲层、有源层、第二导体层、栅极绝缘层和栅极的第二绝缘层，并对第二绝缘层和缓冲层进行图案化，形成暴露出有源层的第一过孔、暴露出有源层的第二过孔和暴露出遮光层的第三过孔；
S206: 在第二绝缘层上形成第二金属层，并对第二金属层进行图案化，形成源极和漏极，漏极通过第一过孔与有源层连接，源极通过第二过孔与有源层连接，源极通过第三过孔与遮光层连接；
S207: 形成覆盖第二绝缘层、源极和漏极的钝化层；
S208: 形成覆盖钝化层的平坦层，并对钝化层和平坦层进行图案化，形成暴露出源极的第四过孔和暴露出第二绝缘层的开口；
S209: 在平坦层和开口上涂布透明金属氧化物，并对透明金属氧化物进行图案化，形成像素电极，像素电极通过第四过孔与源极连接；
S210: 形成覆盖平坦层和像素电极的像素定义层，并对像素定义层进行图案化暴露出位于开口上方的像素电极。
本实施例中，图3为本发明实施例的第一图形层结构图。如图3所示，在基板301上制备遮光层302和第一导体层303，形成第一图形层。优选先清洗基板301，再在基板301上沉积一层金属，金属可选为是Mo，Al，Cu，Ti或者是合金，厚度2000-10000Å，并利用一道光刻做出图形作为遮光层302。优选在基板301上沉积一层ITO或IZO等类似的导电透明金属氧化物，厚度200-2000Å，利用光刻做出图形作为第一导体层303。第一导体层303一方面作为电容的一个极板，并且第一导体层303与遮光层302直接搭接，信号相连。
图4为本发明实施例的第二图形层结构图。如图4所示，在第一图形层上制备缓冲层304、第二导体层306、有源层305、栅极绝缘层307、栅极308和第二绝缘层309，形成第二图形层。缓冲层304可选为一层或多层结构。沉积一层金属氧化物半导体材料（Oxide），金属氧化物半导体材料可以是IGZO，IZTO，IGZTO等，厚度为100-1000Å。将金属氧化物半导体材料蚀刻出图形形成第一半导体层和第二半导体层。沉积一层SiOx或是SiNx或是多层结构薄膜，作为第一绝缘层，厚度1000-3000Å。沉积一层金属作为第一金属层，可以是Mo，Al，Cu，Ti等，或者是合金，厚度2000-8000Å。利用一道黄光，先蚀刻出栅极308，再利用栅极308的图形为自对准，蚀刻第一绝缘层，只在有栅极308的膜层下方，才有第一绝缘层存在，其余地方第一绝缘层均被蚀刻掉，形成栅极绝缘层307。进行整面等离子处理，对于上方没有栅极308和栅极绝缘层307保护的第二半导体层，其处理以后电阻明显降低，形成N+导体层，第一半导体层的一部分也被导体化，形成低阻值区域，第一半导体层在栅极308下方的部分没有被处理到，保持半导体特性，作为TFT沟道。沉积第二绝缘层309，第二绝缘层309材料为ILD，SiOx或是SiNx或是多层结构薄膜，厚度为2000-10000Å。对第二绝缘层309进行黄光和蚀刻形成暴露出有源层305的第一过孔3091、暴露出有源层305的第二过孔3092和暴露出遮光层302的第三过孔3093。
图5为本发明实施例的第三图形层结构图。如图5所示，在第二图形层上制备源极310、漏极311、钝化层312、平坦层313，形成第三图形层。沉积一层金属作为第二金属层，可以是Mo，Al，Cu，Ti等，或者是合金，厚度为2000-8000Å，然后定义出图形，源极310与下方的遮光层302及电容下基板相连。沉积SiOx或是SiNx或是多层结构薄膜作为钝化层312，钝化层312厚度1000-5000Å。制作厚度为0.5-4um的一层光阻材料作为平坦层313，通过黄光在平坦层313上做出第四过孔3131，蚀刻掉电容区域的平坦层313和钝化层312形成开口3132。
在第三图形层上制备像素电极和像素定义层，完成OLED面板的制作。用ITO或IZO等类似的导电透明金属氧化物制作像素电极，像素电极的厚度为200-2000Å，利用一道光刻做出图形。将像素电极作为OLED的阳极与TFT的源极310直接信号相连。制作像素定义层，完成OLED材料的制作，阴极的沉积和封装以后，完成OLED面板的制作。本实施例中，第一导体层303、缓冲层304、第二导体层306、第二绝缘层309与像素电极314形成三层夹心透明电容结构。
与现有技术相比，本发明通过将第一导体层303与遮光层302搭接，将像素电极与源极310连接，去除电容区域的平坦层313和钝化层312，提高了OLED面板的开口率，电容存储能力大幅提升，设计自由度更高，可应用于更大尺寸的OLED面板，提高了电容保持能力。
图6为本发明实施例的OLED面板结构图。如图6所示，该面板包括：基板301；遮光层302，制备于基板301表面；第一导体层303，制备于基板301表面，第一导体层303的一端与遮光层302搭接；缓冲层304，覆盖遮光层302、第一导体层303和基板301；有源层305，制备于缓冲层304表面；第二导体层306，制备于缓冲层304表面，第二导体层306与有源层305间隔设置；栅极绝缘层307，制备于有源层305表面；栅极308，制备于栅极绝缘层307表面；第二绝缘层309，覆盖缓冲层304、有源层305、第二导体层306、栅极绝缘层307和栅极308；漏极311，制备于第二绝缘层309表面，通过贯穿第二绝缘层309的第一过孔3091与有源层305连接；源极310，制备于第二绝缘层309表面，通过贯穿第二绝缘层309的第二过孔3092与有源层305连接；通过贯穿第二绝缘层309和缓冲层304的第三过孔3093与遮光层302连接；钝化层312，覆盖第二绝缘层309、源极310和漏极311；平坦层313，制备于钝化层312表面；像素电极314，制备于平坦层313表面，像素电极314通过贯穿平坦层313和钝化层312的第四过孔3131与源极310连接，像素电极314通过贯穿平坦层313和钝化层312的开口3132与第二绝缘层309接触；像素定义层315，制备于平坦层313和像素电极314表面，并暴露出位于开口3132上方的像素电极314。
本实施例中，有源层305位于遮光层302上方。第二导体层306位于第一导体层303上方。开口3132位于第二导体层306上方。有源层305的宽度小于遮光层302的宽度。栅极绝缘层307的宽度小于有源层305的宽度。栅极308的宽度小于栅极绝缘层307的宽度。
与现有技术相比，本发明通过将第一导体层303与遮光层302搭接，将像素电极314与源极310连接，去除电容区域的平坦层313和钝化层312，提高了OLED面板的开口率，电容存储能力大幅提升，设计自由度更高，可应用于更大尺寸的OLED面板，提高了电容保持能力。
虽然结合附图描述了本发明的实施例，但是本领域技术人员可以在不脱离本发明的精神和范围的情况下作出各种修改和变型，这样的修改和变型均落入由所附权利要求所限定的范围之内。
 工业实用性
与传统的OLED面板的制作方法相比，本发明实施例能够同时提高OLED面板的开口率和电容存储能力，设计自由度高，可应用于更大尺寸的OLED面板。

Claims (20)

  1. 一种OLED面板的制作方法，其中，包括如下步骤：
    在基板上形成遮光层；
    在所述基板和所述遮光层上涂布透明金属氧化物，并对所述透明金属氧化物进行图案化，形成第一导体层，所述第一导体层的一端与所述遮光层搭接；
    在所述基板上依次沉积缓冲层、半导体层、第一绝缘层和第一金属层，并对所述半导体层、所述第一绝缘层和所述第一金属层进行图案化，形成第一半导体层、第二半导体层、栅极绝缘层和栅极，所述第一半导体层与所述第二半导体层间隔设置；
    以所述栅极及所述栅极绝缘层为遮挡，对所述第一半导体层与所述第二半导体层进行等离子处理，得到有源层以及与所述有源层间隔设置的第二导体层；
    形成覆盖所述缓冲层、有源层、第二导体层、栅极绝缘层和栅极的第二绝缘层，并对所述第二绝缘层和所述缓冲层进行图案化，形成暴露出有源层的第一过孔、暴露出有源层的第二过孔和暴露出遮光层的第三过孔；
    在所述第二绝缘层上形成第二金属层，并对所述第二金属层进行图案化，形成源极和漏极，所述漏极通过所述第一过孔与所述有源层连接，所述源极通过所述第二过孔与所述有源层连接，所述源极通过所述第三过孔与所述遮光层连接；
    形成覆盖所述第二绝缘层、所述源极和所述漏极的钝化层；
    形成覆盖所述钝化层的平坦层，并对所述钝化层和所述平坦层进行图案化，形成暴露出源极的第四过孔和暴露出所述第二绝缘层的开口；
    在所述平坦层和所述开口上涂布透明金属氧化物，并对所述透明金属氧化物进行图案化，形成像素电极，所述像素电极通过所述第四过孔与所述源极连接；
    形成覆盖所述平坦层和所述像素电极的像素定义层，并对所述像素定义层进行图案化暴露出位于所述开口上方的像素电极。
  2. 根据权利要求1所述的OLED面板的制作方法，所述第一导体层、所述缓冲层、所述第二导体层、所述第二绝缘层与所述像素电极形成三层夹心透明电容结构。
  3. 根据权利要求1所述的OLED面板的制作方法，所述遮光层的材质为Mo，Al，Cu，Ti中的一种或几种；
    所述遮光层的厚度为2000-10000Å；
    所述第一导体层的厚度为200-2000Å。
  4. 根据权利要求1所述的OLED面板的制作方法，所述第四过孔通过黄光置备。
  5. 根据权利要求1所述的OLED面板的制作方法，所述半导体层的厚度为100-1000Å；
    所述半导体层的材质为IGZO，IZTO，IGZTO中的一种；
    所述栅极绝缘层的厚度为1000-3000Å；
    所述第二金属层的材质为Mo，Al，Cu，Ti中的一种或几种，厚度为2000-8000Å。
  6. 根据权利要求1所述的OLED面板的制作方法，所述第二绝缘层的材质为SiOx和SiNx中的一种或两种的组合；
    所述第二绝缘层的厚度为2000-10000Å。
  7. 根据权利要求1所述的OLED面板的制作方法，所述钝化层的材质为SiOx和SiNx中的一种或两种的组合；
    所述钝化层的厚度为1000-5000Å；
    所述像素电极的材质为ITO或IZO；
    所述像素电极的厚度为200-2000Å。
  8. 根据权利要求1所述的OLED面板的制作方法，所述有源层位于所述遮光层上方；
    所述第二导体层位于所述第一导体层上方；
    所述开口位于所述第二导体层上方。
  9. 根据权利要求1所述的OLED面板的制作方法，所述有源层的宽度小于所述遮光层的宽度；
    所述栅极绝缘层的宽度小于所述有源层的宽度；
    所述栅极的宽度小于所述栅极绝缘层的宽度。
  10. 根据权利要求1所述的OLED面板的制作方法，所述缓冲层的厚度为1000-5000Å；
    所述缓冲层的材质为SiOx和SiNx中的一种或两种的组合。
  11. 一种OLED面板，其中，包括：
    基板；
    遮光层，制备于所述基板表面；
    第一导体层，制备于所述基板表面，所述第一导体层的一端与所述遮光层搭接；
    缓冲层，覆盖所述遮光层、所述第一导体层和所述基板；
    有源层，制备于所述缓冲层表面；
    第二导体层，制备于所述缓冲层表面，所述第二导体层与所述有源层间隔设置；
    栅极绝缘层，制备于所述有源层表面；
    栅极，制备于所述栅极绝缘层表面；
    第二绝缘层，覆盖所述缓冲层、有源层、第二导体层、栅极绝缘层和栅极；
    漏极，制备于所述第二绝缘层表面，通过贯穿所述第二绝缘层的第一过孔与所述有源层连接；
    源极，制备于所述第二绝缘层表面，通过贯穿所述第二绝缘层的第二过孔与所述有源层连接，通过贯穿所述第二绝缘层和所述缓冲层的第三过孔与所述遮光层连接；
    钝化层，覆盖所述第二绝缘层、所述源极和所述漏极；
    平坦层，制备于所述钝化层表面；
    像素电极，制备于所述平坦层表面，所述像素电极通过贯穿所述平坦层和所述钝化层的第四过孔与所述源极连接，所述像素电极通过贯穿所述平坦层和所述钝化层的开口与所述第二绝缘层接触；
    像素定义层，制备于所述平坦层和所述像素电极表面，并暴露出位于所述开口上方的像素电极。
  12. 根据权利要求11所述的OLED面板，所述有源层位于所述遮光层上方；
    所述第二导体层位于所述第一导体层上方；
    所述开口位于所述第二导体层上方。
  13. 根据权利要求11所述的OLED面板，所述有源层的宽度小于所述遮光层的宽度；
    所述栅极绝缘层的宽度小于所述有源层的宽度；
    所述栅极的宽度小于所述栅极绝缘层的宽度。
  14. 根据权利要求11所述的OLED面板，所述第一导体层、缓冲层、第二导体层、第二绝缘层与所述像素电极形成三层夹心透明电容结构。
  15. 根据权利要求11所述的OLED面板，所述遮光层的材质为Mo，Al，Cu，Ti中的一种或几种；
    所述遮光层的厚度为2000-10000Å；
    所述第一导体层的厚度为200-2000Å。
  16. 根据权利要求11所述的OLED面板，所述第四过孔通过黄光置备。
  17. 根据权利要求11所述的OLED面板，所述半导体层的厚度为100-1000Å；
    所述半导体层的材质为IGZO，IZTO，IGZTO中的一种；
    所述第二金属层的厚度为1000-3000Å；
    所述源极和漏极的材质为Mo，Al，Cu，Ti中的一种或几种，厚度为2000-8000Å。
  18. 根据权利要求11所述的OLED面板，所述第二绝缘层的材质为SiOx和SiNx中的一种或两种的组合；
    所述第二绝缘层的厚度为2000-10000Å。
  19. 根据权利要求11所述的OLED面板，所述钝化层的材质为SiOx和SiNx中的一种或两种的组合；
    所述钝化层的厚度为1000-5000Å；
    所述像素电极的材质为ITO或IZO；
    所述像素电极的厚度为200-2000Å。
  20. 根据权利要求11所述的OLED面板，所述缓冲层的厚度为1000-5000Å；
    所述缓冲层的材质为SiOx和SiNx中的一种或两种的组合。
PCT/CN2020/131386 2020-09-03 2020-11-25 Oled 面板的制作方法、 oled 面板 WO2022048044A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/973,012 US12022686B2 (en) 2020-09-03 2020-11-25 Manufacturing method of OLED panel and OLED panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010914076.0A CN112117311A (zh) 2020-09-03 2020-09-03 Oled面板的制作方法、oled面板
CN202010914076.0 2020-09-03

Publications (1)

Publication Number Publication Date
WO2022048044A1 true WO2022048044A1 (zh) 2022-03-10

Family

ID=73804098

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/131386 WO2022048044A1 (zh) 2020-09-03 2020-11-25 Oled 面板的制作方法、 oled 面板

Country Status (3)

Country Link
US (1) US12022686B2 (zh)
CN (1) CN112117311A (zh)
WO (1) WO2022048044A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103904086A (zh) * 2012-12-24 2014-07-02 上海天马微电子有限公司 一种薄膜晶体管阵列基板
CN108957884A (zh) * 2018-07-23 2018-12-07 深圳市华星光电技术有限公司 阵列基板、液晶面板和阵列基板制作方法
CN109696781A (zh) * 2018-12-24 2019-04-30 惠科股份有限公司 阵列基板、阵列基板的制作方法和显示装置
CN110943112A (zh) * 2019-11-26 2020-03-31 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN111276493A (zh) * 2020-02-10 2020-06-12 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN111584593A (zh) * 2020-05-25 2020-08-25 京东方科技集团股份有限公司 显示面板、显示装置以及显示面板的制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101113394B1 (ko) * 2009-12-17 2012-02-29 삼성모바일디스플레이주식회사 액정표시장치의 어레이 기판
CN107799570A (zh) * 2017-10-09 2018-03-13 深圳市华星光电半导体显示技术有限公司 顶栅自对准金属氧化物半导体tft及其制作方法
KR102615707B1 (ko) * 2017-12-29 2023-12-18 엘지디스플레이 주식회사 유기발광표시패널 및 이를 이용한 유기발광표시장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103904086A (zh) * 2012-12-24 2014-07-02 上海天马微电子有限公司 一种薄膜晶体管阵列基板
CN108957884A (zh) * 2018-07-23 2018-12-07 深圳市华星光电技术有限公司 阵列基板、液晶面板和阵列基板制作方法
CN109696781A (zh) * 2018-12-24 2019-04-30 惠科股份有限公司 阵列基板、阵列基板的制作方法和显示装置
CN110943112A (zh) * 2019-11-26 2020-03-31 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN111276493A (zh) * 2020-02-10 2020-06-12 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN111584593A (zh) * 2020-05-25 2020-08-25 京东方科技集团股份有限公司 显示面板、显示装置以及显示面板的制造方法

Also Published As

Publication number Publication date
US12022686B2 (en) 2024-06-25
CN112117311A (zh) 2020-12-22
US20220320473A1 (en) 2022-10-06

Similar Documents

Publication Publication Date Title
US11387309B2 (en) Display substrate and preparation method thereof, and display apparatus
US11925070B2 (en) Display panel
JP7486523B2 (ja) 表示基板及びその製造方法、表示装置
WO2020200168A1 (zh) Amoled显示屏、显示设备及移动终端
WO2016041304A1 (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
WO2021022594A1 (zh) 阵列基板、显示面板及阵列基板的制作方法
WO2020113794A1 (zh) 显示面板及其制造方法
KR20160062646A (ko) 유기 발광 표시 장치 및 그 제조 방법
JP2007157916A (ja) Ｔｆｔ基板及びｔｆｔ基板の製造方法
WO2015100898A1 (zh) 薄膜晶体管、tft阵列基板及其制造方法和显示装置
WO2016000342A1 (zh) 阵列基板及其制作方法、显示装置
CN108428730B (zh) Oled显示基板及其制作方法、显示装置
KR20140042698A (ko) 유기 발광 다이오드, 터치 디스플레이 장치 및 그의 제조 방법
WO2022001405A1 (zh) 显示基板及其制备方法、显示装置
WO2017031940A1 (zh) 一种阵列基板、其制作方法及显示装置
CN109638078A (zh) Tft的制备方法、tft、oled背板和显示装置
WO2022032883A1 (zh) Oled 显示面板及其制备方法
CN113192981A (zh) 一种tft基板、显示装置及tft基板的制备方法
WO2021114368A1 (zh) 显示面板及其制备方法
KR102152846B1 (ko) 유기전계 발광소자 및 이의 제조 방법
US20220352275A1 (en) Oled display panel and method of manufacturing same
TWI549265B (zh) 畫素結構及其製造方法
WO2022227154A1 (zh) 显示面板及其制备方法、显示装置
WO2022051994A1 (zh) 显示基板及其制备方法、显示装置
WO2020037850A1 (zh) 阵列基板及其制造方法、显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20952285

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20952285

Country of ref document: EP

Kind code of ref document: A1