WO2022047784A1 - 一种晶片承载盘 - Google Patents

一种晶片承载盘 Download PDF

Info

Publication number
WO2022047784A1
WO2022047784A1 PCT/CN2020/113762 CN2020113762W WO2022047784A1 WO 2022047784 A1 WO2022047784 A1 WO 2022047784A1 CN 2020113762 W CN2020113762 W CN 2020113762W WO 2022047784 A1 WO2022047784 A1 WO 2022047784A1
Authority
WO
WIPO (PCT)
Prior art keywords
groove
center
area
wafer carrier
protruding structure
Prior art date
Application number
PCT/CN2020/113762
Other languages
English (en)
French (fr)
Inventor
程凯
张丽旸
Original Assignee
苏州晶湛半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州晶湛半导体有限公司 filed Critical 苏州晶湛半导体有限公司
Priority to CN202080103949.8A priority Critical patent/CN116113730A/zh
Priority to PCT/CN2020/113762 priority patent/WO2022047784A1/zh
Publication of WO2022047784A1 publication Critical patent/WO2022047784A1/zh
Priority to US18/073,862 priority patent/US20230105081A1/en

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4581—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber characterised by material of construction or surface finish of the means for supporting the substrate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/301—AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C23C16/303—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/12—Substrate holders or susceptors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68771—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting more than one semiconductor substrate

Definitions

  • the present invention relates to a semiconductor manufacturing equipment, and relates to a wafer carrier for MOCVD.
  • Graphite disk is a very important accessory in MOCVD equipment.
  • the commonly used graphite disks are round, and some grooves are distributed on the graphite disk. These grooves are used to place the substrate, and then the epitaxial layer is grown on the substrate.
  • the graphite disc is made of high-purity graphite and coated with SiC on the surface.
  • the graphite disk containing the substrate is heated by radiation through the heating wire.
  • FIG. 1 is a schematic diagram of a conventional wafer carrier.
  • the wafer carrier 10 includes three grooves 20 , wherein a wafer 30 is placed in one of the grooves 20 .
  • Figure 2 shows a schematic view of the structure at the section A-A' in Figure 1, and the bottom of the groove is generally flat, convex, and concave.
  • the buffer layer needs to be grown by stress engineering technology, and the epitaxial wafer is convexly warped when the active region is grown. Therefore, for the light-emitting structure of GaN-on-silicon, a convex groove is generally used to match the convexity of the epitaxial wafer.
  • the problem of using the convex groove is: when the wafer 30 is in the groove 20, since the wafer carrier 10 rotates at a high speed during the growth of the wafer 30, the wafer 30 in the groove 20 is affected by centrifugal force, and the wafer 30 will be affected by centrifugal force. 30 moves in a direction away from the center C of the wafer carrier, and the protruding structure at the bottom of the groove will make the gap between the part of the wafer 30 far from the center C of the wafer carrier 10 and the bottom of the wafer carrier 10 is relatively large, that is, the wafer 30 will have a relatively large gap.
  • the distance between 30 and the bottom of the groove 20 is quite different, which causes the phenomenon of uneven heating during the growth of the wafer 30 to be very obvious, which has an impact on the quality of the wafer 30, and the wavelength of the III-V nitride light-emitting wafer 30 is more sensitive to temperature. , it is easy to cause a large wavelength difference in the wafer 30 , which will greatly increase the time and cost and reduce the yield for the subsequent chip manufacturing process and sorting work.
  • the purpose of the present invention is to provide a wafer carrier plate that adjusts the shape of the bottom of the groove to effectively improve the uniformity of wafer epitaxy heating, improves the quality and epitaxy of III-V nitride epitaxial growth, and the on-chip wavelength of optoelectronic epitaxial wafers uniformity.
  • the present invention provides a wafer carrying tray, comprising at least one groove, and the groove includes:
  • the bottom of the groove divides the bottom of the groove into a first area close to the center of the wafer carrier and a second area away from the center of the wafer carrier by a first dividing line passing through the center of the groove.
  • the second area, the bottom of the groove includes:
  • a protruding structure is formed on the bottom surface of the groove, the edge of the protruding structure is located on the bottom surface of the groove, the edge of the protruding structure is not coincident with the edge of the bottom surface of the groove, and the bottom of the groove is having an uncovered area not covered by the protruding structure;
  • the average height of the protruding structures located in the second region is higher than the average height of the protruding structures located in the first region.
  • the first dividing line is a straight line, and the first dividing line is perpendicular to a first center line passing through the center of the crystal carrier plate and the center of the groove; or, the first The boundary line is a circular arc whose center is the center of the crystal carrier and whose radius is the distance from the center of the crystal carrier to the center of the groove.
  • the surface of the protruding structure is a curved surface, the curved surface has a vertex, and the projection of the vertex on the horizontal plane is located in the second region at the bottom of the groove.
  • the projection of the vertex on the horizontal plane is located on the first center line.
  • an area of the uncovered area located in the first area is larger than an area of the uncovered area located in the second area.
  • the uncovered area includes a first uncovered area and a second uncovered area, and the first uncovered area and the second uncovered area are distributed on two sides of the first center line.
  • the first uncovered area and the second uncovered area are distributed symmetrically or asymmetrically based on the first centerline.
  • a first groove is provided in the first uncovered area, and the angle between the side surface of the first groove close to the center of the groove and the horizontal plane is a first inclination angle ⁇ 1, where 0 ⁇ ⁇ 1 ⁇ 90°; the second uncovered area is provided with a second groove, and the angle between the side surface of the second groove close to the center of the groove and the horizontal plane is the second inclination angle ⁇ 2, where 0 ⁇ 2 ⁇ 90°.
  • the first inclination angle ⁇ 1 and the second inclination angle ⁇ 2 are the same or different in size.
  • the opening areas of the first trench and the second trench are the same or different in size.
  • the curved surface of the protruding structure is composed of countless curves starting from the vertex to the edge of the protruding structure, and the radius of curvature of each curve in the countless curves is a fixed value;
  • the point where the edge of the protruding structure is closest to the center of the wafer carrier is the first edge point, and the point where the edge of the protruding structure is farthest from the center of the wafer carrier is the second edge point;
  • the radius of curvature of the curve gradually decreases from the first edge point along the edge of the protruding structure to the second edge point.
  • the present invention has the following technical effects:
  • the groove bottom of the wafer carrier of the present invention divides the groove bottom into a first area close to the center of the wafer carrier and a second area away from the center of the wafer carrier by a first dividing line passing through the center of the groove. It includes a bottom surface of the groove and a protruding structure formed on the bottom surface of the groove, the surface of the protruding structure is a curved surface, the apex of the curved surface is located in the second area of the bottom of the groove, and the bottom of the groove has an uncovered structure that is not covered by the protruding structure.
  • the design structure of the groove bottom of the wafer carrier plate can better match the III-V nitride wafer due to centrifugal force and protruding structure.
  • the problem is that the wafer subjected to the centrifugal force of the rotation of the wafer carrier always maintains a reasonable gap between the wafer and the wafer carrier, which reduces the influence of centrifugal force on the growth of the wafer, ensures the stability of temperature and airflow, and makes the temperature field distribution more uniform, thereby improving the epitaxial layer.
  • the quality of the wafer, the improvement of the wavelength uniformity of the luminescent epitaxial wafer, and the improvement of the yield rate have broad application prospects in the field of semiconductor manufacturing equipment design and manufacture.
  • FIG. 1 is a schematic diagram of a conventional wafer carrier
  • Fig. 2 is the structural representation at the section A-A' in Fig. 1;
  • FIG. 3 is a schematic top view of a wafer carrier in an embodiment of the present application.
  • 4a is a schematic diagram showing the position of the first dividing line at the bottom of the groove in the embodiment of the present invention.
  • 4b is a schematic diagram showing the position of the first dividing line at the bottom of the groove according to another embodiment of the present invention.
  • 5a to 5d are schematic top views of protruding structures in grooves according to different embodiments of the present invention.
  • 6a is a schematic top view of a groove according to another embodiment of the present invention.
  • 6b is a schematic top view of a groove according to another embodiment of the present invention.
  • Figure 6c shows a schematic cross-sectional view of the groove at AA' in Figure 6a;
  • FIG. 7 is a schematic structural diagram of a single groove in an embodiment of the present invention.
  • Chip carrier tray 10 The center C of the chip carrier tray
  • the first edge point O1 The second edge point O2
  • the protruding structure 210 The first area S1
  • the protruding structure vertex H The first dividing line L1
  • the first adjustment area 241 The second adjustment area 242
  • FIG. 3 is a schematic top view of the wafer carrier 10 in an embodiment of the application
  • FIG. 4 is a schematic three-dimensional structure diagram of the wafer carrier 10 in an embodiment of the application.
  • the wafer carrier 10 includes at least one groove 20 .
  • the number of the grooves 20 is three, which are arranged around the center C of the wafer carrier 10 in an orderly manner.
  • the number, size and distribution of the grooves of the carrier plate 20 are not limited. Those skilled in the art should know that the number, size and arrangement of the grooves 20 can be flexibly set according to the size of the wafer 30 .
  • the average height of the protruding structures located in the second region is higher than the average height of the protruding structures located in the first region.
  • the groove 20 includes a groove bottom and a groove side.
  • the groove bottom is divided into a first area S1 close to the center C of the wafer carrier and a first area away from the center C of the wafer carrier.
  • the bottom of the groove includes a groove bottom surface and a protruding structure 210 formed on the groove bottom surface 210.
  • the edge of the protruding structure 210 is located on the groove bottom surface.
  • the bottom of the groove has an uncovered area 230 that is not covered by the protruding structure 210 .
  • the average height of the protruding structures 210 located in the second region S2 is higher than the average height of the protruding structures 210 located in the first region S1.
  • the wafer 30 Due to the centrifugal force of the rotation of the wafer carrier 10, the wafer 30 will move in a direction away from the center C of the wafer carrier, and the protruding structure at the bottom of the groove will make the part of the wafer 30 away from the center C of the wafer carrier 10 and the wafer
  • the gap at the bottom of the carrier plate 10 is relatively large, that is, the distance between the wafer and the bottom of the groove 20 is relatively large.
  • the protruding structures 210 at the bottom of the groove are kept away from the wafer carrier.
  • the height of the part of the center C of the disk is appropriately increased, and the height of the part of the protruding structure close to the center C of the wafer carrier disk is appropriately decreased, so that the wafer 30 subjected to the centrifugal force of the rotation of the wafer carrier disk always maintains the groove 10 between the wafer carrier disk and the wafer carrier. 20
  • There is a reasonable gap which reduces the influence of centrifugal force on the growth of the wafer, ensures the stability of temperature and airflow, and makes the temperature field distribution more uniform, thereby improving the quality of the epitaxial layer wafer.
  • FIG. 4a and 4b are schematic diagrams of the position of the first dividing line at the bottom of the groove 20 in the embodiment of the present invention.
  • the first dividing line L1 is a straight line, and the first dividing line L1 is connected to the center C and the center of the crystal carrier plate.
  • the first center lines L2 of the groove center O are perpendicular to each other.
  • the first area S1 and the second area S2 are equal in area, wherein the first area S1 is close to the center C of the crystal carrier, and the second area S2 is far away from the center C of the crystal carrier.
  • the first dividing line L1 is an arc with the center C of the crystal carrier as the center and the distance from the center C of the crystal carrier to the center O of the groove as the radius.
  • the first dividing line L1 divides the bottom of the groove into two parts with unequal areas, the first area S1 and the second area S2 are equal in area, wherein the first area S1 is close to the center C of the crystal carrier, and the second area S2 is far away from the crystal carrier. Center C.
  • the edge of the protruding structure 210 is not in contact with the side of the groove 20
  • the surface of the protruding structure 210 is a curved surface
  • the curved surface has a vertex H.
  • the surrounding vertex in the groove 20 is The curve around H can be regarded as a contour line. It can be seen from the position distribution of the contour line in FIG. 3 that the average height of the protruding structure 210 in the second region S2 is higher than the average height of the protruding structure 210 in the first region S1 .
  • the projection of the vertex H on the horizontal plane is located on the first center line L2 of the second region S2 at the bottom of the groove.
  • the area of the uncovered area 230 located in the first area S1 is larger than the area of the uncovered area 230 located in the second area S2 .
  • the uncovered area 230 includes a first uncovered area 231 and a second uncovered area 232, the first uncovered area 231 and the second uncovered area 232 are distributed on both sides of the first center line L2, and the first uncovered area 231 and The second uncovered area 232 may be connected to each other as a whole, the first uncovered area 231 and the second uncovered area 232 may also be independent of each other, and the first uncovered area 231 and the second uncovered area 232 are based on the first center line L2 Symmetrical or asymmetrical distribution.
  • the width d1 of the uncovered area 230 on the first center line L2 is at the first center Distance R on line L2, where 0 ⁇ d1 ⁇ 1/6R.
  • FIGS. 5a to 5d are top structural views of the groove 20 in different embodiments of the present invention.
  • the first uncovered area 231 and the second uncovered area 232 are independent of each other, wherein, in FIG. 5a The first uncovered area 231 and the second uncovered area 232 of the groove 20 are symmetrically distributed based on the first center line L2, and the first uncovered area 231 and the second uncovered area 232 of the groove 20 in FIG. 5b are based on the first The centerline L2 is asymmetrically distributed.
  • FIGS. 5a to 5b are top structural views of the groove 20 in different embodiments of the present invention.
  • the first uncovered area 231 and the second uncovered area 232 are independent of each other, wherein, in FIG. 5a The first uncovered area 231 and the second uncovered area 232 of the groove 20 are symmetrically distributed based on the first center line L2, and the first uncovered area 231 and the second uncovered area 232 of the groove 20 in FIG. 5b are based on the first
  • the first uncovered area 231 and the second uncovered area 232 are connected to each other as a whole, wherein the first uncovered area 231 and the second uncovered area 232 of the groove 20 in FIG. 5 c
  • the first uncovered area 231 and the second uncovered area 232 of the groove 20 in FIG. 5d are distributed asymmetrically based on the first centerline L2.
  • FIG. 6a and 6b are schematic top views of the groove 20 according to different embodiments of the present invention
  • FIG. 6c is a schematic cross-sectional structure diagram of the groove 20 in FIG. 6a at AA'.
  • the groove 20 in FIG. 6a is similar in structure to the groove 20 in FIG.
  • the difference is that the first uncovered area 231 is provided with a first groove 241, and the side of the first groove close to the center O of the groove is sandwiched between the horizontal plane
  • the angle is the first inclination angle ⁇ 1, where 0 ⁇ 1 ⁇ 90°
  • the second uncovered area 231 is provided with a second groove 242, and the angle between the side surface of the second groove 242 close to the center O of the groove and the horizontal plane is the second Inclination angle ⁇ 2, where 0 ⁇ 2 ⁇ 90°.
  • the first inclination angle ?1 and the second inclination angle ?2 are different in magnitude.
  • first inclination angle ⁇ 1 and the second inclination angle ⁇ 2 can also be selected to be the same.
  • the first trench 241 and the second trench 242 are connected to form an integral trench 240, and the trench 240 is located in the first region.
  • the opening areas of the first trench 241 and the second trench 242 are the same or different in size.
  • FIG. 7 is a schematic structural diagram of a single groove 20 in an embodiment. As shown in FIG. 7 , the projection of the vertex H on the horizontal plane is located on the first center line L2 of the second area S2 at the bottom of the groove.
  • the curved surface of the protruding structure 210 is composed of countless curves starting from the vertex H to the edge of the protruding structure 210 .
  • the radius of curvature of each curve in the countless curves is a fixed value.
  • the point where the edge is closest to the center C of the crystal carrier is the first edge point O1
  • the point where the edge of the protruding structure 210 is farthest from the center C of the wafer carrier is the second edge point O2, wherein the radius of curvature of the countless curves starts from all
  • the first edge point gradually becomes smaller along the edge of the protruding structure 210 to the second edge point.
  • Five curves k1-k5 are shown in FIG. 5.
  • the curvature radii of the five curves k1-k5 are r1, r2, r3, r4 and r5, respectively, protruding from the first edge point O1 near the center C of the wafer carrier. From the edge of the structure 210 to the second edge point O2, it gradually becomes smaller, that is, r5 ⁇ r4 ⁇ r3 ⁇ r2 ⁇ r1.
  • the height of the part of the protruding structure away from the center C of the wafer carrier is appropriately increased,
  • the wafer subjected to the centrifugal force of the rotation of the wafer carrier plate always maintains a reasonable gap between the wafer and the groove 20 of the wafer carrier plate 10, thereby reducing the influence of centrifugal force on the growth of the wafer.
  • the structure of the bottom of the groove is further adjusted, so that the structure of the groove 20 can better adapt to the growth of the wafer and offset the influence of centrifugal force during the growth process.
  • the distribution positions of the protruding structure 210 and the uncovered area 230 at the bottom of the groove are subject to practical application requirements, and can be designed with reference to factors such as the position of the radiant heat source, airflow direction, and airflow size.
  • the groove bottom of the wafer carrier of the present invention is divided into a first area close to the center of the wafer carrier and a second area away from the center of the wafer carrier by a first dividing line passing through the center of the groove.
  • the bottom of the groove includes a bottom surface of the groove and a protruding structure formed on the bottom surface of the groove, the surface of the protruding structure is a curved surface, the apex of the curved surface is located in the second area of the bottom of the groove, and the bottom of the groove has a surface that is not protruded.
  • the problem of the large bottom gap makes the wafer under the centrifugal force of the wafer carrier plate always maintain a reasonable gap between the wafer carrier plate and the wafer carrier plate, which reduces the influence of centrifugal force on the growth of the wafer, ensures stable temperature and airflow, and makes the temperature field distribution more uniform. , thereby improving the quality of the epitaxial layer wafer, improving the wavelength uniformity of the light-emitting epitaxial wafer, and improving the yield, and has a wide application prospect in the field of semiconductor manufacturing equipment design and manufacture.
  • the material of the wafer carrier can be graphite.
  • the present application does not specifically limit the material of the wafer carrier, and those skilled in the art know that other materials can be selected according to design requirements.
  • the above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application.
  • the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

本发明提供一种晶片承载盘，晶片承载盘的凹槽底部以经过凹槽中心的第一分界线将凹槽底部分为靠近所述晶片承载盘中心的第一区域和远离晶片承载盘中心的第二区域，凹槽底部包括凹槽底面以及形成在凹槽底面上的凸出结构，凸出结构的表面为曲面，曲面顶点位于凹槽底部的所述第二区域，位于第二区域的凸出结构的平均高度高于位于第一区域的所述凸出结构的平均高度。晶片承载盘凹槽底部的设计结构能较好匹配III-V族氮化物晶片有源区外延过程中的翘曲，使温场分布更均匀，从而提升提高发光外延片的波长均匀性。

Description

一种晶片承载盘 技术领域
本发明涉及一种半导体制造设备，涉及一种用于MOCVD的晶片承载盘。
背景技术
石墨盘是MOCVD设备中非常重要的配件，目前常用的石墨盘都是圆形，在石墨盘上分布有一些凹槽，这些凹槽用于放置衬底，随后在衬底上生长外延层。石墨盘是由高纯石墨制成，并在表面镀有SiC涂层。外延生长过程，在MOCVD的反应腔中，通过加热丝对盛放有衬底的石墨盘进行辐射加热。
图1所示为现有的晶片承载盘的示意图，晶片承载盘10包括3个凹槽20，其中1个凹槽20中放置了晶片30。图2所示为图1中A-A’截面处的结构示意图，凹槽的底部一般为平、凸、凹三种。针对硅上氮化镓工艺，需要采用应力工程技术生长缓冲层，在生长有源区时，外延片呈凸型翘曲。所以对于硅上GaN的发光结构，一般采用凸型凹槽来匹配外延片的凸。但是使用凸型凹槽会存在的问题为:晶片30至于凹槽20中时，由于晶片30生长过程中，晶片承载盘10高速旋转，凹槽20内的晶片30受离心力的影响，会把晶片30向远离晶片承载盘中心C的方向移动，而凹槽底部的凸出结构，会使得晶片30其远离晶片承载盘10中心C的部分与晶片承载盘10底部的间隙相对较大，即导致晶片30与凹槽20的底部的距离差异较大，造成晶片30生长过程中受热不均匀现象非常明显，对晶片30的质量有影 响，并且III-V族氮化物发光晶片30的波长对温度较为敏感，容易造成晶片30内波长差异较大，会对后续的芯片制程以及分选工作造成时间和成本的大幅增加及良率的降低。
基于以上所述，提供一种可以有效提高晶片外延受热均匀性的用于MOCVD设备中的晶片承载盘结构实属必要。
发明内容
本发明的目的在于提供一种调整凹槽的底部的形状以有效提高晶片外延受热均匀性的晶片承载盘，改善III-V族氮化物外延生长的品质与外延、以及光电外延片的片内波长均匀性。
本发明提供一种晶片承载盘，包括至少一个凹槽，所述凹槽包括：
凹槽底部，所述凹槽底部以经过所述凹槽中心的第一分界线将所述凹槽底部分为靠近所述晶片承载盘中心的第一区域和远离所述晶片承载盘中心的第二区域，所述凹槽底部包括：
凹槽底面；
凸出结构，形成在所述凹槽底面上，所述凸出结构的边缘位于所述凹槽底面，所述凸出结构的边缘与所述凹槽底面的边缘非重合，所述凹槽底部具有未被所述凸出结构覆盖的未覆盖区域；
其中，位于所述第二区域的所述凸出结构的平均高度高于位于所述第一区域的所述凸出结构的平均高度。
作为可选的技术方案，所述第一分界线为直线，所述第一分界线与经过所述晶体承载盘中心和所述凹槽中心的第一中心线相互垂直；或者，所 述第一分界线为以所述晶体承载盘中心为圆心且以所述晶体承载盘中心至所述凹槽中心的距离为半径的圆弧。
作为可选的技术方案，所述凸出结构的表面为曲面，所述曲面具有一个顶点，所述顶点在水平面上的投影位于所述凹槽底部的所述第二区域。
作为可选的技术方案，所述顶点在水平面上的投影位于第一中心线上。
作为可选的技术方案，所述未覆盖区域位于所述第一区域的面积大于所述未覆盖区域位于所述第二区域的面积。
作为可选的技术方案，所述未覆盖区域包括第一未覆盖区域和第二未覆盖区域，所述第一未覆盖区域和所述第二未覆盖区域分布于所述第一中心线的两侧，所述第一未覆盖区域和所述第二未覆盖区域基于所述第一中心线呈对称分布或不对称分布。
作为可选的技术方案，所述第一未覆盖区设置第一沟槽，所述第一沟槽靠近所述凹槽中心的侧面与水平面的夹角为第一倾斜角θ1，其中，0≤θ1≤90°；所述第二未覆盖区设置第二沟槽，所述第二沟槽靠近所述凹槽中心的侧面与水平面的夹角为第二倾斜角θ2，其中，0≤θ2≤90°。
作为可选的技术方案，所述第一倾斜角θ1与第二倾斜角θ2大小相同或者相异。
作为可选的技术方案，所述第一沟槽与所述第二沟槽的开口面积大小相同或者相异。
作为可选的技术方案，所述凸出结构的曲面为无数从所述顶点出发至所述凸出结构的边缘的曲线组成，所述无数曲线中每一条曲线的曲率半径均为固定值；所述凸出结构的边缘最接近所述晶片承载盘中心的点为第一 边缘点，所述凸出结构的边缘最远离所述晶片承载盘中心的点为第二边缘点；其中，所述无数曲线的曲率半径从所述第一边缘点沿着所述凸出结构边缘至所述第二边缘点逐渐变小。
与现有技术相比，本发明具有以下技术效果：
本发明的晶片承载盘凹槽底部以经过凹槽中心的第一分界线将凹槽底部分为靠近所述晶片承载盘中心的第一区域和远离晶片承载盘中心的第二区域，凹槽底部包括凹槽底面以及形成在凹槽底面上的凸出结构，凸出结构的表面为曲面，曲面顶点位于凹槽底部的所述第二区域，凹槽底部具有未被凸出结构覆盖的未覆盖区域；未覆盖区域具有向下的沟槽，晶片承载盘凹槽底部的设计结构能较好匹配III-V族氮化物晶片因为离心力以及凸出结构而导致的晶片与凹槽底部间隙较大的问题，使受晶片承载盘转动离心力作用的晶片始终保持与晶片承载盘间存在合理的间隙，降低了离心力对晶片生长的影响，保证温度与气流稳定，使温场分布更均匀，从而提升外延层晶片质量，提高发光外延片的波长均匀性，提高良率，在半导体制造设备设计制造领域具有广泛的应用前景。
为使本申请的上述和其他目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合附图，作详细说明如下。
附图说明
图1所示为现有的晶片承载盘的示意图；
图2所示为图1中A-A’截面处的结构示意图；
图3所示为本申请一实施例中的晶片承载盘的俯视示意图；
图4a所示为本发明实施例中第一分界线在凹槽底部的位置示意图；
图4b所示为本发明另一实施例第一分界线在凹槽底部的位置示意图；
图5a至图5d所示为本发明不同实施例的凹槽中凸出结构的俯视示意图；
图6a所示为本发明另一实施例凹槽的俯视示意图；
图6b所示为本发明又一实施例凹槽的俯视示意图；
图6c所示为图6a中凹槽于AA’处的截面示意图；
图7所示为本发明一实施例中单个凹槽的结构示意图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
晶片承载盘10                  晶片承载盘中心C
凹槽20                        凹槽中心O
第一边缘点O1                  第二边缘点O2
凸出结构210                   第一区域S1
曲线k1、k2、k3、k4以及k5      第二区域S2
曲率半径r1、r2、r3、r4以及r5  第一中心线L2
凸出结构顶点H                 第一分界线L1
第一未覆盖区域231             第二未覆盖区域232
第一调整区域241               第二调整区域242
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整的描述。
图3所示为本申请一实施例中的晶片承载盘10的俯视示意图，图4所示为本申请一实施例中的晶片承载盘10的立体结构示意图。如图3以及图4所示，晶片承载盘10包括至少一个凹槽20，图3中凹槽20的数目为3个，围绕着晶片承载盘10的中心C有序排列，然而本申请对晶片承载盘20的凹槽个数、大小及分布都不作限制。本领域人员应当知晓，可以根据晶片30的大小，灵活设置凹槽20的数量、大小和排布。
其中，位于所述第二区域的所述凸出结构的平均高度高于位于所述第一区域的所述凸出结构的平均高度。
凹槽20包括凹槽底部和凹槽侧部，凹槽底部以第一分界线L1为界将凹槽底部分为靠近晶片承载盘中心C的第一区域S1和远离晶片承载盘中心C的第二区域S2，其中，第一分界线L1经过凹槽中心O。凹槽底部包括凹槽底面以及形成在凹槽底面210上的凸出结构210，凸出结构210的边缘位于凹槽底面，凸出结构210的边缘与凹槽底面的边缘非重合，所述凹槽底部具有未被凸出结构210覆盖的未覆盖区域230。位于第二区域S2的凸出结构210的平均高度高于位于第一区域S1的凸出结构210的平均高度。由于晶片承载盘10转动离心力的作用，会把晶片30向远离晶片承载盘中心C的方向移动，而凹槽底部的凸出结构，会使得晶片30其远离晶片承载盘10中心C的部分与晶片承载盘10底部的间隙相对较大，即导致晶片与凹槽20的底部的距离差异较大，本发明通过调整凹槽底部凸出结构210的分布位置以及高度分布，使得凸出结构远离晶片承载盘中心C的部分的高度适当增大，凸出结构靠近晶片承载 盘中心C的部分的高度适当减小，使受晶片承载盘转动离心力作用的晶片30始终保持与晶片承载盘间10的凹槽20存在合理的间隙，降低了离心力对晶片生长的影响，保证温度与气流稳定，使温场分布更均匀，从而提升外延层晶片质量。
图4a以及图4b为本发明实施例中第一分界线在凹槽20底部位置示意图，如图4a所示，第一分界线L1为直线，第一分界线L1与经过晶体承载盘中心C和凹槽中心O的第一中心线L2相互垂直。第一区域S1和第二区域S2面积相等，其中第一区域S1靠近晶体承载盘中心C，第二区域S2远离晶体承载盘中心C。在另一实施例中，如4b所示，第一分界线L1为以晶体承载盘中心C为圆心且以晶体承载盘中心C至凹槽中心O的距离为半径的圆弧，圆弧型的第一分界线L1将凹槽底部分成两个面积不相等的部分，第一区域S1和第二区域S2面积相等，其中第一区域S1靠近晶体承载盘中心C，第二区域S2远离晶体承载盘中心C。
如图3所示，凸出结构210的边缘与凹槽20的侧部不相接，凸出结构210的表面为曲面，曲面具有一个顶点H，图3俯视图中凹槽20内的围绕着顶点H周围的曲线，可视为等高线，从图3中等高线位置分布可以看出凸出结构210的在第二区域S2的平均高度高于凸出结构210在第一区域S1的平均高度。顶点H在水平面上的投影位于凹槽底部的第二区域S2的第一中心线L2上。顶点H在水平面上的投影至凹槽中心O的距离d，凹槽中心O至凹槽底面边缘在第一中心线L2上的距离R，其中0≤d≤1/6R。
具体的，如图3所示，未覆盖区域230位于第一区域S1的面积大于未覆盖区域230位于第二区域S2的面积。未覆盖区域230包括第一未覆盖区域231 和第二未覆盖区域232，第一未覆盖区域231和第二未覆盖区域232分布于第一中心线L2的两侧，第一未覆盖区域231和第二未覆盖区域232可以相互连成一个整体，第一未覆盖区域231和第二未覆盖区域232也可以相互独立，第一未覆盖区域231和第二未覆盖区域232基于第一中心线L2呈对称分布或不对称分布。当第一未覆盖区域231和第二未覆盖区域232相互连成一个整体是，未覆盖区域230在第一中心线L2上的宽度d1，凹槽中心O至凹槽20底面边缘在第一中心线L2上的距离R，其中0≤d1≤1/6R。
图5a至图5d为本发明不同实施例中凹槽20的俯视结构图，如图5a至图5b所示，第一未覆盖区域231和第二未覆盖区域232相互独立，其中，图5a中的凹槽20第一未覆盖区域231和第二未覆盖区域232基于第一中心线L2呈对称分布，图5b中的凹槽20第一未覆盖区域231和第二未覆盖区域232基于第一中心线L2呈不对称分布。如图5c至图5d所示,第一未覆盖区域231和第二未覆盖区域232相互连接成一个整体，其中，图5c中的凹槽20第一未覆盖区域231和第二未覆盖区域232基于第一中心线L2呈对称分布，图5d中的凹槽20第一未覆盖区域231和第二未覆盖区域232基于第一中心线L2呈不对称分布。
图6a以及图6b为本发明不同实施例的凹槽20的俯视示意图，图6c为图6a中的凹槽20于AA’处的剖面结构示意图。其中图6a中的凹槽20与图5c中的凹槽20结构类似，区别在于：第一未覆盖区231设置第一沟槽241，第一沟槽靠近凹槽中心O的侧面与水平面的夹角为第一倾斜角θ1，其中，0≤θ1≤90°；第二未覆盖区231设置第二沟槽242，第二沟槽242靠近凹槽中心O的侧面与水平面的夹角为第二倾斜角θ2，其中，0≤θ2≤90°。如图6a以及 图6c所示，第一倾斜角θ1与第二倾斜角θ2大小相异。在实际应用中，第一倾斜角θ1与第二倾斜角θ2大小也可选择相同。在另一实施例中，如图6b所示，第一沟槽241和第二沟槽242连成一个整体的沟槽240，沟槽240位于第一区域。在实际应用中，第一沟槽241与第二沟槽242的开口面积大小相同或者相异。
图7为一实施例中单个凹槽20的结构示意图，如图7所示，顶点H在水平面上的投影位于凹槽底部的第二区域S2的第一中心线L2上。所述凸出结构210的曲面为无数从所述顶点H出发至所述凸出结构210的边缘的曲线组成，所述无数曲线中每一条曲线的曲率半径均为固定值，凸出结构210的边缘最接近晶体承载盘中心C的点为第一边缘点O1，凸出结构210的边缘最远离晶片承载盘中心C的点为第二边缘点O2，其中，所述无数曲线的曲率半径从所述第一边缘点沿着所述凸出结构210边缘至所述第二边缘点逐渐变小。图5中示出了k1-k5五条曲线，k1-k5五条曲线的曲率半径分别为r1、r2、r3、r4以及r5，分别从靠近晶片承载盘中心C的第一边缘点O1沿着凸出结构210边缘至第二边缘点O2逐渐变小，即r5＜r4＜r3＜r2＜r1。
本发明上述实施例，通过调整凸出结构210的顶点位置、凸出结构210在凹槽底部的位置分布、高度分布，从而使得凸出结构远离晶片承载盘中心C的部分的高度适当增大，使受晶片承载盘转动离心力作用的晶片始终保持与晶片承载盘间10的凹槽20存在合理的间隙，降低了离心力对晶片生长的影响。通过在凹槽底部的未覆盖区设置沟槽结构，进一步调整凹槽底部的结构，使得凹槽20的结构更好的适应晶片的生长，抵消生长过程中，离心力的影响。
另外凸出结构210和未覆盖区域230的在凹槽底部的分布位置以实际应用的需求为准，可以参考辐射热源的位置，气流方向以及气流大小等因素进行设计。
综上所述，本发明的晶片承载盘凹槽底部以经过凹槽中心的第一分界线将凹槽底部分为靠近所述晶片承载盘中心的第一区域和远离晶片承载盘中心的第二区域，凹槽底部包括凹槽底面以及形成在凹槽底面上的凸出结构，凸出结构的表面为曲面，曲面顶点位于凹槽底部的所述第二区域，凹槽底部具有未被凸出结构覆盖的未覆盖区域；未覆盖区域具有向下的沟槽，晶片承载盘凹槽底部的设计结构能较好匹配III-V族氮化物晶片因为离心力以及凸出结构而导致的晶片与凹槽底部间隙较大的问题，使受晶片承载盘转动离心力作用的晶片始终保持与晶片承载盘间存在合理的间隙，降低了离心力对晶片生长的影响，保证温度与气流稳定，使温场分布更均匀，从而提升外延层晶片质量，提高发光外延片的波长均匀性，提高良率，在半导体制造设备设计制造领域具有广泛的应用前景。
本申请中，晶片承载盘的材料可为石墨。然而本申请对晶片承载盘的材料不作特别限制，本领域人员知晓，可根据设计需求选择其他的材料。以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种晶片承载盘，包括至少一个凹槽，其特征在于，所述凹槽包括：
    凹槽底部，所述凹槽底部以经过所述凹槽中心的第一分界线将所述凹槽底部分为靠近所述晶片承载盘中心的第一区域和远离所述晶片承载盘中心的第二区域，所述凹槽底部包括：
    凹槽底面；
    凸出结构，形成在所述凹槽底面上，所述凸出结构的边缘位于所述凹槽底面，所述凸出结构的边缘与所述凹槽底面的边缘非重合，所述凹槽底部具有未被所述凸出结构覆盖的未覆盖区域；
    其中，位于所述第二区域的所述凸出结构的平均高度高于位于所述第一区域的所述凸出结构的平均高度。
  2. 根据权利要求1所示的晶片承载盘，其特征在于：所述第一分界线为直线，所述第一分界线与经过所述晶体承载盘中心和所述凹槽中心的第一中心线相互垂直；或者，所述第一分界线为以所述晶体承载盘中心为圆心且以所述晶体承载盘中心至所述凹槽中心的距离为半径的圆弧。
  3. 根据权利要求1所示的晶片承载盘，其特征在于：所述凸出结构的表面为曲面，所述曲面具有一个顶点，所述顶点在水平面上的投影位于所述凹槽底部的所述第二区域。
  4. 根据权利要求3所示的晶片承载盘，其特征在于：所述顶点在水平面上的投影位于第一中心线上。
  5. 根据权利要求1所示的晶片承载盘，其特征在于：所述未覆盖区域位于所述第一区域的面积大于所述未覆盖区域位于所述第二区域的面积。
  6. 根据权利要求1所示的晶片承载盘，其特征在于：所述未覆盖区域包括第一未覆盖区域和第二未覆盖区域，所述第一未覆盖区域和所述第二未覆盖区域分布于所述第一中心线的两侧，所述第一未覆盖区域和所述第二未覆盖区域基于所述第一中心线呈对称分布或不对称分布。
  7. 根据权利要求6所示的晶片承载盘，其特征在于：所述第一未覆盖区设置第一沟槽，所述第一沟槽靠近所述凹槽中心的侧面与水平面的夹角为第一倾斜角θ1，其中，0≤θ1≤90°；所述第二未覆盖区设置第二沟槽，所述第二沟槽靠近所述凹槽中心的侧面与水平面的夹角为第二倾斜角θ2，其中，0≤θ2≤90°。
  8. 根据权利要求7所示的晶片承载盘，其特征在于：所述第一倾斜角θ1与第二倾斜角θ2大小相同或者相异。
  9. 根据权利要求7所示的晶片承载盘，其特征在于：所述第一沟槽与所述第二沟槽的开口面积大小相同或者相异。
  10. 根据权利要求4所示的晶片承载盘，其特征在于：所述凸出结构的曲面为无数从所述顶点出发至所述凸出结构的边缘的曲线组成，所述无数曲线中每一条曲线的曲率半径均为固定值；所述凸出结构的边缘最接近所述晶片承载盘中心的点为第一边缘点，所述凸出结构的边缘最远离所述晶片承载盘中心的点为第二边缘点；其中，所述无数曲线的曲率半径从所述第一边缘点沿着所述凸出结构边缘至所述第二边缘点逐渐变小。
PCT/CN2020/113762 2020-09-07 2020-09-07 一种晶片承载盘 WO2022047784A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202080103949.8A CN116113730A (zh) 2020-09-07 2020-09-07 一种晶片承载盘
PCT/CN2020/113762 WO2022047784A1 (zh) 2020-09-07 2020-09-07 一种晶片承载盘
US18/073,862 US20230105081A1 (en) 2020-09-07 2022-12-02 Wafer susceptor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/113762 WO2022047784A1 (zh) 2020-09-07 2020-09-07 一种晶片承载盘

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/073,862 Continuation US20230105081A1 (en) 2020-09-07 2022-12-02 Wafer susceptor

Publications (1)

Publication Number Publication Date
WO2022047784A1 true WO2022047784A1 (zh) 2022-03-10

Family

ID=80492406

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/113762 WO2022047784A1 (zh) 2020-09-07 2020-09-07 一种晶片承载盘

Country Status (3)

Country Link
US (1) US20230105081A1 (zh)
CN (1) CN116113730A (zh)
WO (1) WO2022047784A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114836826A (zh) * 2022-04-15 2022-08-02 江西兆驰半导体有限公司 一种石墨基座

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140166A (zh) * 2009-12-02 2015-12-09 维易科精密仪器国际贸易(上海)有限公司 用于提高衬底载体的性能的方法
CN105296962A (zh) * 2014-05-30 2016-02-03 东京毅力科创株式会社 成膜装置
JP2017092229A (ja) * 2015-11-10 2017-05-25 信越ポリマー株式会社 基板収納容器
CN109161873A (zh) * 2018-09-29 2019-01-08 华灿光电（浙江）有限公司 一种石墨基座
WO2020220189A1 (zh) * 2019-04-29 2020-11-05 苏州晶湛半导体有限公司 一种晶片承载盘

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140166A (zh) * 2009-12-02 2015-12-09 维易科精密仪器国际贸易(上海)有限公司 用于提高衬底载体的性能的方法
CN105296962A (zh) * 2014-05-30 2016-02-03 东京毅力科创株式会社 成膜装置
JP2017092229A (ja) * 2015-11-10 2017-05-25 信越ポリマー株式会社 基板収納容器
CN109161873A (zh) * 2018-09-29 2019-01-08 华灿光电（浙江）有限公司 一种石墨基座
WO2020220189A1 (zh) * 2019-04-29 2020-11-05 苏州晶湛半导体有限公司 一种晶片承载盘

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114836826A (zh) * 2022-04-15 2022-08-02 江西兆驰半导体有限公司 一种石墨基座
CN114836826B (zh) * 2022-04-15 2023-08-18 江西兆驰半导体有限公司 一种石墨基座

Also Published As

Publication number Publication date
CN116113730A (zh) 2023-05-12
US20230105081A1 (en) 2023-04-06

Similar Documents

Publication Publication Date Title
US11427928B2 (en) Lower side wall for epitaxtail growth apparatus
TWI541928B (zh) 晶圓載具
CN107326342A (zh) 用于mocvd设备中的石墨盘
CN207227547U (zh) 用于mocvd设备中的石墨盘
WO2022047784A1 (zh) 一种晶片承载盘
TWM539150U (zh) 晶圓承載盤
TWI653368B (zh) 用於保持半導體晶圓的基座、用於在半導體晶圓的正面上沉積磊晶層的方法、以及具有磊晶層的半導體晶圓
TWI711114B (zh) 晶座、磊晶成長裝置、磊晶矽晶圓的製造方法以及磊晶矽晶圓
KR20180045807A (ko) 기상 성장 장치, 환형 홀더 및 기상 성장 방법
TWI688119B (zh) 圖案化磊晶基板及半導體結構
CN113622020A (zh) 提高外延片均匀度的外延托盘及其制备方法
US20220005728A1 (en) Wafer susceptor and chemical vapor deposition apparatus
WO2022047785A1 (zh) 一种晶片承载盘
JP7183628B2 (ja) トレイ、半導体基板の製造方法、半導体装置の製造方法および半導体製造装置
CN211848131U (zh) 一种石墨盘
CN110079790A (zh) 石墨基座
CN113279056B (zh) 石墨基板及其制造方法
CN107658211A (zh) 一种半导体晶片的制作方法
KR100612625B1 (ko) 반도체 웨이퍼 실장용 서셉터
JP2022111715A (ja) 基板保持部材
KR20120038287A (ko) 서셉터
KR102209032B1 (ko) 웨이퍼 캐리어
US20220349057A1 (en) Semiconductor wafer carrier structure and metal-organic chemical vapor deposition equipment
US11495709B2 (en) Patterned epitaxial substrate and semiconductor structure
US20230253225A1 (en) Graphite disc

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20952028

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20952028

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20952028

Country of ref document: EP

Kind code of ref document: A1