WO2022041972A1 - 一种芯片的设计方法、设计装置、计算机设备及存储介质 - Google Patents

一种芯片的设计方法、设计装置、计算机设备及存储介质 Download PDF

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Publication number
WO2022041972A1
WO2022041972A1 PCT/CN2021/101364 CN2021101364W WO2022041972A1 WO 2022041972 A1 WO2022041972 A1 WO 2022041972A1 CN 2021101364 W CN2021101364 W CN 2021101364W WO 2022041972 A1 WO2022041972 A1 WO 2022041972A1
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Prior art keywords
power supply
power
supply network
chip
circuit module
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PCT/CN2021/101364
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English (en)
French (fr)
Inventor
林峰
吴增泉
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长鑫存储技术有限公司
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Priority to EP21819313.4A priority Critical patent/EP3989099A4/en
Priority to US17/398,220 priority patent/US20220067264A1/en
Publication of WO2022041972A1 publication Critical patent/WO2022041972A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/18—Chip packaging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Definitions

  • the embodiments of the present application relate to the technical field of chip design, and in particular, to a chip design method, a design device, a computer device, and a storage medium.
  • the present application provides a chip design method, design device, computer equipment and storage medium, so as to shorten the chip design and development cycle and reduce the design cost.
  • an embodiment of the present application provides a method for designing a chip, including: creating a power bus network according to a pad position and a chip plane layout; determining the position of a power port of a circuit module in the power bus network; The power supply bus network creates a power supply network model; according to the power supply network model and the position of the power supply port of the circuit module in the power supply bus network, a netlist embedded with a power supply network is generated; according to the embedded power supply network The netlist of the power supply network is used for circuit simulation.
  • an embodiment of the present application further provides a chip design device, the device includes: a power bus network generation module, configured to create a power bus network according to the pad position and the chip layout diagram; a circuit module position determination module, for determining the position of the power port of the circuit module in the power bus network; a power supply network model generation module for creating a power supply network model according to the power bus network; generating a netlist embedded with the power supply network a module for generating a netlist with an embedded power supply network according to the power supply network model and the position of the power port of the circuit module in the power bus network; a simulation module for generating a netlist with an embedded power supply The netlist of the network is used for circuit simulation.
  • an embodiment of the present application further provides a computer device, including a memory, a processor, and a computer program stored on the memory and running on the processor, where the processor executes the computer program When implementing any chip design method described in the first aspect.
  • an embodiment of the present application further provides a storage medium containing computer-executable instructions, where the computer-executable instructions, when executed by a computer processor, are used to execute any chip design method described in the first aspect .
  • the power bus network is created according to the pad position and the chip plane layout, and the position of the power port of the circuit module in the power bus network is determined, according to
  • the power bus network creates a power supply network model, generates a netlist embedded with the power supply network according to the power supply network model and the position of the power port of the circuit module in the power bus network, and performs circuit simulation according to the netlist embedded with the power supply network,
  • the parasitic parameters in the power bus network are integrated into the circuit netlist for simulation, and the power integrity analysis of the chip is realized to verify whether the power supply network design of the chip meets the requirements.
  • the analysis can be completed in the layout design or in the layout design. After analysis, the difficulty of power supply network design is reduced, thereby shortening the development cycle of chip design and reducing design cost.
  • FIG. 1 is a schematic flowchart of a method for designing a chip according to an embodiment of the present application
  • FIG. 2 is a schematic flowchart of another chip design method provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a power bus network according to an embodiment of the present application.
  • Fig. 4 is the enlarged structural representation of Fig. 3 at A;
  • FIG. 5 is a schematic diagram of an integrated structure of a circuit module and a power bus network provided by an embodiment of the present application;
  • FIG. 6 is a schematic structural diagram of a power supply network model provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a power supply network unit according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an integrated structure of a circuit module and a power supply network model provided by an embodiment of the present application;
  • FIG. 9 is a schematic flowchart of creating a power supply network model according to an embodiment of the present application.
  • FIG. 10 is a schematic flowchart of another chip design method provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a storage system according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a device for designing a chip according to an embodiment of the application.
  • FIG. 13 is a schematic structural diagram of a power supply network model generation module provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a power supply network model generation module according to an embodiment of the present application.
  • 15 is a schematic structural diagram of a netlist generation module embedded with a power supply network according to an embodiment of the present application
  • FIG. 16 is a schematic structural diagram of a computer device according to an embodiment of the present application.
  • FIG. 1 is a schematic flowchart of a chip design method provided by an embodiment of the present application. As shown in FIG. 1 , the chip design method provided by an embodiment of the present application includes:
  • Step 1 Create a power bus network based on the pad location and the chip floor plan.
  • FIG. 2 is a schematic flowchart of another chip design method provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a power bus network provided by an embodiment of the present application, as shown in FIGS. 2 and 3 .
  • First perform layout planning for the chip complete the determination of the length and width of the chip, complete the arrangement of the pads, complete the power supply planning, create the pads, and the power bus plan (Createpadslog&powerbusplan).
  • the arrangement of the pads also considers multiple factors such as the convenience of the chip being applied to the package substrate in the future, and the ease of implementation inside the chip.
  • FIG. 3 the power bus network includes a pad 10 and a power bus 11 , and the pad 10 includes a power pad 101 and a signal pad 102 .
  • the power pad 101 It is used to provide corresponding power for each node of the power bus 11
  • the signal pad 102 is used to provide signals
  • the power bus 11 is connected to the power pad 101 .
  • the power bus 11 may be composed of multiple metal layers.
  • FIG. 4 is an enlarged schematic diagram of the structure at A in FIG. 3 . As shown in FIG.
  • the power bus 11 (refer to FIG. 3 ) is composed of four metal layers M1 , M2 , M3 and M4 , so that Power supplies of different voltages can be delivered through different metal layers. It should be noted that, in other embodiments, the power bus can also be composed of other metal layers, which can be selected according to needs.
  • Step 2 Determine the position of the power port of the circuit module in the power bus network.
  • FIG. 5 is a schematic diagram of the integrated structure of a circuit module and a power bus network provided by an embodiment of the application.
  • the position of the circuit module 12 in the power bus network is determined according to the chip layout diagram, and the position of the circuit module 12 in the power bus network is determined.
  • Each power port of each circuit module 12 is determined, and the position of the power port in the power bus network is determined, so as to prepare for the subsequent determination of the connection path between each power port of each circuit module 12 and the power pad 101 .
  • FIG. 5 is a schematic diagram of the integrated structure of a circuit module and a power bus network provided by an embodiment of the application.
  • the position of the circuit module 12 in the power bus network is determined according to the chip layout diagram, and the position of the circuit module 12 in the power bus network is determined.
  • Each power port of each circuit module 12 is determined, and the position of the power port in the power bus network is determined, so as to prepare for the subsequent determination of the connection path between each power port of each circuit module 12 and the power pad 101 .
  • each circuit module 12 includes two power supply ports, which are respectively used to connect to provide high power
  • the flat power supply pad 101 and the power supply pad 101 providing a low level are determined according to the chip layout diagram to determine the position of the power supply module 1, power supply module 2, power supply module 3 and power supply module 4 in the power bus network, and find out each circuit.
  • Each power port of the module 12 determines the position of the power port in the power bus network, and further determines the connection path between each power port of each circuit module 12 and the power pad 101 .
  • Step 3 Create a power supply network model according to the power bus network.
  • FIG. 6 is a schematic structural diagram of a power supply network model provided by an embodiment of the application
  • FIG. 7 is a schematic structural diagram of a power supply network unit provided by an embodiment of the application, as shown in FIGS. 6 and 7 .
  • the power supply network model includes a plurality of pads 20, and an array formed by a plurality of power supply network units 23, the pads include power supply pads 201 and signal pads 202, and the power supply network units 23 are connected by power lines 21 and/or Or the power bridge wires 22 are connected to each other.
  • Each power supply network unit 23 includes a plurality of power lines 21 and a plurality of power bridge lines 22 , wherein the power lines 21 and the power bridge lines 22 include at least one of a resistor 231 and a capacitor 232 .
  • the value of the parasitic resistance and/or the value of the parasitic capacitance on the power line 21 and the power bridge connection 22 may be calculated and added to the resistance 231 and/or the value of the parasitic resistance and/or the value of the parasitic capacitance of the power supply network unit 23
  • capacitor 232 the power supply network model is made with parasitic parameters on the power bus network.
  • the method of manually establishing the power supply network model in this embodiment is simple and effective, and it is easy to track the optimization and modification of the power supply network.
  • Step 4 Generate a netlist embedded with the power supply network according to the power supply network model and the position of the power port of the circuit module in the power bus network.
  • FIG. 8 is a schematic diagram of an integrated structure of a circuit module and a power supply network model provided by an embodiment of the application.
  • the power bus network is compared with the power supply network model.
  • the position of the power port 12 in the power bus network determines the position of the power port of the circuit module 12 in the power supply network model, and is determined in the power supply network according to the connection path between the power port of the circuit module 12 and the power pad in the power bus network.
  • connection path between the power port and the pad of the circuit module 12 in the model, the power supply network unit 23 located on the connection path is integrated with the circuit netlist to generate a netlist embedded with the power supply network, so that the embedded power supply network
  • the netlist contains parasitics on the power bus net. 8 only shows a schematic diagram of the integrated structure of the circuit module 2 and the power supply network model.
  • PDN2-1 represents the power supply network on the connection path between the power port of the circuit module 2 and the power supply pad 101.
  • PDN2-2, PDN1-1, PDN1-2, PDN3-1, PDN3-2, PDN4-1, PDN4-2 represent the space between each power port of each circuit module 12 and the power pad 101 A collection of power supply network elements on the corresponding path.
  • Step 5 Perform circuit simulation according to the netlist embedded with the power supply network.
  • circuit simulation is performed on the netlist embedded with the power supply network with parasitic parameters on the power bus network, so as to verify in advance whether the power supply network design of the chip meets the requirements, reduce the difficulty of subsequent design, thereby shorten the development cycle of chip design, reduce design cost.
  • circuit simulation can be performed before the layout design is completed, circuit simulation can be performed after the complete layout design, or simulation can be performed after part of the layout design is completed, and the entire design process can be performed. Multiple simulations are performed in the field, and those skilled in the art can choose by themselves.
  • a power bus network is created according to the pad position and the chip plane layout, the position of the power port of the circuit module in the power bus network is determined, and a power supply network model is created according to the power bus network, According to the power supply network model and the position of the power port of the circuit module in the power bus network, a netlist embedded with the power supply network is generated, and the circuit simulation is performed according to the netlist embedded with the power supply network, and the parasitic parameters in the power bus network are integrated Enter the circuit netlist for simulation to realize the power integrity analysis of the chip to verify whether the power supply network design of the chip meets the requirements, which reduces the difficulty of power supply network design, thereby shortening the development cycle of chip design and reducing design costs.
  • the circuit module is a key sequential circuit module.
  • the key sequential circuit module is a circuit module that is more sensitive to power supply. Adding it to the circuit netlist for simulation, ignoring circuit modules that are not sensitive to power supply, and ensuring that the voltage and current of the power supply ports of key sequential circuit modules meet the requirements, it helps to reduce the amount of calculation and improve the simulation speed.
  • the critical timing circuit module includes circuit modules on any one or more timing paths of the chip's read timing path, write timing path, array timing path, and command timing path, and the chip includes a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the circuit modules on the read timing path, write timing path, array timing path, and command timing path of the chip are usually more important and more sensitive to power supply. Therefore, the read timing path, write timing path, array timing path, command timing path
  • the circuit module on the path is set as the key sequence circuit module, and the parasitic parameters of the power bus 11 on the connection path between the power port of the key sequence circuit module and the power pad 101 are added to the circuit netlist for simulation to realize the key sequence circuit module.
  • the power integrity analysis of the key sequence circuit module ensures that the voltage and current of the power port of the key sequence circuit module meet the requirements, which reduces the design difficulty, shortens the development cycle of chip design, and reduces the design cost.
  • creating a power supply network model according to the power bus network includes: creating a layout of the power bus network according to the power bus network; extracting parasitic parameters from the layout of the power bus network; calculating the value of the parasitic parameter; creating according to the value of the parasitic parameter Power supply network model.
  • FIG. 9 is a schematic flowchart of creating a power supply network model using computing software according to an embodiment of the present application. As shown in FIG. 9 , exemplarily, creating a power supply network model according to a power bus network specifically includes:
  • Formation design According to the width, spacing and level of the power bus network in the power bus network, the layout of the power bus network is designed, wherein the layout of the power bus network is a plane geometry description of the physical condition of the power bus network.
  • Power bus network extraction (PG extraction, PG: Power Grid): Using the parasitic parameter extraction function of the software, the parasitic resistance and/or parasitic capacitance in the power distribution network are extracted from the layout of the power bus network.
  • Power calculation Calculate the value of parasitic resistance and/or the value of parasitic capacitance, or the value of other parasitic parameters.
  • Create CPM (CPM creation): Automatically create a CPM (chip power model, chip power model) according to the values of the above parasitic parameters to form a power supply network model.
  • the parasitic parameters in the power distribution network are extracted from the layout of the power bus network by software to create a power supply network model, which helps to improve the accuracy of the power supply network model.
  • the circuit module before performing the extraction of parasitic parameters on the layout of the power bus network, it also includes creating a layout of the circuit module.
  • the layout of the circuit module Before extracting the parasitic parameters of the layout of the power bus network, the layout of the circuit module can be created, so that the parasitic parameter extraction of the layout of the power bus network and the standard parasitic format of the layout of the circuit module can be simultaneously performed by software, which is helpful for Further shorten the chip design and development cycle.
  • create a power supply network model based on the power bus network including:
  • the power supply network unit includes a plurality of power lines and a plurality of power bridge connections, and both the power lines and the power bridge connections include at least one of a resistor and a capacitor;
  • an array formed by a plurality of power supply network units is created to form a power supply network model.
  • the power supply network model can also be established manually.
  • the specific process is as follows.
  • a power supply network unit 23 is created.
  • the power supply network unit 23 includes a plurality of power lines 21 and a plurality of The power bridge connection line 22, the power supply line 21 and the power supply bridge connection line 22 each include at least one of a resistor 231 and a capacitor 232.
  • the position and number of the resistor 231 and the capacitor 232 can be set according to actual needs, and this embodiment of the present application Not limited.
  • an array formed by multiple power supply network units 23 is created, and the multiple power supply network units 23 are electrically connected by power lines 21 and/or power bridge wires 22 to finally form a power supply network model.
  • both the power line 21 and the power bridge connection line 22 can be composed of single-layer or multi-layer metal layers.
  • the power line 21 and the power bridge connection 22 may include multiple power types, such as V1-1, V2-1, V3-1, V1-2, V3-2, V2 in the figure -2, V1-3 and V3-3 power supplies
  • multiple power supply lines 21 include power supply lines 21 of the same power supply type but used for different purposes
  • each power bridge connection line 22 is used to electrically connect the same power supply type but used for different purposes.
  • At least part of the power supply lines 21 and the power supply pads 201 are used for being electrically connected to the power supply lines 21 corresponding to the power supply type, for providing the power supply of the corresponding type.
  • Those skilled in the art can set the number of metal layers, the number and connection relationship of the power lines 21 and the power bridge connections 22 in the power supply network unit 23 by themselves according to actual needs.
  • the values of the resistor 231 and the capacitor 232 are programmable.
  • the values of the resistor 231 and the capacitor 232 are programmable, it is convenient to modify the values of the resistor 231 and the capacitor 232 in the power supply network unit 23.
  • the power supply can be calculated in real time according to the optimization result of the circuit.
  • the value of the parasitic resistance and/or the value of the parasitic capacitance on the line 21 and the power bridge connection line 22, and the value of the parasitic resistance and/or the value of the parasitic capacitance is added to the resistance 231 and/or the capacitance of the power supply network unit 23 by programming 232, which helps to further shorten the chip design and development cycle.
  • the values of the resistor 231 and the capacitor 232 are calculated according to the size and material of the power line 21 or the power bridge connection line 22 .
  • the values of the resistor 231 and the capacitor 232 can be calculated according to the size and material of the power line 21 or the power bridge connection line 22.
  • the circuit is optimized later, it is only necessary to intuitively adjust the size and the size of the power line 21 or the power bridge connection line 22.
  • Material the values of the resistor 231 and the capacitor 232 are updated by calculation.
  • the values of the resistance and capacitance may also be calculated according to the distance and level of the power lines or power bridge connections, so as to obtain more accurate parasitic parameters, which are not limited in this embodiment of the present application.
  • FIG. 10 is a schematic flowchart of another chip design method provided by an embodiment of the application. As shown in FIG. 10 , optionally, before creating a power bus network according to the pad position and the chip layout diagram, the method further includes:
  • creating a power supply network model according to the power bus network includes: according to the power bus network, the package power supply of the chip.
  • the supply network model and/or the signal supply network model creates a power supply network model.
  • the chip design method may also include: creating a control chip, a channel PDN model and/or an SDN model; then creating a power supply network model according to the power bus network includes: according to the power bus network and the control chip, the channel PDN model and/or SDN model to create a power supply network model.
  • FIG. 11 is a schematic structural diagram of a memory system provided by an embodiment of the present application.
  • the chip obtained by the chip design method provided by the embodiment of the present application may be a memory chip, and the control chip is used for The memory chip is controlled to perform operations such as reading and writing, and the control chip and the memory chip are separately packaged and then arranged on the substrate.
  • the control chip and the memory chip are separately packaged and then arranged on the substrate.
  • FIG. 11 is only a storage system architecture to which the design method of this embodiment is applicable.
  • the packaging integration form of the storage chip and the control chip is not limited to the form shown in FIG. 11 .
  • this embodiment is also applicable.
  • the design method of the example is not limited in this embodiment, and those skilled in the art can set it according to their own needs.
  • determining the position of the power port of the circuit module in the power bus network includes:
  • the horizontal and vertical coordinates are defined in the power bus network, and the horizontal and vertical coordinates are used to represent the position of the power port of the circuit module in the power bus network.
  • the power bus network has abscissa X-2, X-1, X0, X1 and X2, ordinate Y0, Y1 and Y2, by determining the abscissa and ordinate of the power port of the circuit module 12 in the power bus network, the position of the power port of the circuit module in the power bus network can be determined location, this method is relatively simple and easy to implement.
  • the position of the power port of the circuit module in the power bus network may also be determined in the form of polar coordinates, which is not limited in this embodiment of the present application.
  • the netlist embedded with the power supply network is generated, including:
  • a power supply network configuration file is generated, the power supply network model and circuit modules are integrated by importing the power supply network configuration file, and a netlist embedded with the power supply network is generated, which is easy to operate and reduces workload.
  • the power supply network configuration file includes at least the abscissa and ordinate information of the power port of the circuit module in the power bus network.
  • the abscissa and vertical coordinate information of the power port of the circuit module in the power supply network configuration file in the power bus network is obtained, the position of the power port of the circuit module in the power supply network model is determined, and then the position of the power supply network model is determined.
  • the connection path between the power port and the pad of the circuit module 12, the power supply network unit 23 located on the connection path is integrated with the circuit netlist to generate a netlist embedded with the power supply network, so that the netlist embedded with the power supply network can be
  • the table contains parasitic parameters on the power bus network.
  • Table 1 below is a schematic diagram of a configuration file of a power supply network provided by an embodiment of the present application.
  • the power supply network configuration file may include the power bus name (Power Grid Name), the name in the PDN model (Netin PDN Model), the instance module (Powerfor Instance Block), and the power pins of the instance module. (Power Pinof Instance Block), decoupling capacitors (Decapon Power Grid), location (Layoutlocation), and notes (Notes) and other information.
  • the example module is the name of the circuit module in the chip
  • the power pin of the example module is the name of the power port of the circuit module
  • the power bus name is the connection between the power port of the circuit module and the power pad unit 201 (refer to FIG.
  • the name of the power bus passed through is the name of the above power bus in the power supply network model, the location is the abscissa and ordinate information of the power port of the circuit module in the power bus network, and the decoupling capacitor refers to whether it needs to be set
  • Decoupling capacitor for example, 0 means no decoupling capacitor, 1 means there is decoupling capacitor, but this embodiment does not limit this
  • this capacitor can provide a relatively stable power supply, and can also reduce the noise coupled to the power supply terminal, indirectly Other components can be reduced to be affected by the noise of this component, and the remarks can provide other information required for integration.
  • a person skilled in the art can set the configuration file of the power supply network according to actual needs, which is not limited in this embodiment of the present application.
  • circuit simulation is performed according to the netlist embedded with the power supply network, it also includes:
  • the circuit simulation is performed according to the modified netlist with embedded power supply nets.
  • the chip design method provided by the present application can be applied to the pre-simulation stage and/or the post-simulation stage without changing the conventional chip design process, and the application is flexible.
  • a power bus network is created according to the pad position and the chip plane layout, the position of the power port of the circuit module in the power bus network is determined, and a power supply network model is created according to the power bus network, According to the power supply network model and the position of the power port of the circuit module in the power bus network, a netlist embedded with the power supply network is generated, and the circuit simulation is performed according to the netlist embedded with the power supply network, and the parasitic parameters in the power bus network are integrated Enter the circuit netlist for simulation, realize the power integrity analysis of the chip, reduce the design difficulty, thereby shorten the development cycle of the chip design and reduce the design cost. And the method can be applied to any simulation stage in the conventional chip design process, and the application is flexible.
  • FIG. 12 is a schematic structural diagram of a chip design device provided by an embodiment of the present application. As shown in FIG. The chip's design device includes:
  • the power bus network generation module 31 is used for creating a power bus network according to the pad position and the chip layout diagram.
  • the circuit module position determination module 32 is used for determining the position of the power port of the circuit module in the power bus network.
  • the power supply network model generation module 33 is used for creating a power supply network model according to the power bus network.
  • the power supply network-embedded netlist generation module 34 is configured to generate a power supply network-embedded netlist according to the power supply network model and the position of the power port of the circuit module in the power bus network.
  • the simulation module 35 is used for circuit simulation according to the netlist embedded with the power supply network.
  • FIG. 13 is a schematic structural diagram of a power supply network model generation module provided by an embodiment of the application. As shown in FIG. 13 , optionally, the power supply network model generation module 33 includes:
  • the layout generating unit 331 of the power bus network is configured to create a layout of the power bus network according to the power bus network.
  • the parasitic parameter extraction unit 332 is configured to extract parasitic parameters for the layout of the power bus network.
  • the parasitic parameter calculation unit 333 is used to calculate the value of the parasitic parameter.
  • the power supply network model generation unit 334 is configured to create a power supply network model according to the values of parasitic parameters.
  • FIG. 14 is a schematic structural diagram of a power supply network model generation module provided by an embodiment of the application. As shown in FIG. 14 , optionally, the power supply network model generation module 33 includes:
  • the power supply network unit generating unit 335 is used to generate a power supply network unit as required, the power supply network unit includes a plurality of power lines and a plurality of power bridge connections, and both the power lines and the power bridge connections contain at least one of a resistor and a capacitor. A sort of.
  • the power supply network model generating unit 336 is configured to create an array formed by a plurality of power supply network units to form a power supply network model.
  • the netlist generation module 34 embedded with a power supply network includes:
  • the power supply network-embedded netlist generation unit 342 generates a power supply network-embedded netlist according to the power supply network configuration file.
  • the chip design apparatus provided by the embodiment of the present application can execute the chip design method provided by any embodiment of the present application, and has functional modules and beneficial effects corresponding to the execution method, and the same or corresponding structure and terminology as the above-mentioned embodiment. It is not repeated here.
  • an embodiment of the present application also provides a computer device, including a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, when the processor executes the computer program, the present invention is implemented.
  • the chip design method provided by any of the embodiments of the application is applied.
  • FIG. 16 is a schematic structural diagram of a computer device provided by an embodiment of the application.
  • the computer device includes a processor 40, a memory 41, an input device 42, and an output device 43; the number of processors 40 in the computer device There may be one or more, and one processor 40 is taken as an example in FIG. 16; the processor 40, memory 41, input device 42 and output device 43 in the computer equipment can be connected by a bus or other means, and in FIG. Connect as an example.
  • the memory 41 can be used to store software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the chip design method in the embodiments of the present application (for example, referring to FIG.
  • the processor 40 executes various functional applications and data processing of the computer device by running the software programs, instructions and modules stored in the memory 41 , that is, implements the above-mentioned chip design method.
  • the memory 41 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like.
  • memory 41 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device.
  • memory 41 may further include memory located remotely from processor 40, which may be connected to the computer device through a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • the input device 42 may be used to receive input numerical or character information and to generate key signal input related to user settings and function control of the computer device.
  • the output device 43 may include a display device such as a display screen.
  • an embodiment of the present application also provides a storage medium containing computer-executable instructions, which is characterized in that, when executed by a computer processor, the computer-executable instructions are used to execute the chip provided by any embodiment of the present application design method.
  • the chip's design methodology includes:
  • Step 1 Create a power bus network based on the pad location and the chip floor plan.
  • Step 2 Determine the position of the power port of the circuit module in the power bus network.
  • Step 3 Create a power supply network model according to the power bus network.
  • Step 4 Generate a netlist embedded with the power supply network according to the power supply network model and the position of the power port of the circuit module in the power bus network.
  • Step 5 Perform circuit simulation according to the netlist embedded with the power supply network.
  • a storage medium containing computer-executable instructions provided by the embodiments of the present application the computer-executable instructions of the storage medium are not limited to the above-mentioned method operations, and can also execute the chip design method provided by any embodiment of the present application. related operations.
  • the present application can be implemented by means of software and necessary general-purpose hardware, and of course can also be implemented by hardware, but in many cases the former is a better implementation manner .
  • the technical solutions of the present application can be embodied in the form of software products in essence or the parts that make contributions to the prior art, and the computer software products can be stored in a computer-readable storage medium, such as a floppy disk of a computer , read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), flash memory (FLASH), hard disk or optical disk, etc., including several instructions to make a computer device (which can be a personal computer , server, or network device, etc.) to execute the methods described in the various embodiments of this application.
  • a computer-readable storage medium such as a floppy disk of a computer , read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), flash memory (FLASH), hard disk or optical disk, etc.
  • the units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be realized; in addition, The specific names of the functional units are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present application.

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Abstract

一种芯片的设计方法、设计装置、计算机设备及存储介质。其中，芯片的设计方法包括根据焊盘位置和芯片平面布局图创建电源总线网络(步骤1)，确定电路模块的电源端口在电源总线网络中的位置(步骤2)，根据电源总线网络创建电源供应网络模型(步骤3)，根据电源供应网络模型和电路模块的电源端口在电源总线网络中的位置生成嵌有电源供应网络的网表(步骤4)，根据嵌有电源供应网络的网表进行电路仿真(步骤5)。该设计方法、设计装置、计算机设备及存储介质，缩短了芯片设计开发周期，降低了设计成本。

Description

一种芯片的设计方法、设计装置、计算机设备及存储介质
交叉引用
本申请引用于2020年08月31日递交的名称为“一种芯片的设计方法、设计装置、计算机设备及存储介质”的第202010901336.0号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及芯片设计技术领域，尤其涉及一种芯片的设计方法、设计装置、计算机设备及存储介质。
背景技术
随着集成电路技术的发展，芯片的信号完整性和电源完整性分析变得越来越重要。随着芯片工艺尺寸的不断降低，芯片电源供应网络的寄生影响越来越大，若设计不好可能导致关键电路模块的时序不满足要求、瞬态噪声愈发严重等，从而影响芯片的实际工作性能，严重时还会引起逻辑错误以至于芯片失效。
在芯片设计中，需要进行(版图设计)前仿真和(版图设计)后仿真的流程。通常在芯片完整版图设计完成后才会进行电源完整性的仿真分析，若仿真发现时序余裕(timingmargin)不满足要求，则需对电源供应网络或电路做多次反复设计、验证，严重增加设计开发周期和成本。
需要说明的是，在上述背景技术部分申请的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本申请提供一种芯片的设计方法、设计装置、计算机设备及存储介质，以缩短芯片设计开发周期，降低设计成本。
第一方面，本申请实施例提供了一种芯片的设计方法，包括：根据焊盘位置和芯片平面布局图创建电源总线网络；确定电路模块的电源端口在所述电源总线网络中的位置；根据所述电源总线网络创建电源供应网络模型；根据所述电源供应网络模型和所述电路模块的电源端口在所述电源总线网络中的位置生成嵌有电源供应网络的网表；根据所述嵌有电源供应网络的网表进行电路仿真。
第二方面，本申请实施例还提供了一种芯片的设计装置，该装置包括：电源总线网络生成模块，用于根据焊盘位置和芯片平面布局图创建电源总线网络；电路模块位置确定模块，用于确定所述电路模块的电源端口在所述电源总线网络中的位置；电源供应网络模型生成模块，用于根据所述电源总线网络创建电源供应网络模型；嵌有电源供应网络的网表生成模块，用于根据所述电源供应网络模型和所述电路模块的电源端口在所述电源总线网络中的位置生成嵌有电源供应网络的网表；仿真模块，用于根据所述嵌有电源供应网络的网表进行电路仿真。
第三方面，本申请实施例还提供了一种计算机设备，包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现第一方面所述的任一芯片的设计方法。
第四方面，本申请实施例还提供了一种包含计算机可执行指令的存储介质，所述计算机可执行指令在由计算机处理器执行时用于执行第一方面所述的 任一芯片的设计方法。
本申请实施例提供的芯片的设计方法、设计装置、计算机设备及存储介质，通过根据焊盘位置和芯片平面布局图创建电源总线网络，确定电路模块的电源端口在电源总线网络中的位置，根据电源总线网络创建电源供应网络模型，根据电源供应网络模型和电路模块的电源端口在电源总线网络中的位置生成嵌有电源供应网络的网表，根据嵌有电源供应网络的网表进行电路仿真，将电源总线网络中的寄生参数整合进电路网表进行仿真，实现芯片的电源完整性分析，以验证芯片的电源供应网络设计是否满足要求，既可以在版图设计完成分析，也可以在版图设计完成后分析，降低了电源供应网络设计的难度，从而缩减芯片设计的开发周期，降低设计成本。
附图说明
图1为本申请实施例提供的一种芯片的设计方法的流程示意图；
图2为本申请实施例提供的另一种芯片的设计方法的流程示意图；
图3为本申请实施例提供的一种电源总线网络的结构示意图；
图4为图3在A处的放大结构示意图；
图5为本申请实施例提供的一种电路模块和电源总线网络的整合结构示意图；
图6为本申请实施例提供的一种电源供应网络模型的结构示意图；
图7为本申请实施例提供的一种电源供应网络单元的结构示意图；
图8为本申请实施例提供的一种电路模块和电源供应网络模型的整合结构示意图；
图9为本申请实施例提供的一种创建电源供应网络模型的流程示意图；
图10为本申请实施例提供的又一种芯片的设计方法的流程示意图；
图11为本申请实施例提供的一种存储系统的结构示意图；
图12为本申请实施例提供的一种芯片的设计装置的结构示意图；
图13为本申请实施例提供的一种电源供应网络模型生成模块的结构示意图；
图14为本申请实施例提供的一种电源供应网络模型生成模块的结构示意图；
图15为本申请实施例提供的一种嵌有电源供应网络的网表生成模块的结构示意图；
图16为本申请实施例提供的一种计算机设备的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
图1为本申请实施例提供的一种芯片的设计方法的流程示意图，如图1所示，本申请实施例提供的芯片的设计方法包括：
步骤1、根据焊盘位置和芯片平面布局图创建电源总线网络。
示例性的，图2为本申请实施例提供的另一种芯片的设计方法的流程示意图，图3为本申请实施例提供的一种电源总线网络的结构示意图，如图2和图3所示，首先对芯片进行布局规划：完成芯片长度和宽度的确定，完成焊盘的排列，完成电源规划，创建焊盘、电源总线计划(Createpadslog&powerbusplan)。 其中，焊盘的排列同时考虑将来芯片应用于封装基板的走线方便以及芯片内部易于实现等多重因素。根据芯片所需的功能，设计电路模块，创建电路原理图和电路网表；完成电路模块和电源总线在芯片中的布局，创建芯片平面布局图(floorplan)。根据焊盘位置和芯片平面布局图创建电源总线网络，如图3所示，电源总线网络包括焊盘10和电源总线11，焊盘10包括电源焊盘101和信号焊盘102，电源焊盘101用于为电源总线11各个节点提供相应的电源，信号焊盘102用于提供信号，电源总线11与电源焊盘101连接。其中，电源总线11可由多层金属层构成。图4为图3在A处的放大结构示意图，如图4所示，以四层金属层为例，电源总线11(参考图3)由M1、M2、M3和M4四层金属层构成，从而可通过不同的金属层传输不同电压的电源。需要说明的是，在其他实施例中，电源总线也可由其他数量层金属层构成，可根据需要自行选择。
步骤2、确定电路模块的电源端口在电源总线网络中的位置。
示例性的，图5为本申请实施例提供的一种电路模块和电源总线网络的整合结构示意图，如图5所示，根据芯片平面布局图确定电路模块12在电源总线网络中的位置，找出各电路模块12的各电源端口，确定电源端口在电源总线网络中的位置，从而为后续确定各电路模块12的各电源端口与电源焊盘101的连接路径做好准备。具体的，如图5所示，以电路模块12包括电源模块1、电源模块2、电源模块3和电源模块4为例，每个电路模块12包括两个电源端口，分别用于连接提供高电平的电源焊盘101和提供低电平的电源焊盘101，根据芯片平面布局图确定电源模块1、电源模块2、电源模块3和电源模块4在电源总线网络中的位置，找出各电路模块12的各电源端口，确定电源端口在电源总线网络中的位置，进而确定各电路模块12的各电源端口与电源焊盘101 的连接路径。
步骤3、根据电源总线网络创建电源供应网络模型。
示例性的，图6为本申请实施例提供的一种电源供应网络模型的结构示意图，图7为本申请实施例提供的一种电源供应网络单元的结构示意图，如图6和图7所示，电源供应网络模型包括多个焊盘20，以及多个电源供应网络单元23构成的阵列，焊盘包括电源焊盘201和信号焊盘202，电源供应网络单元23之间通过电源线21和/或电源桥连线22互相连接。每个电源供应网络单元23均包括多条电源线21和多条电源桥连线22，其中电源线21和电源桥连线22上包含电阻231、电容232中的至少一种。可计算电源线21和电源桥连线22上寄生电阻的值和/或寄生电容的值，并将寄生电阻的值和/或寄生电容的值添加到电源供应网络单元23的电阻231和/或电容232中，使得电源供应网络模型带有电源总线网络上的寄生参数。本实施例中的手动建立电源供应网络模型的方法简单有效，并易于追踪对电源供应网络的优化修改。
步骤4、根据电源供应网络模型和电路模块的电源端口在电源总线网络中的位置生成嵌有电源供应网络的网表。
示例性的，图8为本申请实施例提供的一种电路模块和电源供应网络模型的整合结构示意图，参考图5和图8，将电源总线网络与电源供应网络模型进行比对，根据电路模块12的电源端口在电源总线网络中的位置确定电路模块12的电源端口在电源供应网络模型中的位置，根据电源总线网络中电路模块12的电源端口与电源焊盘的连接路径确定在电源供应网络模型中电路模块12的电源端口与焊盘的连接路径，将位于连接路径上的电源供应网络单元23与电路网表进行整合，生成嵌有电源供应网络的网表，以使嵌有电源供应网络的网表 包含电源总线网络上的寄生参数。其中，图8仅示出了电路模块2和电源供应网络模型的整合结构示意图，在图5中，PDN2-1表示电路模块2的电源端口与电源焊盘101之间连接路径上的电源供应网络单元的集合，同理，PDN2-2、PDN1-1、PDN1-2、PDN3-1、PDN3-2、PDN4-1、PDN4-2代表各电路模块12的各电源端口与电源焊盘101之间相应路径上的电源供应网络单元的集合。
步骤5、根据嵌有电源供应网络的网表进行电路仿真。
其中，对具有电源总线网络上寄生参数的嵌有电源供应网络的网表进行电路仿真，以提前验证芯片的电源供应网络设计是否满足要求，降低后续设计难度，从而缩减芯片设计的开发周期，降低设计成本。需要说明的是，本实施例的设计方法既可以在版图设计完成前进行电路仿真，也可以在完整版图设计后进行电路仿真，还可以在部分版图设计完成后进行仿真，且可以在整个设计过程中进行多次仿真，本领域内技术人员可自行选择。
本申请实施例提供的芯片的设计方法，通过根据焊盘位置和芯片平面布局图创建电源总线网络，确定电路模块的电源端口在电源总线网络中的位置，根据电源总线网络创建电源供应网络模型，根据电源供应网络模型和电路模块的电源端口在电源总线网络中的位置生成嵌有电源供应网络的网表，根据嵌有电源供应网络的网表进行电路仿真，将电源总线网络中的寄生参数整合进电路网表进行仿真，实现芯片的电源完整性分析，以验证芯片的电源供应网络设计是否满足要求，降低了电源供应网络设计的难度，从而缩减芯片设计的开发周期，降低设计成本。
可选的，电路模块为关键时序电路模块。
其中，关键时序电路模块为对电源较为敏感的电路模块，通过将关键时 序电路模块的电源端口与电源焊盘101(参考图5)的连接路径上的电源总线11(参考图3)的寄生参数添加到电路网表进行仿真，忽略对电源不敏感的电路模块，保证关键时序电路模块的电源端口的电压及电流符合需求的同时，有助于减小计算量，提高仿真速度。
可选的，关键时序电路模块包括芯片的读时序路径、写时序路径、阵列时序路径、命令时序路径中任一种或多种时序路径上的电路模块，芯片包括动态随机存储器(DRAM)。
其中，通常在芯片的读时序路径、写时序路径、阵列时序路径、命令时序路径上的电路模块较为重要，对电源较为敏感，因此，将读时序路径、写时序路径、阵列时序路径、命令时序路径上的电路模块设定为关键时序电路模块，将关键时序电路模块的电源端口与电源焊盘101的连接路径上的电源总线11的寄生参数添加到电路网表进行仿真，实现关键时序电路模块的电源完整性分析，保证关键时序电路模块的电源端口的电压及电流符合需求，降低了设计难度，缩减芯片设计的开发周期，降低设计成本。
可选的，根据电源总线网络创建电源供应网络模型包括：根据电源总线网络创建电源总线网络的版图；对电源总线网络的版图进行寄生参数的提取；计算寄生参数的数值；根据寄生参数的数值创建电源供应网络模型。
图9为本申请实施例提供的一种利用计算软件创建电源供应网络模型的流程示意图，如图9所示，示例性的，根据电源总线网络创建电源供应网络模型具体包括：
形成设计(setupdesign)：根据电源总线网络中电源总线的宽度、间距和层次，设计出电源总线网络的版图，其中，电源总线网络的版图为电源总线网 络的物理情况的平面几何形状描述。
电源总线网络提取(PG extraction，PG:Power Grid)：利用软件的寄生参数提取功能，从电源总线网络的版图提取电源分配网络中的寄生电阻和/或寄生电容等。
电源计算(Powercalculation)：计算寄生电阻的数值和/或寄生电容的数值，或其他寄生参数的数值。
创建CPM(CPM creation)：根据上述寄生参数的数值自动创建CPM(芯片电源模型，chippowermodel)，以形成电源供应网络模型。
其中，通过用软件从电源总线网络的版图提取电源分配网络中的寄生参数，创建电源供应网络模型，有助于提高电源供应网络模型的精确度。
可选的，在对电源总线网络的版图进行寄生参数的提取之前，还包括创建电路模块的版图。
具体的，继续参考图2，在芯片设计中，创建芯片平面布局图、电路原理图和电路网表后进行前仿真(创建版图之前)，根据前仿真结果对电路进行优化，前仿真通过后，完成各个电路模块的最终版图设计，创建电路的版图，对版图进行标准寄生格式提取，以获取版图上各电路模块及信号走线的寄生参数，将版图的寄生参数添加到电路中进行后仿真(创建版图之后)，根据后仿真结构进行电路优化，调整版图设计，直到通过后仿真验证。可在对电源总线网络的版图进行寄生参数的提取之前，创建电路模块的版图，从而可以利用软件同时进行电源总线网络的版图的寄生参数提取和电路模块的版图的标准寄生格式提取，有助于进一步缩短芯片设计开发周期。
可选的，根据电源总线网络创建电源供应网络模型，包括：
创建电源供应网络单元，电源供应网络单元包括多条电源线和多条电源桥连线，电源线和电源桥连线均包含电阻和电容中的至少一种；
根据电源总线网络，创建由多个电源供应网络单元形成的阵列，以构成电源供应网络模型。
示例性的，继续参考图6和图7，电源供应网络模型还可通过手动建立，具体过程如下，根据需要，创建电源供应网络单元23，电源供应网络单元23包括多条电源线21和多条电源桥连线22，电源线21和电源桥连线22均包含电阻231和电容232中的至少一种，电阻231和电容232的位置和数量可根据实际需要进行设置，本申请实施例对此不作限定。根据电源总线网络，创建由多个电源供应网络单元23形成的阵列，多个电源供应网络单元23之间通过电源线21和/或电源桥连线22电连接，以最终形成电源供应网络模型。
其中，电源线21和电源桥连线22均可由单层或多层金属层构成。示例性的，继续参考图7，电源线21和电源桥连线22可包括多个电源类型，如图中的V1-1、V2-1、V3-1、V1-2、V3-2、V2-2、V1-3和V3-3电源，多条电源线21包括相同电源种类但用于不同目的的电源线21，各电源桥连线22用于电连接相同电源种类但用于不同目的的至少部分电源线21，电源焊盘201用于电连接至对应电源种类的电源线21，用于为其提供相应种类的电源。本领域技术人员可根据实际需求对金属层的数量以及电源供应网络单元23内电源线21和电源桥连线22的数量、连接关系等进行自行设置。
可选的，电阻231和电容232的值为可编程。
其中，通过设置电阻231和电容232的值为可编程，便于对电源供应网络单元23中电阻231和电容232的值进行修改，在对电路进行优化时，可根据 对电路的优化结果实时计算电源线21和电源桥连线22上寄生电阻的值和/或寄生电容的值，并将寄生电阻的值和/或寄生电容的值通过编程添加到电源供应网络单元23的电阻231和/或电容232中，有助于进一步缩短芯片设计开发周期。
可选的，电阻231和电容232的值根据电源线21或者电源桥连线22的尺寸和材质计算得到。
其中，可根据电源线21或者电源桥连线22的尺寸和材质计算得到电阻231和电容232的值，后续进行电路优化时，只需直观的调整电源线21或者电源桥连线22的尺寸和材质，通过计算更新电阻231和电容232的值。
在其他实施例中，还可根据电源线或者电源桥连线的间距、层次等计算电阻和电容的值，以获得更加精准的寄生参数，本申请实施例对此不作限定。
图10为本申请实施例提供的又一种芯片的设计方法的流程示意图，如图10所示，可选的，根据焊盘位置和芯片平面布局图创建电源总线网络之前，还包括：
创建芯片的封装电源供应网络模型(PDN，power delivery network)和/或信号供应网络模型(SDN，signal distributionNetwork)；则根据电源总线网络创建电源供应网络模型包括：根据电源总线网络、芯片的封装电源供应网络模型和/或信号供应网络模型创建电源供应网络模型。
在其他实施例中，芯片的设计方法也可以包括：创建控制芯片、通道PDN模型和/或SDN模型；则根据电源总线网络创建电源供应网络模型包括：根据电源总线网络和控制芯片、通道PDN模型和/或SDN模型创建电源供应网络模型。
图11为本申请实施例提供的一种存储系统的结构示意图，如图11所示， 示例性的，本申请实施例提供的芯片的设计方法所得出的芯片可以为存储芯片，控制芯片用于控制存储芯片进行读、写等操作，控制芯片和存储芯片分别进行封装后，设置在基板上。继续参考图10，在根据焊盘位置和芯片平面布局图创建电源总线网络之前，创建控制芯片、通道PDN模型和/或SDN模型，以及存储芯片的封装电源供应网络模型和/或信号供应网络模型，将其整合进本实施例中电源网络供应模型的创建中，可进一步提升电路仿真与实际使用性能之间准确性，从而使得仿真结果更符合实际情况，获得精准的仿真结果，继而达到所设计即所得的效果，进一步缩短设计周期，降低设计成本，提高设计成功率。需要说明的是，图11只是本实施例设计方法所适用的一种存储系统架构，存储芯片与控制芯片的封装集成形式不限于图11中的形式，对于其他形式的封装集成，同样适用本实施例的设计方法，本实施例对此不做限定，本领域内技术人员可根据需要自行设置。
可选的，确定电路模块的电源端口在电源总线网络中的位置包括：
确定电路模块的电源端口在电源总线网络中的横纵坐标。
其中，在电源总线网络中定义横纵坐标，用横纵坐标来表示电路模块的电源端口在电源总线网络中的位置，继续参考图5，示例性的，电源总线网络具有横坐标X-2、X-1、X0、X1和X2，纵坐标Y0、Y1和Y2，通过确定电路模块12的电源端口在电源总线网络中的横纵坐标，即可确定电路模块的电源端口在电源总线网络中的位置，该方法较为简单，容易实现。
在其他实施例中，也可采用极坐标的形式确定电路模块的电源端口在电源总线网络中的位置，本申请实施例对此不作限定。
可选的，根据电源供应网络模型和电路模块的电源端口在电源总线网络 中的位置生成嵌有电源供应网络的网表包括：
根据电源供应网络模型和电路模块的电源端口在电源总线网络中的位置生成电源供应网络配置文件，电源供应网络配置文件用于整合电源供应网络模型和电路模块；
根据电源供应网络配置文件生成嵌有电源供应网络的网表。
其中，生成电源供应网络配置文件，通过导入电源供应网络配置文件来整合电源供应网络模型和电路模块，生成嵌有电源供应网络的网表，操作简单，减少工作量。
可选的，电源供应网络配置文件至少包括电路模块的电源端口在电源总线网络中的横纵坐标信息。
其中，通过导入电源供应网络配置文件，获取电源供应网络配置文件中电路模块的电源端口在电源总线网络中的横纵坐标信息，确定电路模块的电源端口在电源供应网络模型中的位置，进而确定电路模块12的电源端口与焊盘的连接路径，将位于连接路径上的电源供应网络单元23与电路网表进行整合，生成嵌有电源供应网络的网表，以使嵌有电源供应网络的网表包含电源总线网络上的寄生参数。
下表1为本申请实施例提供的一种电源供应网络配置文件示意。
Figure PCTCN2021101364-appb-000001
表1
示例性的，如表1所示，电源供应网络配置文件可包括电源总线名称 (Power Grid Name)、PDN模型中名称(Netin PDN Model)、实例模块(Powerfor Instance Block)、实例模块的电源引脚(Power Pinof Instance Block)、去耦电容(Decapon Power Grid)、位置(Layoutlocation)以及备注(Notes)等信息。其中，实例模块为芯片中的电路模块的名称，实例模块的电源引脚为电路模块的电源端口的名称，电源总线名称为该电路模块的电源端口与电源焊盘单元201(参考图6)连接所经过的电源总线名称，PDN模型中名称为上述电源总线在电源供应网络模型中的名称，位置为电路模块的电源端口在电源总线网络中的横纵坐标信息，去耦电容是指是否需要设置去耦电容(例如0代表没有去耦电容，1代表有去耦电容，但本实施例对此不作限定)，此电容可以提供较稳定的电源，同时也可以降低元件耦合到电源端的噪声，间接可以减少其他元件受此元件噪声的影响，备注可提供其他整合所需信息。导入电源供应网络配置文件后，找出实例模块的电源引脚和电源总线名称，与电路网表进行匹配，根据位置和PDN模型中名称在电路网表中添加实例模块的电源引脚和电源总线之间的电源供应网络单元，从而生成嵌有电源供应网络的网表。
在其他实施例中，本领域技术人员可根据实际需要对电源供应网络配置文件进行设置，本申请实施例对此不作限定。
可选的，根据嵌有电源供应网络的网表进行电路仿真后，还包括：
对电源总线网络进行修改或对电路模块进行修改；
生成修改后的嵌有电源供应网络的网表；
根据修改后的嵌有电源供应网络的网表进行电路仿真。
示例性的，继续参考图2和图10，对嵌有电源供应网络的网表进行电路仿真后，对仿真结果进行时序分析，根据分析结果对电源总线网络进行修改或 对电路模块进行修改，从而实现电路优化，然后生成修改后的嵌有电源供应网络的网表，根据修改后的嵌有电源供应网络的网表进行电路仿真，直到通过仿真验证，进行流片工序。
继续参考图2和图10，本申请提供的芯片的设计方法可应用于前仿真阶段和/或后仿真阶段，且无需改变常规的芯片设计流程，应用灵活。
本申请实施例提供的芯片的设计方法，通过根据焊盘位置和芯片平面布局图创建电源总线网络，确定电路模块的电源端口在电源总线网络中的位置，根据电源总线网络创建电源供应网络模型，根据电源供应网络模型和电路模块的电源端口在电源总线网络中的位置生成嵌有电源供应网络的网表，根据嵌有电源供应网络的网表进行电路仿真，将电源总线网络中的寄生参数整合进电路网表进行仿真，实现芯片的电源完整性分析，降低了设计难度，从而缩减芯片设计的开发周期，降低设计成本。且该方法可应用于常规芯片设计流程中的任一仿真阶段，应用灵活。
基于同样的构思，本申请实施例还提供了一种芯片的设计装置，图12为本申请实施例提供的一种芯片的设计装置的结构示意图，如图12所示，本申请实施例提供的芯片的设计装置包括：
电源总线网络生成模块31，用于根据焊盘位置和芯片平面布局图创建电源总线网络。
电路模块位置确定模块32，用于确定电路模块的电源端口在电源总线网络中的位置。
电源供应网络模型生成模块33，用于根据电源总线网络创建电源供应网络模型。
嵌有电源供应网络的网表生成模块34，用于根据电源供应网络模型和电路模块的电源端口在电源总线网络中的位置生成嵌有电源供应网络的网表。
仿真模块35，用于根据嵌有电源供应网络的网表进行电路仿真。
图13为本申请实施例提供的一种电源供应网络模型生成模块的结构示意图，如图13所示，可选的，电源供应网络模型生成模块33包括：
电源总线网络的版图生成单元331，用于根据电源总线网络创建电源总线网络的版图。
寄生参数提取单元332，用于对电源总线网络的版图进行寄生参数的提取。
寄生参数计算单元333，用于计算寄生参数的数值。
电源供应网络模型生成单元334，用于根据寄生参数的数值创建电源供应网络模型。
图14为本申请实施例提供的一种电源供应网络模型生成模块的结构示意图，如图14所示，可选的，电源供应网络模型生成模块33包括：
电源供应网络单元生成单元335，用于根据需要生成电源供应网络单元，电源供应网络单元包括多条电源线和多条电源桥连线，电源线和电源桥连线均包含电阻和电容中的至少一种。
电源供应网络模型生成单元336，用于创建多个电源供应网络单元形成的阵列，以形成电源供应网络模型。
图15为本申请实施例提供的一种嵌有电源供应网络的网表生成模块的结构示意图，如图15所示，可选的，嵌有电源供应网络的网表生成模块34包括：
电源供应网络配置文件生成单元341，根据电源供应网络模型和电路模块的电源端口在电源总线网络中的位置生成电源供应网络配置文件，电源供应网络配置文件用于整合电源供应网络模型和电路模块；
嵌有电源供应网络的网表生成单元342，根据电源供应网络配置文件生成嵌有电源供应网络的网表。
本申请实施例所提供的芯片的设计装置可执行本申请任意实施例所提供的芯片的设计方法，具备执行方法相应的功能模块和有益效果，与上述实施例相同或相应的结构以及术语的解释在此不再赘述。
基于同样的构思，本申请实施例还提供了一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其特征在于，处理器执行计算机程序时实现本申请任意实施例所提供的芯片的设计方法。
图16为本申请实施例提供的一种计算机设备的结构示意图，如图16所示，该计算机设备包括处理器40、存储器41、输入装置42和输出装置43；计算机设备中处理器40的数量可以是一个或多个，图16中以一个处理器40为例；计算机设备中的处理器40、存储器41、输入装置42和输出装置43可以通过总线或其他方式连接，图16中以通过总线连接为例。
存储器41作为一种计算机可读存储介质，可用于存储软件程序、计算机可执行程序以及模块，如本申请实施例中的芯片的设计方法对应的程序指令/模块(例如，参考图12，芯片的设计装置中的电源总线网络生成模块31、电路模块位置确定模块32、电源供应网络模型生成模块33、嵌有电源供应网络的网表生成模块34和仿真模块35)。处理器40通过运行存储在存储器41中的软件程序、指令以及模块，从而执行计算机设备的各种功能应用以及数据处理， 即实现上述的芯片的设计方法。
存储器41可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据终端的使用所创建的数据等。此外，存储器41可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实例中，存储器41可进一步包括相对于处理器40远程设置的存储器，这些远程存储器可以通过网络连接至计算机设备。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
输入装置42可用于接收输入的数字或字符信息，以及产生与计算机设备的用户设置以及功能控制有关的键信号输入。输出装置43可包括显示屏等显示设备。
基于同样的构思，本申请实施例还提供了一种包含计算机可执行指令的存储介质，其特征在于，计算机可执行指令在由计算机处理器执行时用于执行本申请任意实施例所提供的芯片的设计方法。
该芯片的设计方法包括：
步骤1、根据焊盘位置和芯片平面布局图创建电源总线网络。
步骤2、确定电路模块的电源端口在电源总线网络中的位置。
步骤3、根据电源总线网络创建电源供应网络模型。
步骤4、根据电源供应网络模型和电路模块的电源端口在电源总线网络中的位置生成嵌有电源供应网络的网表。
步骤5、根据嵌有电源供应网络的网表进行电路仿真。
当然,本申请实施例所提供的一种包含计算机可执行指令的存储介质, 其计算机可执行指令不限于如上所述的方法操作,还可以执行本申请任意实施例所提供的芯片的设计方法中的相关操作。
通过以上关于实施方式的描述，所属领域的技术人员可以清楚地了解到，本申请可借助软件及必需的通用硬件来实现，当然也可以通过硬件实现，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如计算机的软盘、只读存储器(Read-Only Memory,ROM)、随机存取存储器(Random Access Memory,RAM)、闪存(FLASH)、硬盘或光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
值得注意的是，上述芯片的设计装置的实施例中，所包括的各个单元和模块只是按照功能逻辑进行划分的，但并不局限于上述的划分，只要能够实现相应的功能即可；另外，各功能单元的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。
注意，上述仅为本申请的较佳实施例及所运用技术原理。本领域技术人员会理解，本申请不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本申请的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本申请不仅仅限于以上实施例，在不脱离本申请构思的情况下，还可以包括更多其他等效实施例，而本申请的范围由所附的权利要求范围决定。

Claims (20)

  1. 一种芯片的设计方法，其特征在于，包括：
    根据焊盘位置和芯片平面布局图创建电源总线网络；
    确定电路模块的电源端口在所述电源总线网络中的位置；
    根据所述电源总线网络创建电源供应网络模型；
    根据所述电源供应网络模型和所述电路模块的电源端口在所述电源总线网络中的位置生成嵌有电源供应网络的网表；
    根据所述嵌有电源供应网络的网表进行电路仿真。
  2. 根据权利要求1所述的芯片的设计方法，其特征在于，所述电路模块为关键时序电路模块。
  3. 根据权利要求2所述的芯片的设计方法，其特征在于，所述关键时序电路模块包括所述芯片的读时序路径、写时序路径、阵列时序路径、命令时序路径中任一种或多种时序路径上的电路模块。
  4. 根据权利要求1所述的芯片的设计方法，其特征在于，根据所述电源总线网络创建所述电源供应网络模型包括：
    根据所述电源总线网络创建所述电源总线网络的版图；
    对所述电源总线网络的版图进行寄生参数的提取；
    计算所述寄生参数的数值；
    根据所述寄生参数的数值创建所述电源供应网络模型。
  5. 根据权利要求4所述的芯片的设计方法，其特征在于，在对所述电源总线网络的版图进行所述寄生参数的提取之前，还包括创建所述电路模块的版图。
  6. 根据权利要求1所述的芯片的设计方法，其特征在于，根据所述电源总线网 络创建所述电源供应网络模型，包括：
    创建电源供应网络单元，所述电源供应网络单元包括多条电源线和多条电源桥连线，所述电源线和所述电源桥连线均包含电阻和电容中的至少一种；
    根据所述电源总线网络，创建由多个所述电源供应网络单元形成的阵列，以构成所述电源供应网络模型。
  7. 根据权利要求6所述的芯片的设计方法，其特征在于，所述电阻和/或所述电容的值为可编程。
  8. 根据权利要求7所述的芯片的设计方法，其特征在于，所述电阻和/或电容的值根据所述电源线或者所述电源桥连线的尺寸和材质计算得到。
  9. 根据权利要求1所述的芯片的设计方法，其特征在于，还包括：
    创建所述芯片的封装电源供应网络模型和/或信号供应网络模型；
    根据所述电源总线网络创建所述电源供应网络模型包括：
    根据所述电源总线网络、所述芯片的封装电源供应网络模型和/或所述信号供应网络模型创建所述电源供应网络模型。
  10. 根据权利要求9所述的芯片的设计方法，其特征在于，还包括：
    创建控制芯片、通道PDN模型和/或SDN模型；
    根据所述电源总线网络创建所述电源供应网络模型包括：
    根据所述电源总线网络和所述控制芯片、所述通道PDN模型和/或所述SDN模型创建所述电源供应网络模型。
  11. 根据权利要求1所述的芯片的设计方法，其特征在于，确定所述电路模块的电源端口在所述电源总线网络中的位置包括：
    确定所述电路模块的电源端口在所述电源总线网络中的横纵坐标。
  12. 根据权利要求11所述的芯片的设计方法，其特征在于，根据所述电源供应网络模型和所述电路模块的电源端口在所述电源总线网络中的位置生成所述嵌有电源供应网络的网表包括：
    根据所述电源供应网络模型和所述电路模块的电源端口在所述电源总线网络中的位置生成电源供应网络配置文件，所述电源供应网络配置文件用于整合所述电源供应网络模型和所述电路模块；
    根据所述电源供应网络配置文件生成所述嵌有电源供应网络的网表。
  13. 根据权利要求12所述的芯片的设计方法，其特征在于，所述电源供应网络配置文件至少包括所述电路模块的电源端口在所述电源总线网络中的横纵坐标信息。
  14. 根据权利要求1所述的芯片的设计方法，其特征在于，根据所述嵌有电源供应网络的网表进行电路仿真后，还包括：
    对所述电源总线网络进行修改或对所述电路模块进行修改；
    生成修改后的嵌有电源供应网络的网表；
    根据所述修改后的嵌有电源供应网络的网表进行电路仿真。
  15. 一种芯片的设计装置，其特征在于，包括：
    电源总线网络生成模块，用于根据焊盘位置和芯片平面布局图创建电源总线网络；
    电路模块位置确定模块，用于确定所述电路模块的电源端口在所述电源总线网络中的位置；
    电源供应网络模型生成模块，用于根据所述电源总线网络创建电源供应网络模型；
    嵌有电源供应网络的网表生成模块，用于根据所述电源供应网络模型和所述电路模块的电源端口在所述电源总线网络中的位置生成嵌有电源供应网络的网表；
    仿真模块，用于根据所述嵌有电源供应网络的网表进行电路仿真。
  16. 根据权利要求15所述的芯片的设计装置，其特征在于，所述电源供应网络模型生成模块包括：
    电源总线网络的版图生成单元，用于根据所述电源总线网络创建所述电源总线网络的版图；
    寄生参数提取单元，用于对所述电源总线网络的版图进行寄生参数的提取；
    寄生参数计算单元，用于计算所述寄生参数的数值；
    电源供应网络模型生成单元，用于根据所述寄生参数的数值创建所述电源供应网络模型。
  17. 根据权利要求15所述的芯片的设计装置，其特征在于，所述电源供应网络模型生成模块包括：
    电源供应网络单元生成单元，用于根据需要生成电源供应网络单元，所述电源供应网络单元包括多条电源线和多条电源桥连线，所述电源线和所述电源桥连线均包含电阻和电容中的至少一种；
    电源供应网络模型生成单元，用于创建多个所述电源供应网络单元形成的阵列，以形成所述电源供应网络模型。
  18. 根据权利要求15所述的芯片的设计装置，其特征在于，所述嵌有电源供应网络的网表生成模块包括：
    电源供应网络配置文件生成单元，根据所述电源供应网络模型和所述电路 模块的电源端口在所述电源总线网络中的位置生成电源供应网络配置文件，所述电源供应网络配置文件用于整合所诉电源供应网络模型和所述电路模块；
    嵌有电源供应网络的网表生成单元，根据所述电源供应网络配置文件生成所述嵌有电源供应网络的网表。
  19. 一种计算机设备，包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现如权利要求1-14中任一所述的芯片的设计方法。
  20. 一种包含计算机可执行指令的存储介质，其特征在于，所述计算机可执行指令在由计算机处理器执行时用于执行权利要求1-14中任一所述的芯片的设计方法。
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