WO2022156154A1 - 仿真方法、装置、电源线拓扑网络、测试电路及存储介质 - Google Patents

仿真方法、装置、电源线拓扑网络、测试电路及存储介质 Download PDF

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WO2022156154A1
WO2022156154A1 PCT/CN2021/104786 CN2021104786W WO2022156154A1 WO 2022156154 A1 WO2022156154 A1 WO 2022156154A1 CN 2021104786 W CN2021104786 W CN 2021104786W WO 2022156154 A1 WO2022156154 A1 WO 2022156154A1
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circuit
power supply
simulation
parasitic
power
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PCT/CN2021/104786
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English (en)
French (fr)
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杜涛
徐帆
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长鑫存储技术有限公司
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Priority to US17/448,050 priority Critical patent/US11900038B2/en
Publication of WO2022156154A1 publication Critical patent/WO2022156154A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3947—Routing global
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/10—Processors

Definitions

  • the present application relates to, but is not limited to, a simulation method, device, power line topology network, test circuit and storage medium.
  • the design process of integrated circuit design includes circuit design and pre-simulation, layout design and post-simulation and other processes.
  • the circuit design is specifically to complete the circuit design according to the circuit function
  • the pre-simulation is specifically to simulate the circuit function, including the simulation of parameters such as power consumption, current, voltage, temperature, and input and output characteristics.
  • the pre-simulation does not consider the influence of the parasitic capacitance and resistance generated by the metal wire traces in the circuit.
  • the layout design is completed, the parasitic capacitance and resistance are extracted, and the extracted parasitic capacitance and resistance are added to the circuit for post-simulation and circuit design verification optimization. If the verification fails, adjust the layout design until the verification passes to determine the final layout.
  • the embodiment of the present application provides a simulation method, including:
  • a power line topology network is generated according to the power line layout, the power line topology network includes a plurality of first-layer metal wires arranged horizontally, a plurality of second-layer metal wires arranged vertically, power supply sub-nodes and parasitic elements, and the The parasitic element is located between the two power supply sub-nodes;
  • Timing simulation is performed according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation circuit netlist.
  • the embodiment of the present application also provides a simulation device, including: a memory and a processor;
  • the memory for storing executable instructions for the processor
  • processor is configured to:
  • a power line topology network is generated according to the power line layout, the power line topology network includes a plurality of first-layer metal wires arranged horizontally, a plurality of second-layer metal wires arranged vertically, power supply sub-nodes and parasitic elements, and the The parasitic element is located between the two power supply sub-nodes;
  • Timing simulation is performed according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation circuit netlist.
  • Embodiments of the present application further provide a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, are used to implement the first aspect and each possibility of the first aspect The method of any one of the embodiments of .
  • Embodiments of the present application further provide a computer program product, including a computer program, which, when executed by a processor, implements the first aspect and the method described in any of the possible implementation manners of the first aspect.
  • the embodiment of the present application also provides a power line topology network, including:
  • the parasitic element is located between the two power supply sub-nodes;
  • intersection of the first-layer metal wire and the second-layer metal wire is the power supply sub-node.
  • test circuit including at least one current source and the power line topology network according to any one of the fifth aspect and each possible implementation manner of the fifth aspect;
  • the input current of each of the current sources is the current of each circuit module in the circuit corresponding to the power line topology network
  • the number of the current sources is the same as the number of circuit modules included in the circuit corresponding to the power line topology network.
  • FIG. 1 is a schematic flowchart of a simulation method provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a power line layout
  • FIG. 3 is a schematic diagram of a power line topology network generated according to the power line layout shown in FIG. 2;
  • FIG. 4 is a schematic diagram of a power line topology network generated according to the power line layout shown in FIG. 2;
  • FIG. 5 is a schematic diagram of a circuit module included in a circuit corresponding to the power line topology network shown in FIG. 3;
  • FIG. 6 is a schematic flowchart of a simulation method provided by an embodiment of the present application.
  • Fig. 7 is the test circuit structure schematic diagram corresponding to Fig. 4.
  • FIG. 8 is a schematic flowchart of a simulation method provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a circuit structure obtained by adding the minimum voltage of the power input node of each circuit module to the power input node of each circuit module;
  • FIG. 10 is a schematic structural diagram of a simulation device provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of a simulation apparatus provided by an embodiment of the present application.
  • the present application provides a simulation method, device, power line topology network, test circuit and storage medium.
  • the power line topology network is first generated according to the power line layout, and then the The minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network, and finally the timing simulation is performed according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation circuit netlist.
  • the post-simulation circuit netlist is the post-simulation netlist that does not include the parasitic capacitance and resistance of the layout, that is, the simulation time is approximately the same as the pre-simulation time that does not include power supply parasitics, so the post-simulation results can be obtained quickly, the simulation speed is improved, and the timing
  • the simulation takes into account the minimum voltage of the power input node of each circuit module, and the difference between the minimum voltage and the ideal power supply voltage is the power line voltage drop, so the power line voltage drop can be evaluated by normal timing simulation (the industry term is IR-Drop ) on the timing parameters of the integrated circuit can improve the simulation accuracy, where the timing parameters include, for example, timing parameters such as time delay, thereby realizing a compromise between the simulation accuracy and the simulation speed.
  • the simulation method provided in this application can be applied before layout design.
  • layout design the voltage drop of the power line in the layout of the power line will have an impact on the timing parameters of the integrated circuit.
  • the simulation method provided by this application generates power lines according to the layout of the power lines.
  • Topological network determine the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network, that is, determine the voltage drop of the power line, according to the minimum voltage of the power input node of each circuit module and the integrated circuit.
  • the simulation circuit netlist is used for timing simulation.
  • the simulation results can be used to evaluate the influence of the voltage drop of the power supply line on the timing parameters of the integrated circuit, which can provide guidance for the design of the integrated circuit.
  • the layout design When the layout design is completed, the parasitic resistance and parasitic capacitance of the entire circuit are extracted, and post-simulation is performed. According to the post-simulation results, the timing results can be checked again to provide final guidance for the layout design. Therefore, the layout design error can be reduced. Reduce the development cycle and development cost of integrated circuit design.
  • FIG. 1 is a schematic flowchart of a simulation method provided by an embodiment of the present application.
  • the execution body of the simulation method in this embodiment may be a simulation device or a simulation device, which may be applied before layout design.
  • the simulation methods can include:
  • the power line topology network includes a plurality of first-layer metal wires arranged horizontally, a plurality of second-layer metal wires arranged vertically, power supply sub-nodes and parasitic elements, and parasitic elements between two power supply sub-nodes.
  • FIG. 2 is a schematic diagram of a power line layout.
  • the power line layout is composed of four first-layer metal lines M1 and three second-layer metal lines M2.
  • the first-layer metal lines M1 may be located above or below the second layer metal line M2, and each first layer metal line M1 and each second layer metal line have an intersection.
  • FIG. 3 is a schematic diagram of a power line topology network generated according to the power line layout shown in FIG. 2 , as shown in FIG.
  • the power line topology network includes a plurality of first-layer metal lines M1 arranged horizontally, a plurality of second-layer metal lines M2 arranged vertically, power supply sub-nodes (VDD11-VDD31) and parasitic elements Q, wherein the power line layout The intersection of the metal wire of the first layer and the metal wire of the second layer is the power supply sub-node, the parasitic element is located between the two power supply sub-nodes, and there is a parasitic element between every two power supply sub-nodes.
  • generating the power line topology network according to the power line layout can be:
  • S1012 setting a parasitic element between every two power supply sub-nodes, where the parasitic element includes a first parasitic resistance, a second parasitic resistance and a parasitic capacitance.
  • the first end of the first parasitic resistance is connected to the first power supply sub-node, the second end of the first parasitic resistance is connected to the first end of the second parasitic resistance and the first end of the parasitic capacitance; the second end of the second parasitic resistance
  • the second power supply sub-node is connected; the second end of the parasitic capacitance is connected to the ground terminal.
  • FIG. 4 is a schematic diagram of a power line topology network generated according to the power line layout shown in FIG. 2. As shown in FIG. 4, between every two power supply sub-nodes A parasitic element Q is set, and the parasitic element Q includes a first parasitic resistance R1, a second parasitic resistance R2 and a parasitic capacitance C1.
  • the first parasitic resistance R1 One end is connected to the first power supply sub-node VDD31, the second end of the first parasitic resistance R1 is connected to the first end of the second parasitic resistance R2 and the first end of the parasitic capacitor C1, and the second end of the second parasitic resistance R2 is connected to the second The power supply sub-node VDD32, the second terminal of the parasitic capacitor C1 is connected to the ground terminal.
  • the resistance values of the first parasitic resistance R1 and the second parasitic resistance R2 are both R/2
  • the capacitance value of the parasitic capacitance is C
  • R and C are determined by the following formulas:
  • L is the length of the metal line between the power supply sub-nodes
  • W is the width of the metal line between the power supply sub-nodes
  • Rsh is the square resistance value of the metal
  • Cu is the capacitance value per unit area.
  • the length and width of the metal lines between different power supply sub-nodes are different.
  • the initial length of the metal lines between the power supply sub-nodes can be set according to empirical values. and the initial width to obtain the initial power line topology network, and then perform timing simulation through S102 and S103 according to the initial power line topology network.
  • the length of the metal line between each two power supply sub-nodes in the initial power line topology network can be adjusted. and width, to obtain the adjusted power line topology network, and then perform timing simulation through S102 and S103 according to the adjusted power line topology network, until the power line voltage drop that has less influence on the timing parameters of the integrated circuit is determined through the simulation. topology network.
  • Specific adjustment rules for the length and width of the metal line between each two power supply sub-nodes are not limited in this embodiment of the present application.
  • S102 Determine the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network, where the power input node is one of the power supply sub-nodes in each circuit module.
  • FIG. 5 is a schematic diagram of circuit modules included in a circuit corresponding to the power line topology network shown in FIG. 3 , as shown in FIG.
  • the circuit corresponding to the power line topology network shown in Figure 3 includes 6 circuit modules (X1-X6).
  • the power input node of each circuit module is the VDD shown in Figure 5. It can be seen that the power input of each circuit module A node is one of the power sub-nodes in each circuit module.
  • the post-integrated circuit simulation netlist is a post-layout simulation netlist that does not include parasitic capacitance and resistance, and the simulation result obtained through S103 is a timing analysis result considering the influence of the maximum voltage drop.
  • the power line topology network is first generated according to the power line layout, then the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network is determined, and finally the power line topology network is determined according to each circuit module.
  • the minimum voltage of the power input node and the post-integrated circuit simulation circuit netlist are used for timing simulation.
  • the pre-simulation time of the effect is approximately the same, so the post-simulation results can be obtained quickly, which improves the simulation speed, and the timing simulation considers the minimum voltage of the power input node of each circuit module, and the difference between the minimum voltage and the ideal power supply voltage is the power line. Therefore, the influence of the voltage drop of the power supply line on the timing parameters of the integrated circuit can be evaluated through the normal timing simulation, and the simulation accuracy can be improved, thus achieving a compromise between the simulation accuracy and the simulation speed.
  • FIG. 6 is a schematic flowchart of a simulation method provided by an embodiment of the present application. As shown in FIG. 6 , the simulation method of this embodiment is based on the method shown in FIG. 5 . Optionally, the above S102 may be implemented by the following steps :
  • the first simulation is performed with a preset power supply voltage, and the currents of the 6 circuit modules are obtained as shown in Table 1. shown:
  • circuit module current X1 I1(t) X2 I2(t) X3 I3(t) X4 I4(t) X5 I5(t) X6 I6(t)
  • the foregoing S1022 may include:
  • a current source may be set for the power line topology network, one current source is set for each circuit module, and the number of current sources is the same as the number of circuit modules included in the circuit corresponding to the power line topology network.
  • the input current of each current source is the current In(t) of each circuit module, and the test circuit is obtained.
  • FIG. 7 is a schematic structural diagram of a test circuit corresponding to FIG. 4 , and the test circuit of this embodiment is also called a voltage drop (IR Drop) test circuit, as shown in FIG. 7 ,
  • the first end of each current source P is connected to the power input node of each circuit module, and the second end of each current source P is connected to the ground terminal.
  • the circuit module X1 as an example, the first end of the current source P is connected to the circuit module X1
  • the power supply input node VDD31, the second terminal of the current source P is connected to the ground terminal.
  • circuit simulation is performed on the test circuit to obtain the voltage waveform of the power supply input node of each circuit module.
  • circuit simulation is performed on the test circuit to obtain the voltage waveform of the power input node of each circuit module.
  • circuit simulation is performed on the test circuit to obtain the voltage waveform of the power input node of each circuit module.
  • the test circuit shown in FIG. 7 as an example, for each circuit module in the test circuit, such as taking the circuit module X1 as an example, according to the current In(t) of the circuit module X1 and the power supply sub-nodes VDD31 and VDD31 in the circuit module X1
  • the parasitic element Q between the power supply sub-node VDD32 is simulated by the simulation circuit simulator (Simulation program with integrated circuit emphasis, Spice) to obtain the voltage waveform VDD31(t) of the power input node VDD31 of the circuit module X1
  • a circuit module X1 is used as an example for description here. It can be understood that, by simulating the test circuit, the voltage waveforms VDD31(t) to VDD24(t) of the power input nodes of the six circuit modules
  • S1023. Determine the minimum voltage of the power supply input node of each circuit module according to the voltage waveform of the power supply input node of each circuit module.
  • the voltage waveform is a waveform diagram of voltage values that change with time, and the minimum voltage value of each voltage waveform can be found according to the voltage waveform, that is, the minimum voltage of the power input node of each circuit module, which is a certain
  • the voltage at one moment is recorded as VDDn min in Table 2 below.
  • Table 2 shows the current In(t) corresponding to each module in the test circuit shown in FIG. 7 , the voltage waveform VDDn(t) of the power input node of each circuit module, and the minimum voltage of the power input node of each circuit module Correspondence of VDDn min.
  • the simulation method by performing the first simulation with a preset power supply voltage according to the power line topology network, the current of each circuit module in the circuit corresponding to the power line topology network is obtained.
  • components and the current of each circuit module perform circuit simulation to obtain the voltage waveform of the power input node of each circuit module, and determine the minimum voltage of the power input node of each circuit module according to the voltage waveform of the power input node of each circuit module , thus, the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network is determined.
  • FIG. 8 is a schematic flowchart of a simulation method provided by an embodiment of the present application. As shown in FIG. 8 , the simulation method of this embodiment is based on the method shown in FIG. 6 . Optionally, the above S103 may be implemented by the following steps :
  • FIG. 9 is a schematic diagram of a circuit structure obtained by adding the minimum voltage of the power input node of each circuit module to the power input node of each circuit module.
  • timing simulation is performed on the circuit embedded with the minimum voltage according to the integrated circuit post-simulation circuit netlist, and the obtained simulation result is the timing analysis result considering the influence of the maximum voltage drop.
  • the influence of the voltage drop of the power supply line on the timing parameters of the integrated circuit is accurately evaluated without increasing the simulation time. All the results are based on Spice and the post-layout simulation netlist, which ensures the simulation accuracy, thereby A compromise between simulation accuracy and simulation speed is achieved.
  • FIG. 10 is a schematic structural diagram of a simulation apparatus provided by an embodiment of the present application.
  • the simulation apparatus of this embodiment may include: a generation module 11 , a determination module 12 and a simulation module 13 , wherein the generation module 11 uses
  • the power line topology network includes a plurality of first-layer metal wires arranged horizontally, a plurality of second-layer metal wires arranged vertically, power supply sub-nodes and parasitic elements, and the parasitic elements are located in the between two power supply sub-nodes.
  • the determining module 12 is configured to determine the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network, where the power input node is one of the power sub-nodes in each circuit module.
  • the simulation module 13 is used to perform timing simulation according to the minimum voltage of the power input node of each circuit module and the post-integrated circuit simulation circuit netlist.
  • the generating module 11 is configured to: determine the intersection of the first-layer metal wire and the second-layer metal wire as a power supply sub-node;
  • a parasitic element is arranged between every two power supply sub-nodes, and the parasitic element includes a first parasitic resistance, a second parasitic resistance and a parasitic capacitance, wherein the first end of the first parasitic resistance is connected to the first power supply sub-node, and the first parasitic resistance The second end of the second parasitic resistance is connected to the first end of the second parasitic resistance and the first end of the parasitic capacitance; the second end of the second parasitic resistance is connected to the second power supply sub-node; the second end of the parasitic capacitance is connected to the ground terminal;
  • the power line topology network is obtained.
  • the resistance values of the first parasitic resistance and the second parasitic resistance are both R/2, and the capacitance value of the parasitic capacitance is C;
  • R and C are determined by the following formulas:
  • L is the length of the metal line between the power supply sub-nodes
  • W is the width of the metal line between the power supply sub-nodes
  • Rsh is the square resistance value of the metal
  • Cu is the capacitance value per unit area.
  • the determination module 12 is used to:
  • circuit simulation is performed to obtain the voltage waveform of the power supply input node of each circuit module
  • the minimum voltage of the power input node of each circuit module is determined according to the voltage waveform of the power input node of each circuit module.
  • the determining module 12 is configured to: set a current source for each circuit module according to the current of each circuit module, so as to obtain a test circuit;
  • the circuit simulation of the test circuit is carried out, and the voltage waveform of the power supply input node of each circuit module is obtained.
  • the simulation module 13 is configured to add the minimum voltage of the power input node of each circuit module to the power input node of each circuit module to obtain an embedded minimum voltage circuit;
  • the apparatus provided in the embodiment of the present application can execute the foregoing method embodiment, and for the implementation principle and technical effect, reference may be made to the foregoing method embodiment, and details are not described herein again in this embodiment.
  • FIG. 11 is a schematic structural diagram of a simulation apparatus provided by an embodiment of the present application.
  • the simulation apparatus of this embodiment may include: a memory 101 and a processor 102,
  • the memory 101 is used for storing executable instructions of the processor 102;
  • processor 102 is configured to:
  • the power line topology network is generated according to the power line layout.
  • the power line topology network includes a plurality of first-layer metal wires arranged horizontally, a plurality of second-layer metal wires arranged vertically, power sub-nodes and parasitic elements.
  • the parasitic elements are located in two layers. between power supply sub-nodes;
  • Timing simulation is performed according to the minimum voltage of the power input node of each circuit module and the post-integration circuit netlist.
  • the memory 101 may be independent or integrated with the processor 102 .
  • the emulation apparatus of this embodiment may further include:
  • the bus 103 is used to connect the memory 101 and the processor 102 .
  • this embodiment further includes: a communication interface 104 , where the communication interface 104 can be connected to the processor 102 through the bus 103 .
  • the apparatus may be used to execute each step and/or process in the above method embodiments.
  • Embodiments of the present application further provide a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium runs on the computer, the computer executes the method in the foregoing embodiment.
  • Embodiments of the present application further provide a computer program product, including a computer program, and when the computer program is executed by a processor, the method of the foregoing embodiment is implemented.
  • Embodiments of the present application further provide a power line topology network and a test circuit, which are described below with reference to FIG. 3 , FIG. 4 , and FIG. 7 .
  • An embodiment of the present application provides a power line topology network, including: a plurality of first-layer metal lines arranged horizontally, a plurality of second-layer metal lines arranged vertically, a power supply sub-node, and a parasitic element, wherein the parasitic element is located in two Between power supply sub-nodes, wherein, the intersection of the first-layer metal wire and the second-layer metal wire is the power supply sub-node.
  • the power line topology network includes a plurality of first-layer metal wires M1 arranged horizontally and a plurality of second-layer metal wires M2 arranged vertically. , power supply sub-nodes (VDD11-VDD31) and parasitic element Q, wherein the intersection of the first-layer metal line M1 and the second-layer metal line M2 is the power supply sub-node, and the parasitic element is located between the two power supply sub-nodes. There is a parasitic element between the two power supply sub-nodes.
  • the parasitic element includes a first parasitic resistance, a second parasitic resistance and a parasitic capacitance, wherein a first end of the first parasitic resistance is connected to the first power supply sub-node, and a second end of the first parasitic resistance is connected to the second parasitic resistance
  • the first end of the parasitic capacitor is connected to the first end of the parasitic capacitor
  • the second end of the second parasitic resistance is connected to the second power supply sub-node
  • the second end of the parasitic capacitor is connected to the ground terminal.
  • the parasitic element Q includes a first parasitic resistance R1, a second parasitic resistance R2 and a parasitic capacitance C1, and the power supply sub-node VDD31 and the power supply sub-node VDD32.
  • the first end of the first parasitic resistance R1 is connected to the first power supply sub-node VDD31
  • the second end of the first parasitic resistance R1 is connected to the first end of the second parasitic resistance R2 and the first end of the parasitic capacitor C1.
  • One end, the second end of the second parasitic resistor R2 is connected to the second power supply sub-node VDD32, and the second end of the parasitic capacitor C1 is connected to the ground.
  • the resistance values of the first parasitic resistance and the second parasitic resistance are both R/2, and the capacitance value of the parasitic capacitance is C;
  • R and C are determined by the following formulas:
  • L is the length of the metal line between the power supply sub-nodes
  • W is the width of the metal line between the power supply sub-nodes
  • Rsh is the square resistance value of the metal
  • Cu is the capacitance value per unit area.
  • the power line topology networks shown in FIG. 3 and FIG. 4 are just examples, and the numbers of the first-layer metal wires M1 and the second-layer metal wires M2 can be arbitrarily set in the actual design.
  • the power line topology network provided in this embodiment can be used to implement the above simulation method.
  • the power line topology network can be directly simulated by using S102-S103 in the simulation method shown in FIG.
  • the simulation speed is improved, and the timing simulation considers the minimum voltage of the power input node of each circuit module.
  • the difference between the minimum voltage and the ideal power supply voltage is the power line voltage drop, so the power line voltage drop can be evaluated through normal timing simulation.
  • the influence of the timing parameters of the integrated circuit can improve the simulation accuracy, thus realizing a compromise between the simulation accuracy and the simulation speed.
  • An embodiment of the present application further provides a test circuit, including at least one current source and the power line topology network in the above embodiment, such as the power line topology network shown in FIG. 3 or FIG. 4 , in the test circuit, each current source
  • the input current is the current of each circuit module in the circuit corresponding to the power line topology network
  • the number of current sources is the same as the number of circuit modules included in the circuit corresponding to the power line topology network.
  • the first terminal of each current source is connected to the power input node of each circuit module
  • the second terminal of each current source is connected to the ground terminal
  • the power input node is one of the power supply sub-nodes in each circuit module. one of.
  • the current of each circuit module in the circuit corresponding to the power line topology network is obtained by performing the first simulation with a preset power supply voltage according to the power line topology network.
  • the test circuit shown in Figure 7 there are a total of 6 current sources, the number of current sources is the same as the number of circuit modules 6, and the first end of each current source P is connected to each The power input node of the circuit module, the second end of each current source P is connected to the ground terminal.
  • the circuit module X1 the first end of the current source P is connected to the power input node VDD31 of the circuit module X1, and the second end of the current source P is connected to the power input node VDD31 of the circuit module X1. terminal is connected to the ground terminal.
  • the test circuit provided in this embodiment can be used in the above simulation method to determine the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network.
  • the voltage waveform of the power input node of the circuit module, the minimum voltage of the power input node of each circuit module can be determined according to the voltage waveform of the power input node of each circuit module, so that the minimum voltage of the power input node of each circuit module can be determined according to the minimum voltage of the power input node of each circuit module.

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Abstract

一种仿真方法、装置、电源线拓扑网络、测试电路及存储介质，该方法包括：根据电源线版图生成电源线拓扑网络，电源线拓扑网络包括横向排布的多条第一层金属线、纵向排布的多条第二层金属线、电源子节点和寄生元件，寄生元件位于两个电源子节点之间（S101）；确定与电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，电源输入节点为每个电路模块中的电源子节点中的一个（S102）；根据每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真（S103）。该方法可以通过正常的时序仿真来评估电源线电压降对集成电路时序参数的影响，提高仿真精度和仿真速度。

Description

仿真方法、装置、电源线拓扑网络、测试电路及存储介质
本申请要求于2021年01月19日提交中国专利局、申请号为202110070959.2、申请名称为“仿真方法、装置、电源线拓扑网络、测试电路及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及但不限于一种仿真方法、装置、电源线拓扑网络、测试电路及存储介质。
背景技术
目前，在集成电路设计中，集成电路设计的设计流程包括电路设计及前仿真、版图设计和后仿真等流程。其中，电路设计具体是依据电路功能完成电路的设计，前仿真具体是进行电路功能的仿真，包括功耗、电流、电压、温度、输入输出特性等参数的仿真。前仿真不考虑电路中金属线走线产生的寄生电容电阻的影响，在版图设计完成后，再提取寄生电容电阻，并将提取的寄生电容电阻添加到电路中进行后仿真和电路设计验证优化，如果验证失败，则调整版图设计直至验证通过确定出最终的版图。
上述仿真过程中，一方面需要反复验证，另一方面由于包括寄生电容电阻的版图后仿真的网表规模非常大，仿真时间长，导致仿真速度很慢。
发明内容
本申请实施例提供一种仿真方法，包括：
根据电源线版图生成电源线拓扑网络，所述电源线拓扑网络包括横向排布的多条第一层金属线、纵向排布的多条第二层金属线、电源子节点和寄生元件，所述寄生元件位于两个电源子节点之间；
确定与所述电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，所述电源输入节点为所述每个电路模块中的电源子节点中的一个；
根据所述每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真。
本申请实施例还提供一种仿真装置，包括：存储器和处理器；
所述存储器用于存储所述处理器的可执行指令；
其中，所述处理器被配置为：
根据电源线版图生成电源线拓扑网络，所述电源线拓扑网络包括横向排布的多条第一层金属线、纵向排布的多条第二层金属线、电源子节点和寄生元件，所述寄生元件位于两个电源子节点之间；
确定与所述电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，所述电源输入节点为每个电路模块中的电源子节点中的一个；
根据所述每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真。
本申请实施例还提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，所述计算机执行指令被处理器执行时用于实现第一方面和第一方面各可能的实施方式中任一所述的方法。
本申请实施例还提供一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时实现第一方面和第一方面各可能的实施方式中任一所述的方法。
本申请实施例还提供一种电源线拓扑网络，包括：
横向排布的多条第一层金属线、纵向排布的多条第二层金属线、电源子节点和寄生元件，所述寄生元件位于两个所述电源子节点之间；
其中，所述第一层金属线与所述第二层金属线的交叉点为所述电源子节点。
本申请实施例还提供一种测试电路，包括至少一个电流源和如第五方面和第五方面各可能的实施方式中任一所述的电源线拓扑网络；
其中，每个所述电流源的输入电流为与所述电源线拓扑网络对应的电路中每个电路模块的电流；
所述电流源的数量和与所述电源线拓扑网络对应的电路中包括的电路模块的数量相同。
附图说明
为了更清楚地说明本申请或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种仿真方法的流程示意图；
图2为一种电源线版图的示意图；
图3为根据图2所示的电源线版图生成的一种电源线拓扑网络的示意图；
图4为根据图2所示的电源线版图生成的一种电源线拓扑网络的示意图；
图5为与图3所示电源线拓扑网络对应的电路包括的电路模块示意图；
图6为本申请实施例提供的一种仿真方法的流程示意图；
图7为与图4对应的测试电路结构示意图；
图8为本申请实施例提供的一种仿真方法的流程示意图；
图9为将所述每个电路模块的电源输入节点的最小电压加入到所述每个电路模块的电源输入节点得到的电路结构示意图；
图10为本申请实施例提供的一种仿真装置的结构示意图；
图11为本申请实施例提供的一种仿真装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
现有的集成电路设计流程中，在后仿真中，如果包括电源线版图寄生电容电阻的后仿真的网表规模非常大，这样导致仿真时间非常长，无法满足实际项目需求。而如果后仿真网表中不包括电源线寄生元件，这样将无法正确评估电源版图寄生对电路时序特性的影响，从而降低仿真精度。为解决这一问题，本申请提供一种仿真方法、装置、电源线拓扑网络、测试电路及存储介质，本申请提供的仿真方法中，通过先根据电源线版图生成电源线拓扑网络，接着确定出与电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，最后根据每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真，其中的集成电路后仿真电路网表是不包括寄生电容电阻的版图后仿真的网表，即仿真时间与不包括电源寄生效应的前仿真时间近似相同，因此可以快速得到后仿真结果，提高了仿真速度，且时序仿真考虑了每个电路模块的电源输入节点的最小电压，最小电压与理想的电源电压之差为电源线电压降，因此可以通过正常的时序仿真来评估电源线电压降(业界术语是IR-Drop)对集成电路时序参数的影响，可以提高仿真精度，其中的时序参数例如包括时延等时序参数，从而实现了仿真精度和仿真速度的折中。
本申请提供的仿真方法，可应用于版图设计前，版图设计中，电源线版图中电源线电压降会对集成电路的时序参数产生影响，本申请提供的仿真方法通过根据电源线版图生成 电源线拓扑网络，确定出与电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，即确定出电源线电压降，根据每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真，可以通过仿真结果来评估电源线电压降对集成电路时序参数的影响，可对集成电路设计提供指导意见。当版图设计完成后，提取整个电路的寄生电阻和寄生电容，并进行后仿真，根据后仿真结果可再次检查时序的结果，为版图设计提供最终的指导意见，因此，可以降低版图设计的误差，降低集成电路设计的开发周期和开发成本。
下面通过实施例，对本申请提供的仿真方法、装置、电源线拓扑网络、测试电路及存储介质的流程/结构进行详细说明。
图1为本申请实施例提供的一种仿真方法的流程示意图，本实施例的仿真方法的执行主体可以为仿真装置或仿真设备，可应用于版图设计之前，如图1所示，本实施例的仿真方法可以包括：
S101、根据电源线版图生成电源线拓扑网络，电源线拓扑网络包括横向排布的多条第一层金属线、纵向排布的多条第二层金属线、电源子节点和寄生元件，寄生元件位于两个电源子节点之间。
在一些实施例中，图2为一种电源线版图的示意图，如图2所示，该电源线版图由四条第一层金属线M1和三条第二层金属线M2组成，第一层金属线M1可以位于第二层金属线M2之上或之下，每条第一层金属线M1和每条第二层金属线有交叉点。
根据电源线版图生成电源线拓扑网络，以图2所示的电源线版图为例，图3为根据图2所示的电源线版图生成的一种电源线拓扑网络的示意图，如图3所示，电源线拓扑网络包括横向排布的多条第一层金属线M1、纵向排布的多条第二层金属线M2、电源子节点(VDD11-VDD31)和寄生元件Q，其中，电源线版图中第一层金属线与第二层金属线的交叉点即为电源子节点，寄生元件位于两个电源子节点之间，每两个电源子节点之间均有一个寄生元件。
其中，根据电源线版图生成电源线拓扑网络，作为一种可实施的方式，可以为：
S1011、将第一层金属线与第二层金属线的交叉点确定为电源子节点。
S1012、在每两个电源子节点之间设置寄生元件，寄生元件包括第一寄生电阻、第二寄生电阻和寄生电容。其中，第一寄生电阻的第一端连接第一电源子节点，第一寄生电阻的第二端连接第二寄生电阻的第一端和寄生电容的第一端；第二寄生电阻的第二端连接第二电源子节点；寄生电容的第二端连接接地端。
S1013、根据第一层金属线、第二层金属线、电源子节点和寄生元件，得到电源线拓 扑网络。
以图2所示的电源线版图为例，图4为根据图2所示的电源线版图生成的一种电源线拓扑网络的示意图，如图4所示，在每两个电源子节点之间设置寄生元件Q，寄生元件Q包括第一寄生电阻R1、第二寄生电阻R2和寄生电容C1，以电源子节点VDD31和电源子节点VDD32之间的寄生元件为例，第一寄生电阻R1的第一端连接第一电源子节点VDD31，第一寄生电阻R1的第二端连接第二寄生电阻R2的第一端和寄生电容C1的第一端，第二寄生电阻R2的第二端连接第二电源子节点VDD32，寄生电容C1的第二端连接接地端。
其中，第一寄生电阻R1和第二寄生电阻R2的阻值均为R/2，寄生电容的电容值为C，R和C通过如下公式确定：
R＝Rsh*L/W；
C＝Cu*L*W；
其中，L为电源子节点之间金属线的长度，W为电源子节点之间金属线的宽度，Rsh为金属的方块阻值，Cu为单位面积的电容值。
可以理解的是，不同的电源子节点之间的金属线的长度和宽度均不同，在生成电源线拓扑网络进行后续的仿真时，可以根据经验值设置电源子节点之间的金属线的初始长度和初始宽度，得到初始电源线拓扑网络，接着根据初始电源线拓扑网络通过S102和S103进行时序仿真，根据仿真结果可以调整初始电源线拓扑网络中每两个电源子节点之间的金属线的长度和宽度，得到调整后的电源线拓扑网络，再根据调整后的电源线拓扑网络通过S102和S103进行时序仿真，直到通过仿真确定出电源线电压降对集成电路时序参数的影响较小的电源线拓扑网络。每两个电源子节点之间的金属线的长度和宽度具体的调整规则本申请实施例不做限制。
S102、确定与电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，电源输入节点为每个电路模块中的电源子节点中的一个。
在一些实施例中，以图3或图4所示的电源线拓扑网络为例，图5为与图3所示电源线拓扑网络对应的电路包括的电路模块示意图，如图5所示，与图3所示电源线拓扑网络对应的电路包括6个电路模块(X1-X6)，每个电路模块的电源输入节点为图5中所示的VDD，可以看出，每个电路模块的电源输入节点为每个电路模块中的电源子节点中的一个。
其中，确定与电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，以图5所示电路模块为例，即就是确定电路模块X1-X6中每个电路模块的电源输入节点VDD的最小电压。
S103、根据每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行 时序仿真。
其中，集成电路后仿真电路网表为不包括寄生电容电阻的版图后仿真的网表，经S103得到的仿真结果为考虑到最大电压降影响的时序分析结果。
本实施例提供的仿真方法，通过先根据电源线版图生成电源线拓扑网络，接着确定出与电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，最后根据每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真，其中的集成电路后仿真电路网表是不包括寄生电容电阻的版图后仿真的网表，即仿真时间与不包括电源寄生效应的前仿真时间近似相同，因此可以快速得到后仿真结果，提高了仿真速度，且时序仿真考虑了每个电路模块的电源输入节点的最小电压，最小电压与理想的电源电压之差为电源线电压降，因此可以通过正常的时序仿真来评估电源线电压降对集成电路时序参数的影响，可以提高仿真精度，从而实现了仿真精度和仿真速度的折中。
图6为本申请实施例提供的一种仿真方法的流程示意图，如图6所示，本实施例的仿真方法在图5所示方法的基础上，可选的，上述S102可以通过如下步骤实现：
S1021、根据电源线拓扑网络以预设电源电压进行第一次仿真，得到与电源线拓扑网络对应的电路中每个电路模块的电流。
在一些实施例中，以图5所示的6个电路模块为例，根据图4所示的电源线拓扑网络以预设电源电压进行第一次仿真，得到6个电路模块的电流如下表一所示：
表一6个电路模块的电流
电路模块 电流
X1 I1(t)
X2 I2(t)
X3 I3(t)
X4 I4(t)
X5 I5(t)
X6 I6(t)
其中，电流In(t)，n＝1,2，…，6为一个随时间变化的曲线。
S1022、根据电源子节点之间的寄生元件以及每个电路模块的电流，进行电路仿真，得到每个电路模块的电源输入节点的电压波形。
作为一种可实施的方式，上述S1022可以包括：
首先，根据每个电路模块的电流为每个电路模块设置电流源，得到测试电路。
在一些实施例中，可以是为电源线拓扑网络设置电流源，每个电路模块设置一个电流源，电流源的数量和与电源线拓扑网络对应的电路中包括的电路模块的数量相同，所设置的每个电流源的输入电流为每个电路模块的电流In(t)，得到测试电路。
以图4所示的电源线拓扑网络为例，图7为与图4对应的测试电路结构示意图，本实施例的测试电路也称为电压降(IR Drop)测试电路，如图7所示，每个电流源P的第一端连接每个电路模块的电源输入节点，每个电流源P的第二端连接接地端，以电路模块X1为例，电流源P的第一端连接电路模块X1的电源输入节点VDD31，电流源P的第二端连接接地端。
接着，根据电源子节点之间的寄生元件以及每个电路模块的电流，对测试电路进行电路仿真，得到每个电路模块的电源输入节点的电压波形。
在一些实施例中，得到测试电路后，对测试电路进行电路仿真，得到每个电路模块的电源输入节点的电压波形。以图7所示的测试电路为例，针对测试电路中的每一电路模块，如以电路模块X1为例，根据电路模块X1的电流In(t)和电路模块X1中的电源子节点VDD31和电源子节点VDD32之间的寄生元件Q，进行电路仿真，可以通过仿真电路模拟器(Simulation program with integrated circuit emphasis，Spice)进行仿真，得到电路模块X1的电源输入节点VDD31的电压波形VDD31(t)，这里是以一个电路模块X1为例进行说明。可以理解的是，对测试电路进行仿真，可以得到6个电路模块的电源输入节点的电压波形VDD31(t)～VDD24(t)。
S1023、根据每个电路模块的电源输入节点的电压波形确定每个电路模块的电源输入节点的最小电压。
在一些实施例中，电压波形是随时间变化的电压值的波形图，根据电压波形可以找出每个电压波形的最小电压值，即为每个电路模块的电源输入节点的最小电压，为某一时刻的电压，下表二中记为VDDn min。表二中为图7所示的测试电路中每个模块对应的电流In(t)、每个电路模块的电源输入节点的电压波形VDDn(t)和每个电路模块的电源输入节点的最小电压VDDn min的对应关系。
表二
Figure PCTCN2021104786-appb-000001
本实施例提供的仿真方法，通过根据电源线拓扑网络以预设电源电压进行第一次仿真，得到与电源线拓扑网络对应的电路中每个电路模块的电流，根据电源子节点之间的寄生元件以及每个电路模块的电流，进行电路仿真，得到每个电路模块的电源输入节点的电压波形，根据每个电路模块的电源输入节点的电压波形确定每个电路模块的电源输入节点的最小电压，从而，确定出了与电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压。
图8为本申请实施例提供的一种仿真方法的流程示意图，如图8所示，本实施例的仿真方法在图6所示方法的基础上，可选的，上述S103可以通过如下步骤实现：
S1031、将每个电路模块的电源输入节点的最小电压加入到每个电路模块的电源输入节点，得到嵌入最小电压的电路。
在一些实施例中，图9为将每个电路模块的电源输入节点的最小电压加入到每个电路模块的电源输入节点得到的电路结构示意图。
S1032、根据集成电路后仿真电路网表对嵌入最小电压的电路进行时序仿真。
在一些实施例中，根据集成电路后仿真电路网表对嵌入最小电压的电路进行时序仿真，得到的仿真结果即为考虑了最大电压降影响的时序分析结果。通过本实施例的仿真方法，在不增加仿真时间的基础上，准确评估了电源线电压降对集成电路时序参数的影响，所有结果均基于Spice和版图后仿真网表，保证了仿真精度，从而实现了仿真精度和仿真速度的折中。
图10为本申请实施例提供的一种仿真装置的结构示意图，如图10所示，本实施例的仿真装置可以包括：生成模块11、确定模块12和仿真模块13，其中，生成模块11用于根据电源线版图生成电源线拓扑网络，电源线拓扑网络包括横向排布的多条第一层金属线、 纵向排布的多条第二层金属线、电源子节点和寄生元件，寄生元件位于两个电源子节点之间。
确定模块12用于确定与电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，电源输入节点为每个电路模块中的电源子节点中的一个。
仿真模块13用于根据每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真。
在一些实施例中，生成模块11用于：将第一层金属线与第二层金属线的交叉点确定为电源子节点；
在每两个电源子节点之间设置寄生元件，寄生元件包括第一寄生电阻、第二寄生电阻和寄生电容，其中，第一寄生电阻的第一端连接第一电源子节点，第一寄生电阻的第二端连接第二寄生电阻的第一端和寄生电容的第一端；第二寄生电阻的第二端连接第二电源子节点；寄生电容的第二端连接接地端；
根据第一层金属线、第二层金属线、电源子节点和寄生元件，得到电源线拓扑网络。
在一些实施例中，第一寄生电阻和第二寄生电阻的阻值均为R/2，寄生电容的电容值为C；
R和C通过如下公式确定：
R＝Rsh*L/W；
C＝Cu*L*W；
其中，L为电源子节点之间金属线的长度，W为电源子节点之间金属线的宽度，Rsh为金属的方块阻值，Cu为单位面积的电容值。
在一些实施例中，确定模块12用于：
根据电源线拓扑网络以预设电源电压进行第一次仿真，得到与电源线拓扑网络对应的电路中每个电路模块的电流；
根据电源子节点之间的寄生元件以及每个电路模块的电流，进行电路仿真，得到每个电路模块的电源输入节点的电压波形；
根据每个电路模块的电源输入节点的电压波形确定每个电路模块的电源输入节点的最小电压。
在一些实施例中，确定模块12用于：根据每个电路模块的电流为每个电路模块设置电流源，得到测试电路；
根据电源子节点之间的寄生元件以及每个电路模块的电流，对测试电路进行电路仿真，得到每个电路模块的电源输入节点的电压波形。
在一些实施例中，仿真模块13用于将每个电路模块的电源输入节点的最小电压加入到每个电路模块的电源输入节点，得到嵌入最小电压电路；
根据集成电路后仿真电路网表对嵌入最小电压的电路进行时序仿真。
本申请实施例提供的装置，可执行上述方法实施例，其实现原理和技术效果，可参见上述方法实施例，本实施例此处不再赘述。
图11为本申请实施例提供的一种仿真装置的结构示意图，如图11所示，本实施例的仿真装置可以包括：存储器101和处理器102，
其中，存储器101用于存储处理器102的可执行指令；
其中，处理器102被配置为：
根据电源线版图生成电源线拓扑网络，电源线拓扑网络包括横向排布的多条第一层金属线、纵向排布的多条第二层金属线、电源子节点和寄生元件，寄生元件位于两个电源子节点之间；
确定与电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，电源输入节点为每个电路模块中的电源子节点中的一个；
根据每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真。
可选地，存储器101既可以是独立的，也可以跟处理器102集成在一起。
当存储器101是独立于处理器102之外的器件时，本实施例的仿真装置还可以包括：
总线103，用于连接存储器101和处理器102。
可选地，本实施例还包括：通信接口104，该通信接口104可以通过总线103与处理器102连接。
该装置可以用于执行上述方法实施例中的各个步骤和/或流程。
本申请实施例还提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，当其在计算机上运行时，使得计算机执行如上述实施例的方法。
本申请实施例还提供一种计算机程序产品，包括计算机程序，计算机程序被处理器执行时实现上述实施例的方法。
本申请实施例还提供一种电源线拓扑网络和测试电路，下面结合图3、图4和图7进行说明。
本申请实施例提供一种电源线拓扑网络，包括：横向排布的多条第一层金属线、纵向排布的多条第二层金属线、电源子节点和寄生元件，寄生元件位于两个电源子节点之间，其中，第一层金属线与第二层金属线的交叉点为电源子节点。
以图3所示的电源线拓扑网络为例，如图3所示，该电源线拓扑网络包括横向排布的多条第一层金属线M1、纵向排布的多条第二层金属线M2、电源子节点(VDD11-VDD31)和寄生元件Q，其中，第一层金属线M1与第二层金属线M2的交叉点即为电源子节点，寄生元件位于两个电源子节点之间，每两个电源子节点之间均有一个寄生元件。
可选的，寄生元件包括第一寄生电阻、第二寄生电阻和寄生电容，其中，第一寄生电阻的第一端连接第一电源子节点，第一寄生电阻的第二端连接第二寄生电阻的第一端和寄生电容的第一端，第二寄生电阻的第二端连接第二电源子节点，寄生电容的第二端连接接地端。
以图4所示的电源线拓扑网络为例，如图4所示，寄生元件Q包括第一寄生电阻R1、第二寄生电阻R2和寄生电容C1，以电源子节点VDD31和电源子节点VDD32之间的寄生元件Q为例，第一寄生电阻R1的第一端连接第一电源子节点VDD31，第一寄生电阻R1的第二端连接第二寄生电阻R2的第一端和寄生电容C1的第一端，第二寄生电阻R2的第二端连接第二电源子节点VDD32，寄生电容C1的第二端连接接地端。
可选的，第一寄生电阻和第二寄生电阻的阻值均为R/2，寄生电容的电容值为C；
R和C通过如下公式确定：
R＝Rsh*L/W；
C＝Cu*L*W；
其中，L为电源子节点之间金属线的长度，W为电源子节点之间金属线的宽度，Rsh为金属的方块阻值，Cu为单位面积的电容值。
需要说明的是，图3和图4所示的电源线拓扑网络只是示例，实际设计中第一层金属线M1和第二层金属线M2的条数可以任意设置。
本实施例提供的电源线拓扑网络，可以用于实现上述仿真方法，例如可以直接对电源线拓扑网络通过使用图1所示的仿真方法中S102-S103进行仿真，可以快速得到后仿真结果，提高了仿真速度，且时序仿真考虑了每个电路模块的电源输入节点的最小电压，最小电压与理想的电源电压之差为电源线电压降，因此可以通过正常的时序仿真来评估电源线电压降对集成电路时序参数的影响，可以提高仿真精度，从而实现了仿真精度和仿真速度的折中。
本申请实施例还提供一种测试电路，包括至少一个电流源和上述实施例中的电源线拓扑网络，如图3或图4所示的电源线拓扑网络，该测试电路中，每个电流源的输入电流为与电源线拓扑网络对应的电路中每个电路模块的电流，电流源的数量和与电源线拓扑网络对应的电路中包括的电路模块的数量相同。
在一些实施例中，每个电流源的第一端连接每个电路模块的电源输入节点，每个电流源的第二端连接接地端，电源输入节点为每个电路模块中的电源子节点中的一个。
其中，可选的，与电源线拓扑网络对应的电路中每个电路模块的电流根据电源线拓扑网络以预设电源电压进行第一次仿真得到。
以图7所示的测试电路为例，图7所示的测试电路中，共有6个电流源，电流源的数量和电路模块的数量6相同，每个电流源P的第一端连接每个电路模块的电源输入节点，每个电流源P的第二端连接接地端，以电路模块X1为例，电流源P的第一端连接电路模块X1的电源输入节点VDD31，电流源P的第二端连接接地端。
本实施例提供的测试电路，可以用于上述仿真方法中如何确定与电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，通过测试电路可直接进行电路仿真，得到每个电路模块的电源输入节点的电压波形，根据每个电路模块的电源输入节点的电压波形可以确定每个电路模块的电源输入节点的最小电压，从而可根据每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种仿真方法，包括：
    根据电源线版图生成电源线拓扑网络，所述电源线拓扑网络包括横向排布的多条第一层金属线、纵向排布的多条第二层金属线、电源子节点和寄生元件，所述寄生元件位于两个电源子节点之间；
    确定与所述电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，所述电源输入节点为所述每个电路模块中的电源子节点中的一个；
    根据所述每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真。
  2. 根据权利要求1所述的方法，其中，所述根据电源线版图生成电源线拓扑网络，包括：
    将所述第一层金属线与所述第二层金属线的交叉点确定为所述电源子节点；
    在每两个所述电源子节点之间设置所述寄生元件，所述寄生元件包括第一寄生电阻、第二寄生电阻和寄生电容，其中，所述第一寄生电阻的第一端连接第一电源子节点，所述第一寄生电阻的第二端连接所述第二寄生电阻的第一端和所述寄生电容的第一端；所述第二寄生电阻的第二端连接第二电源子节点；所述寄生电容的第二端连接接地端；
    根据所述第一层金属线、所述第二层金属线、所述电源子节点和所述寄生元件，得到所述电源线拓扑网络。
  3. 根据权利要求2所述的方法，其中，所述第一寄生电阻和所述第二寄生电阻的阻值均为R/2，所述寄生电容的电容值为C；
    所述R和所述C通过如下公式确定：
    R＝Rsh*L/W；
    C＝Cu*L*W；
    其中，所述L为所述电源子节点之间金属线的长度，所述W为所述电源子节点之间金属线的宽度，所述Rsh为金属的方块阻值，所述Cu为单位面积的电容值。
  4. 根据权利要求1所述的方法，其中，所述确定与所述电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，包括：
    根据所述电源线拓扑网络以预设电源电压进行第一次仿真，得到与所述电源线拓扑网络对应的电路中每个电路模块的电流；
    根据所述电源子节点之间的寄生元件以及所述每个电路模块的电流，进行电路仿真，得到所述每个电路模块的电源输入节点的电压波形；
    根据所述每个电路模块的电源输入节点的电压波形确定所述每个电路模块的电源输入节点的最小电压。
  5. 根据权利要求4所述的方法，其中，所述根据所述电源子节点之间的寄生元件以及所述每个电路模块的电流，进行电路仿真，得到所述每个电路模块的电源输入节点的电压波形，包括：
    根据所述每个电路模块的电流为所述每个电路模块设置电流源，得到测试电路；
    根据所述电源子节点之间的寄生元件以及所述每个电路模块的电流，对所述测试电路进行电路仿真，得到所述每个电路模块的电源输入节点的电压波形。
  6. 根据权利要求1所述的方法，其中，所述根据所述每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真，包括：
    将所述每个电路模块的电源输入节点的最小电压加入到所述每个电路模块的电源输入节点，得到嵌入最小电压电路；
    根据集成电路后仿真电路网表对所述嵌入最小电压的电路进行时序仿真。
  7. 一种仿真装置，包括：存储器和处理器；
    所述存储器用于存储所述处理器的可执行指令；
    其中，所述处理器被配置为：
    根据电源线版图生成电源线拓扑网络，所述电源线拓扑网络包括横向排布的多条第一层金属线、纵向排布的多条第二层金属线、电源子节点和寄生元件，所述寄生元件位于两个电源子节点之间；
    确定与所述电源线拓扑网络对应的电路中每个电路模块的电源输入节点的最小电压，所述电源输入节点为每个电路模块中的电源子节点中的一个；
    根据所述每个电路模块的电源输入节点的最小电压和集成电路后仿真电路网表进行时序仿真。
  8. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，所述计算机执行指令被处理器执行时用于实现如权利要求1至6任一项所述的方法。
  9. 一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时实现如权利要求1至6任一项所述的方法。
  10. 一种电源线拓扑网络，包括：
    横向排布的多条第一层金属线、纵向排布的多条第二层金属线、电源子节点和寄 生元件，所述寄生元件位于两个所述电源子节点之间；
    其中，所述第一层金属线与所述第二层金属线的交叉点为所述电源子节点。
  11. 根据权利要求10所述的电源线拓扑网络，其中，所述寄生元件包括第一寄生电阻、第二寄生电阻和寄生电容；
    其中，所述第一寄生电阻的第一端连接第一电源子节点，所述第一寄生电阻的第二端连接所述第二寄生电阻的第一端和所述寄生电容的第一端；
    所述第二寄生电阻的第二端连接第二电源子节点；
    所述寄生电容的第二端连接接地端。
  12. 根据权利要求11所述的电源线拓扑网络，其中，所述第一寄生电阻和所述第二寄生电阻的阻值均为R/2，所述寄生电容的电容值为C；
    所述R和所述C通过如下公式确定：
    R＝Rsh*L/W；
    C＝Cu*L*W；
    其中，所述L为所述电源子节点之间金属线的长度，所述W为所述电源子节点之间金属线的宽度，所述Rsh为金属的方块阻值，所述Cu为单位面积的电容值。
  13. 一种测试电路，包括至少一个电流源和如权利要求10-12任一项所述的电源线拓扑网络；
    其中，每个所述电流源的输入电流为与所述电源线拓扑网络对应的电路中每个电路模块的电流；
    所述电流源的数量和与所述电源线拓扑网络对应的电路中包括的电路模块的数量相同。
  14. 根据权利要求13所述的测试电路，其中，每个所述电流源的第一端连接所述每个电路模块的电源输入节点，每个所述电流源的第二端连接接地端，所述电源输入节点为所述每个电路模块中的电源子节点中的一个。
  15. 根据权利要求13所述的测试电路，其中，与所述电源线拓扑网络对应的电路中每个电路模块的电流根据所述电源线拓扑网络以预设电源电压进行第一次仿真得到。
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