WO2022037066A1 - 有机发光显示面板以及驱动方法 - Google Patents

有机发光显示面板以及驱动方法 Download PDF

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Publication number
WO2022037066A1
WO2022037066A1 PCT/CN2021/083265 CN2021083265W WO2022037066A1 WO 2022037066 A1 WO2022037066 A1 WO 2022037066A1 CN 2021083265 W CN2021083265 W CN 2021083265W WO 2022037066 A1 WO2022037066 A1 WO 2022037066A1
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Prior art keywords
light
row
emitting
electrically connected
pixel
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PCT/CN2021/083265
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English (en)
French (fr)
Inventor
周志伟
钱栋
沈永财
李嘉灵
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上海视涯技术有限公司
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Priority to US17/641,272 priority Critical patent/US11694616B2/en
Publication of WO2022037066A1 publication Critical patent/WO2022037066A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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    • G09G2330/025—Reduction of instantaneous peaks of current

Definitions

  • the present application relates to display technology, for example, to an organic light-emitting display panel and a driving method.
  • the organic light emitting display panel includes a plurality of sub-pixels arranged in an array.
  • Each sub-pixel includes a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit.
  • Each light-emitting element in the related art includes a stacked anode, a hole-assisted transport layer, a light-emitting layer, an electron-assisted transport layer, and a cathode.
  • the hole-assisted transport layer, the light-emitting layer and the electron-assisted transport layer of the light-emitting elements of different colors are all integral film layers, and the hole-assisted transport layer of each light-emitting element , the light-emitting layer, and the electron-assisted transport layer were not interrupted.
  • the hole-assisted transport layer, the light-emitting layer and the electron-assisted transport layer of adjacent light-emitting elements are all integral film layers, when a light-emitting element emits light, some of the holes injected by the anode of the light-emitting element will be assisted by holes.
  • the transmission layer is transmitted to the adjacent light-emitting elements, resulting in lateral leakage current, which will affect the signal voltage of the adjacent light-emitting elements, resulting in blurring and color mixing of the image.
  • the present application provides an organic light-emitting display panel and a driving method, so as to avoid the problem of leakage current between adjacent light-emitting elements affecting the display effect.
  • an embodiment of the present application provides an organic light-emitting display panel, comprising: a plurality of pixel units, each pixel unit comprising a plurality of sub-pixels of different colors; the sub-pixels include a pixel driving circuit and a A light-emitting element electrically connected to a driving circuit; the light-emitting element includes a common layer; the common layer adjacent to the light-emitting element is arranged and connected in the same layer;
  • At least part of the number of sub-pixel columns, two adjacent sub-pixels along the column direction have different emission colors
  • the pixel driving circuits of each sub-pixel in the same row of pixel units are connected to the same light-emitting control signal line; when the light-emitting control signal line transmits an effective light-emitting control pulse, the sub-pixels to which the pixel driving circuit electrically connected to the light-emitting control signal line belongs are located in the same light-emitting control signal line. luminous stage;
  • the pixel drive circuits of each sub-pixel in the same row of pixel units are connected to the same reset control signal line; when the reset control signal line transmits a valid reset pulse, the sub-pixels to which the pixel drive circuits electrically connected to the reset control signal line belong to emit light.
  • the element anode is a reset voltage, and the sub-pixel to which the pixel driving circuit electrically connected to the reset control signal line belongs is in a non-light-emitting stage;
  • the pixel units in the i-th row are in the light-emitting phase at least part of the time period, and the anode of the light-emitting element of the pixel units in the j-th row is a reset voltage, which is used to convert the pixel units in the i-th row through the common layer.
  • the leakage current is derived; wherein, i and j are both positive integers greater than or equal to 1, and the pixel unit of the j-th row and the pixel unit of the i-th row are two adjacent rows of pixel units.
  • the embodiments of the present application further provide a method for driving an organic light-emitting display panel, the method comprising:
  • the potential of the light-emitting control signal line controlling the pixel unit in the i-th row is the first level; the potential of the light-emitting control signal line in the pixel unit in the j-th row is the second level;
  • the potential of the reset control signal line of the pixel unit in the i row is the third level, and the potential of the reset control signal line of the pixel unit in the jth row is the fourth level, so that the anode of the light-emitting element of the pixel unit in the jth row is the reset voltage
  • the pixel units in the j-th row are in the non-light-emitting stage, and are used to derive the leakage current generated by the pixel units in the i-th row through the common layer;
  • i and j are both positive integers greater than or equal to 1, and the jth row of pixel units and the ith row of pixel units are adjacent two rows of pixel units; the first level is an effective light-emitting control pulse; the second voltage Level is an invalid light-emitting control pulse; the third level is a valid reset control pulse; the fourth level is an invalid reset control pulse.
  • the pixel driving circuits of each sub-pixel in the same row of pixel units are connected to the same light-emitting control signal line; when the light-emitting control signal line transmits an effective light-emitting control pulse, the light-emitting control signal line
  • the sub-pixel to which the pixel driving circuit electrically connected by the signal line belongs is in the light-emitting stage; the pixel driving circuit of each sub-pixel in the same row of pixel units is connected to the same reset control signal line; when the reset control signal line transmits a valid reset pulse, the The anode of the light-emitting element of the sub-pixel to which the pixel driving circuit electrically connected to the reset control signal line belongs is a reset voltage, and the sub-pixel to which the pixel driving circuit that is electrically connected to the reset control signal line belongs is in a non-light-emitting stage.
  • the emission colors of two adjacent sub-pixels along the column direction are different; therefore, in each frame of image display period, by controlling at least part of the time period during which the pixel units of the i-th row are in the light-emitting phase, the The anode of the light-emitting element of the pixel unit of row j is the reset voltage; the pixel unit of row j and the pixel unit of row i are two adjacent rows of pixel units to solve the leakage current generation between adjacent sub-pixels of different colors in the column direction crosstalk problem.
  • FIG. 1 is a schematic structural diagram of an organic light-emitting display panel provided by the implementation of this application;
  • FIG. 2 is a schematic structural diagram of another organic light-emitting display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another organic light-emitting display panel according to an embodiment of the present application.
  • FIG. 4 is a driving timing diagram of an organic light-emitting display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a driving sequence of another organic light-emitting display panel according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a driving sequence of another organic light emitting display panel according to an embodiment of the present application.
  • Fig. 7 is the driving timing schematic diagram of the light-emitting control signal line and the reset control signal line of the same row of pixel units;
  • FIG. 8 is a structural diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 9 is another structural diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 10 is a structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • FIG. 11 is a schematic partial structure diagram of another organic light-emitting display panel according to an embodiment of the present application.
  • FIG. 12 is a schematic partial structure diagram of another organic light-emitting display panel provided by an embodiment of the present application.
  • FIG. 13 is a schematic partial structure diagram of another organic light-emitting display panel according to an embodiment of the present application.
  • FIG. 14 is a schematic partial structure diagram of still another organic light emitting display panel according to an embodiment of the present application.
  • An embodiment of the present application provides an organic light-emitting display panel, the organic light-emitting display panel includes: a plurality of pixel units, and each pixel unit includes a plurality of sub-pixels of different colors for realizing color display.
  • the sub-pixel includes a pixel driving circuit and a light emitting element electrically connected to the pixel driving circuit.
  • the pixel driving circuit is used for driving the electrically connected light-emitting element to emit light.
  • the light-emitting elements include a common layer; the common layers of adjacent light-emitting elements are arranged and connected in the same layer.
  • the common layer is an entire film layer without interruption between the light-emitting elements, wherein the common layer may include, for example, at least one of a hole-assisted transport layer, a light-emitting layer, and an electron-assisted transport layer.
  • the pixel driving circuit of each sub-pixel in the same row of pixel units is connected to the same light-emitting control signal line; when the light-emitting control signal line transmits an effective light-emitting control pulse, the sub-pixel to which the pixel driving circuit electrically connected to the light-emitting control signal line belongs is in the light-emitting stage .
  • the pixel drive circuits of each sub-pixel in the same row of pixel units are connected to the same reset control signal line; when the reset control signal line transmits a valid reset pulse, the anode of the light-emitting element of the sub-pixel to which the pixel drive circuit to which the reset control signal line is electrically connected is reset voltage, the sub-pixel to which the pixel driving circuit electrically connected to the reset control signal line belongs is in a non-light-emitting stage;
  • the pixel units in the i-th row are in the light-emitting phase at least part of the time period, and the anode of the light-emitting element of the pixel units in the j-th row is a reset voltage, which is used to convert the pixel units in the i-th row through the common layer.
  • the leakage current is derived; wherein, i and j are both positive integers greater than or equal to 1, and the pixel unit of the j-th row and the pixel unit of the i-th row are two adjacent rows of pixel units.
  • the anodes of the light-emitting elements of the pixel units in the j-th row adjacent to the i-th row are at the reset voltage, and the anodes are reset and do not emit light.
  • FIG. 1 is a schematic structural diagram of an organic light-emitting display panel provided by an embodiment of the present application.
  • the organic light-emitting display panel includes a plurality of pixel units 10 , and each pixel unit 10 includes a plurality of sub-pixels of different colors 11.
  • each pixel unit 10 includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.
  • Each sub-pixel 11 includes a pixel driving circuit and a light emitting element (not shown in FIG. 1 ) electrically connected to the pixel driving circuit.
  • the pixel driving circuits of each sub-pixel in the same row of pixel units are connected to the same light-emitting control signal line; when the light-emitting control signal line transmits effective light-emitting control pulses, the sub-pixels to which the pixel driving circuits electrically connected to the light-emitting control signal line belong are in the light-emitting stage.
  • the pixel driving circuit of each sub-pixel in the pixel unit of the i-th row is connected to the same emission control signal line EMITi.
  • the pixel driving circuits of each sub-pixel in the pixel unit of the i-th row are connected to the same reset control signal line INi.
  • the pixel driving circuits of each sub-pixel in the pixel unit of the j-th row are connected to the same emission control signal line EMITj.
  • the pixel driving circuits of each sub-pixel in the j-th row of pixel units are connected to the same reset control signal line INj.
  • i and j are the row numbers of the pixel units, i and j are both positive integers greater than or equal to 1, and the j-th row of pixel units and the i-th row of pixel units are adjacent two rows of pixel units.
  • x is a positive integer greater than or equal to 1. It is exemplified that the two adjacent sub-pixels of the sub-pixel in the xth column are the green sub-pixel G and the blue sub-pixel B, respectively.
  • the pixel units in the i-th row are in at least part of the time period of the light-emitting phase, and the anodes of the light-emitting elements of the pixel units in the j-th row are at the reset voltage.
  • the sub-pixel in the x-th column of the pixel unit in the i-th row emits light
  • the anode of the light-emitting element of the sub-pixel in the x-th column of the pixel unit in the j-th row is the reset voltage and does not emit light.
  • the green sub-pixel G in the x-th column of the pixel unit in the i-th row It is adjacent to the blue sub-pixel B in the xth column of the jth row pixel unit.
  • the green sub-pixel G in the x-th column of the pixel unit in the i-th row emits light
  • some of the holes injected by its anode are transferred to the blue sub-pixel B in the x-th column of the pixel unit in the j-th row adjacent to it.
  • the anode of the light-emitting element of the blue sub-pixel B in the xth column of the unit is the reset voltage, so the leakage current can be conducted away, and the problem of crosstalk between sub-pixels of different colors is avoided.
  • the light-emitting phases of two adjacent rows of pixel units may be controlled not to overlap.
  • the light-emitting phases of two adjacent rows of pixel units are controlled not to overlap, so the sub-pixels of the i-th row of pixel units are in the entire light-emitting phase.
  • the sub-pixels of the pixel unit in the j-th row do not emit light, and the anode of the light-emitting element is the reset voltage, so that in the column direction, two adjacent sub-pixels of different colors can avoid crosstalk caused by leakage current during the entire light-emitting stage. .
  • the sub-pixel arrangement in FIG. 1 is only a specific example provided by the present application, and is not a limitation of the embodiments of the present application. In other embodiments, other pixel arrangement forms may be selected according to product design requirements, mainly ensuring at least a partial number of sub-pixel columns, and the emission colors of two adjacent sub-pixels along the column direction may be different.
  • the organic light-emitting display panel provided by an embodiment of the present application further includes a first scan driving circuit GIP1 , a second The scan drive circuit GIP2, the third scan drive circuit GIP3, and the fourth scan drive circuit GIP4.
  • the first scan drive circuit GIP1 includes a plurality of cascaded first shift registers 21; the second scan drive circuit GIP2 includes a plurality of cascaded second shift registers 22; the third scan drive circuit GIP3 includes a plurality of cascaded second shift registers 22 The third shift register 23 ; the fourth scan driving circuit GIP4 includes a plurality of cascaded fourth shift registers 24 .
  • each of the light-emitting control signal lines corresponding to the pixel units in the odd-numbered rows (the light-emitting control signal line EMIT2n-1 and the light-emitting control signal line EMIT2n+1 are exemplarily drawn in FIG. 2 ) and a plurality of cascaded first shift registers 21 one by one Corresponding electrical connection; each reset control signal line (reset control signal line IN2n-1, reset control signal line IN2n+1 is exemplarily drawn in FIG.
  • the registers 22 are electrically connected in one-to-one correspondence; each light-emitting control signal line corresponding to the pixel units of the even-numbered rows (the light-emitting control signal line EMIT2n and the light-emitting control signal line EMIT2n+2 are exemplarily drawn in FIG. 2 ) and a plurality of cascaded third
  • the shift registers 23 are electrically connected in one-to-one correspondence; the reset control signal lines corresponding to the pixel units in the even rows (the reset control signal line IN2n and the reset control signal line IN2n+2 are exemplarily drawn in FIG. 2 ) are connected to a plurality of cascaded
  • the fourth shift registers 24 are electrically connected in one-to-one correspondence.
  • the light-emitting control signal lines of the pixel units in the odd rows of the first scan driving circuit provide light-emitting control signals row by row;
  • the reset control signal lines of the pixel units in the odd rows of the second scan driving circuit provide the reset control signals row by row;
  • the light-emitting control signal lines of the pixel units in the even-numbered rows provide the light-emitting control signals row by row;
  • the reset control signal lines of the pixel units in the even-numbered rows of the fourth scan driving circuit provide the reset control signals row by row.
  • FIG. 3 is a schematic structural diagram of an organic light-emitting display panel provided by an embodiment of the present application.
  • the light-emitting control signal lines corresponding to odd-numbered rows of pixel units (the light-emitting control signal line EMIT2n is exemplarily drawn in FIG. 3 ) -1.
  • the light-emitting control signal line EMIT2n+1) is electrically connected;
  • the light-emitting control signal lines corresponding to the pixel units in the even rows are electrically connected ;
  • Each reset control signal line corresponding to the odd-numbered row pixel unit illustrated in FIG.
  • the reset control signal line IN2n-1, the reset control signal line IN2n+1) are electrically connected; each reset control signal corresponding to the even-numbered row pixel unit Lines (reset control signal line IN2n, reset control signal line IN2n+2 are illustrated in FIG. 3) are electrically connected; in each frame of image display period, pixel units in odd rows emit light at the same time; pixel units in even rows emit light at the same time.
  • FIG. 4 is a driving timing diagram of an organic light emitting display panel provided by an embodiment of the present application.
  • pixel units in odd rows emit light simultaneously
  • pixel units in even rows emit light simultaneously.
  • the light emission control stage A2 of each frame of image display period T includes two parts, which are the light emission control stage for odd-numbered lines and the light-emitting control stage for even-numbered lines.
  • the light-emitting control signal lines corresponding to pixel units in each odd-numbered row transmit effective light-emitting control pulses (the effective light-emitting control pulse is exemplarily set as a low level in FIG. 4 ), and the light-emitting control signal lines corresponding to pixel units in each even-numbered row
  • the signal line transmits an invalid light-emitting control pulse (the invalid light-emitting control pulse is exemplarily set to a high level in FIG.
  • the sub-pixel light-emitting elements of each even-numbered row of pixel units do not emit light, and the reset control signal line corresponding to each even-numbered row of pixel units transmits
  • the anode of the light-emitting element of the sub-pixel is the reset voltage.
  • the corresponding light-emitting control signal lines of each even-numbered row pixel unit transmit an effective light-emitting control pulse (the effective light-emitting control pulse is exemplarily set to be low level in FIG.
  • the pixel light-emitting element emits light
  • the light-emitting control signal line corresponding to each odd-numbered row of pixel units transmits an invalid light-emitting control pulse (the invalid light-emitting control pulse is exemplarily set as a high level in FIG. 4 )
  • the sub-pixel light-emitting element of each odd-numbered row pixel unit does not emit light
  • the reset control signal line corresponding to each odd row pixel unit transmits an effective reset pulse
  • the anode of the light-emitting element of the sub-pixel of each odd row pixel unit is the reset voltage.
  • each frame of image display period T includes a data writing phase A1 and a light-emitting control phase A2; in the data writing phase A1 in each frame of image display period T, each row of pixel units sequentially performs Data writing: After the data writing phase A1 of each frame of image display period T ends, the light-emitting control phase A2 is executed.
  • the pixel units in odd-numbered rows emit light at the same time, and the pixel units in even-numbered rows emit light at the same time.
  • the full-screen scanning is performed first to perform data writing. Scank in FIG. 4 refers to the scan signal corresponding to each sub-pixel of the pixel unit in the kth row, and k is positive integer.
  • the light-emitting control stage A2 in each frame of image display period may be configured to include multiple sub-light-emitting control stages; in each sub-light-emitting control stage, pixel units in odd rows emit light at the same time, and pixel units in even rows emit light at the same time.
  • FIG. 5 is a schematic diagram of a driving sequence of another organic light-emitting display panel provided by an embodiment of the present application.
  • the light-emitting control stage A2 in each frame of image display period exemplarily includes two sub-light-emitting control stages, which are sub-light-emitting control stages respectively.
  • each sub-emission control stage all odd-numbered row pixel units emit light at the same time; all even-numbered row pixel units emit light at the same time, in the same sub-emission control stage, the i-th row of pixel units is in at least part of the time period of the light-emitting phase, and the j-th row of pixels
  • the anode of the light-emitting element of the unit is the reset voltage, and the pixel unit in the j-th row and the pixel unit in the i-th row are two adjacent rows of pixel units.
  • FIG. 6 is a schematic diagram of driving timing of another organic light-emitting display panel provided by the embodiment of the present application.
  • the organic light-emitting display panel provided by the embodiment of the present application can realize that each odd-numbered row pixel unit emits light row by row, and each even row pixel unit is row by row. Lighting; and the light-emitting stages of two adjacent odd-numbered lines overlap, and the light-emitting stages of two adjacent even-numbered lines overlap.
  • each frame of image display period includes a data writing phase A1 and a light emission control phase A2.
  • each row of pixel units performs data writing in turn, and in the light emission control phase A2, each odd row pixel unit emits light row by row, and each even row pixel unit emits light row by row; and adjacent The light-emitting stages of two odd-numbered lines overlap, and the light-emitting stages of two adjacent even-numbered lines overlap.
  • the driving method provided by the embodiment of the present application can also perform data writing by full-screen scanning in the data writing stage A1 of each frame of image display period, and then in the light-emitting control stage A2, then make each odd-numbered line
  • the pixel units emit light row by row, and the pixel units of each even row emit light row by row; and the light emitting stages of two adjacent odd rows overlap, and the light emitting stages of two adjacent even rows overlap.
  • FIG. 6 takes the organic light emitting display panel including 2n rows of pixel units as an example for introduction.
  • the embodiment of the present application can also control the light-emitting control phase in the previous frame image display period to overlap with the data writing phase in the next frame image display period.
  • the light emission control phase A2 of the previous frame image display period Tm overlaps with the data writing phase A1 of the next frame image display period Tm+1.
  • each odd row pixel unit is driven to emit light row by row
  • each even row pixel unit is driven to emit light row by row
  • the even row pixel unit emits light continuously to the next frame, because the even row pixel unit emits light row by row.
  • the light emission control phase overlaps with the data writing phase of the next frame, so it does not affect the scan input of the light emission control signal of the next frame.
  • the light-emitting control stage in each frame of image display period includes a plurality of sub-light-emitting control stages; in each sub-light-emitting control stage, the pixel units of each even row emit light row by row; and the lighting phases of two adjacent odd rows overlap, The light-emitting stages of two adjacent even-numbered rows overlap.
  • FIG. 7 is a schematic diagram of the driving timing of the light-emitting control signal line and the reset control signal line of the same row of pixel units.
  • the effective light-emitting control pulse of the light-emitting control signal line EMIT exemplarily low level in FIG. 7
  • the valid reset pulses of the reset control signal line IN do not overlap.
  • the effective reset pulse of the reset control signal line IN should be cut off first. After the effective light-emitting control pulse of the control light-emitting control signal line EMIT is input and the effective light-emitting control pulse of the light-emitting control signal line EMIT is cut off, the effective reset pulse of the reset control signal line IN Re-input, so as to avoid the overlap between the effective reset pulse of the reset control signal line IN and the effective light-emitting control pulse of the light-emitting control signal line EMIT, and short-circuit between the reset signal input terminal and the power signal terminal on the organic light-emitting display panel, resulting in a large current.
  • the embodiment of the present application does not limit the specific circuit structure of the pixel driving circuit of the organic light emitting display panel.
  • the following exemplary provides several pixel driving circuit structures that can achieve the beneficial effects of the present application, rather than limiting the embodiment of the present application.
  • the pixel driving circuit includes:
  • a data writing module 100 a driving module 200, a reset module 300 and a lighting control module 400;
  • the data writing module 100 and the driving module 200 are electrically connected to the first node N1; the driving module 200 and the lighting control module 400 are electrically connected to the second node N2; Electrical connection; the reset module 300 is electrically connected to the reset control signal line IN; the light emission control module 400 is electrically connected to the light emission control signal line EMIT.
  • the data writing module 100 is used for providing a data signal to the first node N1; the driving module 200 is used for driving the light-emitting element 500 to emit light when the light-emitting control module 400 is turned on; the reset module 300 is used for inputting a valid reset on the reset control signal line IN When pulsed, a reset signal U1 is provided to the anode of the light-emitting element, so that the anode of the light-emitting element is the reset voltage U1 (for ease of description, the reset signal and the reset voltage use the same reference numerals herein).
  • the lighting control module 400 may include a first transistor T1; the reset module 300 includes a second transistor T2; the first transistor T1 is an NMOS transistor, and the second transistor T2 is a PMOS transistor; or the second transistor T2 is an NMOS transistor, and the first transistor T2 is an NMOS transistor.
  • a transistor T1 is a PMOS transistor; the light-emitting control signal lines corresponding to each row of pixel units are multiplexed into reset control signal lines.
  • the first transistor T1 is a PMOS transistor
  • the second transistor T2 is an NMOS transistor
  • the first transistor T1 and the second transistor T2 use the same signal line, that is, the light-emitting control signal line EMIT corresponding to each row of pixel units is multiplexed for reset
  • Controlling the signal lines IN can reduce the number of signal lines in the pixel driving circuit and the number of scanning driving circuits in the organic light emitting display panel.
  • the same scanning driving circuit can be used for scanning input of the light emitting control signal and the reset control signal.
  • a current limiting resistor R can be connected in series between the light emitting control module 400 and the reset module 300 to prevent the first transistor T1 and the second transistor T2 from generating a large current at the moment of switching.
  • FIG. 10 is another structural diagram of a pixel driving circuit provided by an embodiment of the present application. As shown in FIG. 10 , it may further include a storage module 600, a threshold compensation module 700, and an initialization module 800.
  • the storage module 600 includes a storage capacitor C
  • the threshold compensation Module 700 includes a third transistor T3
  • initialization module 800 includes a fourth transistor T4.
  • the data writing module 100 includes a fifth transistor T5, and the driving module 200 includes a sixth transistor T6.
  • the pixel driving circuit further includes a seventh transistor T7.
  • control terminal of the third transistor T3 is electrically connected to the control terminal of the fifth transistor T5; the first pole of the third transistor T3 is electrically connected to the first plate of the capacitor C; the second pole of the third transistor T3 and the sixth pole
  • the second pole of the transistor T6 is electrically connected to the second node N2; the first pole of the sixth transistor T6 is electrically connected to the first node N1, and the control terminal of the sixth transistor T6 is electrically connected to the second pole of the fourth transistor T4;
  • the first pole of the fourth transistor T4 is electrically connected to the initialization signal terminal REF; the second pole of the capacitor C and the first pole of the seventh transistor T7 are both electrically connected to the power supply signal terminal PVDD; the second pole of the seventh transistor T7 and The second pole of the fifth transistor T5 is electrically connected to the first node N1; the first pole of the fifth transistor T5 is electrically connected to the data signal terminal DATA; the control terminal of the first transistor T1 and the control terminal of the seventh transistor T7 are both electrical
  • the light-emitting control signal terminal (for inputting the light control signal EMIT) is electrically connected; the first pole of the first transistor T1 is electrically connected to the second node N2; the second pole of the first transistor T1 and the first pole of the second transistor T2 are both electrically connected It is electrically connected to the anode of the light-emitting element 500; the second pole of the second transistor T2 is electrically connected to the reset signal input terminal (for inputting the reset signal U1); the control terminal of the second transistor T2 is electrically connected to the reset control signal terminal (for inputting the reset signal U1).
  • the control signal IN is electrically connected.
  • the first pole of the fourth transistor T4 and the second pole of the second transistor T2 may be electrically connected, that is, the initialization signal terminal and the reset signal input terminal are shared.
  • the signal reset signal U1 input from the reset signal input terminal is equal to the initialization potential REF for initializing the drive module.
  • the signal input to the reset signal input terminal can also be zero potential, ground potential GND, the cathode potential of the light-emitting element, the common negative potential VSS lower than the cathode potential of the light-emitting element, or the common negative potential shared with other circuits in the organic light-emitting display panel. Low potential VGL.
  • FIG. 11 is a schematic partial structure diagram of another organic light-emitting display panel provided by the embodiment of the present application.
  • the organic light-emitting display panel provided by the embodiment of the present application further includes a plurality of inverter groups 40;
  • the phase device group 40 includes a first inverter 41 and a first in-phase device 42;
  • the first inverter 41 includes a first PMOS transistor B1 and a first NMOS transistor C1; the first inverter 42 includes a second PMOS transistor B2 and a second NMOS transistor C2.
  • the control terminal of the first PMOS transistor B1 and the control terminal of the first NMOS transistor C1 are electrically connected to the third node N3; the control terminal of the second PMOS transistor B2 and the control terminal of the second NMOS transistor C2 are both electrically connected to the fourth node N4 ; The third node N3 is electrically connected to the fourth node N4.
  • the first pole of the first PMOS transistor B1 and the second pole of the second NMOS transistor C2 are both electrically connected to the high-level signal terminal VGH; the second pole of the first PMOS transistor B1 is electrically connected to the first pole of the first NMOS transistor C1 connected to the fifth node N5;
  • the second pole of the first NMOS transistor C1 and the first pole of the second PMOS transistor B2 are both electrically connected to the low-level signal terminal VGL; the second pole of the second PMOS transistor B2 is electrically connected to the first pole of the second NMOS transistor C2 connected to the sixth node N6;
  • the fifth node N5 is also electrically connected to the reset control signal line IN corresponding to the sub-pixels with the same timing in the light-emitting phase;
  • the sixth node N6 is also electrically connected to the light-emitting control signal line EMIT corresponding to the sub-pixels with the same light-emitting phase timing.
  • the same gate driving circuit can be used to generate the reset control signal and the light-emitting control signal at the same time.
  • the inverter group 40 may simultaneously generate the reset control signal IN and the light emission control signal EMIT.
  • the reset control signal line and the reset control signal are marked as IN
  • the light emission control signal line and the light emission control signal are marked as EMIT.
  • the width-length ratio of the first PMOS transistor B1 is set Greater than the width to length ratio of the second NMOS transistor C2
  • the aspect ratio of the first NMOS transistor C1 Less than the width to length ratio of the second PMOS transistor B2
  • the generated reset control signal and the light emission control signal have a certain delay, that is, the outputs of the first inverter 41 and the first inverter 42 are delayed.
  • the driving sequence shown in FIG. 7 is generated to avoid a short circuit between the reset signal input terminal and the power signal terminal on the organic light emitting display panel, and a large current is generated.
  • the inverter group can also be set to include a first RC circuit D1 and a second RC circuit D2. , a third RC circuit D3 and a fourth RC circuit D4.
  • the first RC circuit D1 is electrically connected between the control terminal of the first PMOS transistor B1 and the third node N3; the second RC circuit D2 is electrically connected between the control terminal of the first NMOS transistor C1 and the third node N3; the third The RC circuit D3 is electrically connected between the control terminal of the second PMOS transistor B2 and the fourth node N4; the fourth RC circuit D4 is electrically connected between the control terminal of the second NMOS transistor C2 and the fourth node N4; the first RC circuit
  • the time constant ⁇ D1 of D1 is smaller than the time constant ⁇ D3 of the third RC circuit D3 ; the time constant ⁇ D2 of the second RC circuit D2 is greater than the time constant ⁇ D4 of the fourth RC circuit D4 :
  • the outputs of the first inverter 41 and the first inverter 42 are delayed different.
  • an embodiment of the present application further provides a schematic diagram of a partial structure of an organic light-emitting display panel.
  • the organic light-emitting display panel provided by the embodiment of the present application further includes a plurality of inverter groups 40;
  • the inverter group 40 includes a first inverter 41 , a second inverter 42 and a third inverter 43 .
  • the first inverter 41 includes a first PMOS transistor B1 and a first NMOS transistor C1;
  • the second inverter 42 includes a second PMOS transistor B2 and a second NMOS transistor C2;
  • the third inverter 43 includes a third PMOS transistor B3 and the third NMOS transistor C3;
  • the control terminal of the first PMOS transistor B1 and the control terminal of the first NMOS transistor C1 are electrically connected to the third node N3;
  • the control terminal of the second PMOS transistor B2 is electrically connected to the control terminal of the second NMOS transistor C2 is connected to the fourth node N4;
  • the control terminal of the third PMOS transistor B3 and the control terminal of the third NMOS transistor C3 are electrically connected to the fifth node N5.
  • the first pole of the first PMOS transistor B1, the first pole of the second PMOS transistor B2 and the first pole of the third PMOS transistor B3 are all electrically connected to the high-level signal terminal VGH; the second pole of the first PMOS transistor B1 is electrically connected to the high-level signal terminal VGH.
  • the first pole of the first NMOS transistor C1 is electrically connected to the sixth node N6; the second pole of the first NMOS transistor C1, the second pole of the second NMOS transistor C2 and the second pole of the third NMOS transistor C3 are all connected to the low voltage.
  • the flat signal terminal VGL is electrically connected; the second pole of the second PMOS transistor B2 and the first pole of the second NMOS transistor C2 are electrically connected to the seventh node N7; the second pole of the third PMOS transistor B3 is electrically connected to the third NMOS transistor C3
  • the first pole is electrically connected to the eighth node N8; the third node N3 is electrically connected to the fourth node N4; the sixth node N6 is also electrically connected to the reset control signal line IN corresponding to the sub-pixels with the same light-emitting stage timing;
  • the seventh node N7 It is electrically connected to the fifth node N5; the eighth node N8 is electrically connected to the light-emitting control signal line EMIT corresponding to the sub-pixels with the same light-emitting stage timing sequence.
  • a reset control signal is output to the reset control signal line through one inverter, and a light emission control signal is output to the light emission control signal line through two inverters connected in series, so that the reset control signal received by the same sub-pixel and the light emission control signal
  • the timing of the signals meets the requirements of the above embodiments.
  • the sum of the charging and discharging time constant t B2 of the second PMOS transistor B2 and the charging and discharging time constant t C3 of the third NMOS transistor C3 can be set to be greater than the charging and discharging time of the first PMOS transistor B1.
  • the time constant t B1 , the sum of the charging and discharging time constant t C2 of the second NMOS transistor C2 and the charging and discharging time constant t B3 of the third PMOS transistor B3 is less than the charging and discharging time constant t C1 of the first NMOS transistor C1 :
  • the timing delays of the lighting control signal and the reset control signal are different.
  • the inverter group 40 may further include a first RC circuit D1; the first RC circuit D1 is located between the third node N3 and the control terminal of the first NMOS transistor C1.
  • the sum of the charging and discharging time constant t B2 of the second PMOS transistor B2 and the charging and discharging time constant t C3 of the third NMOS transistor C3 is greater than the charging and discharging time constant t B1 of the first PMOS transistor B1; the charging and discharging time of the second NMOS transistor C2
  • the sum of the constant t C2 and the charging and discharging time constant t B3 of the third PMOS transistor B3 is less than the sum of the charging and discharging time constant t C1 of the first NMOS transistor C1 and the time constant ⁇ D1 of the first RC circuit D1:
  • Embodiments of the present application further provide a method for driving an organic light-emitting display panel, the method is applicable to the organic light-emitting display panel described in any of the above embodiments, and the method includes:
  • the potential of the light-emitting control signal line controlling the pixel unit in the i-th row is the first level; the potential of the light-emitting control signal line in the pixel unit in the j-th row is the second level;
  • the potential of the reset control signal line of the pixel unit in the i row is the third level, and the potential of the reset control signal line of the pixel unit in the jth row is the fourth level, so that the anode of the light-emitting element of the pixel unit in the jth row is the reset voltage
  • the pixel units in the j-th row are in the non-light-emitting stage, and are used to derive the leakage current generated by the pixel units in the i-th row through the common layer;
  • i and j are both positive integers greater than or equal to 1, and the jth row of pixel units and the ith row of pixel units are adjacent two rows of pixel units; the first level is the effective light-emitting control pulse; the second level is the invalid light-emitting control pulse; the third level is the valid reset control pulse; the fourth level is the invalid reset control pulse.
  • the anodes of the light-emitting elements of the pixel units in the j-th row adjacent to the i-th row are at the reset voltage, and the anodes are reset and do not emit light.
  • the light-emitting phases of two adjacent rows of pixel units may be controlled not to overlap. That is, when the sub-pixels of the pixel unit in the i-th row are in the entire light-emitting stage, the sub-pixels of the pixel unit in the j-th row do not emit light, and the anode of the light-emitting element is the reset voltage, so that in the column direction, two adjacent sub-pixels of different colors The problem of crosstalk caused by leakage current can be avoided in the whole light-emitting stage.
  • each light-emitting control signal line corresponding to odd-numbered rows of pixel units in the organic light-emitting display panel may be electrically connected; each light-emitting control signal line corresponding to even-numbered pixel units is electrically connected; and each reset control signal corresponding to odd-numbered row pixel units.
  • the lines are electrically connected; the reset control signal lines corresponding to the pixel units in the even rows are electrically connected; in each frame of image display period, the pixel units in the odd rows emit light at the same time; the pixel units in the even rows are electrically connected.
  • the driving sequence shown in FIG. 4 drives the organic light emitting display panel to emit light.
  • this embodiment of the present application may also control pixel units in odd rows to emit light row by row, and pixel units in even rows to emit light row by row; and the emission phases of two adjacent odd rows overlap, and the emission phases of two adjacent even rows overlap.
  • the organic light emitting display panel is driven to emit light according to the driving sequence shown in FIG. 6 .
  • the driving method provided in the embodiment of the present application can control each frame of image display cycle to include a data writing phase and a light-emitting control phase; in the data writing phase in each frame of image display cycle, each row of pixel units sequentially performs data writing. ; After the data writing phase of the image display period of each frame is completed, a light-emitting control phase is performed, in which the pixel units of odd-numbered rows emit light simultaneously; the pixel units of even-numbered rows emit light simultaneously.
  • each frame of image display cycle includes a data writing stage and a light-emitting control stage; in the data writing stage in each frame of image display period, each row of pixel units performs data writing in turn; in the light-emitting control stage, each odd row of pixel units is performed one by one.
  • the rows emit light, and the pixel units of each even row emit light row by row; and the luminescence stages of two adjacent odd rows overlap, and the luminescence stages of two adjacent even rows overlap.
  • the light-emitting control stage in each frame of image display period can also be set to include multiple sub-light-emitting control stages; in each sub-light-emitting control stage, the pixel units in odd rows emit light at the same time; the pixel units in even rows emit light at the same time, or in each In each sub-emission control stage, each odd row pixel unit emits light row by row, and each even row pixel unit emits light row by row; and the emission phases of two adjacent odd rows overlap, and the emission phases of two adjacent even rows overlap.
  • the light-emitting control signal lines and the reset control signal lines of the pixel units in the same row satisfy: the effective light-emitting control pulses of the light-emitting control signal lines and the effective reset pulses of the reset control signal lines do not overlap. , to avoid short circuit between the reset signal input terminal and the power signal terminal on the organic light emitting display panel, resulting in a large current.

Abstract

一种有机发光显示面板以及驱动方法，同一行像素单元（10）中的各子像素（11）的像素驱动电路连接同一发光控制信号线；发光控制信号线传输有效发光控制脉冲时，该发光控制信号线电连接的像素驱动电路所属子像素（11）处于发光阶段（A2）；同一行像素单元（10）中的各子像素（11）的像素驱动电路连接同一复位控制信号线；该复位控制信号线电连接的像素驱动电路所属子像素（11）的发光元件阳极为复位电压；在每帧图像显示周期（T）内，第i行像素单元（10）处于发光阶段（A2）的至少部分时间段，第j行像素单元（10）的发光元件阳极为复位电压；第j行像素单元（10）和第i行像素单元（10）为相邻两行像素单元（10）。

Description

有机发光显示面板以及驱动方法
本申请要求申请日为2020年8月21日、申请号为202010849008.0的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术，例如涉及一种有机发光显示面板以及驱动方法。
背景技术
近年来，有机发光显示面板在移动显示终端屏幕和中大尺寸的显示屏上逐渐占据主流。有机发光显示面板包括阵列排布的多个子像素。每个子像素包括像素驱动电路以及与该像素驱动电路电连接的发光元件。
相关技术中每个发光元件均包括叠层设置的阳极、空穴辅助传输层、发光层、电子辅助传输层以及阴极。为了提高子像素密度，或者制备较小尺寸的显示面板，不同颜色的发光元件的空穴辅助传输层、发光层以及电子辅助传输层均为整层膜层，各个发光元件的空穴辅助传输层、发光层以及电子辅助传输层没有中断。由于相邻发光元件的空穴辅助传输层、发光层以及电子辅助传输层均为整层膜层，当某个发光元件发光时，该发光元件的阳极注入的空穴会有部分通过空穴辅助传输层传输至与其相邻的发光元件，产生横向的漏电流，该漏电流将影响相邻发光元件的信号电压，从而导致图像的模糊和混色。
发明内容
本申请提供一种有机发光显示面板以及驱动方法，以避免相邻发光元件之间产生漏电流影响显示效果的问题。
第一方面，本申请实施例提供了一种有机发光显示面板，包括：多个像素 单元，每个像素单元包括多个不同颜色的子像素；所述子像素包括像素驱动电路和与所述像素驱动电路电连接的发光元件；所述发光元件包括公共层；相邻所述发光元件的公共层同层设置且连接；
至少部分数量的子像素列，沿列方向相邻两子像素的发光颜色不同；
同一行像素单元中的各子像素的像素驱动电路连接同一发光控制信号线；所述发光控制信号线传输有效发光控制脉冲时，该所述发光控制信号线电连接的像素驱动电路所属子像素处于发光阶段；
同一行像素单元中的各子像素的像素驱动电路连接同一复位控制信号线；所述复位控制信号线传输有效复位脉冲时，该所述复位控制信号线电连接的像素驱动电路所属子像素的发光元件阳极为复位电压，该所述复位控制信号线电连接的像素驱动电路所属子像素处于非发光阶段；
在每帧图像显示周期内，第i行像素单元处于发光阶段的至少部分时间段，第j行像素单元的发光元件阳极为复位电压，用于将所述第i行像素单元通过公共层产生的漏流导出；其中，i和j均为大于等于1的正整数，第j行像素单元和第i行像素单元为相邻两行像素单元。
第二方面，本申请实施例还提供了一种有机发光显示面板的驱动方法，所述方法包括：
在第i行像素单元的至少部分发光阶段，控制第i行像素单元的发光控制信号线的电位为第一电平；第j行像素单元的发光控制信号线的电位为第二电平；第i行像素单元的复位控制信号线的电位为第三电平，第j行像素单元的复位控制信号线的电位为第四电平，以使第j行像素单元的发光元件阳极为复位电压，第j行像素单元处于非发光阶段，用于将所述第i行像素单元通过公共层产生的漏流导出；
其中，i和j均为大于等于1的正整数，第j行像素单元和第i行像素单元为相邻两行像素单元；所述第一电平为有效发光控制脉冲；所述第二电平为无效发光控制脉冲；所述第三电平为有效复位控制脉冲；所述第四电平为无效复位控制脉冲。
本申请实施例提供的有机发光显示面板中，同一行像素单元中的各子像素的像素驱动电路连接同一发光控制信号线；所述发光控制信号线传输有效发光控制脉冲时，该所述发光控制信号线电连接的像素驱动电路所属子像素处于发光阶段；同一行像素单元中的各子像素的像素驱动电路连接同一复位控制信号线；所述复位控制信号线传输有效复位脉冲时，该所述复位控制信号线电连接的像素驱动电路所属子像素的发光元件阳极为复位电压，该所述复位控制信号线电连接的像素驱动电路所属子像素处于非发光阶段。由于存在至少部分数量的子像素列，沿列方向相邻两子像素的发光颜色不同；因此可以通过在每帧图像显示周期内，控制第i行像素单元处于发光阶段的至少部分时间段，第j行像素单元的发光元件阳极为复位电压；第j行像素单元和第i行像素单元为相邻两行像素单元，以解决列方向上相邻的不同颜色的子像素之间的漏流产生的串扰问题。
附图说明
图1为本申请实施提供的一种有机发光显示面板的结构示意图；
图2为本申请实施例提供的又一种有机发光显示面板的结构示意图；
图3为本申请实施例提供的又一种有机发光显示面板的结构示意图；
图4为本申请实施例提供的一种有机发光显示面板的驱动时序图；
图5为本申请实施例提供的又一种有机发光显示面板的驱动时序示意图；
图6为本申请实施例提供的又一种有机发光显示面板的驱动时序示意图；
图7为同一行像素单元的发光控制信号线和复位控制信号线的驱动时序示 意图；
图8为本申请实施例提供的一种像素驱动电路结构图；
图9为本申请实施例提供的又一种像素驱动电路结构图；
图10为本申请实施例提供的又一种像素驱动电路结构图；
图11为本申请实施例提供的又一种有机发光显示面板的局部结构示意图；
图12为本申请实施例提供的又一种有机发光显示面板的局部结构示意图；
图13为本申请实施例提供的又一种有机发光显示面板的局部结构示意图；
图14为本申请实施例提供的又一种有机发光显示面板的局部结构示意图。
具体实施方式
本申请实施提供的一种有机发光显示面板，该有机发光显示面板包括：多个像素单元，每个像素单元包括多个不同颜色的子像素，用于实现彩色显示。子像素包括像素驱动电路和与像素驱动电路电连接的发光元件。像素驱动电路用于驱动电连接的发光元件发光。发光元件包括公共层；相邻发光元件的公共层同层设置且连接。即公共层为整层膜层，在各个发光元件之间没有中断，其中，公共层例如可以包括空穴辅助传输层、发光层以及电子辅助传输层中的至少一种。
存在至少部分数量的子像素列，沿列方向相邻两子像素的发光颜色不同。其中，同一行像素单元中的各子像素的像素驱动电路连接同一发光控制信号线；发光控制信号线传输有效发光控制脉冲时，该发光控制信号线电连接的像素驱动电路所属子像素处于发光阶段。
同一行像素单元中的各子像素的像素驱动电路连接同一复位控制信号线；复位控制信号线传输有效复位脉冲时，该复位控制信号线电连接的像素驱动电 路所属子像素的发光元件阳极为复位电压，该复位控制信号线电连接的像素驱动电路所属子像素处于非发光阶段；
在每帧图像显示周期内，第i行像素单元处于发光阶段的至少部分时间段，第j行像素单元的发光元件阳极为复位电压，用于将所述第i行像素单元通过公共层产生的漏流导出；其中，i和j均为大于等于1的正整数，第j行像素单元和第i行像素单元为相邻两行像素单元。
即，在第i行像素单元处于发光阶段的至少部分时间段内，与第i行相邻的第j行像素单元的发光元件阳极为复位电压，对阳极进行复位，不发光。因此若发光的第i行像素单元的某一颜色子像素对其临近的第j行像素单元的不同颜色子像素产生漏流，由于第j行像素单元的子像素的发光元件阳极为复位电压，可以将漏流导出，所以可以避免不同颜色子像素之间的串扰。
图1为本申请实施例提供的一种有机发光显示面板的结构示意图，如图1所示，该有机发光显示面板包括多个像素单元10，每个像素单元10包括多个不同颜色的子像素11。图1示例性的设置每个像素单元10包括红色子像素R、绿色子像素G和蓝色子像素B。每个子像素11包括像素驱动电路和与像素驱动电路电连接的发光元件(图1中未示出)。
同一行像素单元中的各子像素的像素驱动电路连接同一发光控制信号线；发光控制信号线传输有效发光控制脉冲时，该发光控制信号线电连接的像素驱动电路所属子像素处于发光阶段。如图1，第i行像素单元中的各子像素的像素驱动电路连接同一发光控制信号线EMITi。第i行像素单元中的各子像素的像素驱动电路连接同一复位控制信号线INi。第j行像素单元中的各子像素的像素驱动电路连接同一发光控制信号线EMITj。第j行像素单元中的各子像素的像素驱动电路连接同一复位控制信号线INj。其中,i和j为像素单元的行序号,i和j 均为大于等于1的正整数，第j行像素单元和第i行像素单元为相邻两行像素单元。
举例而言，若存在第x列子像素，沿列方向上，相邻的子像素的发光颜色不同。x为大于等于1的正整数。示例性的以第x列子像素相邻两子像素分别为绿色子像素G和蓝色子像素B为例。在每帧图像显示周期内，第i行像素单元处于发光阶段的至少部分时间段，第j行像素单元的发光元件阳极为复位电压。
第i行像素单元的第x列子像素发光，第j行像素单元的第x列子像素的发光元件阳极为复位电压，不发光，参见图1，第i行像素单元第x列的绿色子像素G与第j行像素单元第x列的蓝色子像素B相邻。若第i行像素单元第x列的绿色子像素G发光时，其阳极注入的空穴有部分传输至与其相邻第j行像素单元第x列的蓝色子像素B，由于第j行像素单元第x列的蓝色子像素B的发光元件阳极为复位电压，因此可以将漏电流导走，避免了不同颜色子像素之间的串扰问题。
可选的，本申请实施例可以在每帧图像显示周期内，控制相邻两行像素单元的发光阶段不交叠。为了实现良好的显示效果，可选的，本申请实施例在每帧图像显示周期内，控制相邻两行像素单元的发光阶段不交叠，因此第i行像素单元的子像素在整个发光阶段时，第j行像素单元的子像素均不发光，且发光元件阳极为复位电压，以使列方向上，相邻的两不同颜色的子像素在整个发光阶段均能避免漏电流导致的串扰问题。
图1中的子像素排列仅为本申请提供的一个具体示例，并非对本申请实施例的限定。在其他实施方式中，可以根据产品的设计需求，选择其他像素排列的形式，主要保证至少部分数量的子像素列，沿列方向相邻两子像素的发光颜色不同即可。
图2为本申请实施例提供的一种有机发光显示面板的结构示意图，如图1所示，可选的，本申请实施例提供的有机发光显示面板还包括第一扫描驱动电路GIP1、第二扫描驱动电路GIP2、第三扫描驱动电路GIP3以及第四扫描驱动电路GIP4。第一扫描驱动电路GIP1包括多个级联的第一移位寄存器21；第二扫描驱动电路GIP2包括多个级联的第二移位寄存器22；第三扫描驱动电路GIP3包括多个级联的第三移位寄存器23；第四扫描驱动电路GIP4包括多个级联的第四移位寄存器24。
奇数行像素单元对应的各发光控制信号线(图2中示例性的画出发光控制信号线EMIT2n-1、发光控制信号线EMIT2n+1)与多个级联的第一移位寄存器21一一对应电连接；奇数行像素单元对应的各复位控制信号线(图2中示例性的画出复位控制信号线IN2n-1、复位控制信号线IN2n+1)与多个级联的第二移位寄存器22一一对应电连接；偶数行像素单元对应的各发光控制信号线(图2中示例性的画出发光控制信号线EMIT2n、发光控制信号线EMIT2n+2)与多个级联的第三移位寄存器23一一对应电连接；偶数行像素单元对应的各复位控制信号线(图2中示例性的画出复位控制信号线IN2n、复位控制信号线IN2n+2)与多个级联的第四移位寄存器24一一对应电连接。
第一扫描驱动电路各奇数行像素单元的发光控制信号线逐行提供发光控制信号；第二扫描驱动电路各奇数行像素单元的复位控制信号线逐行提供复位控制信号；第三扫描驱动电路各偶数行像素单元的发光控制信号线逐行提供发光控制信号；第四扫描驱动电路各偶数行像素单元的复位控制信号线逐行提供复位控制信号。
图3为本申请实施例提供的一种有机发光显示面板的结构示意图，如图3所示，奇数行像素单元对应的各发光控制信号线(图3中示例性的画出发光控 制信号线EMIT2n-1、发光控制信号线EMIT2n+1)电连接；偶数行像素单元对应的各发光控制信号线(图3中示例性的画出发光控制信号线EMIT2n、发光控制信号线EMIT2n+2)电连接；奇数行像素单元对应的各复位控制信号线(图3中示例性的画出复位控制信号线IN2n-1、复位控制信号线IN2n+1)电连接；偶数行像素单元对应的各复位控制信号线(图3中示例性的画出复位控制信号线IN2n、复位控制信号线IN2n+2)电连接；在每帧图像显示周期内，奇数行像素单元同时发光；偶数行像素单元。
图4为本申请实施例提供的一种有机发光显示面板的驱动时序图，如图4所示，在每帧图像显示周期T内，奇数行像素单元同时发光，偶数行像素单元同时发光。参见图4，每帧图像显示周期T的发光控制阶段A2包括两部分，分别为奇数行发光控制阶段和偶数行发光控制阶段。
在奇数行发光控制阶段中，各奇数行像素单元对应的发光控制信号线传输有效发光控制脉冲(图4中示例性设置有效发光控制脉冲为低电平)，各偶数行像素单元对应的发光控制信号线传输无效发光控制脉冲(图4中示例性设置无效发光控制脉冲为高电平)，各偶数行像素单元的子像素发光元件不发光，并且各偶数行像素单元对应的复位控制信号线传输有效复位脉冲，其子像素的发光元件的阳极为复位电压。在偶数行发光控制阶段A2中，各偶数行像素单元的对应的发光控制信号线传输有效发光控制脉冲(图4中示例性设置有效发光控制脉冲为低电平)，各偶数行像素单元的子像素发光元件发光，各奇数行像素单元对应的发光控制信号线传输无效发光控制脉冲(图4中示例性设置无效发光控制脉冲为高电平)，各奇数行像素单元的子像素发光元件不发光，并且各奇数行像素单元对应的复位控制信号线传输有效复位脉冲，各奇数行像素单元的子像素的发光元件的阳极为复位电压。
在上述实施例的基础上，可选的，每帧图像显示周期T包括数据写入阶段A1和发光控制阶段A2；在每帧图像显示周期T中的数据写入阶段A1，各行像素单元依次进行数据写入；在每帧图像显示周期T的数据写入阶段A1结束后，执行发光控制阶段A2。在发光控制阶段A2，奇数行像素单元同时发光，偶数行像素单元同时发光。例如参见图4，在每帧图像显示周期T的数据写入阶段A1，先全屏扫描进行数据写入，图4中Scank是指第k行像素单元的各子像素所对应的扫描信号，k为正整数。
可选的，每帧图像显示周期中的发光控制阶段A2可设置包括多个子发光控制阶段；在每个子发光控制阶段，奇数行像素单元同时发光，偶数行像素单元同时发光。
图5为本申请实施例提供的又一种有机发光显示面板的驱动时序示意图，参见图5，每帧图像显示周期中的发光控制阶段A2示例性的包括两个子发光控制阶段，分别为子发光控制阶段A21和子发光控制阶段A22。在每个子发光控制阶段，所有的奇数行像素单元同时发光；所有的偶数行像素单元同时发光，在同一子发光控制阶段，第i行像素单元处于发光阶段的至少部分时间段，第j行像素单元的发光元件阳极为复位电压，第j行像素单元和第i行像素单元为相邻两行像素单元。
图6为本申请实施例提供的又一种有机发光显示面板的驱动时序示意图，本申请实施例提供的有机发光显示面板，可以实现各奇数行像素单元逐行发光，各偶数行像素单元逐行发光；且相邻两奇数行的发光阶段交叠，相邻两偶数行的发光阶段交叠。
可选的，在上述实施例的基础上，每帧图像显示周期包括数据写入阶段A1和发光控制阶段A2。在每帧图像显示周期中的数据写入阶段A1，各行像素单元 依次进行数据写入，在发光控制阶段A2，各奇数行像素单元逐行发光，各偶数行像素单元逐行发光；且相邻两奇数行的发光阶段交叠，相邻两偶数行的发光阶段交叠。例如参见图6，本申请实施例提供的该种驱动方式也可以在每帧图像显示周期的数据写入阶段A1，先全屏扫描进行数据写入，然后在发光控制阶段A2，再使各奇数行像素单元逐行发光，各偶数行像素单元逐行发光；且相邻两奇数行的发光阶段交叠，相邻两偶数行的发光阶段交叠。图6以有机发光显示面板包括2n行像素单元为例进行介绍。
本申请实施例还可以控制前一帧图像显示周期中的发光控制阶段与后一帧图像显示周期的数据写入阶段交叠。例如参见图6，前一帧图像显示周期Tm的发光控制阶段A2与后一帧图像显示周期Tm+1的数据写入阶段A1交叠。如图6所示，在发光控制阶段中，各奇数行像素单元逐行驱动发光、各偶数行像素单元逐行驱动发光，偶数行像素单元的发光持续到下一帧，因为偶数行像素单元的发光控制阶段与下一帧的数据写入阶段交叠，因此不影响下一帧的发光控制信号的扫描输入。
可选的，在每帧图像显示周期中的发光控制阶段包括多个子发光控制阶段；在每个子发光控制阶段，各偶数行像素单元逐行发光；且相邻两奇数行的发光阶段交叠，相邻两偶数行的发光阶段交叠。
在上述各实施例的基础上，可选的，同一行像素单元的发光控制信号线和复位控制信号线满足：发光控制信号线的有效发光控制脉冲与复位控制信号线的有效复位脉冲不交叠。图7为同一行像素单元的发光控制信号线和复位控制信号线的驱动时序示意图，如图7所示，发光控制信号线EMIT的有效发光控制脉冲(图7示例性的为低电平)与复位控制信号线IN的有效复位脉冲(图7示例性的为低电平)不交叠。即复位控制信号线IN的有效复位脉冲应先截止，在 控制发光控制信号线EMIT的有效发光控制脉冲输入，发光控制信号线EMIT的有效发光控制脉冲截止后，复位控制信号线IN的有效复位脉冲再输入，从而避免复位控制信号线IN的有效复位脉冲和发光控制信号线EMIT的有效发光控制脉冲有交叠，使有机发光显示面板上的复位信号输入端与电源信号端之间短路，产生大电流。
本申请实施例对有机发光显示面板的像素驱动电路的具体电路结构不作限定，下面示例性提供几种可以实现本申请有益效果的几种像素驱动电路结构，而并非对本申请实施例的限定。
在上述各实施例的基础上，可选的，参见图8，像素驱动电路包括：
数据写入模块100、驱动模块200、复位模块300和发光控制模块400；
其中，数据写入模块100与驱动模块200电连接于第一节点N1；驱动模块200与发光控制模块400电连接于第二节点N2；复位模块300以及发光控制模块400均与发光元件500的阳极电连接；复位模块300与复位控制信号线IN电连接；发光控制模块400与发光控制信号线EMIT电连接。数据写入模块100用于向第一节点N1提供数据信号；驱动模块200用于在发光控制模块400导通时，驱动发光元件500发光；复位模块300用于在复位控制信号线IN输入有效复位脉冲时向发光元件的阳极提供复位信号U1，以使发光元件的阳极为复位电压U1(为便于描述，本文中复位信号与复位电压采用同一附图标记)。
可选的，发光控制模块400可以包括第一晶体管T1；复位模块300包括第二晶体管T2；第一晶体管T1为NMOS管，第二晶体管T2为PMOS管；或者第二晶体管T2为NMOS管，第一晶体管T1为PMOS管；每行像素单元对应的发光控制信号线复用为复位控制信号线。
参见图9，第一晶体管T1为PMOS管，第二晶体管T2为NMOS管，第一晶体 管T1和第二晶体管T2使用同一信号线，即每行像素单元对应的发光控制信号线EMIT复用为复位控制信号线IN，可以减少像素驱动电路中信号线的数量，并且可以减少有机发光显示面板中扫描驱动电路的数量，例如发光控制信号以及复位控制信号可以使用同一扫描驱动电路进行扫描输入。
在上述实施例的基础上，可选的，还可以在发光控制模块400与复位模块300之间串联限流电阻R，以避免第一晶体管T1和第二晶体管T2在开关切换瞬间产生大电流。
图10为本申请实施例提供的又一种像素驱动电路结构图，如图10所示，还可以包括存储模块600、阈值补偿模块700以及初始化模块800，存储模块600包括存储电容C，阈值补偿模块700包括第三晶体管T3，初始化模块800包括第四晶体管T4。数据写入模块100包括第五晶体管T5，驱动模块200包括第六晶体管T6。像素驱动电路还包括第七晶体管T7。
其中，第三晶体管T3的控制端与第五晶体管T5的控制端电连接；第三晶体管T3的第一极与电容C的第一极板电连接；第三晶体管T3的第二极以及第六晶体管T6的第二极均与第二节点N2电连接；第六晶体管T6的第一极与第一节点N1电连接，第六晶体管T6的控制端与第四晶体管T4的第二极电连接；第四晶体管T4的第一极与初始化信号端REF电连接；电容C的第二极板以及第七晶体管T7的第一极均与电源信号端PVDD电连接；第七晶体管T7的第二极以及第五晶体管T5的第二极均与第一节点N1电连接；第五晶体管T5的第一极与数据信号端DATA电连接；第一晶体管T1的控制端与第七晶体管T7的控制端均与发光控制信号端(用于输入光控制信号EMIT)电连接；第一晶体管T1的第一极与第二节点N2电连接；第一晶体管T1的第二极以及第二晶体管T2的第一极均与发光元件500的阳极电连接；第二晶体管T2的第二极与复位信号输入端(用 于输入复位信号U1)电连接；第二晶体管T2的控制端与复位控制信号端(用于输入复位控制信号IN)电连接。
可选的，第四晶体管T4的第一极与第二晶体管T2的第二极可以电连接，即初始化信号端与复位信号输入端共用。复位信号输入端输入的信号复位信号U1等于为驱动模块进行初始化的初始化电位REF。
复位信号输入端输入的信号还可以是零电位、地电位GND、发光元件的阴极电位、低于发光元件的阴极电位的公共负电位VSS,亦或者是与有机发光显示面板中其他电路共用的公共低电位VGL。
图11为本申请实施例提供的又一种有机发光显示面板的局部结构示意图，如图11所示，本申请实施例提供的有机发光显示面板还包括多个反相器组40；每个反相器组40包括第一反相器41和第一同相器42；
第一反相器41包括第一PMOS管B1和第一NMOS管C1；第一同相器42包括第二PMOS管B2和第二NMOS管C2。
第一PMOS管B1的控制端与第一NMOS管C1的控制端电连接于第三节点N3；第二PMOS管B2的控制端以及第二NMOS管C2的控制端均电连接于第四节点N4；第三节点N3与第四节点N4电连接。
第一PMOS管B1的第一极以及第二NMOS管C2的第二极均与高电平信号端VGH电连接；第一PMOS管B1的第二极与第一NMOS管C1的第一极电连接于第五节点N5；
第一NMOS管C1的第二极以及第二PMOS管B2的第一极均与低电平信号端VGL电连接；第二PMOS管B2的第二极与第二NMOS管C2的第一极电连接于第六节点N6；
第五节点N5还与发光阶段时序相同的子像素对应的复位控制信号线IN电 连接；
第六节点N6还与发光阶段时序相同的子像素对应的发光控制信号线EMIT电连接。
本申请实施例通过设置反相器组，可以使用同一个栅极驱动电路同时产生复位控制信号和发光控制信号。如图11所示，反相器组40可以同时产生复位控制信号IN和发光控制信号EMIT。本文中为便于描述，将复位控制信号线和复位控制信号均标记为IN，将发光控制信号线和发光控制信号均标记为EMIT。
在上述实施例的基础上，可选的，设置第一PMOS管B1的宽长比
Figure PCTCN2021083265-appb-000001
大于第二NMOS管C2的宽长比
Figure PCTCN2021083265-appb-000002
第一NMOS管C1的宽长比
Figure PCTCN2021083265-appb-000003
小于第二PMOS管B2的宽长比
Figure PCTCN2021083265-appb-000004
Figure PCTCN2021083265-appb-000005
本申请实施例通过调整反相器组中MOS管的宽长比，使得产生的复位控制信号和发光控制信号具有一定的延迟，即第一反相器41和第一同相器42的输出延时不同，产生如图7所示的驱动时序，避免有机发光显示面板上的复位信号输入端与电源信号端之间短路，产生大电流。
可选的，为使第一反相器41和第一同相器42的输出延时不同，如图12所示，还可以设置反相器组包括第一RC电路D1、第二RC电路D2、第三RC电路D3以及第四RC电路D4。
第一RC电路D1电连接于第一PMOS管B1的控制端与第三节点N3之间；第二RC电路D2电连接于第一NMOS管C1的控制端与第三节点N3之间；第三RC电路D3电连接于第二PMOS管B2的控制端与第四节点N4之间；第四RC电路D4电连接于第二NMOS管C2的控制端与第四节点N4之间；第一RC电路D1的时间 常数τ D1小于第三RC电路D3的时间常数τ D3；第二RC电路D2的时间常数τ D2大于第四RC电路D4的时间常数τ D4：
τ D1<τ D3；τ D2>τ D4；
通过调整第一RC电路D1、第二RC电路D2、第三RC电路D3以及第四RC电路D，满足上述时间常数关系，使第一反相器41和第一同相器42的输出延时不同。
可选的，本申请实施例还提供一种有机发光显示面板的局部结构示意图，如图13所示，本申请实施例提供的有机发光显示面板还包括多个反相器组40；每个反相器组40包括第一反相器41、第二反相器42和第三反相器43。
第一反相器41包括第一PMOS管B1和第一NMOS管C1；第二反相器42包括第二PMOS管B2和第二NMOS管C2；第三反相器43包括第三PMOS管B3和第三NMOS管C3；第一PMOS管B1的控制端与第一NMOS管C1的控制端电连接于第三节点N3；第二PMOS管B2的控制端与第二NMOS管C2的控制端电连接于第四节点N4；第三PMOS管B3的控制端与第三NMOS管C3的控制端电连接于第五节点N5。
第一PMOS管B1的第一极、第二PMOS管B2的第一极以及第三PMOS管B3的第一极均与高电平信号端VGH电连接；第一PMOS管B1的第二极与第一NMOS管C1的第一极电连接于第六节点N6；第一NMOS管C1的第二极、第二NMOS管C2的第二极以及第三NMOS管C3的第二极均与低电平信号端VGL电连接；第二PMOS管B2的第二极与第二NMOS管C2的第一极电连接于第七节点N7；第三PMOS管B3的第二极与第三NMOS管C3的第一极电连接于第八节点N8；第三节点N3与第四节点N4电连接；第六节点N6还与发光阶段时序相同的子像素对应的复位控制信号线IN电连接；第七节点N7与第五节点N5电连接；第八节点N8与 发光阶段时序相同的子像素对应的发光控制信号线EMIT电连接。
本申请实施例通过一个反相器向复位控制信号线输出复位控制信号，通两个串联的反相器向发光控制信号线输出发光控制信号，以使同一子像素接收的复位控制信号和发光控制信号的时序满足上述各实施例的要求。
可选的，在上述实施例的基础上，可以设置第二PMOS管B2的充放电时间常数t B2与第三NMOS管C3的充放电时间常数t C3之和大于第一PMOS管B1的充放电时间常数t B1，第二NMOS管C2的充放电时间常数t C2与第三PMOS管B3的充放电时间常数t B3之和小于第一NMOS管C1的充放电时间常数t C1:
t B1<t B2+t C3；t C2+t B3<t C1；
通过调整第一反相器41、第二反相器42和第三反相器43中的MOS管的充放电时间常数满足上述关系，使发光控制信号和复位控制信号的时序延时不同。
可选的，参见图14，反相器组40还可以包括第一RC电路D1；第一RC电路D1位于第三节点N3与第一NMOS管C1的控制端之间。
第二PMOS管B2的充放电时间常数t B2与第三NMOS管C3的充放电时间常数t C3之和大于第一PMOS管B1的充放电时间常数t B1；第二NMOS管C2的充放电时间常数t C2与第三PMOS管B3的充放电时间常数t B3之和小于第一NMOS管C1的充放电时间常数t C1与第一RC电路D1的时间常数τ D1之和：
t B1<t B2+t C3；t C2+t B3<t C1+τ D1。
本申请实施例还提供一种有机发光显示面板的驱动方法，该方法适用于上述任一实施例所述的有机发光显示面板，该方法包括：
在第i行像素单元的至少部分发光阶段，控制第i行像素单元的发光控制信号线的电位为第一电平；第j行像素单元的发光控制信号线的电位为第二电平；第i行像素单元的复位控制信号线的电位为第三电平，第j行像素单元的 复位控制信号线的电位为第四电平，以使第j行像素单元的发光元件阳极为复位电压，第j行像素单元处于非发光阶段，用于将所述第i行像素单元通过公共层产生的漏流导出；
其中，i和j均为大于等于1的正整数，第j行像素单元和第i行像素单元为相邻两行像素单元；第一电平为有效发光控制脉冲；第二电平为无效发光控制脉冲；第三电平为有效复位控制脉冲；第四电平为无效复位控制脉冲。
在第i行像素单元处于发光阶段的至少部分时间段内，与第i行相邻的第j行像素单元的发光元件阳极为复位电压，对阳极进行复位，不发光。因此若发光的第i行像素单元的某一颜色子像素对其临近的第j行像素单元的不同颜色子像素产生漏流，由于第j行像素单元的子像素的发光元件阳极为复位电压，可以将漏流导出，所以可以避免不同颜色子像素之间的串扰。
可选的，本申请实施例可以在每帧图像显示周期内，控制相邻两行像素单元的发光阶段不交叠。即第i行像素单元的子像素在整个发光阶段时，第j行像素单元的子像素均不发光，且发光元件阳极为复位电压，以使列方向上，相邻的两不同颜色的子像素在整个发光阶段均能避免漏电流导致的串扰问题。
可选的，可以设置有机发光显示面板中的奇数行像素单元对应的各发光控制信号线电连接；偶数行像素单元对应的各发光控制信号线电连接；奇数行像素单元对应的各复位控制信号线电连接；偶数行像素单元对应的各复位控制信号线电连接；在每帧图像显示周期内，奇数行像素单元同时发光；偶数行像素单元。例如如图4所示的驱动时序驱动有机发光显示面板进行发光。
可选的，本申请实施例还可以控制各奇数行像素单元逐行发光，各偶数行像素单元逐行发光；且相邻两奇数行的发光阶段交叠，相邻两偶数行的发光阶段交叠，例如按照如图6所示的驱动时序驱动有机发光显示面板进行发光。
可选的，本申请实施例提供的驱动方法可以控制每帧图像显示周期包括数据写入阶段和发光控制阶段；在每帧图像显示周期中的数据写入阶段，各行像素单元依次进行数据写入；在每帧图像显示周期的数据写入阶段结束后，执行发光控制阶段，在所述发光控制阶段，奇数行像素单元同时发光；偶数行像素单元同时发光。
或者，每帧图像显示周期包括数据写入阶段和发光控制阶段；在每帧图像显示周期中的数据写入阶段，各行像素单元依次进行数据写入；在发光控制阶段，各奇数行像素单元逐行发光，各偶数行像素单元逐行发光；且相邻两奇数行的发光阶段交叠，相邻两偶数行的发光阶段交叠。
在一实施例中，还可以控制前一帧图像显示周期中的发光控制阶段与后一帧图像显示周期的数据写入阶段交叠。
可选的，还可以设置每帧图像显示周期中的所述发光控制阶段包括多个子发光控制阶段；在每个子发光控制阶段，奇数行像素单元同时发光；偶数行像素单元同时发光，或者在每个子发光控制阶段，各奇数行像素单元逐行发光，各偶数行像素单元逐行发光；且相邻两奇数行的发光阶段交叠，相邻两偶数行的发光阶段交叠。
在上述各实施例的基础上，可选的，同一行像素单元的发光控制信号线和复位控制信号线满足：发光控制信号线的有效发光控制脉冲与复位控制信号线的有效复位脉冲不交叠，避免有机发光显示面板上的复位信号输入端与电源信号端之间短路，产生大电流。

Claims (20)

  1. 一种有机发光显示面板，包括：多个像素单元，每个像素单元包括多个不同颜色的子像素；所述子像素包括像素驱动电路和与所述像素驱动电路电连接的发光元件；所述发光元件包括公共层；相邻所述发光元件的公共层同层设置且连接；
    至少部分数量的子像素列，沿列方向相邻两子像素的发光颜色不同；
    同一行像素单元中的各子像素的像素驱动电路连接同一发光控制信号线；所述发光控制信号线传输有效发光控制脉冲时，该所述发光控制信号线电连接的像素驱动电路所属子像素处于发光阶段；
    同一行像素单元中的各子像素的像素驱动电路连接同一复位控制信号线；所述复位控制信号线传输有效复位脉冲时，该所述复位控制信号线电连接的像素驱动电路所属子像素的发光元件阳极为复位电压，该所述复位控制信号线电连接的像素驱动电路所属子像素处于非发光阶段；
    在每帧图像显示周期内，第i行像素单元处于发光阶段的至少部分时间段，第j行像素单元的发光元件阳极为复位电压，用于将所述第i行像素单元通过公共层产生的漏流导出；其中，i和j均为大于等于1的正整数，第j行像素单元和第i行像素单元为相邻两行像素单元；
    在每帧图像显示周期内，相邻两行像素单元的发光阶段不交叠。
  2. 根据权利要求1所述的有机发光显示面板，还包括第一扫描驱动电路、第二扫描驱动电路、第三扫描驱动电路以及第四扫描驱动电路；
    所述第一扫描驱动电路包括多个级联的第一移位寄存器；所述第二扫描驱动电路包括多个级联的第二移位寄存器；所述第三扫描驱动电路包括多个级联的第三移位寄存器；所述第四扫描驱动电路包括多个级联的第四移位寄存器；
    奇数行像素单元对应的各发光控制信号线与多个级联的第一移位寄存器一 一对应电连接；奇数行像素单元对应的各复位控制信号线与多个级联的第二移位寄存器一一对应电连接；偶数行像素单元对应的各发光控制信号线与多个级联的第三移位寄存器一一对应电连接；偶数行像素单元对应的各复位控制信号线与多个级联的第四移位寄存器一一对应电连接。
  3. 根据权利要求1所述的有机发光显示面板，其中，奇数行像素单元对应的各发光控制信号线电连接；偶数行像素单元对应的各发光控制信号线电连接；奇数行像素单元对应的各复位控制信号线电连接；偶数行像素单元对应的各复位控制信号线电连接；
    在每帧图像显示周期内，奇数行像素单元同时发光；偶数行像素单元同时发光。
  4. 根据权利要求1所述的有机发光显示面板，其中，
    各奇数行像素单元逐行发光，各偶数行像素单元逐行发光；且相邻两奇数行的发光阶段交叠，相邻两偶数行的发光阶段交叠。
  5. 根据权利要求4所述的有机发光显示面板，其中，每帧图像显示周期包括数据写入阶段和发光控制阶段；
    在每帧图像显示周期中的数据写入阶段，各行像素单元依次进行数据写入；
    在每帧图像显示周期的数据写入阶段结束后，执行发光控制阶段，在所述发光控制阶段，奇数行像素单元同时发光；偶数行像素单元同时发光。
  6. 根据权利要求4所述的有机发光显示面板，其中，每帧图像显示周期包括数据写入阶段和发光控制阶段；
    在每帧图像显示周期中的数据写入阶段，各行像素单元依次进行数据写入；
    在所述发光控制阶段，各奇数行像素单元逐行发光，各偶数行像素单元逐行发光；且相邻两奇数行的发光阶段交叠，相邻两偶数行的发光阶段交叠。
  7. 根据权利要求6所述的有机发光显示面板，其中，前一帧图像显示周期中的发光控制阶段与后一帧图像显示周期的数据写入阶段交叠。
  8. 根据权利要求5所述的有机发光显示面板，其中，在每帧图像显示周期中的所述发光控制阶段包括多个子发光控制阶段；
    在每个所述子发光控制阶段，奇数行像素单元同时发光；偶数行像素单元同时发光。
  9. 根据权利要求6所述的有机发光显示面板，其中，在每帧图像显示周期中的所述发光控制阶段包括多个子发光控制阶段；
    在每个所述子发光控制阶段，各奇数行像素单元逐行发光，各偶数行像素单元逐行发光；且相邻两奇数行的发光阶段交叠，相邻两偶数行的发光阶段交叠。
  10. 根据权利要求1所述的有机发光显示面板，其中，同一行像素单元的发光控制信号线和复位控制信号线满足：
    所述发光控制信号线的有效发光控制脉冲与所述复位控制信号线的有效复位脉冲不交叠。
  11. 根据权利要求1所述的有机发光显示面板，其中，所述像素驱动电路包括：
    数据写入模块、驱动模块、复位模块和发光控制模块；
    其中，所述数据写入模块与所述驱动模块电连接于第一节点；所述驱动模块电与所述发光控制模块电连接于第二节点；所述复位模块与所述发光控制模块均与所述发光元件的阳极电连接；所述复位模块与所述复位控制信号线电连接；所述发光控制模块与所述发光控制信号线电连接；
    所述数据写入模块用于向所述第一节点提供数据信号；所述驱动模块用于 在所述发光控制模块导通时，驱动所述发光元件发光；所述复位模块向所述发光元件的阳极提供复位信号。
  12. 根据权利要求11所述的有机发光显示面板，其中，所述发光控制模块包括第一晶体管；所述复位模块包括第二晶体管；所述第一晶体管为NMOS管，所述第二晶体管为PMOS管；或者所述第二晶体管为NMOS管，所述第一晶体管为PMOS管；每行像素单元对应的所述发光控制信号线复用为所述复位控制信号线。
  13. 根据权利要求12所述的有机发光显示面板，其中，所述发光控制模块与所述复位模块之间串联有限流电阻。
  14. 根据权利要求1所述的有机发光显示面板，其中，还包括多个反相器组；每个所述反相器组包括第一反相器和第一同相器；
    所述第一反相器包括第一PMOS管和第一NMOS管；所述第一同相器包括第二PMOS管和第二NMOS管；
    所述第一PMOS管的控制端与第一NMOS管的控制端电连接于第三节点；所述第二PMOS管的控制端以及所述第二NMOS管的控制端均电连接于第四节点；所述第三节点与所述第四节点电连接；
    所述第一PMOS管的第一极以及所述第二NMOS管的第二极均与高电平信号端电连接；所述第一PMOS管的第二极与所述第一NMOS管的第一极电连接于第五节点；
    所述第一NMOS管的第二极以及所述第二PMOS管的第一极均与低电平信号端电连接；所述第二PMOS管的第二极与所述第二NMOS管的第一极电连接于第六节点；
    所述第五节点还与发光阶段时序相同的子像素对应的所述复位信号控制线 电连接；
    所述第六节点还与发光阶段时序相同的子像素对应的所述发光控制信号线电连接。
  15. 根据权利要求14所述的有机发光显示面板，其中，第一PMOS管的宽长比大于第二NMOS管的宽长比；第一NMOS管的宽长比小于第二PMOS管的宽长比。
  16. 根据权利要求14所述的有机发光显示面板，其中，所述反相器组还包括第一RC电路、第二RC电路、第三RC电路以及第四RC电路；
    所述第一RC电路电连接于所述第一PMOS管的控制端与所述第三节点之间；所述第二电路电连接于所述第一NMOS管的控制端与所述第三节点之间；
    所述第三RC电路电连接于所述第二PMOS管的控制端与所述第四节点之间；所述第四电路电连接于所述第二NMOS管的控制端与所述第四节点之间；
    所述第一RC电路的时间常数小于所述第三RC电路的时间常数；
    所述第二RC电路的时间常数大于所述第四RC电路的时间常数。
  17. 根据权利要求1所述的有机发光显示面板，还包括多个反相器组；每个所述反相器组包括第一反相器、第二反相器和第三反相器；
    所述第一反相器包括第一PMOS管和第一NMOS管；所述第二反相器包括第二PMOS管和第二NMOS管；所述第二反相器包括第三PMOS管和第三NMOS管；所述第一PMOS管的控制端与所述第一NMOS管的控制端电连接于第三节点；所述第二PMOS管的控制端与所述第二NMOS管的控制端电连接于第四节点；
    所述第三PMOS管的控制端与所述第三NMOS管的控制端电连接于第五节点；
    所述第一PMOS管的第一极、所述第二PMOS管的第一极以及所述第三PMOS管的第一极均与高电平信号端电连接；所述第一PMOS管的第二极与所述第一 NMOS管的第一极电连接于第六节点；所述第一NMOS管的第二极、所述第二NMOS管的第二极以及所述第三NMOS管的第二极均与低电平信号端电连接；所述第二PMOS管的第二极与所述第二NMOS管的第一极电连接于第七节点；所述第三PMOS管的第二极与所述第三NMOS管的第一极电连接于第八节点；所述第三节点与所述第四节点电连接；所述第六节点还与发光阶段时序相同的子像素对应的所述复位信号控制线电连接；所述第七节点与所述第五节点电连接；所述第八节点与发光阶段时序相同的子像素对应的所述发光控制信号线电连接。
  18. 根据权利要求17所述的有机发光显示面板，其中，
    所述第二PMOS管的充放电时间常数与所述第三NMOS管的充放电时间常数之和大于所述第一PMOS管的充放电时间常数；
    所述第二NMOS管的充放电时间常数与第三PMOS管的充放电时间常数之和小于第一NMOS管的充放电时间常数。
  19. 根据权利要求17所述的有机发光显示面板，其中，所述反相器组还包括第一RC电路；所述第一RC电路位于所述第三节点与所述第一NMOS管的控制端之间；
    所述第二PMOS管的充放电时间常数与所述第三NMOS管的充放电时间常数之和大于所述第一PMOS管的充放电时间常数；
    所述第二NMOS管的充放电时间常数与所述第三PMOS管的充放电时间常数之和小于所述第一NMOS管的充放电时间常数与所述第一RC电路的时间常数之和。
  20. 一种有机发光显示面板的驱动方法，适用于权利要求1-19中任一项所述的有机发光显示面板，所述方法包括：
    在第i行像素单元的至少部分发光阶段，控制第i行像素单元的发光控制 信号线的电位为第一电平；第j行像素单元的发光控制信号线的电位为第二电平；第i行像素单元的复位控制信号线的电位为第三电平，第j行像素单元的复位控制信号线的电位为第四电平，以使第j行像素单元的发光元件阳极为复位电压，第j行像素单元处于非发光阶段，用于将所述第i行像素单元通过公共层产生的漏流导出；
    其中，i和j均为大于等于1的正整数，第j行像素单元和第i行像素单元为相邻两行像素单元；所述第一电平为有效发光控制脉冲；所述第二电平为无效发光控制脉冲；所述第三电平为无效复位控制脉冲；所述第四电平为有效复位控制脉冲。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111968576B (zh) 2020-08-21 2022-01-07 上海视涯技术有限公司 一种有机发光显示面板以及驱动方法
WO2023279374A1 (zh) * 2021-07-09 2023-01-12 京东方科技集团股份有限公司 显示基板和显示装置
CN113593471B (zh) * 2021-07-29 2022-12-02 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板、显示装置
CN113707091B (zh) * 2021-09-07 2022-11-01 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
WO2023070530A1 (zh) * 2021-10-29 2023-05-04 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板、显示装置

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1417767A (zh) * 2001-11-09 2003-05-14 三洋电机株式会社 对光学元件的亮度数据具有初始化功能的显示器
KR20070109674A (ko) * 2006-05-12 2007-11-15 엘지.필립스 엘시디 주식회사 평면표시장치의 화소구조
CN101739954A (zh) * 2008-11-07 2010-06-16 索尼株式会社 显示设备以及电子产品
CN102110410A (zh) * 2009-12-25 2011-06-29 索尼公司 显示装置和电子装置
JP2011145622A (ja) * 2010-01-18 2011-07-28 Toshiba Mobile Display Co Ltd 表示装置および表示装置の駆動方法
CN103003864A (zh) * 2010-07-12 2013-03-27 夏普株式会社 显示装置及其驱动方法
CN103168324A (zh) * 2010-10-21 2013-06-19 夏普株式会社 显示装置及其驱动方法
US20160211315A1 (en) * 2011-07-29 2016-07-21 Seiko Epson Corporation Electro-optical device, driving method of electro-optical device, and electronic apparatus
CN108281461A (zh) * 2016-12-30 2018-07-13 乐金显示有限公司 有机发光显示装置
CN108648708A (zh) * 2018-05-08 2018-10-12 深圳市华星光电技术有限公司 显示面板的驱动方法、显示面板及显示装置
US20190371236A1 (en) * 2017-03-24 2019-12-05 Sharp Kabushiki Kaisha Display device, and driving method of pixel circuit of display device
CN110689833A (zh) * 2014-05-27 2020-01-14 索尼公司 显示装置
CN111833816A (zh) * 2020-08-21 2020-10-27 上海视涯技术有限公司 一种有机发光显示面板以及驱动方法
CN111968576A (zh) * 2020-08-21 2020-11-20 上海视涯技术有限公司 一种有机发光显示面板以及驱动方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5196512B2 (ja) * 2004-03-31 2013-05-15 ルネサスエレクトロニクス株式会社 ディスプレイパネル駆動方法，ドライバ，及びディスプレイパネル駆動用プログラム
JP2013231920A (ja) * 2012-05-01 2013-11-14 Samsung R&D Institute Japan Co Ltd 電気光学装置およびその駆動方法
KR101970574B1 (ko) * 2012-12-28 2019-08-27 엘지디스플레이 주식회사 Oled 표시 장치
KR102218779B1 (ko) * 2014-07-04 2021-02-19 엘지디스플레이 주식회사 Oled 표시 장치
CN106710529B (zh) * 2016-12-19 2019-02-05 上海天马有机发光显示技术有限公司 一种像素驱动电路、驱动方法及有机发光显示面板
CN106920513B (zh) * 2017-05-12 2019-09-24 京东方科技集团股份有限公司 显示面板的驱动电路、显示面板和显示装置
US11158256B2 (en) * 2017-12-06 2021-10-26 Apple Inc. Methods and apparatus for mitigating charge settling and lateral leakage current on organic light-emitting diode displays
JP7105098B2 (ja) * 2018-05-01 2022-07-22 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 表示装置
KR20200068120A (ko) * 2018-12-04 2020-06-15 삼성디스플레이 주식회사 유기 발광 표시 장치를 위한 표시 패널 구동 방법
CN110189702B (zh) * 2019-06-28 2021-01-01 合肥视涯技术有限公司 一种有机发光显示面板及其驱动方法

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1417767A (zh) * 2001-11-09 2003-05-14 三洋电机株式会社 对光学元件的亮度数据具有初始化功能的显示器
KR20070109674A (ko) * 2006-05-12 2007-11-15 엘지.필립스 엘시디 주식회사 평면표시장치의 화소구조
CN101739954A (zh) * 2008-11-07 2010-06-16 索尼株式会社 显示设备以及电子产品
CN102110410A (zh) * 2009-12-25 2011-06-29 索尼公司 显示装置和电子装置
JP2011145622A (ja) * 2010-01-18 2011-07-28 Toshiba Mobile Display Co Ltd 表示装置および表示装置の駆動方法
CN103003864A (zh) * 2010-07-12 2013-03-27 夏普株式会社 显示装置及其驱动方法
CN103168324A (zh) * 2010-10-21 2013-06-19 夏普株式会社 显示装置及其驱动方法
US20160211315A1 (en) * 2011-07-29 2016-07-21 Seiko Epson Corporation Electro-optical device, driving method of electro-optical device, and electronic apparatus
CN110689833A (zh) * 2014-05-27 2020-01-14 索尼公司 显示装置
CN108281461A (zh) * 2016-12-30 2018-07-13 乐金显示有限公司 有机发光显示装置
US20190371236A1 (en) * 2017-03-24 2019-12-05 Sharp Kabushiki Kaisha Display device, and driving method of pixel circuit of display device
CN108648708A (zh) * 2018-05-08 2018-10-12 深圳市华星光电技术有限公司 显示面板的驱动方法、显示面板及显示装置
CN111833816A (zh) * 2020-08-21 2020-10-27 上海视涯技术有限公司 一种有机发光显示面板以及驱动方法
CN111968576A (zh) * 2020-08-21 2020-11-20 上海视涯技术有限公司 一种有机发光显示面板以及驱动方法

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