Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
  • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
  • H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
  • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
  • H03L7/104—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional signal from outside the loop for setting or controlling a parameter in the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Definitions

• the invention relates in general to generating a plurality of synchronized radio frequency (RF) signals each having a respective output frequency, phase, and amplitude, e.g. for driving a plasma processing system.
• the invention relates to a control unit, a radio frequency power generator, and a method for generating a plurality of synchronized radio frequency signals each having a respective output frequency, phase, and amplitude.
• the invention relates to an arrangement of at least two such radio frequency power generators.
• US 2010/0164561 Al describes an example for generating radio frequency signals.
• US 2013/0170512 Al describes multiple phase-locked loops for high-power RF -power combiners, wherein by means of each respective phase-locked loop one respective radio frequency output signal is generated, meaning that for each individual RF output signal one phase-locked loop is required.
• Scalability is therefore rather limited, or requires at least high efforts with respect to high design and manufacturing complexity, high operational complexity to keep the individual RF output signals synchronized within required tolerances for example (cf. noise or thermal drift), high number of electronic components, high cost, and the like.
• a control unit a radio frequency power generator, and a method each for generating a plurality of synchronized radio frequency signals being distinguished by an improved performance, where performance is assessed, inter alia, on the qualities of scalability, operational robustness, frequency precision, application flexibility, manufacturing ease and cost.
• a control unit e.g. as part of a radio frequency (for short, also referred to as RF herein) power generator, for generating a plurality of synchronized RF output signals each having a respective output frequency, phase, and amplitude comprises: a signal comparator configured to compare a reference signal having a reference frequency and a reference phase with a feedback signal having a feedback frequency and a feedback phase, and the signal comparator being configured to generate an error signal representative of a difference between the reference signal and the feedback signal; and a data processing unit, e.g.
• RF radio frequency
• an electronic data processing unit such as a microprocessor, microcontroller, digital signal processor and the like, receiving as an input signal the error signal generated by the signal comparator, and outputting a plurality of waveform tuning signals as a function of the error signal; further comprising: a plurality of waveform generators each receiving at least one of the plurality of waveform tuning signals output by the data processing unit, wherein each waveform generator generates a time-dependent amplitude signal as a function of the received respective waveform tuning signal; wherein one predetermined amplitude signal of the generated plurality of amplitude signals represents the feedback signal input to the signal comparator, and the other amplitude signals represent the respective RF output signals to be generated; and wherein the data processing unit is configured to adjust both the waveform tuning signal corresponding to the one predetermined amplitude signal representing the feedback signal such as to minimize the error signal, and the other waveform tuning signals corresponding to the other amplitude signals representing the RF output signals based on the adjusted waveform tuning signal of the predetermined amplitude signal representing the feedback
• the term “signal” denotes a function that conveys information about a phenomenon, e.g. a varying voltage or current.
• the signal may comprise an analog or a digital signal unless otherwise actually specified.
• the error signal is minimal or may be zero when the feedback signal (almost) equals the reference signal, e.g. with respect to their respective phases and/or frequencies. The bigger the difference between the reference signal and the feedback signal, the greater the amount of the error signal.
• waveform tuning signal denotes information, be it represented either analogously or digitally, characterizing the time- dependent amplitude signal, again either as an analogously or digitally represented information (e.g. a digital bitstream representing discrete amplitude values of the RF output signal to be generated by the control unit).
• the waveform generator generates the time-dependent amplitude signal as a function of the respective waveform tuning signal input thereto.
• one of the plurality of time-dependent amplitude signals is associated with the feedback signal, whereas the other amplitude signals are respectively associated with one of the plurality of RF output signals to be generated by the control unit.
• the arrangement of the data processing unit being configured to adjust the waveform tuning signal corresponding to the one predetermined amplitude signal representing the feedback signal such as to minimize the error signal output by the signal comparator, and the signal comparator which receives the reference signal and the feedback signal as input signals constitutes a control loop, e.g. a phase-locked loop (herein also referred to as PLL for short).
• a control loop e.g. a phase-locked loop (herein also referred to as PLL for short).
• the control unit facilitates the generation of a multitude of RF output signals mutually synchronized and also synchronized to the reference signal (through the feedback signal) by using only one single control loop.
• all output RF signals are frequency locked to the reference signal, and - in case they have the same frequency as the reference signal (i.e. feedback signal) - they are even phase-locked.
• the analog RF output signals may be used to drive multi-stage power amplifier circuits to produce medium- or high-frequency power signals.
• some output signals may be used to serve as reference signals for further synchronized signal sources, e.g. additional medium- or high- frequency power supplies.
• all other output signals can have arbitrary frequencies and phase differences, as required for the specific application.
• the generated RF output signals possibly having several different frequencies and/or phases and/or amplitudes with respect to each other may be routed into respective power amplifiers.
• the resulting power RF output signals may then be used to supply a plasma processing system for semiconductor wafers with RF power of multiple frequencies, for example.
• RF power of multiple frequencies in plasma processes advantageously allows to adjust multiple parameters to better control, among others, ion density, electron density, and plasma uniformity over a large area: this ultimately results in quality improvement of the semiconductor being processed because various key process parameters can be adjusted more independently compared to a single-frequency powered process.
• the RF output signals may be used also as so-called common exciter (CEX) signals to synchronize additional power generators.
• CEX common exciter
• RF output signals to be used as CEX signals for further power generators may be generated to have a specific phase difference to other RF output signals of the same frequency.
• the phase difference can either be implemented already in the CEX signal from the first power generator, or it can be added by a (e.g. digital) waveform generator in the other power generator(s).
• control unit may be set up with different phase shifts for plasma systems which process large area substrates where RF power is fed into multiple input ports.
• the phase differences between the individual input ports may be adjusted such as to produce a most homogeneous process result over the entire substrate surface.
• the control unit according to the invention is scalable to any number of RF output signals (also referred to as channels herein) which are all synchronized to the same reference signal and/or phase locked (depending on if the RF output signal of a channel has the same frequency as the frequency of the reference signal, is a multiple of the reference frequency, or has a constant phase offset to the reference frequency). For this, only one single (PLL) control loop is needed.
• the reference loop (control loop) and an arbitrary number of RF output channel s/signals are fully synchronized (time base sync / phase lock), however, still their signals are fully decoupled.
• any newly generated RF output signal on any channel with any frequency or output amplitude is immediately locked. There is absolutely no (zero) settling time or transitory effects. The same holds true for any intentional changes of frequency or phase of any of the RF output signals. Due to the disclosed concept herein no other feedback/control loop is needed.
• non-precision internal system clocks i.e. cost advantage
• offsets and variations of these nonprecision clocks e.g. thermal drifts
• Variations of the system clock will automatically cause the waveform tuning signals corresponding to the RF output signals to be adjusted such that they are always locked to the feedback signal and the reference signal, respectively.
• the reference frequency and the output frequency of a PLL signal generator are different (e.g. 1 MHz as reference, and 10 MHz as output frequency).
• the output signal cannot be used directly as a feedback signal for the comparator circuit, e.g. a phase-frequency discriminator (PFD).
• the feedback signal has to be transformed into a signal of the same frequency as the reference by means of a divider circuit (e.g. with a 1 : 10 ratio).
• a divider circuit e.g. with a 1 : 10 ratio.
• Such a divider is required with conventional solutions such as shown, for example, in the afore-mentioned patent application publication US 2013/0170512 Al.
• the present invention there is no need for a divider, since always a feedback signal with the same frequency as the reference is generated.
• the other RF output signals which will be used for the application can have any frequency and/or phase-shift, independent from the reference signal. Nevertheless, they are synchronized with the (PLL) reference signal via the feedback signal.
• the use of one single specific output signal as the feedback signal for the (PLL) control loop allows to simplify also pulsing operations.
• Those RF output signals which shall be pulsed can be modulated directly via the respective waveform generator by setting the corresponding time-dependent amplitude signal to zero, while the feedback signal is left unchanged without switching it off. Therefore, the synchronization is maintained at all times independent of the pulse pattern.
• the pulsing has to be achieved by modulating the amplitude after branching the control signal for the PLL loop, e.g. by means of a switch. If the signal were already pulsed at the source, the feedback signal would be modulated as well, and this would cause loss of synchronization after every pulse.
• the feedback signal for the PLL which is branched off the main output signal would vary in amplitude as well. This would affect the accuracy of the PLL loop by amplitude/phase noise for low amplitudes.
• the feedback signal has always the same amplitude without variation, i.e. being independent from amplitude modulations of the RF output signals. Since there is zero settling time for changes to frequency and/or phase of the RF output signals, this also means that changes in frequency or phase of different output channel s/signals can be timed against each other.
• a master generator may provide CEX signals for the connected slave generator(s), or a chain of generators is formed in which each generator may provide a CEX signal for the next generator in the sequence.
• the length of the CEX signal cable adds an intrinsic phase shift to the CEX signal which is received by the slave generator.
• phase shifts due to cable length can easily be compensated on either the sending or the receiving generator by adding an appropriate compensating phase shift to the respective RF output signal. Configurations with identical or individual intentional phase shifts between the CEX input signals of a multitude of generators and a master generator can be realized with the invention.
• the control unit ensures high system scalability, high operational robustness, in particular low susceptibility to interference due to noise, temperature and the like, high signal precision/synchronization with respect to frequency and phase, a high degree of freedom with respect to a multitude of different application scenarios, and also facilitates comparatively low design and manufacturing complexity and cost.
• the signal comparator is configured to compare at least one of a phase difference and a frequency difference of the reference signal and the feedback signal, wherein the error signal is representative of at least one of said phase difference and frequency difference.
• a PLL as a control loop requires the evaluation of the phase difference between the signals to be compared.
• it may suffice to compare the frequencies of the signals to be compared for example by means of a counter device, thus an evaluation of the phase difference between the reference and the feedback signals may be omitted.
• the signal comparator is at least one of a phase discriminator (PD), phase-frequency discriminator (PFD), a frequency mixer, and a counter.
• the reference signal comprises one of a precision crystal oscillator signal, an oven- controlled crystal oscillator (OCXO) signal, an atomic clock signal, a high-precision oscillator signal synchronized with an atomic clock, and a common exciter (CEX) signal generated by an RF generator, e.g. an RF generator according to another aspect of the invention as described further below.
• OCXO oven- controlled crystal oscillator
• CEX common exciter
• control unit further comprises a reference signal source configured to generate the reference signal, e.g. the reference signals as set forth above, i.e. a precision crystal oscillator, an oven-controlled crystal oscillator (OCXO), a high-precision oscillator synchronized with an atomic clock.
• a reference signal source configured to generate the reference signal, e.g. the reference signals as set forth above, i.e. a precision crystal oscillator, an oven-controlled crystal oscillator (OCXO), a high-precision oscillator synchronized with an atomic clock.
• control unit comprises a series connection of a loop filter and an analog-to-digital-converter (ADC) configured and arranged such as to generate a digital representation of the error signal from the signal comparator.
• ADC analog-to-digital-converter
• the digital representation of the error signal is fed to the data processing unit.
• the data processing unit is a digital data processing unit outputting a plurality of digital waveform tuning words as the waveform tuning signals as an input for the plurality of waveform generators.
• the digital data processing unit may be, without limitation, a microprocessor, microcontroller, digital signal processor, and the like.
• the waveform tuning words are digital representations of the respective waveform tuning signals.
• the waveform tuning words may be structured as a group of several digital bits, e.g. 8, 12, 16, 32, 64, and the like, however, without being limited to the afore-listed values.
• the waveform tuning word may comprise bits for frequency information, bits for phase information, and/or bits for amplitude information (e.g. an amplitude multiplication factor).
• the waveform tuning word comprises at least one of a frequency information, a phase information, and an amplitude information for generating the time-dependent amplitude signal.
• each of the waveform generators comprises a direct digital synthesis (DDS) core generating a digital bitstream representative of digital amplitude values constituting the respective time-dependent amplitude signal.
• DDS direct digital synthesis
• control unit comprises at least one digital-to-analog-converter (DAC) converting the digital amplitude values contained in the bitstreams generated by the waveform generators into the feedback signal and the RF output signals, respectively.
• DAC digital-to-analog-converter
• the digital-to-analog- converter is one of a multi-channel digital-to-analog-converter, a plurality of single-channel digital-to-analog-converters, a plurality of dual-channel digital-to- analog-converters or a combination thereof.
• the DAC converting all the digital amplitude values into both the feedback signal and the RF output signals may be embodied by a combination of several dual-channel DACs, thus reducing the overall number of required DACs by the factor of two compared to using only single-channel DACs.
• one multi-channel DAC may be used comprising at least as many conversion channels as are necessary to convert the feedback signal and all the RF output signals to be generated.
• the control unit comprises at least one signal reconstruction filter filtering at least one of the RF output signals after conversion by the DAC.
• the reconstruction filter may be a low-pass or a band-pass filter, for example, which removes unwanted frequency components and noise.
• a reconstruction filter may be omitted depending on the specific design of the signal comparator circuit.
• control unit comprises a feedback signal reconstruction filter filtering the feedback signal after conversion by the DAC.
• reconstruction filter may be a low-pass or a bandpass filter, for example, which removes unwanted frequency components and noise.
• At least one of the data processing unit and the plurality of waveform generators is/are formed by at least one of a field programmable gate array (FPGA), a System-on-Chip (SoC), and an application-specific integrated circuit (ASIC).
• FPGA field programmable gate array
• SoC System-on-Chip
• ASIC application-specific integrated circuit
• control unit comprises a system clock generating a system clock signal, wherein the plurality of waveform generators and the digital-to-analog converter (DAC) are driven by the system clock signal.
• system clock may be a non-precision system clock (cost advantage).
• any temporal variations of the (non-precision) system clock frequency and its derived clock signals are automatically compensated since all waveform tuning signals/words corresponding to the RF output signals are calculated from the waveform tuning signal/word corresponding to the feedback signal which is locked to the reference signal/frequency.
• a waveform generator clock signal for driving the waveform generators and a DAC clock signal for driving the DAC are different predetermined rational fractions of the system clock signal of the system clock.
• different driving clock signals are derived from the common system clock signal for the waveform generators and the DAC(s), respectively.
• the system clock signal and all derived clock signals e.g. waveform generator clock signals and/or data processing clock signal (e.g. an FPGA clock signal if the waveform generator and/or the data processing unit is/are formed by an FPGA as mentioned above) and DAC clock signals, are not precision clock signals. Their values might slightly deviate from the specified (nominal) value, and in addition, their values might vary over time depending on environmental factors, e.g. thermal effects.
• FPGA clock (signal) is used in the description below to denote a clock (signal) driving at least the waveform generators, and optionally also the data processing unit. It is to be emphasized, however, that the term FPGA clock (signal) is not to be meant being limited to only FPGA embodiments of the waveform generators and/or the data processing unit.
• FPGA clock shall comprise embodiments where the waveform generators and/or the data processing unit are embodied by a System-on-Chip (SoC) or an application-specific integrated circuit (ASIC) or other circuit means known in the art suitable to embody the waveform generators and/or the data processing unit according to the invention.
• SoC System-on-Chip
• ASIC application-specific integrated circuit
• the FPGA clock frequency is typically a rational number multiple mi/ni of the system clock frequency, e.g. 33.3 MHz for a 100 MHz system clock frequency (wherein mi and ni are integer numbers).
• the DAC clock frequency is derived from the system clock and is typically a rational number multiple m2/ri2 of the system clock, e.g. system clock frequency 100 MHz, DAC clock frequency 1 GHz (wherein m2 and ri2 are integer numbers).
• the described invention allows to synchronize the internal clocks of the control unit with the precision reference frequency, e.g. an internal precision oscillator or an externally provided precision CEX signal.
• the precision reference frequency e.g. an internal precision oscillator or an externally provided precision CEX signal.
• the waveform tuning signal/word corresponding to the feedback signal which is required to exactly match the reference signal/frequency is adjusted by means of the error signal output by the signal comparator until the deviation between the reference signal/frequency and the feedback signal/frequency is minimized, e.g. equals zero.
• each waveform generator comprises a direct digital synthesis (DDS) core
• FPGA clock where N is the number of bits of a DDS phase accumulator, fpLL is the frequency of the (PLL) feedback signal, and FTWPLL is a waveform tuning word corresponding to the (PLL) feedback signal.
• DAC clock where m2/ri2 is the rational factor between the system clock and the FPGA clock.
• waveform tuning signals/words FTW corresponding to all other RF output signals are calculated from FTWPLL, they continuously follow any changes of FTWPLL.
• a presumed FPGA clock frequency of 200 MHz which in reality is 202 MHz, would cause all other frequencies to be 1 % higher than their intended value, e.g. instead of an appropriate ISM frequency (ISM: Industrial, Scientific and Medical Band) of 13.56 MHz, the output signal of a generator would be 13.70 MHz. In case of a thermal drift, the output frequency would more and more drift away from the intended value.
• ISM Industrial, Scientific and Medical Band
• control unit further comprises a memory device, e.g. RAM, EPROM, Flash, ROM, and the like, storing a plurality of predeterminable waveform set values each corresponding to a respective one of the waveform tuning signals of the RF output signals to be generated.
• data processing unit is further configured to output the plurality of waveform tuning signals as a function of the waveform set values.
• the waveform set values may comprise at least one of a frequency information, a phase information, and an amplitude information corresponding to the respective frequency information, phase information, or amplitude information represented by the waveform tuning signal and waveform tuning word, respectively.
• control unit comprises a control device configured to modify the waveform set values stored in the memory device according to a predefined schedule, e.g. an applicationspecific processing recipe.
• a control device configured to modify the waveform set values stored in the memory device according to a predefined schedule, e.g. an applicationspecific processing recipe.
• a highly dynamic and time-variable processing scheme may be accomplished using the control unit according to the invention (e.g. pulsing operations).
• a radio frequency (RF) power generator for generating a plurality of synchronized radio frequency (RF) output signals each having a respective output frequency, phase, and amplitude, comprises: a DC power supply; at least one power amplifier receiving power from the DC power supply, and configured to amplify at least one of the plurality of RF output signals; and a control unit for generating the plurality of RF output signals, wherein the control unit is configured according to any of the embodiments disclosed herein according to the invention.
• RF output signals of the RF power generator according to the invention are necessarily amplified. Particularly, the amplification by the power amplifier is only required for RF power output signals, however, not for common exciter (CEX) signals which may be output and used to synchronize further RF power generators, for example, as will be described in more detail further below.
• CEX common exciter
• the RF power generator comprises a common exciter input connected to the control unit for receiving an external common exciter (CEX) signal as the reference signal.
• CEX common exciter
• a high precision reference signal may be generated external of the RF power generator according to the invention by means of another RF power generator.
• the other RF power generator can be an RF power generator according to the invention without being limited thereto.
• An arrangement including other RF power generators being fed the CEX output signal generated by the RF power generator according to the invention as a reference input signal is also conceivable.
• the RF power generator comprises at least one common exciter (CEX) output providing a respective one of the plurality of RF output signals as an external CEX signal.
• CEX common exciter
• such output CEX signal may not be amplified by a power amplifier amplifying other RF output signals which may be used as RF power output signals to drive a plasma process, for example.
• the CEX output signal may be used to synchronize further RF power generators as described herein.
• the RF power generator comprises a user interface device (input/output device), e.g. a display, keyboard, touch screen and the like, for at least one of setting the output frequencies, phases, and amplitudes of the RF output signals to be generated as well as monitoring an operational state of the RF power generator.
• a user interface device input/output device
• the user interface setting of temporal sequences of respective output frequencies phase shifts and amplitudes will become feasible.
• periodic modulation of the amplitude of the RF output signals may be used for pulsing applications as described herein.
• the user interface may also be configured to receive sequences of commands for setting output frequencies, phases, and amplitudes in a temporal sequence from an external computer.
• an arrangement of at least two radio frequency (RF) power generators each for generating a plurality of synchronized radio frequency (RF) output signals each having a respective output frequency, phase, and amplitude provides that one of the RF power generators is configured according to the afore-mentioned embodiment comprising the common exciter (CEX) output, and at least one other of the RF power generators is configured according to the afore-mentioned embodiment comprising the common exciter (CEX) input; wherein the RF power generators are interconnected such that the common exciter output of the one of the RF power generators is connected to the common exciter input of the at least one other of the RF power generators.
• RF radio frequency
• the CEX signal output via the CEX output of the one RF power generator is used as a precision reference signal to synchronize the other RF power generator(s).
• the CEX output signal may have a different frequency and/or phase than the reference signal input to the RF power generator generating the CEX output signal.
• the CEX output signal is not power amplified by a power amplifier as already described above. However, a small preamplification by a preamplifier may be advantageously applied to the CEX output signal before outputting it via the CEX output.
• the CEX output signals differ from the RF power output signals of the RF power generator in that they are not used as a user signal (e.g. to excite a plasma in a plasma process) but rather as a control/reference signal for synchronizing subsequent RF power generators.
• a method for generating a plurality of synchronized radio frequency (RF) output signals each having a respective output frequency, phase, and amplitude comprises the steps of: (i) comparing a reference signal having a reference frequency and a reference phase with a feedback signal having a feedback frequency and a feedback phase; (ii) generating an error signal representative of a difference between the reference signal and the feedback signal; (iii) generating a plurality of waveform tuning signals as a function of the error signal; (iv) generating a plurality of time-dependent amplitude signals each one as a function of a respective one of the plurality of waveform tuning signals; (v) selecting one predetermined amplitude signal of the generated plurality of amplitude signals as a representation of the feedback signal in step (i); and (vi) outputting the other amplitude signals as the respective RF output signals to be generated; wherein in step (iii) the one waveform tuning signal corresponding to the one predetermined amplitude signal
• the method further comprises the steps of: (vii) setting at least one of a frequency, phase, and amplitude as predeterminable signal parameters for at least one of the plurality of RF output signals; (viii) repeating steps (i) to (vi) above for a predetermined time interval; and (ix) repeating steps (vii) and (viii) a predefined number of times.
• Fig. 1 illustrates a functional diagram of an exemplary embodiment of an RF power generator according to the invention comprising an exemplary embodiment of a control unit according to the invention.
• Fig. 2 illustrates a functional diagram of another exemplary embodiment of an RF power generator according to the invention comprising another exemplary embodiment of a control unit according to the invention.
• Fig. 3 illustrates a functional diagram of yet another exemplary embodiment of an RF power generator according to the invention comprising a more detailed functional diagram of the control unit in Fig. 2.
• Fig. 4 shows a functional diagram of an exemplary embodiment of an arrangement of two RF power generators according to the invention.
• Fig. 5 depicts a functional diagram of another exemplary embodiment of an arrangement of two RF power generators according to the invention.
• Fig. 6 shows a functional diagram of still another exemplary embodiment of an arrangement of two RF power generators according to the invention.
• Fig. 7 illustrates a functional diagram of an exemplary embodiment of an arrangement of three RF power generators according to the invention.
• Fig. 8 shows a functional diagram of another exemplary embodiment of an arrangement of three RF power generators according to the invention.
• Fig. 9 shows a flow chart of an exemplary embodiment of a method for generating RF output signals according to the invention.
• Fig. 1 illustrates a functional diagram of an exemplary embodiment of an RF power generator 1 according to the invention comprising an exemplary embodiment of a control unit 2 according to the invention.
• Fig. 2 illustrates a functional diagram of another exemplary embodiment of an RF power generator 20 according to the invention comprising another exemplary embodiment of a control unit 21 according to the invention.
• Figs. 1 and 3 in an alternating fashion, the latter showing i.a. a more detailed functional diagram of the control unit 21 in Fig. 2.
• references made to Fig. 3 relate only to common components shared by both the control unit 2 and the control unit 21.
• the control unit 2 in Fig. 1 and the control unit 21 in Figs. 2 and 3, respectively only differ in the way a reference signal is generated and input to the respective control units 2 and 21, respectively, as will become clearer along with the description of Fig. 2.
• a signal comparator 3 e.g. a phase discriminator (PD), phase-frequency discriminator (PFD), a frequency mixer, or a counter, configured to compare a reference signal 4 having a reference frequency f re f and a reference phase tc r with a feedback signal 5 having a feedback frequency fpLL and a feedback phase ⁇ I>PLL.
• the control unit 2 is configured to generate an error signal 6 representative of a difference between the reference signal 4 and the feedback signal 5.
• the signal comparator 3 compares at least one of a phase difference and a frequency difference of the reference signal 4 and the feedback signal 5 so that the error signal 6 is representative of at least one of said phase difference and frequency difference.
• control unit 2 as illustrated in Fig. 1 comprises a data processing unit 7, e.g. a digital data processing unit such as a microprocessor, microcontroller, digital signal processor and the like, receiving as an input signal the error signal 6 generated by the signal comparator 3, and outputting a plurality of waveform tuning signals FTWPLL, FTWi (cf. Fig. 3) as a function of the error signal 6.
• the error signal 6 input to the data processing unit 7 may comprise a digital representation 6’ of the error signal 6 as will be elucidated in more detail further below.
• waveform tuning signals FTWPLL, FTWi are formed by digital waveform tuning words, wherein the waveform tuning words each comprise at least one of a frequency information, a phase information, and an amplitude information.
• the control unit 2 further comprises a plurality of waveform generators DDSPLL, DDSi (in the present case each one embodied as a direct digital synthesis cores) each receiving one of the plurality of waveform tuning signals FTWPLL, FTWi output by the data processing unit 7, wherein each waveform generator DDSPLL, DDSi generates a time-dependent amplitude signal APLLO, Ai(t) as a function of the received respective waveform tuning signal FTWPLL, FTWi.
• the time-dependent amplitude signals APLL(I), Ai(t) are formed as a digital bitstream representing digital amplitude values for each corresponding RF output signal RF ou t,i.
• One predetermined amplitude signal, i.e. amplitude signal APLL(I), of the generated plurality of amplitude signals APLL(I), Ai(t) represents the feedback signal 5 input to the signal comparator 3, and the other amplitude signals Ai(t) represent the respective RF output signals RF ou t,i to be generated.
• the data processing unit 7 is configured to adjust both the waveform tuning signal FTWPLL corresponding to the one predetermined amplitude signal APLL(I) representing the feedback signal 5 such as to minimize the error signal 6, and the other waveform tuning signals FTWi corresponding to the other amplitude signals Ai(t) representing the RF output signals RF O ut,i based on the adjusted waveform tuning signal FTWPLL of the predetermined amplitude signal APLLO representing the feedback signal 5.
• the control loop formed by the signal comparator 3 receiving the reference signal 4 and the feedback signal 5, and the data processing unit 7 can be considered a PLL control loop, without being limited thereto.
• Fig. 1 shows that the control unit 2 further comprises a reference signal source 8, i.e. a signal source internal to the control unit 2, configured to generate the reference signal 4.
• the internal reference signal source 8 may be a precision crystal oscillator or an oven-controlled crystal oscillator (OCXO), and the like.
• Fig. 1 illustrates that the control unit 2 comprises a series connection of a loop filter 9 and an analog-to-digital-converter ADC configured and arranged such as to generate a digital representation 6’ of the error signal 6 from the signal comparator 3, and to feed the digital representation of the error signal 6’ to the data processing unit 7.
• ADC analog-to-digital-converter
• Fig. 1 also shows that in the control unit 2 the data processing unit 7 and the plurality of waveform generators DDSPLL, DDSi are formed by a field programmable gate array FPGA, however, not being limited thereto.
• SoC System-on-Chip
• ASIC application-specific integrated circuit
• Fig. 1 also shows that in the control unit 2 the data processing unit 7 and the plurality of waveform generators DDSPLL, DDSi are formed by a field programmable gate array FPGA, however, not being limited thereto.
• SoC System-on-Chip
• ASIC application-specific integrated circuit
• the exemplary control unit 2 depicted in Fig. 1 also comprises at least one digital-to-analog-converter DAC, in the present case a multi-channel DAC, converting the digital amplitude values APLL(I), Ai(t) contained in the bitstreams generated by the waveform generators DDSPLL, DDSi into the feedback signal 5 and the RF output signals RF O ut,i, respectively.
• digital-to-analog-converter DAC in the present case a multi-channel DAC, converting the digital amplitude values APLL(I), Ai(t) contained in the bitstreams generated by the waveform generators DDSPLL, DDSi into the feedback signal 5 and the RF output signals RF O ut,i, respectively.
• a plurality of single-channel digital-DACs instead of one multi-channel DAC shown in Fig. 1, a plurality of single-channel digital-DACs, a plurality of dual-channel DACs, a plurality of x-channel DACs or any combination thereof may be used.
• the control unit 2 in Fig. 1 further comprises a plurality of signal reconstruction filters Fi filtering the respective RF output signals RF ou t,i after conversion by the digital-to-analog converter DAC.
• the feedback signal reconstruction filter FPLL filtering the feedback signal 5 after conversion by the digital-to-analog converter DAC may be provided or may be omitted.
• the exemplary control unit 2 also comprises a system clock CLK generating a system clock signal 10.
• the plurality of waveform generators DDSPLL, DDSi and the digital-to-analog converter DAC are driven by the system clock signal 10, wherein a more detailed description of the system clock signal 10 and its specific use by the waveform generators DDSPLL, DDSi and the DAC will be given along with the discussion of Fig. 3 further below.
• a memory device e.g. RAM, EPROM, Flash, ROM, and the like, storing a plurality of predeterminable waveform set values f sv ,i each corresponding to one respective of the waveform tuning signals FTWi of the RF output signals RF ou t,i to be generated, wherein the data processing unit 7 is further configured to output the plurality of waveform tuning signals FTWi as a function of the waveform set values f sv ,i.
• the waveform set values fsv.i may comprise a frequency information, a phase information, and/or an amplitude information with regard to the respective RF output signal RF ou t,i to be generated.
• control unit 2 presented in Fig. 1 also comprises a control device 12, e.g. a microprocessor, microcontroller, and the like, configured to modify the waveform set values f sv ,i stored in the memory device 11 according to a predefined schedule, e.g. a plasma processing method.
• a control device 12 e.g. a microprocessor, microcontroller, and the like, configured to modify the waveform set values f sv ,i stored in the memory device 11 according to a predefined schedule, e.g. a plasma processing method.
• the memory device 11 and the control device 12 are formed as one integrated electronic component/unit, however, without being limited thereto.
• the control unit 2 is part of the RF power generator 1 for generating the plurality of synchronized RF output signals RF ou t,i each having a respective output frequency fi, phase ⁇ I>i, and amplitude Ai.
• the RF power generator 1 comprises a DC power supply 13, and power amplifiers PAi each receiving power from the DC power supply 13.
• Each power amplifier PAi is configured to amplify the respective RF output signal RFoutj.
• the detailed and specific settings of the DC power supply 13 may vary depending on the required gain of the power amplifiers and may be controlled by the control device 12 as required by the waveform set values f sv ,i. For example, a lookup table and an algorithm to determine the best settings of the output power level of the DC power supply 13 may be used.
• control unit 21 of the RF power generator 20 illustrated in Fig. 2 essentially differs from the control unit 2 shown in Fig. 1 only in that the reference signal 4 is not generated by an internal reference signal source 8 (cf. Fig. 1) but input to the control unit 21 from an external reference signal source 14.
• This reference signal source 14 being external to the control unit 21 and the RF power generator 20 may be an atomic clock providing an atomic clock reference signal, a high-precision oscillator synchronized with an atomic clock providing a high- precision oscillator signal, a precision crystal oscillator, an oven-controlled crystal oscillator (OCXO), or another RF power generator (not shown in Fig. 2) generating a common exciter CEX signal which is input to a common exciter input CEXin.
• Fig. 3 illustrates a functional diagram of yet another exemplary embodiment of an RF power generator 30 according to the invention comprising a more detailed functional diagram of the control unit 21 in Fig. 2.
• the RF power generator 30 comprises a common exciter input CEXin connected to the control unit 21 for receiving an external common exciter signal CEX as the reference signal 4. Furthermore, the exemplary RF power generator 30 further comprises two common exciter outputs CEXouti,2 each providing a respective one of the plurality of RF output signals RF ou t,k-i, RF ou t,k as an external common exciter signal CEX. It is to be noted that in the case according to Fig. 3, the two RF output signals RF ou t,k-i, RF ou t,k output on the respective CEX output CEX ou ti,2 have not been power-amplified by one of the power amplifiers PAi. Instead, they are output after being filtered by the respective signal reconstruction filters Fk-i, Fk. However, a small preamplification of the CEX output signals on CEX ou ti,2 by an appropriate preamplifier (not shown) may be provided.
• the RF generator 30 also comprises a user interface device 31, e.g. a touch screen, for setting the output frequencies fi, phases ⁇ bi, and/or amplitudes Ai of the respective RF output signals RF ou t,i and for monitoring an operational state of the RF power generator 30.
• a user interface device 31 e.g. a touch screen
• the user interface device 31 is part of the RF power generator 30. However, alternatively, it may be a component of the control unit 21 too.
• Fig. 3 also illustrates that a waveform generator clock signal 32 (herein also referred to as an FPGA clock signal) for driving the waveform generators DDSPLL, DDSi and a DAC clock signal 33 for driving the digital-to-analog converter DAC are different predetermined rational fractions mi/ and n , respectively, of the system clock signal 10.
• a waveform generator clock signal 32 herein also referred to as an FPGA clock signal
• DDSi digital-to-analog converter DAC
• Fig. 4 shows a functional diagram of an exemplary embodiment of an arrangement 35 of two RF power generators, e.g. RF power generators 20 and 30, according to the invention.
• RF power generator 30 comprises a common exciter input CEXin and a common exciter output CEX ou t as well as two RF power output signals RF ou ti,2.
• RF power generator 20 comprises one common exciter input CEXin and one RF power output signal RF ou t3.
• such an arrangement may be used as a dual -frequency plasma power supply, e.g. 13.56 MHz and 60 MHz, or 13.56 MHz and 400 kHz as shown in Fig. 4. Due to the synchronization concept according to the invention described herein, the two power output signals RF ou ti and RF ou t2 of the power generator 30 in Fig. 4 are automatically frequency-locked.
• power generator 30 in Fig. 4 acts as a master generator providing appropriate CEX signals to synchronize all connected power generators, i.e. generator 20 in Fig. 4 for example.
• any existing conventional power generator which requires a dedicated CEX input signal can be synchronized with such a master power generator as the generator 30 in Fig. 4 for example.
• the synchronized power generators may even be phase-shifted with respect to the master generator, and even cable length- induced phase shifts ⁇ b c (as mentioned in the general description part of this specification) may already be compensated on the master generator side.
• the master generator 30 generates two frequencies (in this case 400 kHz and 13.56 MHz) as its own power output signals RF ou ti,2, and provides a third frequency CEX signal CEXout to generator 20 (also maybe a conventional generator which can only be synced with its specific operating frequency, in this case 40.68 MHz for example).
• Fig. 5 depicts a functional diagram of another exemplary embodiment of an arrangement 40 of two RF power generators according to the invention.
• two linked RF power generators e.g. generators 30 and 20 are synchronized to each other, wherein power generator 20 uses a CEX input signal CEXin already phase-shifted by A ⁇ I> in the master generator 30.
• Fig. 6 shows a functional diagram of still another exemplary embodiment of an arrangement 45 of two RF power generators, e.g. power generators 20 and 30, according to the invention.
• power generator 20 of the two linked RF power generators 20 and 30 is synchronized via a CEX ou t signal from generator 30 and additionally phase-shifted internally by A .
• Fig. 7 illustrates a functional diagram of an exemplary embodiment of an arrangement 50 of three RF power generators according to the invention.
• a so-called daisy chain of three phase-locked power generators e.g. the RF power generators 30, 30’, 30”, wherein 30’ and 30” denote hardware duplicates of the power generator 30, is formed, in which each generator adds an individual phase shift A i, Ad via its internal digital waveform generator(s). Cable length-induced phase shifts A ⁇ b c as shown in Fig. 4 are not explicitly indicated in Fig. 7, however, they may be compensated as described with Fig. 4 above.
• the three daisy chain-linked RF power generators 30, 30’, 30” generate the same output frequency. Only the CEX ou t signals for the next generator in the chain are phase-shifted individually by each generator.
• Fig. 8 shows a functional diagram of another exemplary embodiment of an arrangement 55 of several RF power generators 30, 302, ... 30 n according to the invention, wherein the generators 302 ... 30 n are hardware duplicates of the power generator 30.
• phase-locked generators 302 . . . 30 n of the same frequency with different phase-shifts A i, e.g. in a star-like configuration, with one central master generator 30 is shown. All generators are synchronized via CEX signals from the master generator 30.
• the required phaseshifts A ⁇ b, can either be implemented in the CEX signals on the master generator end or be added by the respective digital waveform generators in the slave generators 302 ... 3 On.
• the generators 302 ... 30 n share the same CEX ou t signal from generator 30 without phase-shift A towards the reference frequency at CEXini of the master generator 30, and add individual phase-shifts A ⁇ b, internally.
• phaseshifts caused by cables may be compensated by using the invention, i. e. by adding a compensating phaseshift in the master or slave generator.
• Fig. 9 shows a flow chart of an exemplary embodiment of a method for generating synchronized RF output signals RF ou t,i each having a respective output frequency fi, phase ⁇ bi, and amplitude Ai, according to the invention.
• one of the RF output signals is selected as a control loop feedback signal, e.g. feedback signal 5.
• the feedback signal is set to the same frequency as an external or internal precision reference frequency and an appropriate amplitude and phase offset for use as the feedback signal (PLL control signal).
• step SI 10 a starting or set value for the frequency tuning word FTWPLL of the feedback signal is set, e.g. selected from a lookup table.
• step SI 20 all other RF output signals are defined by frequency, amplitude, and phase offset. If RF output signals are supposed to vary over time, a suitable time interval for changing RF output signal parameters is determined.
• step S140 the time-dependent amplitude value sequences Ai(t) for each frequency tuning word FTWi is generated via the respective DDSi cores.
• step SI 50 the amplitude sequences APLL(I), Ai(t) for each frequency are converted into analog signals by the multi-channel DAC.
• Step 160 the output signals are filtered by respective signal reconstruction filters Fi (optionally also FPLL) to produce sinusoidal output waveforms with frequencies fpLL and fi.
• Fi signal reconstruction filters
• Step 170 the feedback signal fpLL is compared to the reference signal f re f and the error signal 6 is produced.
• step 180 a digitized representation 6’ of the error signal 6 is used to calculate an optimized frequency tuning word FTWPLL.
• step 190 it is checked if the predetermined time interval TI has expired. If it is not expired, the method returns to step S130 (inner loop).
• step S120 outer loop
• DDSPLL direct digital synthesis core for feedback signal f frequency fpLL frequency of feedback signal fref frequency of reference signal f sv frequency set value

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