WO2022023866A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2022023866A1
WO2022023866A1 PCT/IB2021/056483 IB2021056483W WO2022023866A1 WO 2022023866 A1 WO2022023866 A1 WO 2022023866A1 IB 2021056483 W IB2021056483 W IB 2021056483W WO 2022023866 A1 WO2022023866 A1 WO 2022023866A1
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Prior art keywords
transistor
wiring
potential
current
insulator
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PCT/IB2021/056483
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English (en)
French (fr)
Japanese (ja)
Inventor
郷戸宏充
津田一樹
黒川義元
大下智
金村卓郎
力丸英史
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to CN202180059759.5A priority Critical patent/CN116157911A/zh
Priority to US18/016,745 priority patent/US20230284429A1/en
Priority to KR1020237004663A priority patent/KR20230043882A/ko
Priority to JP2022539784A priority patent/JP7724221B2/ja
Publication of WO2022023866A1 publication Critical patent/WO2022023866A1/ja
Anticipated expiration legal-status Critical
Priority to JP2025129917A priority patent/JP2025159013A/ja
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Definitions

  • one aspect of the present invention is not limited to the above technical fields.
  • the technical fields of one aspect of the present invention disclosed in the present specification and the like include semiconductor devices, image pickup devices, display devices, light emitting devices, power storage devices, storage devices, display systems, electronic devices, lighting devices, input devices, and input / output devices.
  • Devices, their driving methods, or their manufacturing methods can be mentioned as an example.
  • the mechanism of the brain is incorporated as an electronic circuit, and it has a circuit corresponding to "neurons” and "synapses" of the human brain. Therefore, such integrated circuits may also be referred to as “neuromorphic,” “brainmorphic,” or “brain-inspired.”
  • the integrated circuit has a non-Von Neumann architecture, and is expected to be able to perform parallel processing with extremely low power consumption as compared with the Von Neumann architecture in which the power consumption increases as the processing speed increases.
  • a model of information processing that imitates a neural network having "neurons” and “synapses” is called an artificial neural network (ANN).
  • ANN artificial neural network
  • the operation of the weighted sum of the neuron outputs, that is, the product-sum operation is the main operation.
  • Non-Patent Document 1 proposes a product-sum calculation circuit using a non-volatile memory element.
  • the product-sum calculation circuit in each memory element, the operation in the sub-threshold region of the transistor having silicon in the channel formation region is used, and the data corresponding to the multiplier and the input data corresponding to the multiplicand stored in each memory element are used. Outputs the current corresponding to the multiplication with. Further, in the product-sum calculation circuit, data corresponding to the product-sum calculation is acquired by the sum of the currents output by the memory elements in each column. Since the product-sum calculation circuit has a memory element inside, it is not necessary to read and write data from an external memory in multiplication and addition. Therefore, it is expected that the number of times of data transfer due to reading and writing can be reduced, and the power consumption can be reduced.
  • the above-mentioned product-sum calculation circuit performs a calculation using data stored in an external memory
  • a data signal or potential is given to each wiring when writing and reading the data.
  • the voltage applied to the drain terminal fluctuates between when the data is written and when the data is read. Fluctuations in the voltage of the drain terminal cause fluctuations in transistor characteristics, for example, the threshold voltage, which may reduce the accuracy of the data to be read.
  • One aspect of the present invention is to provide a semiconductor device with improved accuracy of read data.
  • One aspect of the present invention is to provide a semiconductor device having excellent arithmetic processing capacity per unit electric power.
  • One aspect of the present invention is to provide a semiconductor device having a novel configuration and capable of multiply-accumulate operation.
  • one aspect of the present invention does not necessarily have to solve all of the above problems, as long as it can solve at least one problem. Moreover, the description of the above-mentioned problem does not prevent the existence of other problems. Issues other than these are self-evident from the description of the description, claims, drawings, etc., and the issues other than these should be extracted from the description of the specification, claims, drawings, etc. Is possible.
  • One aspect of the present invention includes a first transistor, a second transistor, a third transistor, and a capacitance, and the first transistor is a third transistor via the first transistor when it is in the off state. It has the function of holding the first potential according to the first data given to the gate, and the capacitance is held at the gate of the third transistor according to the change of the potential according to the second data given to one electrode.
  • the second transistor has a function of changing the generated first potential to the second potential, and the second transistor has a function of changing the potential of either the source or the drain of the third transistor to a potential corresponding to the potential of the gate of the second transistor.
  • the third transistor has a function of flowing an output current according to the potential of the gate of the third transistor to the other of the source and the drain, and the output current flows when the third transistor operates in the sub-threshold region. It is a semiconductor device that is a current.
  • One aspect of the present invention includes a first transistor, a second transistor, a third transistor, and a capacitance, and the first transistor is a third transistor via the first transistor when it is in the off state. It has the function of holding the first potential according to the first data given to the gate, and the capacitance is held at the gate of the third transistor according to the change of the potential according to the second data given to one electrode.
  • the second transistor has a function of changing the generated first potential to the second potential, and the second transistor has a function of changing the potential of either the source or the drain of the third transistor to a potential corresponding to the potential of the gate of the second transistor.
  • the third transistor has a function of flowing an output current according to the potential of the gate of the third transistor to the other of the source and the drain, and the output current flows when the third transistor operates in the sub-threshold region. It is a current, and the second transistor and the third transistor each have a back gate, and the potential given to the back gate is the other potential of the source or drain of the third transistor, which is a semiconductor device.
  • One aspect of the present invention includes a first transistor, a second transistor, a third transistor, and a capacitance, and the first transistor is a third transistor via the first transistor when it is in the off state. It has the function of holding the first potential according to the first data given to the gate, and the capacitance is held at the gate of the third transistor according to the change of the potential according to the second data given to one electrode.
  • the second transistor has a function of changing the generated first potential to the second potential, and the second transistor has a function of changing the potential of either the source or the drain of the third transistor to a potential corresponding to the potential of the gate of the second transistor.
  • the third transistor has a function of flowing an output current according to the potential of the gate of the third transistor to the other of the source and the drain, and the output current flows when the third transistor operates in the sub-threshold region. It is a current, and the second transistor and the third transistor each have a back gate, and the potential given to the back gate is lower than the other potential of the source or drain of the third transistor, which is a semiconductor device.
  • the first transistor is preferably a semiconductor device having a semiconductor layer having a metal oxide in a channel forming region.
  • a semiconductor device containing In, Ga, and Zn as the metal oxide is preferable.
  • the second transistor and the third transistor are preferably semiconductor devices having a semiconductor layer having silicon in the channel forming region, respectively.
  • One aspect of the present invention is an electronic device having the semiconductor device of the above-mentioned aspect of the present invention and a housing, and performing a neural network calculation by the semiconductor device.
  • One aspect of the present invention can provide a semiconductor device with improved accuracy of read data.
  • One aspect of the present invention can provide a semiconductor device having excellent arithmetic processing capacity per unit electric power.
  • One aspect of the present invention can provide a semiconductor device having a novel configuration and capable of multiply-accumulate operation.
  • FIG. 1 is a diagram illustrating a configuration example of a semiconductor device.
  • 2A and 2B are diagrams illustrating a configuration example of a semiconductor device.
  • 3A and 3B are diagrams illustrating a configuration example of a semiconductor device.
  • 4A, 4B, 4C and 4D are diagrams illustrating a configuration example of a semiconductor device.
  • FIG. 5 is a diagram illustrating a configuration example of a semiconductor device.
  • 6A and 6B are diagrams illustrating a configuration example of a semiconductor device.
  • FIG. 7 is a diagram illustrating a configuration example of an arithmetic circuit.
  • 8A, 8B and 8C are diagrams illustrating a configuration example of an arithmetic circuit.
  • 9A, 9B, 9C and 9D are diagrams illustrating a configuration example of an arithmetic circuit.
  • 10A, 10B, and 10C are diagrams illustrating a configuration example of an arithmetic circuit.
  • FIG. 11 is a timing chart illustrating a configuration example of the arithmetic circuit.
  • 12A and 12B are diagrams illustrating a neural network.
  • FIG. 13 is a diagram showing a configuration example of a transistor.
  • 14A and 14B are diagrams showing a configuration example of a transistor.
  • FIG. 15 is a diagram illustrating a configuration example of an integrated circuit.
  • 16A and 16B are diagrams illustrating application examples of integrated circuits.
  • 17A and 17B are diagrams illustrating application examples of integrated circuits.
  • 18A, 18B and 18C are diagrams illustrating application examples of integrated circuits.
  • FIG. 19 is a diagram illustrating an application example of an integrated circuit.
  • 20A, 20B, and 20C are diagrams illustrating a configuration example of a semiconductor device.
  • 21A, 21B, and 21C are diagrams illustrating simulation results of a semiconductor device.
  • 22A, 22B, and 22C are diagrams illustrating the simulation results of the semiconductor device.
  • FIG. 23 is a diagram illustrating an arithmetic unit.
  • 24A and 24B are diagrams illustrating an arithmetic unit.
  • FIG. 25 is a diagram illustrating an arithmetic unit.
  • 26A and 26B are diagrams illustrating an arithmetic unit.
  • 27A and 27B are diagrams illustrating an arithmetic unit.
  • FIG. 28 is a diagram illustrating an arithmetic unit.
  • FIG. 29 is a diagram illustrating an arithmetic unit.
  • the ordinal numbers "1st”, “2nd”, and “3rd” are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. Further, for example, the component referred to in “first” in one of the embodiments of the present specification and the like is regarded as another embodiment or the component referred to in “second” in the scope of claims. It is possible. Further, for example, the component referred to in “first” in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the scope of claims.
  • the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (eg, signals, voltages, circuits, elements, electrodes, wiring, etc.).
  • a code for identification such as "_1", “_2”, “_n”, “_m, n” is added to the code. May be described.
  • the second wiring GL is described as wiring GL_2.
  • the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
  • a semiconductor circuit, an arithmetic unit, and a storage device, including a semiconductor element such as a transistor, are one aspect of a semiconductor device. It may be said that a display device (liquid crystal display device, light emission display device, etc.), projection device, lighting device, electro-optic device, power storage device, storage device, semiconductor circuit, image pickup device, electronic device, and the like have a semiconductor device.
  • FIG. 1 is a diagram for explaining a semiconductor device 10 which is one aspect of the present invention.
  • the semiconductor device 10 has a reference cell 21 and a calculation cell 31.
  • the reference cell 21 has a transistor 22, a transistor 23, a transistor 24, and a capacitance 25.
  • the arithmetic cell 31 has a transistor 32, a transistor 33, a transistor 34, and a capacitance 35. As shown in FIG. 1, the transistor and capacitance included in the reference cell 21 and the arithmetic cell 31 are connected to at least one of the wiring WSL, the wiring XCL, the wiring VBL, the wiring WCL, and the wiring giving the ground potential.
  • the reference cell 21 has a function of executing a calculation operation in the calculation cell 31 by flowing a set current at the time of writing data and at the time of reading data. Specifically, the reference cell 21 holds a reference voltage in the reference cell 21 by flowing a reference current when writing data, and then inputs data (X) to be given to the calculation cell 31 when reading the data. It has a function of flowing the current corresponding to the reference cell 21 to the reference cell 21 and controlling the current flowing to the calculation cell 31.
  • the reference cell 21 may be simply referred to as a cell.
  • the gate of the transistor 22 is connected to the wiring WSL.
  • One of the source or drain of the transistor 22 is connected to one of the source or drain of the transistor 23 and the wiring XCL.
  • the other of the source or drain of the transistor 22 is connected to one electrode of the gate and capacitance 25 of the transistor 24.
  • the transistor 22 can hold the reference voltage in the reference cell 21 by writing the reference voltage to the holding node (gate of the transistor 24) in the reference cell 21 as an on state at the time of data writing and turning it off.
  • the gate of the transistor 23 is connected to the wiring VBL.
  • the back gate of the transistor 23 is connected to the other of the source or drain of the transistor 24.
  • One of the source or drain of the transistor 23 is connected to one of the source or drain of the transistor 22 and the wiring XCL.
  • the other of the source or drain of the transistor 23 is connected to one of the source or drain of the transistor 24.
  • the transistor 23 makes the potential of either the source or the drain of the transistor 24 a potential corresponding to the potential of the gate of the transistor 23.
  • the gate of the transistor 24 is connected to the other electrode of the source or drain of the transistor 22 and one electrode of the capacitance 25.
  • a node to which the gate of the transistor 24, the other of the source or drain of the transistor 22 and one of the electrodes of the capacitance 25 are connected is also referred to as a holding node.
  • the holding node can be set to a potential corresponding to the current flowing through the transistor 24.
  • the back gate of the transistor 24 is connected to the other of the source or drain of the transistor 24.
  • the other of the source or drain of the transistor 24 is connected to a wire that provides a low power potential (eg, ground potential).
  • the wiring that gives the ground potential functions as a wiring for passing a current between the source and the drain of the transistor 24.
  • the other of the source or drain of the transistor 24 is connected to the back gate of the transistor 23 and the back gate of the transistor 24. Since a fixed potential is applied to the back gate of the transistor 23 and the back gate of the transistor 24, the transistor characteristics of the transistor 23 and the transistor 24 are stabilized. The transistor 24 causes an output current corresponding to the potential of the gate of the transistor 24 to flow to the other of the source and the drain.
  • One electrode of the capacitance 25 is connected to the other of the source or drain of the transistor 22 and the gate of the transistor 24.
  • the other electrode of capacitance 25 is connected to the wiring XCL.
  • the capacitance 25 changes the potential of one electrode in response to a change in the potential of the other electrode when one electrode is in an electrically floating state.
  • the calculation cell 31 has a function of internally holding a voltage corresponding to the current by passing a current corresponding to the weight data (W) held in the calculation cell 31 at the time of writing data. Further, the calculation cell 31 has a function of flowing a current corresponding to the calculation of the weight data and the input data by boosting the voltage held at the time of writing the data according to the current flowing through the reference cell 21 at the time of reading the data.
  • the weight data may be referred to as first data
  • the input data may be referred to as second data.
  • the arithmetic cell 31 may be simply referred to as a cell.
  • the weight data is, for example, data (weight data) corresponding to the weight parameter used in the product-sum operation of the artificial neural network.
  • the gate of the transistor 32 is connected to the wiring WSL.
  • One of the source or drain of the transistor 32 is connected to one of the source or drain of the transistor 33 and the wiring WCL.
  • the other of the source or drain of the transistor 32 is connected to one electrode of the gate and capacitance 35 of the transistor 34.
  • the transistor 32 can hold the voltage corresponding to the weight data in the calculation cell 31 by writing the voltage corresponding to the weight data in the calculation cell 31 as an on state at the time of data writing and turning it off.
  • the gate of the transistor 33 is connected to the wiring VBL.
  • the back gate of the transistor 33 is connected to the other of the source or drain of the transistor 34.
  • One of the source or drain of the transistor 33 is connected to one of the source or drain of the transistor 32 and the wiring WCL.
  • the other of the source or drain of the transistor 33 is connected to one of the source or drain of the transistor 34.
  • the transistor 33 makes the potential of either the source or the drain of the transistor 34 a potential corresponding to the potential of the gate of the transistor 33.
  • the gate of the transistor 34 is connected to the other electrode of the source or drain of the transistor 32 and one electrode of the capacitance 35.
  • a node to which the gate of the transistor 34, the other of the source or drain of the transistor 32, and one of the electrodes of the capacitance 35 are connected is also referred to as a holding node.
  • the back gate of the transistor 34 is connected to the other of the source or drain of the transistor 34.
  • the other of the source or drain of the transistor 34 is connected to a wire that provides a low power potential (eg, ground potential).
  • the wiring that gives the ground potential functions as a wiring for passing a current between the source and the drain of the transistor 34.
  • the other of the source or drain of the transistor 34 is connected to the back gate of the transistor 33 and the back gate of the transistor 34.
  • the transistor 34 Since a fixed potential is applied to the back gate of the transistor 33 and the back gate of the transistor 34, the transistor characteristics of the transistor 33 and the transistor 34 are stabilized.
  • the transistor 34 causes an output current corresponding to the potential of the gate of the transistor 34 to flow to the other of the source and the drain.
  • One electrode of the capacitance 35 is connected to the other of the source or drain of the transistor 32 and the gate of the transistor 34.
  • the other electrode of capacitance 35 is connected to the wiring XCL.
  • the capacitance 35 changes the potential of one electrode in response to a change in the potential of the other electrode when one electrode is in an electrically floating state.
  • the transistor 24 and the transistor 34 operate in the subthreshold region unless otherwise specified.
  • the drain current Id of the transistor operating in the subthreshold region can be expressed by the equation (1).
  • q is the elementary charge
  • V g is the gate voltage
  • V th is the threshold voltage
  • ⁇ is a coefficient determined by the device structure and the like.
  • k B is the Boltzmann constant
  • T is the temperature.
  • the drain current Id of the transistor operating in the subthreshold region does not depend on the drain voltage.
  • the current flowing through the transistor 24 and the transistor 34 is the amount of current flowing when operating in the subthreshold region.
  • the current in the subthreshold region of the transistor 24 and the transistor 34 can reduce the influence of the variation of the drain voltage. Therefore, the accuracy of the data obtained by the calculation can be improved.
  • the subthreshold region refers to a region in which the gate voltage is lower than the threshold voltage in the graph showing the gate voltage (Vg) -drain current (Id) characteristics of the transistor.
  • the subthreshold region refers to a region in which a current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that considers only drift current).
  • the subthreshold region is a region in which the drain current increases exponentially with an increase in the gate voltage.
  • the subthreshold region shall include a region that can be regarded as the region described above.
  • the drain current when the transistor operates in the subthreshold region is called the subthreshold current.
  • the subthreshold current increases exponentially with respect to the gate voltage, regardless of the drain voltage. In the circuit operation using the subthreshold current, the influence of the variation of the drain voltage can be reduced.
  • the transistor 32 and the transistor 22 have a function of holding the potentials of the gate of the transistor 24 and the gate of the transistor 34 by turning them off. Specifically, it has a function of holding a potential according to the data given to the gate of the transistor 34 via the transistor 32.
  • the transistor 32 and the transistor 22 are preferably OS transistors as an example.
  • the channel forming region of the transistor 32 and the transistor 22 is more preferably an oxide containing at least one of indium, gallium, and zinc.
  • indium and element M includes, for example, aluminum, gallium, yttrium, copper, vanadium, berylium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, lanthanum, etc.
  • element M includes, for example, aluminum, gallium, yttrium, copper, vanadium, berylium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, lanthanum, etc.
  • cerium, neodymium, hafnium, tantalum, tungsten, gallium and the like can be mentioned), and oxides containing at least one of zinc may be used.
  • the OS transistor has an extremely small leakage current, that is, the current flowing between the source and drain in the off state.
  • an OS transistor as the transistor 32 and / or the transistor 22
  • the leakage current of the transistor 32 and / or the transistor 22 can be suppressed, so that the power consumption of the semiconductor device 10 can be reduced.
  • the fluctuation of the potential held in each of the gate of the transistor 24 and the gate of the transistor 34 can be made very small, the refreshing operation of the potential can be reduced. Further, by reducing the refresh operation, the power consumption of the semiconductor device 10 can be reduced. Further, by making the leakage current from the holding node to the wiring WCL or the wiring XCL very small, the cell can hold the potential of the holding node for a long time.
  • the drain current per 1 ⁇ m of channel width such as less than 1 ⁇ 10 -20 A, less than 1 ⁇ 10 -22 A, or less than 1 ⁇ 10 -24 A. It is possible to pass an extremely small current.
  • the OS transistor has a channel width of 1.0 ⁇ 10 -8 A or less, 1.0 ⁇ 10 -12 A or less, or 1.0 ⁇ 10 -15 A or less when the gate voltage is the threshold voltage of the transistor. A drain current per 1 ⁇ m can be passed. Therefore, the OS transistor can pass subthreshold currents of different sizes in the range of the gate voltage operating in the subthreshold region.
  • the OS transistor can take a large range of the gate voltage operating in the subthreshold region. Specifically, when the threshold voltage of the OS transistor is Vth , in the subthreshold region, ( Vth -1.0V) or more and Vth or less, or ( Vth -0.5V) or more and Vth or less. It is possible to perform circuit operation using the gate voltage in the voltage range of.
  • the off-current is large and the range of gate voltage operating in the subthreshold region is narrow.
  • the OS transistor can operate in a wider gate voltage range than the Si transistor.
  • the OS transistor Since the bandgap of the metal oxide that functions as an oxide semiconductor is 2.5 eV or more, the OS transistor has a minimum off current. As an example, when the voltage between the source and drain is 3.5 V and the room temperature (25 ° C) is normal, the off current per 1 ⁇ m of channel width is less than 1 ⁇ 10 -20 A, 1 ⁇ 10 -22 A, or 1 ⁇ 10. It can be less than -24A . Therefore, the OS memory has an extremely small amount of charge leaked from the holding node via the OS transistor.
  • the metal oxides applied to the OS transistor are Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (M is: Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf) and the like.
  • M is: Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf
  • oxides containing indium and zinc include aluminum, gallium, ittrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. , Magnesium, etc. may be included, or a plurality of species may be contained.
  • the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystal portion such as CAAC-OS, CAC-OS, and nc-OS.
  • CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor ductor.
  • CAC-OS is an abbreviation for Cloud-Aligned Composite oxide semiconductor ductor.
  • nc-OS is an abbreviation for nanocrystalline oxide semiconductor ductor.
  • CAAC-OS has a c-axis orientation and has a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have strain.
  • the strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.
  • the CAC-OS has a function of flowing electrons (or holes) as carriers and a function of not flowing electrons as carriers. By separating the function of flowing electrons and the function of not flowing electrons, both functions can be maximized. That is, by using CAC-OS in the channel formation region of the OS transistor, both a high on current and an extremely low off current can be realized.
  • the OS transistor is a storage type transistor that has a large number of electrons as carriers. Therefore, the influence of DIBL (Drain-Induced Barrier Lowering), which is one of the short-channel effects, is smaller than that of an inverting transistor having a pn junction. That is, the OS transistor has a higher resistance to the short channel effect than the Si transistor.
  • DIBL Drain-Induced Barrier Lowering
  • the current consumption can be reduced because the OS transistor can be operated in a wide current range in the subthreshold region.
  • the transistors 33 and 34 and the transistors 23 and 24 can be manufactured at the same time as the transistor 22 and the transistor 32 by using the OS transistor, the manufacturing process of the arithmetic circuit may be shortened. be.
  • the transistors 33, 34 and the transistors 23, 24 can be transistors (hereinafter, referred to as Si transistors) containing silicon in the channel forming region, other than the OS transistor.
  • Si transistors transistors
  • the silicon for example, amorphous silicon (sometimes referred to as hydrided amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon and the like can be used.
  • the transistors 33, 34 and the transistors 23, 24 are Si transistors
  • a configuration that functions as a back gate of the transistor for example, a configuration in which an electrode or a body electrode is provided, and a potential given to the back gate is the source of the transistors 34, 24.
  • the transistor 22 and the transistor 32 shown in FIG. 1 have a back gate, but the semiconductor device according to one aspect of the present invention is not limited thereto.
  • the transistor 22 and the transistor 32 shown in FIG. 1 may have a configuration that does not have a back gate, that is, a transistor having a single gate structure.
  • the potential or signal given to the back gate can be a fixed potential such as a ground potential or a signal given to the gate.
  • the transistors 32 to 34 and the transistors 22 to 24 shown in FIG. 1 are n-channel transistors, but the semiconductor device according to one aspect of the present invention is not limited thereto.
  • the transistors 32 to 34 and a part or all of the transistors 22 to 24 may be replaced with p-channel transistors.
  • the transistors 32 to 34 and a part or all of the transistors 22 to 24 may operate as desired, if necessary.
  • the voltage given by the wiring may be changed.
  • the above-mentioned examples of changes regarding the structure and polarity of the transistor are not limited to the transistors 32 to 34 and the transistors 22 to 24.
  • the structure, polarity, and the like of the transistor described in other parts of the specification or the transistor shown in other drawings may be changed in the same manner.
  • the wiring WSL is given a signal that controls the on or off of the transistor 22 and the transistor 32 that function as switches.
  • the wiring WSL functions as a write word line when writing data to the reference cell 21 and the calculation cell 31.
  • Data is written to the reference cell 21 and the calculation cell 31 by applying a current or a voltage corresponding to the data to be written to the wiring XCL or the wiring WCL.
  • the data is written by turning on the transistor 22 and the transistor 32.
  • the wiring WCL is set to H level (high level potential).
  • the wiring WCL is set to L level (low level potential).
  • the wiring WCL has a function of flowing a current amount (weight current or current I Wut ) according to weight data (also referred to as first data or first input data) to the calculation cell 31, or a potential held in the calculation cell. It has a function of giving a constant potential Vd for passing a current according to the above.
  • the wiring XCL has a current amount (reference current or current I Xut ) corresponding to the reference data or a current corresponding to the input data (also referred to as a second data or a second input data) with respect to the reference cell 21 and the calculation cell 31. It has a function to flow an amount (input current or current IX ).
  • Wiring VBL is wiring to which a constant potential Vb is given.
  • the constant potential Vb is a potential for fixing the potentials of the drain terminals of the transistor 24 and the transistor 34 in the reference cell 21 and the calculation cell 31.
  • the drain current Id is the drain voltage Vd because the threshold voltage is lowered due to the drain-induced barrier lowering (DIBL). Will depend on. Therefore, it is effective to apply a constant potential Vb to the gates of the transistor 23 and the transistor 33 to reduce the change in the drain voltage of the transistor 24 and the transistor 34. With this configuration, the accuracy of the data obtained by the calculation can be improved.
  • FIG. 2A shows an outline of an operation at the time of writing data
  • FIG. 2B shows an outline of an operation at the time of reading data.
  • a reference cell unit 20 having a plurality of reference cells 21_1 to 21_m (corresponding to the reference cell 21 in FIG. 1), and a plurality of calculation cells 31_1, 1 to 31_m, n (calculation cells 31 in FIG. 1).
  • the arithmetic cell unit 30 is provided.
  • a plurality of wiring XCLs are illustrated as wirings XCL_1 to XCL_m.
  • a plurality of wiring WCLs are illustrated as wirings WCL_1 to WCL_n. Both m and n are natural numbers.
  • the cells included in the reference cell unit 20 and the calculation cell unit 30 are arranged in a matrix of n + 1 in the row direction and m in the column direction.
  • the reference cell unit 20 and the calculation cell unit 30 may have two or more cells in the row direction and one or more cells in the column direction, as long as they are arranged in a matrix.
  • the terminal CP of the reference cell 21 in the reference cell unit 20 corresponds to the other electrode of the capacitance 25 in FIG.
  • the terminal TW of the reference cell 21 in the reference cell unit 20 corresponds to a terminal to which one of the source or drain of the transistor 22 of FIG. 1 and one of the source or drain of the transistor 23 are connected.
  • the terminal CP of the calculation cell 31 in the calculation cell unit 30 corresponds to the other electrode of the capacitance 35 in FIG.
  • the terminal TX of the arithmetic cell 31 in the arithmetic cell unit 30 corresponds to a terminal to which one of the source or drain of the transistor 32 of FIG. 1 and one of the source or drain of the transistor 33 are connected.
  • a current I Xut is passed through the reference cell 21 in each row.
  • the current given to each row is the normalized current I Xut , which is equal.
  • the current I Xut corresponds to the amount of current (reference current) according to the reference data. Since it is connected to the calculation cell 31 in each row via a capacitance, no current flows.
  • the reference cell 21 operates so as to maintain a voltage corresponding to the flowing current.
  • currents I W1 to I Wn are passed through the arithmetic cells in each column.
  • the currents I W1 to I Wn may be different for each column.
  • currents IX1 to IXm are passed through the reference cells 21 in each row.
  • the currents IX1 to IXm may be different for each row.
  • the current I Xut is preferably equal to the current I Wut .
  • the voltage held in the reference cell 21 is boosted by the currents IX1 to IXm . Since the wirings XCL_1 to XCL_m are also boosted in response to this boosting, the voltage held by the capacitive coupling of the capacitance 35 in the arithmetic cell 31 is boosted. Then, the potentials of the wirings WCL_1 to WCL_n are set to the voltage Vd. At this time, the amount of current Ir flowing through the transistor 34 corresponds to the product of the current value (I W ) held in the calculation cell 31 at the time of data writing and the current value ( IX ) passed through the reference cell 21 at the time of data reading. (Current Ir11 to Irmn ). By estimating the sum of the currents Ir11 to Irm flowing in each column, it is possible to output data corresponding to the calculation result of the sum of products of the input data and the weight data.
  • the sizes (for example, channel length, channel width, transistor configuration, etc.) of the transistors 32 to 34 included in each of the cells included in the arithmetic cell unit 30 are equal to each other.
  • the transistors 22 to 24 included in each of the cells included in the reference cell portion 20 have the same size.
  • the size of the transistor 22 and the size of the transistor 32 are equal to each other.
  • the size of the transistor 23 and the size of the transistor 33 are equal to each other.
  • the size of the transistor 24 and the size of the transistor 34 are equal to each other.
  • the size of the transistor 32 contained in each of the cells 31_1, 1 to 31_m, n is made equal, and the size of the transistor 33 included in each of the cells 31_1, 1 to 31_m, n is made equal.
  • the sizes of the transistors 34 contained in each of cells 31_1, 1 to 31_m, n is substantially the same under the same conditions. Can perform operations.
  • the same conditions here are, for example, the input potentials of the transistor 32 to the source, drain, gate, etc., the input potentials of the transistor 33 to the source, drain, gate, etc., and the source, drain, gate, etc. of the transistor 34. It refers to the input potential, the voltage held in each of the cells 31_1 and 1 to the cells 31_m and n, and the like. Further, the size of the transistor 22 included in each of the cells 21_1 to 21_m is made equal, the size of the transistor 23 included in each of the cells 21_1 to 21_m is made equal, and the size of the transistor 23 is made equal to each of the cells 21_1 to 21_m.
  • cells 21_1 to 21_m can have substantially the same operation and the result of the operation.
  • the same conditions are, for example, the input potentials of the transistor 22 to the source, drain, gate, etc., the input potentials of the transistor 23 to the source, drain, gate, etc., and the source, drain, gate, etc. of the transistor 24. It refers to the input potential, the voltage held in each of the cells 21_1 to 21_m, and the like.
  • the wiring WSL is set to H level, and the transistor 22 and the transistor 32 are set to the ON state (ON).
  • a current I Xut which corresponds to a reference current, is passed through the wiring XCL. Further, a current I W is passed through the wiring WCL.
  • the transistor 22 is turned on.
  • the potential of the holding node, which is the gate of the transistor 24, is V g1 , which is the potential at which the current I Xut flows through the transistor 24.
  • the transistor 24 can pass the current of the current I Xut between the source and the drain of the transistor 24.
  • such an operation may be referred to as “setting (programming) the current flowing between the source and drain of the transistor 24 of the reference cell 21 in IXut ".
  • the transistor 32 is turned on.
  • the potential of the holding node, which is the gate of the transistor 34, is V g2 , which is the potential at which the current I W flows through the transistor 34.
  • the current flowing between the source and drain of the transistor 34 of the arithmetic cell 31 is set to IW .
  • the current I Xut given to the reference cell 21 via the wiring XCL at the time of writing data can be expressed by the equation (2).
  • V g1 is the potential of the holding node which is the gate of the transistor 24.
  • V th1' is the threshold voltage of the transistor 24.
  • the current I W given to the calculation cell 31 via the wiring WCL at the time of writing data can be expressed by the equation (3).
  • V g2 is the potential of the holding node which is the gate of the transistor 34.
  • V th1 is the threshold voltage of the transistor 34.
  • the current I W can be represented by the product of the weight data w and the normalized current I Wut .
  • the voltage Vb applied to the wiring VBL is Vb>Vth2'andVb> Vth2, where Vth2 is the threshold voltage of the transistor 33 and Vth2'is the threshold voltage of the transistor 23.
  • the drain voltage of the transistor 24 can be set to (Vb-Vth2). Therefore, the drain voltage of the transistor 34 can be set to (Vb-Vth2'). That is, the drain voltage of the transistor 24 and the transistor 34 can be set to a potential that does not depend on the potential of the wiring WCL and the wiring XCL. Therefore, it is possible to suppress the decrease in the threshold voltage due to the DIBL of the transistor 34 and the transistor 24, and improve the accuracy of the data obtained by the calculation.
  • a period for holding the set current can be provided in the period between the time of writing the data and the time of reading the data.
  • the transistor 22 and the transistor 32 are turned off.
  • the transistor 22 and the transistor 32 can continue to hold the potential of the holding node corresponding to the set current by using the OS transistor.
  • the wiring WSL is set to the L level, and the transistor 22 is set to the OFF state (OFF).
  • a current IX corresponding to an input current is passed through the wiring XCL.
  • the potential of the holding node, which is the gate of the transistor 24, fluctuates as V g1 + ⁇ due to the current IX flowing through the transistor 24, and the potential of the wiring XCL also fluctuates.
  • the wiring WSL is set to the L level, and the transistor 32 is set to the OFF state (OFF). Therefore, the holding node of the arithmetic cell 31 is electrically in a floating state (floating).
  • the potential V g2 of the holding node of the calculation cell 31 fluctuates due to the capacitance coupling of the capacitance 35 due to the fluctuation of the potential of the wiring XCL due to the operation of the reference cell 21, and becomes V g1 + ⁇ .
  • a current Ir flows through the transistor 34 of the calculation cell 31.
  • V g1 + ⁇ is the potential change of the holding node of the reference cell 21 due to the current IX flowing through the reference cell 21.
  • ⁇ can be represented by the input data x shown in equation (5).
  • the current IX can be represented by the product of the input data x and the normalized current IXut .
  • the wiring WCL is set to a voltage V d so that a current flows through the calculation cell 31 in each row. Then, the current Ir flowing through the transistor 34 of the calculation cell 31 can be expressed by the equation (6) by changing the potential of the holding node of the calculation cell 31 to V g2 + ⁇ .
  • Ir in equations (3), (5) to (6) can be estimated as a current corresponding to the product of the weight data w and the input data x. Since the current flowing in the calculation cell 31 of each row can be added up, the current flowing in the wiring WCL is output to the outside according to the calculation result of the product-sum calculation process according to the weight data w and the input data x. It can output a signal.
  • the arithmetic cell 31A shown in FIGS. 4A and 4B is a circuit diagram shown as a comparative example in which the transistor 22 and the transistor 33 are not present in the semiconductor device 10 of FIG.
  • the threshold value of the transistor 34A included in the calculation cell 31A is set to 0.5V in order to explain a specific operation example.
  • the potential Vb is 0.7V.
  • the transistor 32A is turned off, and V d corresponding to the potential of the wiring WCL is set to 1.2 V. Since it is necessary to pass the current Ir through the arithmetic cells in each row, it is necessary to set V d higher during the data read operation.
  • the drain voltage of the transistor 34A becomes 0.4V and 1.2V in the data writing operation and the data reading operation, and the voltage difference becomes large. Therefore, the current Ir flowing through the calculation cell 31A also has a large variation.
  • FIGS. 4C and 4D show the case where the same operation as in FIGS. 4A and 4B is performed for comparison.
  • FIGS. 4C and 4D illustrate each configuration of the arithmetic cell 31.
  • the threshold voltages of the transistor 33 and the transistor 34 are both set to 0.5V.
  • the potential Vb is 0.7V.
  • the drain voltage of the transistor 34 is 0.2 V, which is a voltage obtained by lowering the voltage Vb by the threshold voltage of the transistor 33.
  • the transistor 32 is turned off and V d , which corresponds to the voltage of the wiring WCL, is set to 1.2 V. Since it is necessary to pass the current Ir through the arithmetic cells in each row, it is necessary to set V d higher during the data read operation.
  • the drain voltage of the transistor 34 is 0.2 V, which is a voltage obtained by lowering the voltage Vb by the threshold voltage of the transistor 33, as in FIG. 4C.
  • the drain voltage of the transistor 34A is 0.2V in both the data writing operation and the data reading operation, and the voltage difference becomes small. Therefore, the variation of the current Ir flowing through the calculation cell 31 can be reduced.
  • the semiconductor device 10B shown in FIG. 5 has a reference cell 21B and an arithmetic cell 31B.
  • the reference cell 21B has a transistor 22, a transistor 23B, a transistor 24B, and a capacitance 25.
  • the arithmetic cell 31B has a transistor 32, a transistor 33B, a transistor 34B, and a capacitance 35.
  • a voltage V body is applied to the back gates of the transistor 23B and the transistor 24B.
  • the voltage V body is a voltage smaller than the ground potential. The transistor characteristics of the transistor 23B and the transistor 24B are stabilized.
  • a voltage V body is applied to the transistor 33B and the back gate of the transistor 34B.
  • the transistor characteristics of the transistor 33B and the transistor 34B are stabilized.
  • the semiconductor device 10B of FIG. 5 will be described in the same manner as in FIGS. 4A, 4B and 4C, 4D with reference to FIGS. 6A and 6B.
  • FIGS. 6A and 6B illustrate each configuration of the arithmetic cell 31B.
  • the threshold voltages of the transistor 33B and the transistor 34B are both set to 0.8V.
  • the voltage Vb is 1.0V.
  • the threshold voltage of the transistor 33B and the transistor 34B is expressed as being positively shifted, for example, from 0.5V to 0.8V by a voltage V body of, for example, -1V.
  • the drain voltage of the transistor 34B is 0.2V, which is a voltage obtained by lowering the voltage Vb by the threshold voltage of the transistor 33B.
  • the transistor 32 is turned off and V d , which corresponds to the voltage of the wiring WCL, is set to 1.2 V. Since it is necessary to pass the current Ir through the arithmetic cells in each row, it is necessary to set V d higher during the data read operation.
  • the drain voltage of the transistor 34B is 0.2V, which is a voltage obtained by lowering the voltage Vb by the threshold voltage of the transistor 33B, as in FIG. 6A.
  • the drain voltage of the transistor 34B becomes 0.2V in both the data writing operation and the data reading operation, and the voltage difference becomes small. Therefore, it is possible to reduce the variation in the current Ir in the arithmetic cell to be read.
  • the change in the drain voltage of the transistor 33B can be reduced by the voltage V body .
  • the difference in the drain voltage of the transistor 33B between the data writing operation and the data reading operation is 0.5V (difference between 1.2V and 0.7V).
  • the difference in the drain voltage of the transistor 33B between the data writing operation and the data reading operation is 0.8V (difference between 1.2V and 0.4V). Is.
  • the semiconductor device 10B of FIG. 5 can suppress fluctuations in the characteristics of the transistor due to fluctuations in the drain voltage, and can reduce variations in the current Ir in the data read operation.
  • one aspect of the present invention can provide a semiconductor device with improved accuracy of read data.
  • the arithmetic unit has a circuit capable of multiply-accumulate operation.
  • the arithmetic unit may be referred to as an arithmetic circuit.
  • FIG. 7 shows a configuration example of an arithmetic unit that performs a product-sum operation of the first data and the second data.
  • the arithmetic unit MAC1 shown in FIG. 7 performs a product-sum calculation of the first data (weight data) corresponding to the potential held in each cell and the input second data (input data), and the product-sum operation. It is a circuit that calculates the activation function using the result of the calculation.
  • the first data and the second data can be, for example, analog data or multi-valued data (discrete data).
  • the arithmetic unit MAC1 has a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, a circuit SWS2, a cell array CA, and a conversion circuit ITRZ_1 to a conversion circuit ITRZ_n.
  • the cell array CA has cells 31_1 to 1 to cells 31_m, n and cells 21_1 to 21_m.
  • each of the cells 31_1, 1 to 31_m, n has a transistor 32, a transistor 33, a transistor 34, and a capacity 35, as in the arithmetic cell 31 described in the above embodiment.
  • each of the cells 21_1 to 21_m has a transistor 22, a transistor 23, a transistor 24, and a capacity 25, as in the reference cell 21 described in the above embodiment.
  • “one of the source or drain” described in the first embodiment may be described as a "first terminal”
  • the other of the source or drain may be described as a "second terminal”.
  • the capacity "one electrode” may be described as "first terminal”
  • the “other electrode” may be described as "second terminal”.
  • connection point between the first terminal of the transistor 32, the gate of the transistor 34, and the first terminal of the capacity 35 is a node NN_1.
  • similar connection points are designated as node NN_1n, node NN_m1 and node NN_mn.
  • similar connection points are designated as node NN_ref1 and node NNref_m. Note that the nodes NN_1 to node NN_mn and the nodes NNref_1 to node NNref_m function as holding nodes for their respective cells.
  • the circuit SWS1 has a transistor F3_1 to a transistor F3_n as an example.
  • the first terminal of the transistor F3_1 is electrically connected to the wiring WCL_1, the second terminal of the transistor F3_1 is electrically connected to the circuit WCS, and the gate of the transistor F3_1 is electrically connected to the wiring SWL1. ..
  • the first terminal of the transistor F3_n is electrically connected to the wiring WCL_n, the second terminal of the transistor F3_n is electrically connected to the circuit WCS, and the gate of the transistor F3_n is electrically connected to the wiring SWL1. ..
  • each of the transistors F3_1 to F3_n for example, a transistor applicable to the transistor of the cell array CA can be used.
  • the circuit SWS1 functions as a circuit for making a conduction state or a non-conduction state between the circuit WCS and each of the wiring WCL_1 to the wiring WCL_n.
  • the circuit SWS2 has a transistor F4_1 to a transistor F4_n as an example.
  • the first terminal of the transistor F4_1 is electrically connected to the wiring WCL_1, the second terminal of the transistor F4_1 is electrically connected to the input terminal of the conversion circuit ITRZ_1, and the gate of the transistor F4_1 is electrically connected to the wiring SWL2. It is connected.
  • the first terminal of the transistor F4_n is electrically connected to the wiring WCL_n, the second terminal of the transistor F4_n is electrically connected to the input terminal of the conversion circuit ITRZ_n, and the gate of the transistor F4_n is electrically connected to the wiring SWL2. It is connected.
  • each of the transistors F4_1 to the transistor F4_n for example, a transistor applicable to the transistor of the cell array CA can be used. In particular, it is preferable to use an OS transistor as each of the transistors F4_1 to F4_n.
  • the circuit SWS2 has a function of setting a conduction state or a non-conduction state between the wiring WCL_1 and the conversion circuit ITRZ_1 and between the wiring WCL_n and the conversion circuit ITRZ_n.
  • the circuit WCS has a function of supplying data to be stored in each cell of the cell array CA.
  • the circuit XCS is electrically connected to the wiring XCL_1 to the wiring XCL_m.
  • the circuit XCS has a function of passing a current of a current amount according to the reference data described later or a current of a current amount according to the second data to each of the cells 21_1 and the cells 21_m of the cell array CA.
  • the circuit WSD is electrically connected to the wiring WSL_1 to the wiring WSL_m.
  • the circuit WSD writes the first data to the cells 31_1 to 1 to the cells 31_m, n
  • the circuit WSD supplies a predetermined signal to the wiring WSL_1 to the wiring WSL_m to obtain a row of the cell array CA to which the first data is written.
  • the circuit WSD is electrically connected to the wiring SWL1 and the wiring SWL2 as an example.
  • the circuit WSD has a function of making a predetermined signal between the circuit WCS and the cell array CA in a conductive state or a non-conducting state by supplying a predetermined signal to the wiring SWL1, and a conversion circuit by supplying a predetermined signal to the wiring SWL2. It has a function of making the ITRZ_1 to the conversion circuit ITRZ_n a conductive state or a non-conducting state between the cell array CA.
  • Each of the conversion circuit ITRZ_1 to the conversion circuit ITRZ_n has an input terminal and an output terminal as an example.
  • the output terminal of the conversion circuit ITRZ_1 is electrically connected to the wiring OL_1
  • the output terminal of the conversion circuit ITRZ_n is electrically connected to the wiring OL_n.
  • Each of the conversion circuit ITRZ_1 to the conversion circuit ITRZ_n has a function of converting a voltage according to the amount of the current by inputting a current to the input terminal and outputting the voltage from the output terminal.
  • the voltage may be, for example, an analog voltage, a digital voltage, or the like.
  • each of the conversion circuit ITRZ_1 to the conversion circuit ITRZ_n may have a function-based arithmetic circuit. In this case, for example, the converted voltage may be used to perform a function calculation by the calculation circuit, and the result of the calculation may be output to the wiring OL_1 to the wiring OL_n.
  • a sigmoid function for example, a tanh function, a softmax function, a ReLU function, a threshold function, or the like can be used as the above-mentioned functions.
  • Circuit WCS Circuit XCS
  • circuit WCS Circuit XCS
  • FIG. 8A is a block diagram showing an example of the circuit WCS. Note that FIG. 8A also shows the circuit SWS1, the transistor F3, the wiring SWL1, and the wiring WCL in order to show the electrical connection with the circuits around the circuit WCS. Further, the transistor F3 is any one of the transistor F3_1 to the transistor F3_n included in the arithmetic unit MAC1 of FIG. 7, and the wiring WCL is the wiring WCL_1 to the wiring WCL_n included in the arithmetic unit MAC1 of FIG. Either one.
  • the circuit WCS shown in FIG. 8A has a switch SWW as an example.
  • the first terminal of the switch SWW is electrically connected to the second terminal of the transistor F3, and the second terminal of the switch SWW is electrically connected to the wiring VINIL1.
  • the wiring VINIL1 functions as a wiring that gives a potential for initialization to the wiring WCL, and the potential for initialization can be a ground potential (GND), a low level potential, a high level potential, or the like.
  • the switch SWW is turned on only when a potential for initialization is applied to the wiring WCL, and is turned off at other times.
  • the switch SWW for example, an analog switch or an electric switch such as a transistor can be applied.
  • a transistor for example, a transistor applicable to the transistor included in the cell array CA can be used as the transistor.
  • a mechanical switch may be applied.
  • the circuit WCS of FIG. 8A has a plurality of current source CSs as an example.
  • the circuit WCS has a function of outputting the first data of K bits (2 K value) (K is an integer of 1 or more) as a current, and in this case, the circuit WCS has 2K -1 pieces. It has a current source CS.
  • the circuit WCS has one current source CS that outputs information corresponding to the value of the first bit as a current, and has two current source CSs that output information corresponding to the value of the second bit as a current. It also has 2K-1 current sources CS that output information corresponding to the value of the K-bit as a current.
  • each current source CS has a terminal T1 and a terminal T2.
  • the terminal T1 of each current source CS is electrically connected to the second terminal of the transistor F3 included in the circuit SWS1.
  • the terminal T2 of one current source CS is electrically connected to the wiring DW_1
  • each of the terminals T2 of the two current source CSs is electrically connected to the wiring DW_1, and two K-1 current sources.
  • Each of the terminals T2 of the CS is electrically connected to the wiring DW_K.
  • the plurality of current sources CS included in the circuit WCS each have a function of outputting the same constant current I Wut from the terminal T1.
  • the constant current I Wut corresponds to the standardized current I Wut described in the first embodiment.
  • the error of the constant current I Wut output from each of the terminals T1 of the plurality of current sources CS is preferably 10% or less, more preferably 5% or less, and even more preferably 1% or less.
  • the wiring DW_1 to the wiring DW_K function as wiring for transmitting a control signal for outputting a constant current I Wut from the electrically connected current source CS.
  • the current source CS electrically connected to the wiring DW_1 causes I Wut to flow through the second terminal of the transistor F3 as a constant current.
  • the current source CS electrically connected to the wiring DW_1 does not output I Wut.
  • the current flowing by one current source CS electrically connected to the wiring DW_1 corresponds to the value of the first bit
  • the current flowing by the two current source CS electrically connected to the wiring DW_1 corresponds to the value of the first bit.
  • the current flowing through the K current sources CS electrically connected to the wiring DW_K, which corresponds to the value of the second bit, corresponds to the value of the K bit.
  • FIG. 8A illustrates the circuit WCS when K is an integer of 3 or more, but when K is 1, the circuit WCS of FIG. 8A is electrically connected to the wiring DW_2 to the wiring DW_K.
  • the configuration may be such that the current source CS is not provided.
  • the circuit WCS of FIG. 8A may be configured so as not to provide the current source CS electrically connected to the wiring DW_3 to the wiring DW_K.
  • the current source CS1 shown in FIG. 9A is a circuit applicable to the current source CS included in the circuit WCS of FIG. 8A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.
  • the first terminal of the transistor Tr1 is electrically connected to the wiring VDDL, and the second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. It is connected.
  • the second terminal of the transistor Tr2 is electrically connected to the terminal T1, and the gate of the transistor Tr2 is electrically connected to the terminal T2. Further, the terminal T2 is electrically connected to the wiring DW.
  • the wiring DW is any one of the wiring DW_1 to the wiring DW_n in FIG. 8A.
  • Wiring VDDL functions as wiring that gives a constant voltage.
  • the constant voltage can be, for example, a high level potential.
  • the constant voltage given by the wiring VDDL is set to a high level potential
  • a high level potential is input to the first terminal of the transistor Tr1.
  • the potential of the second terminal of the transistor Tr1 is set to a potential lower than the high level potential.
  • the first terminal of the transistor Tr1 functions as a drain
  • the second terminal of the transistor Tr1 functions as a source.
  • the gate-source voltage of the transistor Tr1 is 0V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) in the current range of the subthreshold region flows between the first terminal and the second terminal of the transistor Tr1.
  • the amount of the current is preferably 1.0 ⁇ 10 -8 A or less, and more preferably 1.0 ⁇ 10 -12 A or less. Further, it is more preferably 1.0 ⁇ 10 -15 A or less. Further, for example, it is more preferable that the current is within a range in which the current increases exponentially with respect to the gate-source voltage. That is, the transistor Tr1 functions as a current source for passing a current in the current range when operating in the subthreshold region.
  • the current corresponds to the above-mentioned I Wut or the later-mentioned I Xut .
  • the transistor Tr2 functions as a switching element.
  • the first terminal of the transistor Tr2 functions as a drain and the second terminal of the transistor Tr2 functions as a source.
  • the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, the voltage between the back gate and the source is 0V. Therefore, when the threshold voltage of the transistor Tr2 is within an appropriate range, the transistor Tr2 is turned on by inputting a high level potential to the gate of the transistor Tr2, and the gate of the transistor Tr2 is low. When the level potential is input, the transistor Tr2 is turned off.
  • the current in the current range of the subthreshold region described above flows from the second terminal of the transistor Tr1 to the terminal T1, and when the transistor Tr2 is in the off state, the current is the transistor Tr1. It is assumed that the current does not flow from the second terminal to the terminal T1.
  • the circuit applicable to the current source CS included in the circuit WCS of FIG. 8A is not limited to the current source CS1 of FIG. 9A.
  • the current source CS1 has a configuration in which the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, but the back gate of the transistor Tr2 is electrically connected to another wiring. It may be configured as such.
  • An example of such a configuration is shown in FIG. 9B.
  • the current source CS2 shown in FIG. 9B has a configuration in which the back gate of the transistor Tr2 is electrically connected to the wiring VTHL.
  • the threshold voltage of the transistor Tr2 can be changed. In particular, by increasing the threshold voltage of the transistor Tr2, the off-current of the transistor Tr2 can be reduced.
  • the current source CS1 has a configuration in which the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, but the back gate of the transistor Tr2 and the second terminal are connected to each other.
  • the voltage may be held by the capacity.
  • FIG. 9C An example of such a configuration is shown in FIG. 9C.
  • the current source CS3 shown in FIG. 9C has a transistor Tr3 and a capacitance C6 in addition to the transistor Tr1 and the transistor Tr2.
  • the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 are electrically connected via the capacitance C6, and the back gate of the transistor Tr1 and the first terminal of the transistor Tr3 are electrically connected.
  • the current source CS3 has a configuration in which the second terminal of the transistor Tr3 is electrically connected to the wiring VTL, and the gate of the transistor Tr3 is electrically connected to the wiring VWL.
  • the current source CS3 can make the wiring VTL and the back gate of the transistor Tr1 conductive by applying a high level potential to the wiring VWL to turn on the transistor Tr3.
  • a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1.
  • the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 can be maintained by the capacitance C6. That is, the threshold voltage of the transistor Tr1 can be changed by determining the voltage applied to the back gate of the transistor Tr1 by the wiring VTL, and the threshold voltage of the transistor Tr1 is fixed by the transistor Tr3 and the capacitance C6. can do.
  • the circuit applicable to the current source CS included in the circuit WCS of FIG. 8A may be the current source CS4 shown in FIG. 9D.
  • the current source CS4 has a configuration in which the back gate of the transistor Tr2 is electrically connected to the wiring VTHL instead of the second terminal of the transistor Tr2 in the current source CS3 of FIG. 9C. That is, the current source CS4 can change the threshold voltage of the transistor Tr2 according to the potential given by the wiring VTHL, similarly to the current source CS2 of FIG. 9B.
  • the current source CS4 when a large current flows between the first terminal and the second terminal of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to allow the current to flow from the terminal T1 to the outside of the current source CS4. ..
  • the current source CS4 applies a high level potential to the wiring VTHL, lowers the threshold voltage of the transistor Tr2, and raises the on-current of the transistor Tr2, so that the first terminal of the transistor Tr1 ⁇ 2nd. A large current flowing between the terminals can be passed from the terminal T1 to the outside of the current source CS4.
  • the circuit WCS outputs a current corresponding to the first data of the K bit. can do.
  • the amount of the current can be, for example, a current flowing between the first terminal and the second terminal within the range in which the transistor 34 operates in the subthreshold region.
  • the circuit WCS of FIG. 8B has a configuration in which one current source CS of FIG. 9A is connected to each of the wiring DW_1 to the wiring DW_K.
  • the channel width of the transistor Tr1_1 is w_1
  • the channel width of the transistor Tr1_2 is w_2
  • the channel width of the transistor Tr1_K is w_K
  • the circuit WCS shown in FIG. 8B corresponds to the first data of the K bit, similarly to the circuit WCS of FIG. 8A. It can output current.
  • the transistor Tr1 including the transistor Tr1_1 to the transistor Tr2_K
  • the transistor Tr2 including the transistor Tr2_1 to the transistor Tr2_K
  • the transistor Tr3 for example, a transistor applicable to the transistor of the cell array CA can be used.
  • an OS transistor it is preferable to use an OS transistor as the transistor Tr1 (including the transistor Tr1_1 to the transistor Tr2_K), the transistor Tr2 (including the transistor Tr2_1 to the transistor Tr2_K), and the transistor Tr3.
  • FIG. 8C is a block diagram showing an example of the circuit XCS. Note that FIG. 8C also shows the wiring XCL in order to show the electrical connection with the circuits around the circuit WCS. Further, the wiring XCL is any one of the wiring XCL_1 and the wiring XCL_m included in the arithmetic unit MAC1 of FIG. 7.
  • the circuit XCS shown in FIG. 8C has a switch SWX as an example.
  • the first terminal of the switch SWX is electrically connected to the wiring XCL and the plurality of current sources CS, and the second terminal of the switch SWX is electrically connected to the wiring VINIL 2.
  • the wiring VINIL 2 functions as a wiring that gives a potential for initialization to the wiring XCL, and the potential for initialization can be a ground potential (GND), a low level potential, a high level potential, or the like. Further, the potential for initialization given by the wiring VINIL2 may be equal to the potential given by the wiring VINIL1.
  • the switch SWX is turned on only when a potential for initialization is applied to the wiring XCL, and is turned off at other times.
  • the switch SWX can be, for example, a switch applicable to the switch SWW.
  • the circuit configuration of the circuit XCS of FIG. 8C can be substantially the same as that of the circuit WCS of FIG. 8A.
  • the circuit XCS has a function of outputting reference data as a current and a function of outputting second data of L bits (2 L value) (L is an integer of 1 or more) as a current.
  • the circuit XCS has 2 L -1 current source CS.
  • the circuit XCS has one current source CS that outputs information corresponding to the value of the first bit as a current, and has two current source CSs that output information corresponding to the value of the second bit as a current. It has 2 L-1 current sources CS that output information corresponding to the value of the L-th bit as a current.
  • the value of the first bit can be "1" and the value of the second and subsequent bits can be "0".
  • the terminal T2 of one current source CS is electrically connected to the wiring DX_1, and each of the terminals T2 of the two current source CSs is electrically connected to the wiring DX_1 .
  • Each of the terminals T2 of the current source CS is electrically connected to the wiring DX_L.
  • the plurality of current sources CS included in the circuit XCS each have a function of outputting IXut from the terminal T1 as the same constant current.
  • the wiring DX_1 to the wiring DX_L function as wiring for transmitting a control signal for outputting the IXut from the electrically connected current source CS. That is, the circuit XCS has a function of passing a current corresponding to the information of the L bits sent from the wiring DX_1 to the wiring DX_L to the wiring XCL.
  • the constant current I Xut output from each of the terminals T1 of the plurality of current source CSs is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, it is assumed that there is no error in the constant current I Xut output from the terminals T1 of the plurality of current sources CS included in the circuit XCS.
  • any one of the current source CS1 to the current source CS4 of FIGS. 9A to 9D can be applied as in the current source CS of the circuit WCS.
  • the wiring DW shown in FIGS. 9A to 9D may be replaced with the wiring DX.
  • the circuit XCS can pass a current in the current range of the subthreshold region to the wiring XCL as reference data or the second data of the L bit.
  • the same circuit configuration as the circuit WCS shown in FIG. 8B can be applied.
  • the circuit WCS shown in FIG. 8B is replaced with the circuit XCS
  • the wiring DW_1 is replaced with the wiring DX_1
  • the wiring DW_K is replaced with the wiring DX_L
  • the switch SWW is replaced with the switch SWX
  • the wiring VINIL1 is replaced. It may be considered by replacing it with the wiring VINIL2.
  • Conversion circuit ITRZ_1 to conversion circuit ITRZ_n >>
  • a specific example of a circuit applicable to the conversion circuit ITRZ_1 to the conversion circuit ITRZ_n included in the arithmetic unit MAC1 of FIG. 7 will be described.
  • the conversion circuit ITRZ1 shown in FIG. 10A is an example of a circuit applicable to the conversion circuit ITRZ_1 to the conversion circuit ITRZ_n of FIG. 7. Note that FIG. 10A also shows the circuit SWS2, the wiring WCL, the wiring SWL2, and the transistor F4 in order to show the electrical connection with the circuits around the conversion circuit ITRZ1. Further, the wiring WCL is any one of the wiring WCL_1 to the wiring WCL_n included in the arithmetic unit MAC1 of FIG. 7, and the transistor F4 is the transistor F4_1 to the transistor F4_n included in the arithmetic unit MAC1 of FIG. Either one.
  • the conversion circuit ITRZ1 of FIG. 10A is electrically connected to the wiring WCL via the transistor F4. Further, the conversion circuit ITRZ1 is electrically connected to the wiring OL.
  • the conversion circuit ITRZ1 has a function of converting the current flowing from the conversion circuit ITRZ1 to the wiring WCL or the current flowing from the wiring WCL to the conversion circuit ITRZ1 into an analog voltage and outputting the analog voltage to the wiring OL. That is, the conversion circuit ITRZ1 has a current-voltage conversion circuit.
  • the conversion circuit ITRZ1 of FIG. 10A has a resistor R5 and an operational amplifier OP1 as an example.
  • the inverting input terminal of the operational amplifier OP1 is electrically connected to the first terminal of the resistor R5 and the second terminal of the transistor F4.
  • the non-inverting input terminal of the operational amplifier OP1 is electrically connected to the wiring VRL.
  • the output terminal of the operational amplifier OP1 is electrically connected to the second terminal of the resistor R5 and the wiring OL.
  • Wiring VRL functions as wiring that gives a constant voltage.
  • the constant voltage may be, for example, a ground potential (GND), a low level potential, or the like.
  • the conversion circuit ITRZ1 has the configuration shown in FIG. 10A, so that the current flowing from the wiring WCL to the conversion circuit ITRZ1 via the transistor F4, or the current flowing from the conversion circuit ITRZ1 to the wiring WCL via the transistor F4. , It can be converted into an analog voltage and output to the wiring OL.
  • the inverting input terminal of the operational capacitor OP1 becomes virtual ground, so the analog voltage output to the wiring OL is based on the ground potential (GND). It can be a voltage.
  • the conversion circuit ITRZ1 of FIG. 10A is configured to output an analog voltage, but the circuit configuration applicable to the conversion circuit ITRZ_1 to the conversion circuit ITRZ_n of FIG. 7 is not limited to this.
  • the conversion circuit ITRZ1 may be configured to have an analog-digital conversion circuit ADC as shown in FIG. 10B.
  • the input terminal of the analog-digital conversion circuit ADC is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, and the analog-to-digital conversion circuit ADC has.
  • the output terminal is electrically connected to the wiring OL.
  • the conversion circuit ITRZ2 of FIG. 10B can output a digital signal to the wiring OL.
  • the conversion circuit ITRZ2 when the digital signal output to the wiring OL is 1 bit (binary value), the conversion circuit ITRZ2 may be replaced with the conversion circuit ITRZ3 shown in FIG. 10C.
  • the conversion circuit ITRZ3 of FIG. 10C has a configuration in which a comparator CMP1 is provided in the conversion circuit ITRZ1 of FIG. 10A. Specifically, in the conversion circuit ITRZ3, the first input terminal of the comparator CMP1 is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, and the second input terminal of the comparator CMP1 is wired VRL2. The output terminal of the comparator CMP1 is electrically connected to the wiring OL.
  • the wiring VRL2 functions as a wiring that gives a potential for comparison with the potential of the first terminal of the comparator CMP1.
  • the conversion circuit ITRZ3 of FIG. 10C has a magnitude of the voltage converted from the current flowing between the source and the drain of the transistor F4 by the current-voltage conversion circuit and the voltage given by the wiring VRL2.
  • a low level potential or a high level potential can be output to the wiring OL.
  • the conversion circuit ITRZ_1 to the conversion circuit ITRZ_n applicable to the arithmetic unit MAC1 of FIG. 7 is not limited to the conversion circuit ITRZ1 to the conversion circuit ITRZ3 shown in FIGS. 10A to 10C, respectively.
  • the conversion circuit ITRZ1 to the conversion circuit ITRZ3 have a functional arithmetic unit.
  • the arithmetic unit of the function system can be an arithmetic unit such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function.
  • FIG. 11 shows a timing chart of an operation example of the arithmetic unit MAC1.
  • the timing chart of FIG. 11 shows wiring SWL1, wiring SWL2, wiring WSL_i (i is an integer of 1 or more and m-1 or less), wiring WSL_i + 1, and wiring in the period from time T11 to time T23 and in the vicinity thereof. It shows the fluctuation of the potential of XCL_i, wiring XCL_i + 1, node NN_i, j (j is an integer of 1 or more and n-1 or less), node NN_i + 1, j, node NNref_i, and node NNref_i + 1. Further, in the timing chart of FIG.
  • the currents I 34_i, j flowing between the first terminal and the second terminal of the transistors 33, 34 included in the cells 31_i, j and the transistors included in the cell 21_i are shown.
  • the fluctuation of the current I 24_i + 1 flowing between the first terminal and the second terminal of the transistors 23 and 24 included in the cell 21_i + 1 are also shown.
  • the circuit WCS of FIG. 8A is applied as the circuit WCS of the arithmetic unit MAC1, and the circuit XCS of FIG. 8C is applied as the circuit XCS of the arithmetic unit MAC1.
  • the source potentials of the transistor 24 and the transistor 34 are set to the ground potential GND. Further, before the time T11, it is assumed that the potentials of the node NN_i, j, the node NN_i + 1, j, the node NNref_i, and the node NNref_i + 1 are set to the ground potential GND as the initial setting. Specifically, for example, the potential for initialization of the wiring VINIL1 in FIG. 8A is set to the ground potential GND, and the switch SWW, the transistor F3, and the respective transistors 32 included in the cell 31_i, j and the cell 31_i + 1, j are used.
  • the potentials of the nodes NN_i, j and the nodes NN_i + 1, j can be set to the ground potential GND. Further, for example, the potential for initialization of the wiring VINIL2 in FIG. 8C is set to the ground potential GND, and the switch SWX and the respective transistors 22 included in the cells 31_i, j and the cells 31_i + 1, j are turned on. , Nodes NNref_i, j, and nodes NNref_i + 1, j can be set to the ground potential GND.
  • the gate potentials of the transistor 23 and the transistor 33 are constant potential Vb.
  • the first terminals of the transistor 23 and the transistor 33 can be set to the voltage Vb-Vth which is lower than the constant potential Vb by the threshold voltage. .. Therefore, it is possible to suppress the rise of the second terminal (drain side) of the transistors 24 and 34.
  • ⁇ From time T11 to time T12 a high level potential (denoted as High in FIG. 11) is applied to the wiring SWL1 and a low level potential (denoted as Low in FIG. 11) is applied to the wiring SWL2.
  • a high level potential is applied to each gate of the transistor F3_1 to the transistor F3_n, each of the transistor F3_1 to the transistor F3_n is turned on, and a low level potential is applied to each gate of the transistor F4_1 to the transistor F4_n.
  • Transistor F4_1 to transistor F4_n are each turned off.
  • a low level potential is applied to the wiring WSL_i and the wiring WSL_i + 1.
  • a low level potential is applied to the gate of the transistor 32 included in the cells 31_i, 1 to 31_i, n in the i-th row of the cell array CA and the gate of the transistor 22 included in the cell 21_i.
  • each transistor 32 and the transistor 22 are turned off.
  • a low level potential is applied to the gate of the transistor 32 included in the cells 31_i + 1,1 to the cells 31_i + 1, n in the i + 1 row of the cell array CA and the gate of the transistor 22 included in the cell 21_i + 1. , Each transistor 32 and the transistor 22 are turned off.
  • the ground potential GND is applied to the wiring XCL_i and the wiring XCL_i + 1.
  • the wiring XCL shown in FIG. 8C is the wiring XCL_i and the wiring XCL_i + 1
  • the potential for initializing the wiring VINIL2 is set to the ground potential GND, and the switch SWX is turned on.
  • Wiring XCL_i, and wiring XCL_i + 1 can be set to the ground potential GND.
  • the first data is not input to the wiring DW_1 to the wiring DW_K.
  • the wiring XCL shown in FIG. 8C is each of the wiring XCL_1 to the wiring XCL_K, the second data is not input to the wiring DX_1 to the wiring DX_L.
  • a low level potential is input to each of the wiring DW_1 to the wiring DW_K in the circuit WCS of FIG. 8A, and the low level is input to each of the wiring DX_1 to the wiring DX_L in the circuit XCS of FIG. 8C. It is assumed that the electric potential is input.
  • a high level potential is applied to the wiring WSL_i between time T12 and time T13.
  • a high level potential is applied to the gate of the transistor 32 included in the cells 31_i, 1 to 31_i, n in the i-th row of the cell array CA and the gate of the transistor 22 included in the cell 21_i.
  • each transistor 32 and the transistor 22 are turned on.
  • a low level potential is applied to the wiring WSL_1 to the wiring WSL_m excluding the wiring WSL_i, and the cells 31_1 to cells 31_1, 1 to cells 31_m, n other than the i-th row of the cell array CA are used. It is assumed that the included transistor 32 and the transistor 22 included in the cells 21_1 to the cell 21_m other than the i-th row are in the off state.
  • ground potential GND is continuously applied to the wiring XCL_1 to the wiring XCL_m from before the time T12.
  • the first terminal of the transistor 32 included in the cells 31_i and j in the i-th row of the cell array CA and the wiring WCL_j are in a conductive state, and the cell array CA is in a conductive state. Since the first terminal of the transistor 32 included in cells 31_1, j to cells 31_m, j other than the i-th row and the wiring WCL_j are in a non-conducting state, a current flows from the wiring WCL_j to the cells 31_i, j. The quantity I 0 _i, j flows.
  • the transistor 32 included in the cells 31_i and j is turned on.
  • the gate-source voltage becomes V g _i, j-GND, and the current I 0 _i, j is set as the current flowing between the first terminal and the second terminal of the transistor 34.
  • the current I ref 0 flows from the circuit XCS to the wiring XCL_i as reference data.
  • the wiring XCL shown in FIG. 8C is the wiring XCL_i
  • a high level potential is input to the wiring DX_1 and a low level potential is input to each of the wiring DX_1 to the wiring DX_K, and a current is input from the circuit XCS to the wiring XCL_i.
  • the current I ref0 flows from the wiring XCL_i to the cell 21_i.
  • the transistor 22 included in cell 21_i is turned on.
  • the gate-source voltage becomes V gm_i -GND
  • the current I ref 0 is set as the current flowing between the first terminal and the second terminal of the transistor 24.
  • a low level potential is applied to the wiring WSL_i between time T14 and time T15.
  • a low level potential is applied to the gate of the transistor 32 included in the cells 31_i, 1 to 31_i, n in the i-th row of the cell array CA and the gate of the transistor 22 included in the cell 21_i. Then, each transistor 32 and the transistor 22 are turned off.
  • the capacitance 35 When the transistor 32 included in the cells 31_i, j is turned off, the capacitance 35 has V g , which is the difference between the potential of the gate (node NN_i, j) of the transistor 34 and the potential of the wiring XCL_i. _I, j-V gm _i is retained. Further, when the transistor 32 included in the cell 21_i is turned off, the capacitance 25 holds 0, which is the difference between the potential of the gate (node NNref_i) of the transistor 24 and the potential of the wiring XCL_i. Ru.
  • GND is applied to the wiring XCL_i between the time T15 and the time T16.
  • the potential for initialization of the wiring VINIL2 is set to the ground potential GND, and the potential of the wiring XCL_i is turned on by turning on the switch SWX. Can be grounded potential GND.
  • the potentials of the nodes NN_i, 1 to NN_i, n are changed by the capacitive coupling by the capacitance 35 contained in each of the cells 31_i, 1 to 31_i, n in the i-th row, and are included in the cell 21_i.
  • the potential of the node NNref_i changes due to the capacitive coupling due to the capacitance 25.
  • the amount of change in the potential of the nodes NN_i, 1 to node NN_i, n is the capacitance coupling coefficient determined by the amount of change in the potential of the wiring XCL_i and the configuration of each of the cells 31_i, 1 to 31_i, n included in the cell array CA. It becomes the potential multiplied by.
  • the capacitive coupling coefficient is calculated by the capacitance of the capacitance 35, the gate capacitance of the transistor 34, the parasitic capacitance, and the like.
  • the potential of the node NNref_i also changes due to the capacitive coupling by the capacitance 25 contained in the cell 21_i.
  • the capacitance coupling coefficient by the capacitance 25 is p as in the capacitance 35
  • the potential of the node NNref_i in the cell 21_i decreases by p (V gm_i -GND) from the potential between the time T14 and the time T15.
  • p 1 is set as an example. Therefore, the potential of the node NNref_i between the time T15 and the time T16 becomes GND.
  • a low level potential is applied to the wiring WSL_1 to the wiring WSL_m excluding the wiring WSL_i + 1, and the cells 31_1 to cells 31_1, 1 to cells 31_m, n other than the i + 1th row of the cell array CA are used. It is assumed that the included transistor 32 and the transistor 22 included in the cells 21_1 to cells 21_m other than the i + 1th row are in the off state.
  • ground potential GND is continuously applied to the wiring XCL_1 to the wiring XCL_m from before the time T16.
  • the first terminal of the transistor 32 included in the cell 31_i + 1, j in the i + 1th row of the cell array CA and the wiring WCL_j are in a conductive state, and the cells 31_1 other than the i + 1th row of the cell array CA are in a conductive state.
  • J to cell 31_m , j is in a non-conducting state between the first terminal of the transistor 32 and the wiring WCL_j. ..
  • the transistor 32 included in the cells 31_i + 1, j is turned on.
  • the gate-source voltage becomes V g _i + 1, j-GND, and the current I 0 _i + 1, j is set as the current flowing between the first terminal and the second terminal of the transistor 34.
  • the current I ref 0 flows from the circuit XCS to the wiring XCL_i + 1 as reference data.
  • the wiring XCL shown in FIG. 8C is the wiring XCL_i + 1
  • the wiring DX_1 has a high level potential
  • the wiring DX_1 to the wiring DX_K have a low level potential.
  • Is input, and the current I ref0 I Xut flows from the circuit XCS to the wiring XCL_i + 1.
  • the first terminal of the transistor 22 included in the cell 21_i + 1 and the wiring XCL_i + 1 are in a conductive state, so that the current I ref0 flows from the wiring XCL_i + 1 to the cell 21_i + 1.
  • the transistor 22 included in cell 21_i + 1 is turned on.
  • the gate-source voltage becomes V gm _i + 1-GND
  • the current I ref 0 is set as the current flowing between the first terminal and the second terminal of the transistor 24.
  • the capacitance 35 When the transistor 32 included in the cell 31_i + 1, j is turned off, the capacitance 35 has V g , which is the difference between the potential of the gate (node NN_i + 1, j) of the transistor 34 and the potential of the wiring XCL_i + 1. _I + 1, j-V gm _i + 1 is retained. Further, when the transistor 32 included in the cell 21_i + 1 is turned off, the capacitance 25 holds 0, which is the difference between the potential of the gate of the transistor 24 (node NNref_i + 1) and the potential of the wiring XCL_i + 1. Ru.
  • the voltage held by the capacitance 25 may be a voltage that is not 0 (here, for example, V ds ) depending on the transistor characteristics of the transistor 22 and the transistor 24 in the operation from the time T18 to the time T19. be.
  • the potential of the node NNref_i + 1 may be considered as the potential obtained by adding V ds to the potential of the wiring XCL_i + 1.
  • the ground potential GND is applied to the wiring XCL_i + 1.
  • the wiring XCL shown in FIG. 8C is the wiring XCL_i + 1
  • the potential for initialization of the wiring VINIL2 is set to the ground potential GND
  • the potential of the wiring XCL_i + 1 is set by turning on the switch SWX. Can be grounded potential GND.
  • the potentials of the nodes NN_i, 1 to NN_i + 1, n are changed by the capacitive coupling by the capacitance 35 included in each of the cells 31_i + 1,1 to the cells 31_i + 1, n in the i + 1 row, and are included in the cell 21_i + 1.
  • the potential of the node NNref_i + 1 changes due to the capacitive coupling due to the capacitance 25.
  • the amount of change in the potential of the nodes NN_i + 1,1 to the node NN_i + 1, n is the capacitance coupling coefficient determined by the amount of change in the potential of the wiring XCL_i + 1 and the configuration of each cell 31_i + 1,1 to cell 31_i + 1, n included in the cell array CA. It becomes the potential multiplied by.
  • the capacitive coupling coefficient is calculated by the capacitance of the capacitance 35, the gate capacitance of the transistor 34, the parasitic capacitance, and the like.
  • the potential of the node NNref_i + 1 also changes due to the capacitive coupling by the capacitance 25 contained in the cell 21_i + 1.
  • the capacitance coupling coefficient by the capacitance 25 is p as in the capacitance 35
  • the potential of the node NNref_i + 1 in the cell 21_i + 1 decreases by p (V gm_i + 1-GND) from the potential between the time T18 and the time T19.
  • p 1 is set as an example. Therefore, the potential of the node NNref_i + 1 between the time T20 and the time T21 becomes GND.
  • a low level potential is applied to the wiring SWL1 between the time T20 and the time T21.
  • a low level potential is applied to the respective gates of the transistors F3_1 to F3_n, and each of the transistors F3_1 to F3_n is turned off.
  • a current of x_iI ref0 which is x_i times the current I ref0 , flows from the circuit XCS to the wiring XCL_i as the second data.
  • a high level potential or a low level potential is input to each of the wiring DX_1 to the wiring DX_K according to the value of x_i.
  • X_iI ref0 x_iI Xut flows from the circuit XCS to the wiring XCL_i as a current.
  • x_i corresponds to the value of the second data.
  • the potential of the wiring XCL_i is assumed to change from 0 to V gm_i + ⁇ V_i.
  • the capacitance of the nodes NN_i, 1 to NN_i, n by the capacitance 35 contained in each of the cells 31_i, 1 to the cells 31_i, n in the i-th row of the cell array CA The potential also changes. Therefore, the potentials of the nodes NN_i, j in the cells 31_i , j are V g_i, j + p ⁇ V_i.
  • the potential of the node NNref_i in the cell 21_i is V gm_i + p ⁇ V_i.
  • the currents flowing between the first terminal and the second terminal of the transistor 34 included in the cells 31_i, j are the first data w_i, j, the second data x_i, and the second data x_i, as described in the first embodiment. Is proportional to the product of.
  • a current of x_i + 1I ref0 flows from the circuit XCS to the wiring XCL_i + 1 as the second data.
  • the wiring XCL shown in FIG. 8C is the wiring XCL_i + 1
  • a high level potential or a low level potential is input to each of the wiring DX_1 to the wiring DX_K according to the value of x_i + 1.
  • X_i + 1I ref0 x_i + 1I Xut flows as a current from the circuit XCS to the wiring XCL_i + 1.
  • x_i + 1 corresponds to the value of the second data.
  • the potential of the wiring XCL_i + 1 changes from 0 to V gm_i + 1 + ⁇ V_i + 1.
  • the capacity coupling by the capacitance 35 contained in each of the cells 31_i + 1,1 to the cells 31_i + 1, n in the i + 1 row of the cell array CA causes the nodes NN_i + 1,1 to the nodes NN_i + 1, n to be coupled.
  • the potential also changes. Therefore, the potential of the node NN_i + 1, j of the cell 31_i + 1, j becomes V g_i + 1, j + p ⁇ V_i + 1.
  • the potential of the node NNref_i + 1 in the cell 21_i + 1 is V gm_i + 1 + p ⁇ V_i + 1.
  • the current flowing between the first terminal and the second terminal of the transistor 34 included in the cell 31_i + 1, j is the first data w_i + 1, j and the second data as described in the first embodiment. It is proportional to the product of a certain x_i + 1.
  • the current output from the conversion circuit ITRZ_j is a current proportional to the sum of the products of the weighting coefficients w_i, j and w_i + 1, j which are the first data and the signal values x_i and x_i + 1 of the neuron which are the second data. It becomes.
  • the product-sum operation can be performed as described above.
  • the arithmetic unit MAC1 simultaneously executes the product-sum operation process for the number of the remaining columns among the plurality of columns by using one of the plurality of columns as a cell holding I ref0 and xI ref0 as currents. can do. That is, by increasing the number of columns in the memory cell array, it is possible to provide a semiconductor device that realizes high-speed multiply-accumulate processing. Therefore, it is possible to provide an arithmetic unit having excellent arithmetic processing capacity per unit electric power.
  • the transistor included in the arithmetic unit MAC1 is an OS transistor or a Si transistor has been described, but one aspect of the present invention is not limited to this.
  • the transistor included in the arithmetic unit MAC1 is, for example, a transistor in which Ge or the like is included in the channel forming region, a transistor in which a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe is contained in the channel forming region, or a carbon nanotube. Can be used as a transistor included in the channel forming region, a transistor in which an organic semiconductor is included in the channel forming region, or the like can be used.
  • a hierarchical artificial neural network (hereinafter referred to as a neural network) will be described.
  • the operation of the hierarchical neural network can be performed by using the semiconductor device and the arithmetic unit described in the above-described embodiment.
  • the synaptic coupling strength can be changed by giving existing information to the neural network.
  • the process of giving existing information to the neural network and determining the bond strength may be called "learning".
  • the bond strength is determined
  • new information can be output based on the bond strength.
  • the process of outputting new information based on the given information and the bond strength may be referred to as "inference” or "cognition”.
  • the signal input from the neuron in the previous layer to the neuron in the next layer is the connection strength of the synapse connecting the neurons (hereinafter referred to as a weighting coefficient).
  • the weighting coefficient is the weighting data described in the above embodiment. Corresponds to.
  • neural network models include Hopfield type and hierarchical type.
  • a neural network having a multi-layer structure may be referred to as a “deep neural network” (DNN), and machine learning by a deep neural network may be referred to as “deep learning”.
  • DNN deep neural network
  • machine learning by a deep neural network may be referred to as “deep learning”.
  • a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers.
  • the hierarchical neural network 100 shown in FIG. 12A shows an example thereof, and the neural network 100 has a first layer to an R layer (R here can be an integer of 4 or more). ing.
  • R can be an integer of 4 or more
  • the first layer corresponds to the input layer
  • the R layer corresponds to the output layer
  • the other layers correspond to the intermediate layer.
  • FIG. 12A shows the (k-1) th layer and the kth layer (here, k is an integer of 3 or more and R-1 or less) as the intermediate layer, and the other intermediate layers. Is not shown.
  • Each layer of the neural network 100 has one or more neurons.
  • the first layer has neurons N 1 (1) to neurons N p (1) (where p is an integer of 1 or more), and the layer (k-1) has neurons N 1 .
  • the kth layer is neuron N 1 (k) to neuron N n (k) (
  • n is an integer of 1 or more
  • the layer R has neurons N 1 (R) to neurons N q (R) (where q is an integer of 1 or more).
  • FIG. 12B shows the neuron N j (k) in the k-th layer, the signal input to the neuron N j ( k) , and the signal output from the neuron N j (k).
  • the degree of signal transmission is determined by the strength of synaptic connections (hereinafter referred to as weighting factors) that connect these neurons.
  • weighting factors the strength of synaptic connections that connect these neurons.
  • the signal output from the neurons in the previous layer is multiplied by the corresponding weighting factor and input to the neurons in the next layer.
  • i be an integer of 1 or more and m or less, and set the weight coefficient of the synapse between the neuron N i (k-1) in the (k-1) layer and the neuron N j (k) in the kth layer as wi ( k ).
  • j (k) When j (k) is set, the signal input to the neuron Nj (k) in the kth layer can be expressed by the equation (7).
  • the result of the sum of products may be biased as a bias.
  • the bias is b, the equation (8) can be rewritten into the following equation (9).
  • the neuron N j (k) produces an output signal z j (k ) in response to u j (k) .
  • the output signal z j ( k) from the neuron N j (k) is defined by the following equation (10).
  • the function f (u j (k) ) is an activation function in a hierarchical neural network, and a step function, a linear ramp function, a sigmoid function, or the like can be used.
  • the activation function may be the same or different in all neurons.
  • the activation function of neurons may be the same or different in each layer.
  • the signal output by the neurons in each layer, the weighting factor w, or the bias b may be an analog value or a digital value.
  • the digital value may be, for example, a binary value or a ternary value. A value with a larger number of bits may be used.
  • an analog value for example, a linear ramp function, a sigmoid function, or the like may be used as the activation function.
  • binary digital values for example, a step function with an output of -1 or 1 or 0 or 1 may be used.
  • the signal output by the neurons in each layer may have three or more values.
  • the activation function has three values, for example, a step function in which the output is -1, 0, or 1, or 0, 1, or 2.
  • a step function or the like may be used.
  • a step function of -2, -1, 0, 1, or 2 may be used.
  • the neural network 100 By inputting an input signal to the first layer (input layer), the neural network 100 is sequentially input from the front layer in each layer from the first layer (input layer) to the last layer (output layer). Based on the signal, an output signal is generated using the equation (7), the equation (8) (or the equation (9)), and the equation (10), and the output signal is output to the next layer.
  • the signal output from the last layer (output layer) corresponds to the result calculated by the neural network 100.
  • the weighting coefficient w s [k-1] (k-1) s_K (k) (s [k-1] is 1 or more m.
  • the following integers are used, and s_K is an integer of 1 or more and n or less) as the first data.
  • the output signal z s [k-1] (k-1) from the neurons N s [k-1] ( k-1) is used as the second data, and the current corresponding to the second data is applied from the circuit XCS to the wiring XCL of each line.
  • the sum of products of the first data and the second data can be obtained from the current IS input to the conversion circuit ITRZ .
  • the value of the activation function is used as a signal to be the output signal z s_K (k) of the neuron N s_K (k) in the kth layer. Can be done.
  • the weighting coefficients w s [R-1] (R-1) s [R] (R) (s [R-1]. ] Is an integer of 1 or more, and s [R] is an integer of 1 or more and q or less) as the first data, and the current corresponding to the first data is sequentially stored in each cell IM in the same column.
  • the output signal z s [R-1] ( R-1) from the neurons N s [R-1] (R-1) in the R-1) layer is used as the second data, and the current corresponding to the second data is circuited.
  • the sum of products of the first data and the second data can be obtained from the current IS input to the conversion circuit ITRZ .
  • the output signal z s [R] of the neurons N s [R] (R) in the R layer uses the value of the activation function as a signal. It can be (R) .
  • the input layer described in the present embodiment may function as a buffer circuit that outputs an input signal to the second layer.
  • FIG. 13 shows a part of the cross-sectional structure of the semiconductor device.
  • the semiconductor device shown in FIG. 13 includes a transistor 550, a transistor 500, and a capacitive element 600.
  • 14A is a cross-sectional view of the transistor 500 in the channel length direction
  • FIG. 14B is a cross-sectional view of the transistor 500 in the channel width direction.
  • the transistor 500 corresponds to an OS transistor included in the reference cell 21 and the arithmetic cell 31 shown in the above embodiment, that is, a transistor having an oxide semiconductor in the channel forming region.
  • the transistor 550 corresponds to a Si transistor included in the reference cell 21 and the arithmetic cell 31 shown in the above embodiment, that is, a transistor having silicon in the channel forming region.
  • the capacitance element 600 corresponds to the capacitance of the reference cell 21 and the calculation cell 31.
  • the transistor 500 is provided above the transistor 550, and the capacitive element 600 is provided above the transistor 550 and the transistor 500.
  • the transistor 550 is provided on the substrate 311.
  • the substrate 311 is, for example, a p-type silicon substrate.
  • the substrate 311 may be an n-type silicon substrate.
  • the oxide layer 314 is preferably an insulating layer (also referred to as a BOX layer) formed in a substrate 311 by embedded oxidation (Blured oxide), for example, silicon oxide.
  • the transistor 550 is provided on a single crystal silicon, a so-called SOI (Silicon On Insulator) substrate, which is provided on the substrate 311 via an oxide layer 314.
  • SOI Silicon On Insulator
  • the substrate 311 in the SOI substrate is provided with an insulator 313 that functions as an element separation layer.
  • the substrate 311 also has a well region 312.
  • the well region 312 is a region to which n-type or p-type conductivity is imparted depending on the conductive type of the transistor 550.
  • the single crystal silicon in the SOI substrate is provided with a semiconductor region 315, a low resistance region 316a that functions as a source region or a drain region, and a low resistance region 316b. Further, a low resistance region 316c is provided on the well region 312.
  • the transistor 550 can be provided so as to be superimposed on the well region 312 to which the impurity element that imparts conductivity is added.
  • the well region 312 can function as a bottom gate electrode of the transistor 550 by independently changing the potential via the low resistance region 316c. Therefore, the threshold voltage of the transistor 550 can be controlled.
  • the threshold voltage of the transistor 550 can be made larger and the off-current can be reduced. Therefore, by applying a negative potential to the well region 312, the drain current when the potential applied to the gate electrode of the Si transistor is 0V can be reduced.
  • the power consumption of the semiconductor device 10 having the transistor 550 and the arithmetic unit MAC1 and the like can be reduced, and the arithmetic efficiency can be improved.
  • the transistor 550 is preferably of a so-called Fin type in which the upper surface of the semiconductor layer and the side surface in the channel width direction are covered with the conductor 318 via the insulator 317.
  • the on-characteristics of the transistor 550 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 550 can be improved.
  • the transistor 550 may be either a p-channel type transistor or an n-channel type transistor.
  • the conductor 318 may function as a first gate (also referred to as a top gate) electrode. Further, the well region 312 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the potential applied to the well region 312 can be controlled via the low resistance region 316c.
  • the low resistance region 316a which is the region where the channel of the semiconductor region 315 is formed, the region in the vicinity thereof, the source region, or the drain region, and the low resistance region 316b, which is connected to the electrode controlling the potential of the well region 312.
  • the region 316c or the like preferably contains a semiconductor such as a silicon-based semiconductor, and preferably contains single crystal silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used.
  • the transistor 550 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
  • the low resistance region 316a, the low resistance region 316b, and the low resistance region 316c are elements that impart n-type conductivity such as arsenic and phosphorus, or boron. It contains elements that impart p-type conductivity such as.
  • the conductor 318 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.
  • a conductive material such as a material or a metal oxide material can be used.
  • a silicide such as nickel silicide may be used as the conductor 318.
  • the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
  • the low resistance region 316a, the low resistance region 316b, and the low resistance region 316c may be configured to be provided by laminating another conductor, for example, a silicide such as nickel silicide. With this configuration, the conductivity of the region that functions as an electrode can be enhanced. At this time, an insulator that functions as a side wall spacer (also referred to as a side wall insulating layer) may be provided on the side surface of the conductor 318 that functions as the gate electrode and the side surface of the insulator that functions as the gate insulating film. .. With this configuration, it is possible to prevent the conductor 318 and the low resistance region 316a and the low resistance region 316b from being in a conductive state.
  • a silicide such as nickel silicide
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are laminated in this order so as to cover the transistor 550.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, etc. are used. Just do it.
  • silicon oxide refers to a material having a higher oxygen content than nitrogen as its composition
  • silicon nitride as its composition refers to a material having a higher nitrogen content than oxygen as its composition. Is shown.
  • aluminum nitride refers to a material whose composition has a higher oxygen content than nitrogen
  • aluminum nitride refers to a material whose composition has a higher nitrogen content than oxygen. Is shown.
  • the insulator 322 may have a function as a flattening film for flattening a step generated by a transistor 550 or the like provided below the insulator 322.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • the insulator 324 it is preferable to use a film having a barrier property such that hydrogen, impurities, etc. do not diffuse in the region where the transistor 500 is provided from the substrate 311 or the transistor 550.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by the CVD method can be used.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550.
  • the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.
  • the amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS).
  • TDS heated desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is such that the amount desorbed in terms of hydrogen atoms is converted per area of the insulator 324 when the surface temperature of the film is in the range of 50 ° C. to 500 ° C. It may be 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 has a lower dielectric constant than the insulator 324.
  • the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3.
  • the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the relative permittivity of the insulator 324.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitive element 600, a conductor 328 connected to the transistor 500, a conductor 330, and the like.
  • the conductor 328 and the conductor 330 have a function as a plug or wiring.
  • the conductor having a function as a plug or a wiring may collectively give the same reference numeral to a plurality of configurations.
  • the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • each plug and wiring As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or laminated. be able to. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are laminated in this order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 has a function as a plug or wiring for connecting to the transistor 550.
  • the conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 350 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 356 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen.
  • the conductor having a barrier property against hydrogen for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 550 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 354 and the conductor 356.
  • the insulator 360, the insulator 362, and the insulator 364 are laminated in this order.
  • a conductor 366 is formed on the insulator 360, the insulator 362, and the insulator 364.
  • the conductor 366 has a function as a plug or wiring.
  • the conductor 366 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 360 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 366 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 364 and the conductor 366.
  • the insulator 370, the insulator 372, and the insulator 374 are laminated in this order.
  • a conductor 376 is formed on the insulator 370, the insulator 372, and the insulator 374.
  • the conductor 376 has a function as a plug or wiring.
  • the conductor 376 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 370 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 376 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 374 and the conductor 376.
  • the insulator 380, the insulator 382, and the insulator 384 are laminated in this order.
  • a conductor 386 is formed on the insulator 380, the insulator 382, and the insulator 384.
  • the conductor 386 has a function as a plug or wiring.
  • the conductor 386 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 380 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 386 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen.
  • the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to the present embodiment has been described. It is not limited to this.
  • the number of wiring layers similar to the wiring layer including the conductor 356 may be 3 or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be 5 or more.
  • the insulator 510, the insulator 512, the insulator 514, and the insulator 516 are laminated in this order.
  • a substance having a barrier property against oxygen or hydrogen it is preferable to use a substance having a barrier property against oxygen or hydrogen.
  • the insulator 510 and the insulator 514 it is preferable to use a film having a barrier property against hydrogen or impurities in the region where the transistor 500 is provided, for example, from the region where the substrate 311 or the transistor 550 is provided. Therefore, the same material as the insulator 324 can be used.
  • Silicon nitride formed by the CVD method can be used as an example of a film having a barrier property against hydrogen.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550.
  • metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • the same material as the insulator 320 can be used for the insulator 512 and the insulator 516. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 512 and the insulator 516.
  • the insulator 510, the insulator 512, the insulator 514, and the insulator 516 are embedded with a conductor 518, a conductor (for example, a conductor 503) constituting the transistor 500, and the like.
  • the conductor 518 has a function as a plug or wiring for connecting to the capacitive element 600 or the transistor 550.
  • the conductor 518 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the conductor 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having a barrier property against oxygen, hydrogen, and water.
  • the transistor 550 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.
  • a transistor 500 is provided above the insulator 516.
  • the transistor 500 has a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, and an insulator 522 arranged on the insulator 516 and the insulator 503. And an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, and each other on the oxide 530b. Insulator 580 and an opening which are arranged on the conductor 542a and the conductor 542b and which are arranged apart from each other and have an opening formed by superimposing between the conductor 542a and the conductor 542b. It has an insulator 545 arranged on the bottom surface and side surfaces of the insulator 545, and a conductor 560 arranged on the forming surface of the insulator 545.
  • the insulator 544 is arranged between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b, and the insulator 580.
  • the conductor 560 includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. It is preferable to have.
  • the insulator 574 is arranged on the insulator 580, the conductor 560, and the insulator 545.
  • the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.
  • the transistor 500 shows a configuration in which two layers of oxide 530a and oxide 530b are laminated in a region where a channel is formed and in the vicinity thereof, but the present invention is not limited to this.
  • a single layer of the oxide 530b or a laminated structure of three or more layers may be provided.
  • the conductor 560 is shown as a laminated structure of two layers, but the present invention is not limited to this.
  • the conductor 560 may have a single-layer structure or a laminated structure of three or more layers.
  • the transistor 500 shown in FIGS. 13, 14A, and 14B is an example, and the transistor 500 is not limited to the configuration thereof, and an appropriate transistor may be used depending on the circuit configuration, driving method, and the like.
  • the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b function as a source electrode or a drain electrode, respectively.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the arrangement of the conductor 560, the conductor 542a and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing the alignment margin, the occupied area of the transistor 500 can be reduced. As a result, the semiconductor device can be miniaturized and highly integrated.
  • the conductor 560 is formed in a region between the conductor 542a and the conductor 542b in a self-aligned manner, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Therefore, the switching speed of the transistor 500 can be improved and high frequency characteristics can be provided.
  • the conductor 560 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 without interlocking with the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, it is possible to increase the threshold voltage of the transistor 500 and reduce the off-current. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when it is not applied.
  • the conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to cover the channel forming region formed in the oxide 530. Can be done.
  • the configuration of a transistor that electrically surrounds a channel forming region by an electric field of a pair of gate electrodes is referred to as a curved channel (S-channel) configuration.
  • S-channel configuration disclosed in the present specification and the like is different from the Fin type configuration and the planar type configuration.
  • the conductor 503 has the same configuration as the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside.
  • the transistor 500 shows a configuration in which the conductor 503a and the conductor 503b are laminated, the present invention is not limited to this.
  • the conductor 503 may be provided as a single layer or a laminated structure having three or more layers.
  • a conductive material for the conductor 503a which has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate).
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one such as an oxygen atom and an oxygen molecule
  • the function of suppressing the diffusion of impurities or oxygen is the function of suppressing the diffusion of any one or more of the above impurities or the above oxygen.
  • the conductor 503a since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 503b from being oxidized and the conductivity from being lowered.
  • the conductor 503 When the conductor 503 also functions as a wiring, it is preferable to use a highly conductive material containing tungsten, copper, or aluminum as a main component for the conductor 503b.
  • the conductor 503 is shown by laminating the conductor 503a and the conductor 503b, but the conductor 503 may have a single-layer structure.
  • the insulator 522 and the insulator 524 have a function as a second gate insulating film.
  • the insulator 524 in contact with the oxide 530 it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition.
  • the oxygen is easily released from the membrane by heating.
  • oxygen released by heating may be referred to as "excess oxygen”. That is, it is preferable that the insulator 524 is formed with a region containing excess oxygen (also referred to as “excess oxygen region”).
  • the defect (hereinafter, may be referred to as VOH) functions as a donor and may generate electrons as carriers.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Further, since hydrogen in an oxide semiconductor is easily moved by stress such as heat and electric field, if a large amount of hydrogen is contained in the oxide semiconductor, the reliability of the transistor may be deteriorated. In one aspect of the invention, it is preferred to reduce VOH in the oxide 530 as much as possible to achieve high purity or substantially high purity.
  • impurities such as water and hydrogen in the oxide semiconductor must be removed (also referred to as “dehydration” or “dehydrogenation treatment”). It is important to supply oxygen to the oxide semiconductor to compensate for the oxygen deficiency (also referred to as “dehydrogenation treatment”).
  • an oxide material in which a part of oxygen is desorbed by heating is those whose oxygen desorption amount in terms of oxygen atoms is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 in TDS (Therml Desorption Spectroscopy) analysis.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • the insulator having the excess oxygen region and the oxide 530 may be brought into contact with each other to perform one or more of heat treatment, microwave treatment, or RF treatment. By performing this treatment, water or hydrogen in the oxide 530 can be removed.
  • a reaction in which the bond of VoH is cleaved occurs, in other words, a reaction of “VOH ⁇ Vo + H ” occurs, and dehydrogenation can be performed.
  • a part of the hydrogen generated at this time may be combined with oxygen to form H2O and may be removed from the oxide 530 or the insulator in the vicinity of the oxide 530. Further, a part of hydrogen may be gettered to the conductor 542.
  • the microwave processing for example, it is preferable to use a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side.
  • a device having a power source for generating high-density plasma for example, by using a gas containing oxygen and using a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be generated.
  • the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
  • oxygen and argon are used as the gas to be introduced into the apparatus for performing microwave treatment, and the oxygen flow rate ratio (O 2 / (O 2 + Ar)) is 50% or less, preferably 10% or more and 30. It is better to do it at% or less.
  • the heat treatment in a state where the surface of the oxide 530 is exposed.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 450 ° C. or lower, more preferably 350 ° C. or higher and 400 ° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • oxygen can be supplied to the oxide 530 to reduce oxygen deficiency (VO).
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas. good.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more, and then continuously heat-treated in an atmosphere of nitrogen gas or an inert gas.
  • the oxygen deficiency in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo + O ⁇ null" can be promoted. Further, the oxygen supplied to the hydrogen remaining in the oxide 530 reacts with the hydrogen, so that the hydrogen can be removed (dehydrated) as H2O . As a result, it is possible to suppress the hydrogen remaining in the oxide 530 from recombination with the oxygen deficiency to form VOH.
  • the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).
  • oxygen for example, oxygen atom, oxygen molecule, etc.
  • the insulator 522 has a function of suppressing the diffusion of oxygen, impurities, etc., the oxygen contained in the oxide 530 does not diffuse to the conductor 503 side, which is preferable. Further, it is possible to prevent the conductor 503 from reacting with oxygen contained in the insulator 524, the oxide 530, and the like.
  • the insulator 522 may be, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or It is preferable to use an insulator containing a so-called high-k material such as (Ba, Sr) TiO 3 (BST) in a single layer or in a laminated state. As the transistor becomes finer and more integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for an insulator that functions as a gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • a so-called high-k material such as (Ba, Sr) TiO 3 (BST)
  • an insulator containing an oxide of one or both of aluminum and hafnium which are insulating materials having a function of suppressing diffusion of impurities and oxygen (which oxygen is difficult to permeate).
  • the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
  • the insulator 522 releases oxygen from the oxide 530 and / or mixes impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530. Functions as a layer that suppresses.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon nitride nitride, or silicon nitride may be laminated on the above insulator.
  • the insulator 522 and the insulator 524 are shown as the second gate insulating film having a laminated structure of two layers, but the second gate insulating film is It may have a single layer, three layers, or a laminated structure of four or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • the transistor 500 uses a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel forming region.
  • a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel forming region.
  • an In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium). , Hafnium, tantalum, tungsten, or one or more selected from gallium, etc.) and the like.
  • the metal oxide that functions as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method.
  • ALD Atomic Layer Deposition
  • the oxide 530 can suppress the diffusion of impurities from the composition formed below the oxide 530a to the oxide 530b.
  • the oxide 530 has a laminated structure of a plurality of oxide layers having different atomic number ratios of each metal atom.
  • the atomic number ratio of the element M in the constituent elements is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used in the oxide 530b.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a.
  • the energy at the lower end of the conduction band of the oxide 530a is higher than the energy at the lower end of the conduction band of the oxide 530b.
  • the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the lower end of the conduction band at the junction of the oxides 530a and 530b can be said to be continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.
  • the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, so that a mixed layer having a low defect level density can be formed.
  • the oxide 530b is an In-Ga-Zn oxide
  • the main path of the carrier is oxide 530b.
  • the defect level density at the interface between the oxide 530a and the oxide 530b can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.
  • a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided on the oxide 530b.
  • the conductors 542a and 542b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium.
  • Iridium, strontium, a metal element selected from lanthanum, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like is preferably used.
  • tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.
  • the conductor 542a and the conductor 542b are shown as a single-layer structure, but a laminated structure of two or more layers may be used.
  • a tantalum nitride film and a tungsten film may be laminated.
  • the titanium film and the aluminum film may be laminated.
  • a two-layer structure in which an aluminum film is laminated on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a tungsten film. It may be a two-layer structure in which copper films are laminated.
  • a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.
  • a region 543a and a region 543b may be formed as a low resistance region at the interface of the oxide 530 with the conductor 542a (conductor 542b) and its vicinity thereof.
  • the region 543a functions as one of the source region or the drain region
  • the region 543b functions as the other of the source region or the drain region.
  • a channel forming region is formed in a region sandwiched between the region 543a and the region 543b.
  • the oxygen concentration in the region 543a (region 543b) may be reduced. Further, in the region 543a (region 543b), a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the component of the oxide 530 may be formed. In such a case, the carrier density of the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.
  • the insulator 544 is provided so as to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and come into contact with the insulator 524.
  • insulator 544 a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Can be used. Further, as the insulator 544, silicon nitride oxide, silicon nitride or the like can also be used.
  • the insulator 544 it is preferable to use aluminum or an oxide containing one or both oxides of hafnium, such as aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate). ..
  • hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent step.
  • the conductors 542a and 542b are materials having oxidation resistance or materials whose conductivity does not significantly decrease even if oxygen is absorbed, the insulator 544 is not an essential configuration. It may be appropriately designed according to the desired transistor characteristics.
  • the insulator 544 By having the insulator 544, it is possible to prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. Further, it is possible to suppress the oxidation of the conductor 542 due to the excess oxygen contained in the insulator 580.
  • the insulator 545 functions as a first gate insulating film. Like the above-mentioned insulator 524, the insulator 545 is preferably formed by using an insulator that contains excessive oxygen and releases oxygen by heating.
  • silicon oxide with excess oxygen silicon oxide, silicon nitride, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, carbon, silicon oxide with nitrogen, and pores.
  • Silicon oxide having can be used.
  • silicon oxide and silicon nitride nitride are preferable because they are heat-stable.
  • the insulator 545 By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel forming region of the oxide 530b. Further, as with the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 545 is reduced.
  • the film thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. Further, the above-mentioned microwave treatment may be performed before and / or after the formation of the insulator 545.
  • a metal oxide may be provided between the insulator 545 and the conductor 560.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560.
  • the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 530.
  • oxidation of the conductor 560 due to excess oxygen can be suppressed.
  • a material that can be used for the insulator 544 may be used.
  • the insulator 545 may have a laminated structure as in the case of the second gate insulating film.
  • an insulator that functions as a gate insulating film is made of a high-k material and heat.
  • the conductor 560 functioning as the first gate electrode is shown as a two-layer structure in FIGS. 14A and 14B, it may have a single-layer structure or a laminated structure of three or more layers.
  • the conductor 560a has a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ( N2O, NO, NO2 , etc.) and copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 545 to reduce the conductivity.
  • impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ( N2O, NO, NO2 , etc.) and copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b into a film by a sputtering method, the electric resistance value of the conductor 560a can be lowered to form a conductor. This can be called an OC (Oxide Conductor) electrode.
  • the conductor 560b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material.
  • the insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544.
  • the insulator 580 preferably has an excess oxygen region.
  • silicon, resin, or the like silicon oxide and silicon nitride nitride are preferable because they are thermally stable.
  • silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later step.
  • the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 in which oxygen is released by heating, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.
  • the opening of the insulator 580 is formed so as to overlap the region between the conductor 542a and the conductor 542b.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the conductor 560 may have a shape having a high aspect ratio.
  • the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape having a high aspect ratio, the conductor 560 is formed without collapsing during the process. Can be done.
  • the insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545.
  • an excess oxygen region can be provided in the insulator 545 and the insulator 580. Thereby, oxygen can be supplied into the oxide 530 from the excess oxygen region.
  • the insulator 574 use one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like. Can be done.
  • aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, the aluminum oxide formed by the sputtering method can have a function as a barrier film for impurities such as hydrogen as well as an oxygen supply source.
  • an insulator 581 that functions as an interlayer film on the insulator 574. It is preferable that the insulator 581 has a reduced concentration of impurities such as water or hydrogen in the membrane, similarly to the insulator 524 and the like.
  • the conductor 540a and the conductor 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544.
  • the conductor 540a and the conductor 540b are provided so as to face each other with the conductor 560 interposed therebetween.
  • the conductor 540a and the conductor 540b have the same configuration as the conductor 546 and the conductor 548 described later.
  • An insulator 582 is provided on the insulator 581.
  • the insulator 582 it is preferable to use a substance having a barrier property against oxygen and / or hydrogen. Therefore, the same material as the insulator 514 can be used for the insulator 582.
  • a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • an insulator 586 is provided on the insulator 582.
  • the same material as the insulator 320 can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 586.
  • a conductor 546, a conductor 548, etc. are embedded in the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586. There is.
  • the conductor 546 and the conductor 548 have a function as a plug or wiring for connecting to the capacitive element 600, the transistor 500, or the transistor 550.
  • the conductor 546 and the conductor 548 can be provided by using the same materials as the conductor 328 and the conductor 330.
  • an opening may be formed so as to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed so as to cover the opening.
  • an insulator having a high barrier property against hydrogen or water By wrapping the transistor 500 with the above-mentioned insulator having a high barrier property, it is possible to prevent moisture and hydrogen from invading from the outside.
  • a plurality of transistors 500 may be bundled together and wrapped with an insulator having a high barrier property against hydrogen or water.
  • an opening is formed so as to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 is formed, and the above-mentioned insulator having a high barrier property is provided so as to be in contact with the insulator 522 or the insulator 514.
  • the insulator having a high barrier property to hydrogen or water for example, the same material as the insulator 522 or the insulator 514 may be used.
  • the capacitive element 600 has a conductor 610, a conductor 620, and an insulator 630.
  • the conductor 612 may be provided on the conductor 546 and the conductor 548.
  • the conductor 612 has a function as a plug or wiring for connecting to the transistor 500.
  • the conductor 610 has a function as an electrode of the capacitive element 600.
  • the conductor 612 and the conductor 610 can be formed at the same time.
  • the conductor 612 and the conductor 610 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as components.
  • a metal nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film can be used.
  • the conductor 612 and the conductor 610 are shown in a single-layer configuration, but the configuration is not limited to this, and a laminated configuration of two or more layers may be used.
  • a conductor having a barrier property and a conductor having a high adhesion to the conductor having a high conductivity may be formed between the conductor having the barrier property and the conductor having a high conductivity.
  • the conductor 620 is provided so as to be superimposed on the conductor 610 via the insulator 630.
  • a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum which has both heat resistance and conductivity, and it is particularly preferable to use tungsten.
  • tungsten When it is formed at the same time as other configurations such as a conductor, Cu (copper) or Al (aluminum), which is a low resistance metal material, may be used.
  • An insulator 640 is provided on the conductor 620 and the insulator 630.
  • the insulator 640 can be provided by using the same material as the insulator 320. Further, the insulator 640 may function as a flattening film that covers the uneven shape below the insulator 640.
  • FIG. 15 is an example of a semiconductor chip 391 incorporating an integrated circuit 390.
  • the semiconductor chip 391 shown in FIG. 15 has a lead 392 and an integrated circuit 390.
  • various circuits including the semiconductor device 10 and the arithmetic unit MAC1 shown in the above embodiment are provided on the die of 1.
  • the integrated circuit 390 has a laminated structure and is roughly classified into a layer having a Si transistor (Si transistor layer 393), a wiring layer 394, and a layer having an OS transistor (OS transistor layer 395). Since the OS transistor layer 395 can be laminated on the Si transistor layer 393, the semiconductor chip 391 can be easily miniaturized.
  • QFP Quad Flat Package
  • Other configuration examples include insert-mounted DIP (Dual In-line Package), PGA (Pin Grid Array), surface-mounted SOP (Small Outline Package), SSOP (Shrink Small Outline Package), and TS. Thin-Small Outline Package), LCC (Leaded Chip Carrier), QFN (Quad Flat Non-readed package), BGA (Ball Grid Array), FBGA (Pin Grid Array), FBGA (Fine Grid) TP Structures such as Package) and QTP (Quad Tape-carrier Package) can be appropriately used.
  • the semiconductor device 10 having the Si transistor and the arithmetic unit MAC1 can all be formed on the Si transistor layer 393, the wiring layer 394, and the OS transistor layer 395. That is, the elements constituting the semiconductor device can be formed by the same manufacturing process. Therefore, in the semiconductor chip shown in FIG. 15, it is not necessary to increase the manufacturing process even if the number of constituent elements increases, and the semiconductor device can be incorporated at low cost.
  • a novel semiconductor device and an electronic device can be provided.
  • FIGS. 16 to 16 show the electronic devices, mobile bodies, and arithmetic systems to which the integrated circuit 390 described in the above embodiment (or the semiconductor chip 391 incorporating the integrated circuit 390) can be applied. It will be described with reference to 19.
  • FIG. 16A illustrates an external view of an automobile as an example of a moving body.
  • FIG. 16B is a diagram that simplifies the exchange of data in the automobile.
  • the automobile 590 has a plurality of cameras 591 and the like. Further, the automobile 590 is equipped with various sensors (not shown) such as an infrared radar, a millimeter wave radar, and a laser radar.
  • the integrated circuit 390 can be used for the camera 591 and the like.
  • the camera 591 processes a plurality of images obtained in a plurality of imaging directions 592 by the integrated circuit 390 described in the above embodiment, and the plurality of images are collected by the host controller 594 or the like via the bus 593 or the like.
  • the host controller 594 or the like By analyzing this, it is possible to determine the surrounding traffic conditions such as the presence or absence of guard rails or pedestrians, and perform automatic driving. It can also be used in systems for road guidance, danger prediction, and the like.
  • the obtained image data is subjected to arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (security purpose, etc.), and object recognition (purpose of automatic driving).
  • arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (security purpose, etc.), and object recognition (purpose of automatic driving).
  • Etc. image compression, image correction (wide dynamic range), image restoration of lensless image sensor, positioning, character recognition, reduction of reflection reflection, etc. can be performed.
  • the automobile is described as an example of the moving body, but the moving body is not limited to the automobile.
  • moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the computer of one aspect of the present invention is applied to these moving objects. Therefore, it is possible to provide a system using artificial intelligence.
  • FIG. 17A is an external view showing an example of a portable electronic device.
  • FIG. 17B is a diagram simplifying the exchange of data in a portable electronic device.
  • the portable electronic device 595 includes a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, and the like.
  • the integrated circuit 390 can be provided on the printed wiring board 596.
  • the portable electronic device 595 improves user convenience by processing and analyzing a plurality of data obtained by the speaker 597, the camera 598, the microphone 599, etc. by using the integrated circuit 390 described in the above embodiment. be able to.
  • the obtained image data is subjected to arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (security purpose, etc.), and object recognition (purpose of automatic driving).
  • arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (security purpose, etc.), and object recognition (purpose of automatic driving).
  • Etc. image compression, image correction (wide dynamic range), image restoration of lensless image sensor, positioning, character recognition, reduction of reflection reflection, etc. can be performed.
  • the portable game machine 1100 shown in FIG. 18A has a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, an operation key 1107, and the like.
  • the housing 1101, the housing 1102 and the housing 1103 can be removed.
  • the connection unit 1105 provided in the housing 1101 to the housing 1108 the video output to the display unit 1104 can be output to another video device.
  • the housing 1102 and the housing 1103 are integrated and function as an operation unit.
  • the integrated circuit 390 shown in the previous embodiment can be incorporated into the chips and the like provided on the boards of the housing 1102 and the housing 1103.
  • FIG. 18B is a USB connection type stick-type electronic device 1120.
  • the electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a substrate 1124.
  • the board 1124 is housed in the housing 1121.
  • a memory chip 1125 and a controller chip 1126 are attached to the substrate 1124.
  • the integrated circuit 390 shown in the previous embodiment can be incorporated into the controller chip 1126 or the like of the substrate 1124.
  • FIG. 18C is a humanoid robot 1130.
  • the robot 1130 has sensors 2101 to 2106 and a control circuit 2110.
  • the integrated circuit 390 shown in the previous embodiment can be incorporated in the control circuit 2110.
  • the integrated circuit 390 described in the above embodiment can be used as a server that communicates with the electronic device instead of being built in the electronic device.
  • the arithmetic system is composed of the electronic device and the server.
  • FIG. 19 shows a configuration example of the system 3000.
  • the system 3000 is composed of an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via the Internet line 3003.
  • the server 3002 has a plurality of racks 3004.
  • a plurality of boards 3005 are provided in the plurality of racks, and the integrated circuit 390 described in the above embodiment can be mounted on the board 3005.
  • a neural network is configured on the server 3002.
  • the server 3002 can perform the operation of the neural network by using the data input from the electronic device 3001 via the Internet line 3003.
  • the result of the calculation by the server 3002 can be transmitted to the electronic device 3001 via the Internet line 3003, if necessary. This makes it possible to reduce the burden of calculation in the electronic device 3001.
  • the semiconductor devices 10 and 10B shown in the first embodiment and a comparative example thereof will be described.
  • a Monte Carlo simulation of variations in output current according to the input data was performed, and the calculation accuracy of the semiconductor devices 10 and 10B was verified.
  • FIG. 20A shows a configuration without transistors 23 and 33 in the semiconductor device 10 as a comparative example.
  • transistors M11, M21, M12, and M22 are illustrated.
  • the connection of each circuit and wiring is as shown in the figure.
  • the transistors M11 and M21 are OS transistors.
  • the transistors M12 and M22 are Si transistors.
  • the channel length (L) and channel length (W) of the OS transistor were both set to 60 nm.
  • the channel length (L) of the Si transistor was 0.65 ⁇ m, and the channel length (W) was 0.4 ⁇ m.
  • the wiring WSL had a high level potential of 2.5 V when writing data and a low level potential of ⁇ 0.8 V when reading data.
  • the drain voltage Vd was set to 1.2V at the time of data reading. 0V was applied to the back gate of the OS transistor. 1nA was given as IW to be flowed as weight data. When the current IX flowing as input data was changed from 0nA to 1.0nA, the current Ir flowing through the wiring WCL was observed. The number of trials of the Monte Carlo simulation was set to 50.
  • FIG. 20B shows the configuration of the semiconductor device 10.
  • transistors M11, M21, M12, M22, M13, and M23 are illustrated.
  • the connection of each circuit and wiring is as shown in the figure.
  • the transistors M11 and M21 are OS transistors.
  • the transistors M12, M22, M13, and M23 are Si transistors.
  • the channel length (L) and channel length (W) of the OS transistor were both set to 60 nm.
  • the channel length (L) of the Si transistor was 0.65 ⁇ m, and the channel length (W) was 0.4 ⁇ m.
  • the wiring WSL had a high level potential of 2.5 V when writing data and a low level potential of ⁇ 0.8 V when reading data.
  • the drain voltage Vd was set to 1.2V at the time of data reading.
  • the voltage Vb applied to the wiring VBL was 0.7 V at 27 ° C and 0.8 V at 85 ° C.
  • 0V was applied to the back gate of the OS transistor. 1nA was given as IW to be flowed as weight data.
  • the number of trials of the Monte Carlo simulation was set to 50.
  • FIG. 20C shows the configuration of the semiconductor device 10B.
  • transistors M11, M21, M12, M22, M13, and M23 are illustrated.
  • the connection of each circuit and wiring is as shown in the figure.
  • the transistors M11 and M21 are OS transistors.
  • the transistors M12, M22, M13, and M23 are Si transistors.
  • the channel length (L) and channel length (W) of the OS transistor were both set to 60 nm.
  • the channel length (L) of the Si transistor was 0.65 ⁇ m, and the channel length (W) was 0.4 ⁇ m.
  • the wiring WSL had a high level potential of 2.5 V when writing data and a low level potential of ⁇ 0.8 V when reading data.
  • the drain voltage Vd was set to 1.2V at the time of data reading.
  • the voltage Vb applied to the wiring VBL was 0.6 V at 27 ° C and 0.8 V at 85 ° C.
  • the V body given to the back gate of the Si transistor was set to -0.5V.
  • 0V was applied to the back gate of the OS transistor.
  • 1nA was given as IW to be flowed as weight data.
  • the number of trials of the Monte Carlo simulation was set to 50.
  • FIG. 21A is a diagram showing the output result of the current Ir with respect to the current IX of FIG. 20A at 27 ° C.
  • FIG. 21B is a diagram showing the output result of the current Ir with respect to the current IX of FIG. 20B at 27 ° C.
  • 21C is a diagram showing the output result of the current Ir with respect to the current IX of FIG. 20C at 27 ° C.
  • FIG. 22A is a diagram showing the output result of the current Ir with respect to the current IX of FIG. 20A at 85 ° C.
  • FIG. 22B is a diagram showing the output result of the current Ir with respect to the current IX of FIG. 20B at 85 ° C.
  • FIG. 22C is a diagram showing the output result of the current Ir with respect to the current IX of FIG. 20C at 85 ° C.
  • Table 1 shows ⁇ / ⁇ and bit precision ( ⁇ ) in FIGS. 21A to 21C or 22A to 22C.
  • ⁇ represents the standard deviation and ⁇ represents the mean.
  • ⁇ / ⁇ indicates the variation of the data in each figure. Further, ⁇ in the table is obtained by converting ⁇ / ⁇ into bit accuracy. It can be said that the smaller the value of ⁇ / ⁇ or the larger the value of ⁇ , the higher the calculation accuracy.
  • (A) in Table 1 represents the configuration in FIG. 20A
  • (B) in the table represents the configuration in FIG. 20B (semiconductor device 10)
  • (C) in the table represents the configuration in FIG. 20C (semiconductor device 10B). Represents.
  • an arithmetic unit which is a device to which the semiconductor device of one aspect of the present invention can be applied, is prototyped and the output signal is measured according to the input signal.
  • the arithmetic unit can perform arithmetic with extremely excellent arithmetic efficiency, with the current consumption per cell being several nA.
  • the trial production was performed using a process combining a 60 nm CAAC-IGZO FET (a transistor containing an In-Ga-Zn oxide having a CAAC structure in the channel formation region) and a 55 nm Si CMOS.
  • the cell array was a block diagram shown in FIG. 23, and the cells were 512 rows and 512 columns.
  • the columns of the cell MC are grouped into a pair of two columns, the absolute value of the weight data W is stored in one column when the weight data is positive, and the weight data is stored in the other column. When it is negative, the absolute value of the weight data W is stored.
  • the differential current flowing through the paired wiring was read out as a digital value by the analog-digital conversion circuit ADC.
  • the W-driver corresponding to the circuit WCS of the second embodiment, the W-driver corresponding to the circuit WCS of the second embodiment, the X-driver corresponding to the circuit XCS of the second embodiment, and the second embodiment.
  • the G-driver corresponding to the circuit WSD of the above is illustrated.
  • the W-driver has a circuit (WDAC control logic) for controlling the writing of weight data (weight data), a current output type digital-to-analog conversion circuit (IDAC), and a switch controlled by a signal (write en.).
  • the X-driver has a circuit (XDAC control logic) and an IDAC that control the writing of input data (active data).
  • FIG. 23 illustrates an MCA corresponding to the cell array CA of the second embodiment, a cell DC corresponding to the reference cell 21, and a cell MC corresponding to the calculation cell 31.
  • each wiring has input data (x [0], x [i]), weight data (w [0] +, w [0] ⁇ ), and control signals (G [0], G []. i]) is given, and the current ( ⁇ W i0 + X i ), ⁇ W i0 ⁇ X i )) corresponding to the positive and negative weight data is output to the R-driver.
  • the R-driver has a switch controlled by a signal (read en.), A digital-to-analog conversion circuit (ADC) that operates according to a differential signal, and a circuit (ADC control logic) that controls an ADC, and has a product-sum operation.
  • ADC digital-to-analog conversion circuit
  • ADC control logic ADC control logic
  • FIG. 24A is a perspective view showing the structure of the CAAC-IGZO FET, Si CMOS, and capacitance (MIM) included in the arithmetic unit.
  • the CAAC-IGZO FET functions as a top gate electrode (TGE), a gate insulating layer (TGI) on the top gate electrode side, a back gate electrode (BGE), a gate insulating layer (BGI) on the back gate electrode side, and a source or drain. It has an electrode (S / D) and the like.
  • the transistor is a transistor having an S-channel structure.
  • FIG. 24B shows the top gate voltage-drain current characteristics (also referred to as Id-Vg characteristics) of a typical CAAC-IGZO FET side by side with the Id-Vg characteristics of a Si transistor (SiO, norm).
  • the CAAC-IGZO FET has a feature that the off-current (Off) is very small and the ratio of the on-current (Ion) to the off-current is large as compared with the Si transistor (SiO, norm). ..
  • FIG. 25 is a chip photograph of the prototype arithmetic unit.
  • the W-driver, the X-driver, the G-driver, and the R-driver are arranged around the memory cell array.
  • the chip size is 4 mm ⁇ 4 mm.
  • FIG. 26A is a graph showing changes in the current Iy output from the cell MC in response to changes in the input data when the current Iw according to the weight data is changed by 0.05 nA from 0 to 0.5 nA.
  • the horizontal axis is the current Ix according to the input data
  • the vertical axis is the current Iy.
  • the current output from the cell MC increased proportionally with the change of the input data and the weight data.
  • the value of the correlation coefficient r was 0.999, which was good.
  • FIG. 26B is a graph showing the change of the current Iy according to the change of the weight data when the current Ix corresponding to the input data is changed by 0.05 nA from 0 to 0.5 nA.
  • the horizontal axis is the current Iw according to the weight data
  • the vertical axis is the current Iy.
  • the current output from the cell MC increased proportionally with the change of the weight data and the input data.
  • the value of the correlation coefficient r was as good as 0.997.
  • FIG. 27A is a graph for observing the influence of variation between cell MCs.
  • the horizontal axis is the current Iy output from the cell MC when the current Ix corresponding to the input data is 0.5 nA, and the current Iw corresponding to the weight data is 0.05 nA from 0 to 0.4 nA.
  • CDF cumulative distribution function
  • FIG. 27B is a graph for observing the holding characteristics of the potential held by passing the current Iw according to the weight data in the cell MC.
  • the holding time (Time) is taken as the horizontal axis
  • the current Ix corresponding to the input data is 0.5 nA
  • the current Iw corresponding to the weight data is changed by 0.1 nA from 0 to 0.4 nA.
  • It is a graph which shows the change of Iy. As shown in FIG. 27B, the results were particularly good in the range where the current corresponding to the weight data was small.
  • FIG. 28 is a pie chart showing a meeting of power consumption of each circuit in the prototype arithmetic unit. As shown in FIG. 28, the control circuit (Control logic) occupies 66%, the R-driver is 27%, the X-driver is 4%, and the power consumption ratio in the memory array (MC-Array) is 3%. It became a small one.
  • FIG. 29 is a graph showing simulation results when 3 ⁇ in the distribution of the threshold voltage of the OS transistor is 0.1V, 0.3V, and 0.5V. The smaller 3 ⁇ is, the smaller the variation in the threshold voltage of the OS transistor is.
  • the current Ix corresponding to the input data is 1.0 nA
  • the current Iw corresponding to the weight data is 1.0 nA
  • the output current Iy is 1.0 nA. Even if repeated, the closer the current Iy is to 1.0 nA, the better the result.
  • the current Iy which is the output current, becomes a constant value, and good results are obtained.
  • each embodiment can be made into one aspect of the present invention by appropriately combining with other embodiments or configurations shown in Examples. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined.
  • the content described in one embodiment is another content (may be a part of the content) described in the embodiment, and / or one or more. It can be applied, combined, or replaced with respect to the content described in another embodiment (may be a part of the content).
  • figure (which may be a part) described in one embodiment is another part of the figure, another figure (which may be a part) described in the embodiment, and / or one or more.
  • figures (which may be a part) described in another embodiment of the above more figures can be formed.
  • the components are classified by function and shown as blocks independent of each other.
  • it is difficult to separate the components for each function and there may be a case where a plurality of functions are involved in one circuit, or a case where one function is involved across a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately paraphrased according to the situation.
  • the size, the thickness of the layer, or the area is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to that scale. It should be noted that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in the signal, voltage, or current due to noise, or variations in the signal, voltage, or current due to timing deviation.
  • Electrode and “wiring” do not functionally limit these components.
  • an “electrode” may be used as part of a “wiring” and vice versa.
  • the terms such as “electrode” or “wiring” include the case where a plurality of “electrodes” or “wiring” are integrally formed.
  • a node can be paraphrased as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on a circuit configuration or a device structure.
  • terminals, wiring, etc. can be paraphrased as nodes.
  • voltage and potential can be paraphrased as appropriate.
  • the voltage is a potential difference from a reference potential.
  • the reference potential is a ground voltage (ground voltage)
  • the voltage can be paraphrased as a potential.
  • the ground potential does not always mean 0V.
  • the potential is relative, and the potential given to the wiring or the like may be changed depending on the reference potential.
  • the terms “high level potential” and “low level potential” do not mean a specific potential.
  • the high level potentials provided by both wirings do not have to be equal to each other.
  • the low-level potentials provided by both wirings do not have to be equal to each other. ..
  • the "current” is a charge transfer phenomenon (electrical conduction).
  • the description “electrical conduction of a positively charged body is occurring” means “electrical conduction of a negatively charged body in the opposite direction”. Is happening. " Therefore, in the present specification and the like, “current” refers to a charge transfer phenomenon (electrical conduction) associated with carrier transfer, unless otherwise specified.
  • the carrier here include electrons, holes, anions, cations, complex ions, and the like, and the carriers differ depending on the system in which the current flows (for example, semiconductor, metal, electrolyte, in vacuum, etc.).
  • the "current direction” in wiring or the like is the direction in which the carrier that becomes a positive charge moves, and is described as a positive current.
  • the direction in which the carrier, which becomes a negative charge, moves is opposite to the direction of the current, and is represented by a negative current. Therefore, in the present specification and the like, if there is no disclaimer regarding the positive or negative current (or the direction of the current), the description such as “current flows from element A to element B” means “current flows from element B to element A”. Can be rephrased as. Further, the description such as “a current is input to the element A” can be rephrased as "a current is output from the element A” or the like.
  • a and B are connected means that A and B are electrically connected.
  • the fact that A and B are electrically connected refers to an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) between A and B. ) Is present, it means a connection capable of transmitting an electric signal between A and B.
  • the case where A and B are electrically connected includes the case where A and B are directly connected.
  • the fact that A and B are directly connected means that the electric signal between A and B is transmitted between A and B via wiring (or an electrode) or the like without going through the object.
  • a possible connection is a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.
  • a switch is a switch that is in a conducting state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows.
  • the switch means a switch having a function of selecting and switching a path through which a current flows.
  • the channel length means, for example, in the top view of a transistor, a region or a channel where a semiconductor (or a part where a current flows in the semiconductor when the transistor is on) and a gate overlap is formed.
  • the distance between the source and the drain in the area means, for example, in the top view of a transistor, a region or a channel where a semiconductor (or a part where a current flows in the semiconductor when the transistor is on) and a gate overlap is formed. The distance between the source and the drain in the area.
  • the channel width is a source in, for example, a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap, or a region where a channel is formed.

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