JP7724221B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP7724221B2
JP7724221B2 JP2022539784A JP2022539784A JP7724221B2 JP 7724221 B2 JP7724221 B2 JP 7724221B2 JP 2022539784 A JP2022539784 A JP 2022539784A JP 2022539784 A JP2022539784 A JP 2022539784A JP 7724221 B2 JP7724221 B2 JP 7724221B2
Authority
JP
Japan
Prior art keywords
transistor
wiring
current
potential
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022539784A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2022023866A1 (https=
JPWO2022023866A5 (https=
Inventor
宏充 郷戸
一樹 津田
義元 黒川
智 大下
卓郎 金村
英史 力丸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of JPWO2022023866A1 publication Critical patent/JPWO2022023866A1/ja
Publication of JPWO2022023866A5 publication Critical patent/JPWO2022023866A5/ja
Priority to JP2025129917A priority Critical patent/JP2025159013A/ja
Application granted granted Critical
Publication of JP7724221B2 publication Critical patent/JP7724221B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Physics & Mathematics (AREA)
  • Molecular Biology (AREA)
  • Computer Hardware Design (AREA)
  • Neurology (AREA)
  • General Health & Medical Sciences (AREA)
  • Biophysics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computational Linguistics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Software Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Computing Systems (AREA)
  • Artificial Intelligence (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Dram (AREA)
JP2022539784A 2020-07-31 2021-07-19 半導体装置 Active JP7724221B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025129917A JP2025159013A (ja) 2020-07-31 2025-08-04 半導体装置

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP2020129876 2020-07-31
JP2020129876 2020-07-31
JP2021017030 2021-02-05
JP2021017030 2021-02-05
JP2021107848 2021-06-29
JP2021107848 2021-06-29
PCT/IB2021/056483 WO2022023866A1 (ja) 2020-07-31 2021-07-19 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025129917A Division JP2025159013A (ja) 2020-07-31 2025-08-04 半導体装置

Publications (3)

Publication Number Publication Date
JPWO2022023866A1 JPWO2022023866A1 (https=) 2022-02-03
JPWO2022023866A5 JPWO2022023866A5 (https=) 2024-07-08
JP7724221B2 true JP7724221B2 (ja) 2025-08-15

Family

ID=80036203

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2022539784A Active JP7724221B2 (ja) 2020-07-31 2021-07-19 半導体装置
JP2025129917A Pending JP2025159013A (ja) 2020-07-31 2025-08-04 半導体装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2025129917A Pending JP2025159013A (ja) 2020-07-31 2025-08-04 半導体装置

Country Status (5)

Country Link
US (1) US20230284429A1 (https=)
JP (2) JP7724221B2 (https=)
KR (1) KR20230043882A (https=)
CN (1) CN116157911A (https=)
WO (1) WO2022023866A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230047392A (ko) 2020-08-03 2023-04-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 전자 기기

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012252766A (ja) 2010-09-02 2012-12-20 Semiconductor Energy Lab Co Ltd 半導体装置の駆動方法
US20150003165A1 (en) 2012-01-12 2015-01-01 Sharp Kabushiki Kaisha Semiconductor memory circuit and device
JP2018124977A (ja) 2016-10-12 2018-08-09 株式会社半導体エネルギー研究所 半導体装置、及び該半導体装置を有するシステム
WO2018211378A1 (ja) 2017-05-19 2018-11-22 株式会社半導体エネルギー研究所 半導体装置または記憶装置
WO2020079523A1 (ja) 2018-10-19 2020-04-23 株式会社半導体エネルギー研究所 半導体装置、及び電子機器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9842842B2 (en) * 2014-03-19 2017-12-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and semiconductor device and electronic device having the same
CN110637415B (zh) * 2017-05-31 2024-10-01 株式会社半导体能源研究所 比较电路、半导体装置、电子构件以及电子设备
JP6956784B2 (ja) * 2017-06-08 2021-11-02 株式会社半導体エネルギー研究所 撮像装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012252766A (ja) 2010-09-02 2012-12-20 Semiconductor Energy Lab Co Ltd 半導体装置の駆動方法
US20150003165A1 (en) 2012-01-12 2015-01-01 Sharp Kabushiki Kaisha Semiconductor memory circuit and device
JP2018124977A (ja) 2016-10-12 2018-08-09 株式会社半導体エネルギー研究所 半導体装置、及び該半導体装置を有するシステム
WO2018211378A1 (ja) 2017-05-19 2018-11-22 株式会社半導体エネルギー研究所 半導体装置または記憶装置
WO2020079523A1 (ja) 2018-10-19 2020-04-23 株式会社半導体エネルギー研究所 半導体装置、及び電子機器

Also Published As

Publication number Publication date
WO2022023866A1 (ja) 2022-02-03
CN116157911A (zh) 2023-05-23
JPWO2022023866A1 (https=) 2022-02-03
JP2025159013A (ja) 2025-10-17
US20230284429A1 (en) 2023-09-07
KR20230043882A (ko) 2023-03-31

Similar Documents

Publication Publication Date Title
JP7854547B2 (ja) 半導体装置
JP7842280B2 (ja) 半導体装置及び電子機器
JP7811676B2 (ja) 半導体装置
JP2026075093A (ja) 半導体装置、電子機器
JP7397944B2 (ja) 半導体装置
CN113383342A (zh) 半导体装置及电子设备
JP7684946B2 (ja) 半導体装置
CN113614727A (zh) Ai系统及ai系统的工作方法
US20250174259A1 (en) Semiconductor device and electronic device
JP7799127B2 (ja) 有機ｅｌ表示装置
JP2025159013A (ja) 半導体装置
JP2025065240A (ja) 半導体装置
JP2025069341A (ja) 半導体装置
WO2023148580A1 (ja) 半導体装置の動作方法
WO2025181636A1 (ja) 半導体装置、演算装置及び電子機器
JP7651555B2 (ja) 半導体装置
CN120712570A (zh) 半导体装置及电子设备
WO2025114843A1 (ja) 乗算回路、演算回路及び電子機器
WO2025248410A1 (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20240628

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20240628

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20250507

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250619

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20250708

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20250804

R150 Certificate of patent or registration of utility model

Ref document number: 7724221

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150