WO2022021741A1 - 一种侧向结构雪崩光电探测器及其制备方法 - Google Patents

一种侧向结构雪崩光电探测器及其制备方法 Download PDF

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WO2022021741A1
WO2022021741A1 PCT/CN2020/136025 CN2020136025W WO2022021741A1 WO 2022021741 A1 WO2022021741 A1 WO 2022021741A1 CN 2020136025 W CN2020136025 W CN 2020136025W WO 2022021741 A1 WO2022021741 A1 WO 2022021741A1
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region
epitaxial growth
growth layer
semiconductor material
substrate
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French (fr)
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胡晓
肖希
陈代高
王磊
张宇光
李淼峰
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武汉光谷信息光电子创新中心有限公司
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Publication of WO2022021741A1 publication Critical patent/WO2022021741A1/zh

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Definitions

  • the present application relates to the technical field of photonic integrated chip detection, and in particular, to a lateral structure avalanche photodetector and a preparation method thereof.
  • Photodetector is one of the key optoelectronic devices in optical communication, optical interconnection and optoelectronic integration technology. It is widely used in various fields of military and national economy, and avalanche photodetector is subject to high responsivity and sensitivity. The market welcomes.
  • the current avalanche photodetectors have shortcomings such as unsatisfactory gain-bandwidth product and uneven distribution of electric field in the absorption region, so further improvement is needed.
  • the embodiments of the present application provide a lateral structure avalanche photodetector and a preparation method thereof in order to solve at least one problem existing in the background art.
  • An aspect of the embodiments of the present application provides an avalanche photodetector with a lateral structure, including:
  • the substrate includes a first semiconductor material region; an avalanche region of the avalanche photodetector is formed in the first semiconductor material region;
  • a first epitaxial growth layer is formed on the substrate by using a second semiconductor material different from the first semiconductor material; the first epitaxial growth layer is formed as an absorption region of the avalanche photodetector; the first epitaxial growth layer is The upper surface of the growth layer is a light absorption surface, and the light absorption surface protrudes from the upper surface of the first semiconductor material region; the lower surface of the first epitaxial growth layer is lower than the upper surface of the first semiconductor material region; The absorption region and the avalanche region are spaced apart along a first direction parallel to the plane of the substrate;
  • a second epitaxial growth layer is formed on the substrate using a first semiconductor material; the second epitaxial growth layer at least includes a first portion and a second epitaxial growth layer located on both sides of the first epitaxial growth layer along the first direction. Two parts, the first part and the second part respectively cover the two sidewalls of the first epitaxial growth layer protruding above the first semiconductor material region, the first part and the second part respectively formed as at least a portion of the first charge region and the second charge region;
  • the first charge region, the absorption region, the second charge region, and the avalanche region at least partially overlap in the first direction.
  • the substrate is a silicon-on-insulator substrate, and the first semiconductor material region is a region where a top silicon layer of the silicon-on-insulator substrate is located;
  • the lower surface of the first epitaxial growth layer is lower than the upper surface of the first semiconductor material region, which specifically includes: the bottom end of the first epitaxial growth layer is embedded in the top silicon layer.
  • the second epitaxial growth layer is located between the first semiconductor material region and the first epitaxial growth layer, and one side of the second epitaxial growth layer is connected to the second epitaxial growth layer.
  • the first semiconductor material region is in contact, and the other side is in contact with the sidewall of the first epitaxial growth layer.
  • the second epitaxial growth layer has P-type doping.
  • the first semiconductor material is silicon; the second semiconductor material is germanium.
  • the optical waveguide includes at least a first waveguide portion and a second waveguide portion; wherein,
  • the first waveguide portion is used for coupling an optical signal to the first epitaxial growth layer, the first waveguide portion includes a first end for inputting an optical signal, and is connected to the first end along a propagation direction of the optical signal. the second end opposite the end;
  • the second waveguide portion is arranged outside the second end along the propagation direction of the optical signal, and the second waveguide portion is formed as a distributed Bragg reflector structure.
  • the period width of the distributed Bragg reflector structure is 200 nm-500 nm; wherein, the duty ratio of the optical waveguide material is 30-70%.
  • first metal electrode and a second metal electrode both of which are arranged along a direction perpendicular to the plane of the substrate;
  • a first contact region and a second contact region with opposite doping types are also formed in the first semiconductor material region, and the first charge region, the absorption region, the second charge region and the avalanche region are located in the region.
  • the first direction is located between the first contact area and the second contact area; the first metal electrode and the second metal electrode are in contact with the first contact area and the second contact area, respectively district contact;
  • the distance between any one of the first metal electrode and the second metal electrode and the optical waveguide is greater than or equal to 500 nm.
  • Embodiments of the present application also provide a method for preparing a lateral structure avalanche photodetector, the method comprising the following steps:
  • a selective epitaxial growth process is performed to form a first epitaxial growth layer in the groove, and the material of the first epitaxial growth layer is a second semiconductor material different from the first semiconductor material; the first epitaxial growth layer is formed is the absorption region of the avalanche photodetector; the upper surface of the first epitaxial growth layer is a light absorption surface, and the light absorption surface protrudes from the upper surface of the first semiconductor material region;
  • the selective epitaxial growth process is performed again, and a second epitaxial growth layer is formed by using the first semiconductor material;
  • the second epitaxial growth layer at least comprises two sides of the first epitaxial growth layer along a first direction parallel to the plane of the substrate.
  • a first part and a second part, the first part and the second part respectively cover two sidewalls of the first epitaxial growth layer protruding above the first semiconductor material region;
  • the first semiconductor material region performing a selective doping process to form an avalanche region within the first semiconductor material region, forming the first portion and the second portion of the second epitaxially grown layer as a first charge region and a second charge region, respectively at least a portion of a charge region; the first charge region, the absorption region, the second charge region, and the avalanche region at least partially overlap along the first direction.
  • the substrate is a silicon-on-insulator substrate, and the first semiconductor material region is a region where a top silicon layer of the silicon-on-insulator substrate is located;
  • the performing an etching process on the first semiconductor material region specifically includes: forming a groove with a bottom end located in the top silicon layer.
  • a second epitaxial growth layer filling the groove and covering the sidewalls of the first epitaxial growth layer, the second epitaxial growth layer being located between the first semiconductor material region and the first epitaxial growth layer, One side of the second epitaxial growth layer is in contact with the first semiconductor material region, and the other side is in contact with the sidewall of the first epitaxial growth layer.
  • the performing the selective doping process includes: performing P-type doping on the second epitaxial growth layer.
  • the first semiconductor material is silicon; the second semiconductor material is germanium.
  • the method further includes:
  • optical waveguide extending above the first epitaxial growth layer and separated from the upper surface of the first epitaxial growth layer by a predetermined distance
  • the optical waveguide includes at least a first waveguide portion and a second waveguide portion; wherein,
  • the first waveguide portion is used for coupling an optical signal to the first epitaxial growth layer, the first waveguide portion includes a first end for inputting an optical signal, and is connected to the first end along a propagation direction of the optical signal. the second end opposite the end;
  • the second waveguide portion is arranged outside the second end along the propagation direction of the optical signal, and the second waveguide portion is formed as a distributed Bragg reflector structure.
  • the period width of the distributed Bragg reflector structure is 200 nm-500 nm; wherein, the duty ratio of the optical waveguide material is 30-70%.
  • the performing a selective doping process further includes: forming a first contact region and a second contact region with opposite doping types in the first semiconductor material region; the first charge region, the absorption region, the second charge region, and the avalanche region are located between the first contact region and the second contact region in the first direction;
  • the method further includes: forming a first metal electrode and a second metal electrode arranged perpendicular to the plane direction of the substrate; the first metal electrode and the second metal electrode are respectively connected to the first contact area and the second metal electrode. contacting the second contact area;
  • the distance between any one of the first metal electrode and the second metal electrode and the optical waveguide is greater than or equal to 500 nm.
  • the lateral structure avalanche photodetector and the manufacturing method thereof provided by the embodiments of the present application, wherein the lateral structure avalanche photodetector includes: a substrate, the substrate includes a first semiconductor material region; The avalanche region of the avalanche photodetector is formed in the first semiconductor material region; the first epitaxial growth layer is formed on the substrate using a second semiconductor material different from the first semiconductor material; the first epitaxial growth layer is formed on the substrate The layer is formed as the absorption region of the avalanche photodetector; the upper surface of the first epitaxial growth layer is a light absorption surface, and the light absorption surface protrudes from the upper surface of the first semiconductor material region; the first epitaxy The lower surface of the growth layer is lower than the upper surface of the first semiconductor material region; the absorption region and the avalanche region are spaced along a first direction parallel to the substrate plane; the second epitaxial growth layer adopts the first semiconductor material is formed on the substrate; the second epi
  • the embodiments of the present application not only set the lower surface of the first epitaxial growth layer to be lower than the upper surface of the first semiconductor material region, so as to realize the first charge region, the absorption region, and the second charge region
  • the avalanche region and the avalanche region at least partially overlap in the first direction, so that the electric field distribution in the absorption region is more uniform, the transport of photogenerated carriers is easy, and the gain bandwidth product is improved;
  • the upper surface (ie the light absorption surface) of the first epitaxial growth layer protrudes from the upper surface of the first semiconductor material region, and the first epitaxial growth layer protrudes above the first semiconductor material region.
  • the two sidewalls are covered by the second epitaxial growth layer, that is, covered by the first charge region and the second charge region, so that the first epitaxial growth layer absorbs the light signal at the upper surface, and is on the first side.
  • the electrical signal is transmitted at the upward sidewall, which is beneficial to the coupling of the optical signal and the pumping of photogenerated carriers; at the same time, the first charge region and the second charge region are formed by the second epitaxial growth layer, so that the The electric field strength can be adjusted independently, reducing the dark current of the avalanche photodetector.
  • FIG. 1a and FIG. 1b are respectively a structural cross-sectional view and a top view of a lateral structure avalanche photodetector provided in an embodiment of the present application;
  • 2a to 2e are structural cross-sectional views of different embodiments of the second epitaxial growth layer in the avalanche photodetector
  • FIG. 3 is a schematic flowchart of a method for fabricating a lateral structure avalanche photodetector according to an embodiment of the present application
  • 4a to 4i are cross-sectional views of the device structure in the manufacturing process of the lateral structure avalanche photodetector provided by the embodiment of the present application.
  • Silicon photonics technology is a new generation technology for the development and integration of optical devices based on silicon and silicon-based substrate materials (such as SiGe/Si, silicon-on-insulator, etc.) using existing complementary metal-oxide-semiconductor (CMOS) processes.
  • CMOS complementary metal-oxide-semiconductor
  • Silicon photonics technology combines the ultra-large-scale and ultra-high-precision manufacturing characteristics of integrated circuit technology with the advantages of ultra-high speed and ultra-low power consumption of photonic technology. It is a disruptive technology to deal with the failure of Moore's Law. This combination is enabled by the scalability of semiconductor wafer fabrication, thereby reducing costs.
  • the photodetector has the function of realizing the conversion of optical signals to electrical signals.
  • III-V semiconductor materials are more suitable for photodetectors, III-V semiconductor materials are incompatible with silicon technology and cannot be used with silicon. Effective monolithic integration is carried out; considering the compatibility of germanium material with CMOS process, a technology of using germanium material as a light absorbing layer material to form a germanium-silicon photodetector has been proposed in the art.
  • Silicon photonic integrated chips can use germanium-silicon materials compatible with CMOS technology to realize avalanche photoelectric detection. It uses silicon materials as optical waveguides and at the same time as avalanche gain regions, and germanium materials absorb photons.
  • the current avalanche photodetector structure has the following shortcomings: the electric field distribution in the absorption region of the avalanche photodetector is not uniform, resulting in a decrease in responsivity; the absorption region size is too large, which easily leads to an unsatisfactory gain-bandwidth product.
  • the silicon material acts as a waveguide for transmitting light on the one hand, and on the other hand, also Doped by P or N type in order to form an electric field to extract photogenerated carriers, the absorption region of germanium material is also doped by P or N type, and these dopings will cause optical absorption loss, thereby reducing the quantum efficiency of the detector.
  • An embodiment of the present application provides an avalanche photodetector with a lateral structure, including: a substrate, the substrate includes a first semiconductor material region; the avalanche photodetector is formed in the first semiconductor material region an avalanche region of the photodetector; a first epitaxial growth layer is formed on the substrate using a second semiconductor material different from the first semiconductor material; the first epitaxial growth layer is formed as an absorption region of the avalanche photodetector;
  • the upper surface of the first epitaxial growth layer is a light absorption surface, and the light absorption surface protrudes from the upper surface of the first semiconductor material region; the lower surface of the first epitaxial growth layer is lower than the first semiconductor material the upper surface of the region; the absorption region and the avalanche region are spaced along a first direction parallel to the plane of the substrate; a second epitaxial growth layer is formed on the substrate by using the first semiconductor material; the second The epitaxial growth layer at least includes a first part and
  • the two sidewalls above the first semiconductor material region, the first part and the second part are respectively formed as at least a part of the first charge region and the second charge region; the first charge region, the absorption The region, the second charge region, and the avalanche region at least partially overlap in the first direction.
  • the avalanche photodetector includes: a substrate including a region of a first semiconductor material.
  • the substrate may be an elemental semiconductor material substrate (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (for example, a silicon germanium (SiGe) substrate, etc.), Or silicon-on-insulator (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.
  • the embodiments of the present application are described by taking the substrate as an SOI substrate as an example, and the first semiconductor material region is the region where the top silicon layer 103 of the SOI substrate is located.
  • the substrate further includes a buried oxide layer 102 under the top silicon layer 103 and a bottom silicon layer 101 .
  • the buried oxide layer 102 is, for example, a silicon dioxide layer.
  • the bottom silicon layer 101 may have a thicker thickness than the top silicon layer 103 .
  • the first semiconductor material region is a partial region of the substrate close to the upper surface layer.
  • a multiplication region 185 of the avalanche photodetector is formed within the region of the first semiconductor material.
  • the multiplication region of the avalanche photodetector refers to a region where carrier multiplication occurs.
  • the absorption region of the avalanche photodetector can convert the incident optical signal into multiple electron-hole pairs, and these hole-electron pairs flow to the electrode under the action of the electric field to form a photocurrent; the multiplication region can absorb the absorption through the action of avalanche multiplication.
  • the photocurrent formed in the region is further amplified; and then the photocurrent is conducted through a pair of metal electrodes to realize photodetection.
  • the first semiconductor material is not strictly limited here.
  • the first semiconductor material is Si.
  • the multiplication region of the avalanche photodetector is a broad concept, which can be used as a general term for the region where carrier multiplication occurs; as a specific implementation manner, the multiplication region may include From the absorption region to the P+ doped region, the I-intrinsic region and the N+ doped region arranged in sequence in the direction away from the absorption region; wherein, the I-intrinsic region is specifically subjected to impact ionization to generate electron-hole pairs
  • the P+ doped region can also be called the charge region.
  • the region where impact ionization occurs and electron-hole pairs are generated is called the avalanche region; Instead, a general and narrow concept in the field is adopted.
  • the avalanche region may be specifically an I-intrinsic region.
  • the multiplication region 185 includes a second charge region 114 , a second I-intrinsic region (avalanche region) 115 and an N+ doped region 116 .
  • an avalanche region of the avalanche photodetector is formed in the first semiconductor material region (for details, please refer to the second I-intrinsic region 115 in FIG. 1a ).
  • the first epitaxial growth layer 120 is formed on the substrate using a second semiconductor material different from the first semiconductor material; the first epitaxial growth layer 120 is formed as the absorption region 180 of the avalanche photodetector.
  • the upper surface of the first epitaxial growth layer 120 is a light absorption surface, and the light absorption surface protrudes from the upper surface of the first semiconductor material region; that is, the upper surface of the first epitaxial growth layer 120 is higher than the The upper surface of the first semiconductor material region (refer to 103 in the figure).
  • the lower surface of the first epitaxial growth layer 120 is lower than the upper surface of the first semiconductor material region (refer to 103 in the figure); thus, the absorption region 180 and the multiplication region 185 are in the direction along the substrate plane at least partially overlap.
  • the substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; in the case of ignoring the flatness of the top and bottom surfaces, the direction perpendicular to the top and bottom surfaces of the substrate is defined as the second direction.
  • the second direction is also the stacking direction of each layer structure subsequently deposited on the substrate, or the height direction of the device.
  • the surface where the top surface and the bottom surface of the substrate are located, or strictly speaking, the central plane in the thickness direction of the substrate, is determined as the substrate plane; the direction parallel to the substrate plane is the direction along the substrate plane.
  • Two mutually intersecting first and third directions are defined in the plane direction of the substrate; for example, the first and third directions are two directions that are perpendicular to each other.
  • the first direction is the direction in which the absorption region and the multiplication region are arranged in sequence/the width direction of the device, or the direction of current movement; the third direction is the propagation direction of the optical signal.
  • the lateral structure avalanche photodetector refers to an avalanche photodetector that applies a voltage to the absorption region and the avalanche region based on a lateral electric field, thereby extracting photogenerated carriers and forming a current through the lateral electric field.
  • the "lateral direction" here may specifically refer to the first direction in the embodiments of the present application. In other words, in the first direction, the two ends of the absorption region and the avalanche region (specifically, the two ends of the first charge region, the absorption region, the second charge region and the avalanche region) terminal) to apply a voltage to realize photodetection.
  • the absorption region and the avalanche region are spaced apart along a first direction parallel to the plane of the substrate.
  • the lower surface of the first epitaxial growth layer is lower than the upper surface of the top silicon layer, so that the formed absorption region and the multiplication region at least partially intersect in the direction along the substrate plane
  • the absorption region and the avalanche region are formed to at least partially overlap in the direction along the plane of the substrate; that is, the plane of the absorption region and the avalanche region in the direction perpendicular to the plane of the substrate ( The projections in the plane) as determined by the second and third directions overlap at least partially.
  • the generated photocurrent can move in a linear direction (such as the first direction) substantially parallel to the substrate plane, so that the electric field distribution in the absorption region is more uniform, the transport of photogenerated carriers is facilitated, and the gain is improved Bandwidth product.
  • the absorption region 180 and the multiplication region 185 at least partially overlap in the direction along the plane of the substrate, including: the absorption region 180 and the multiplication region 185 in the third direction
  • the borders are aligned with each other and are approximately equal in width. Specifically, it includes: the boundaries of the absorption region 180 and the avalanche region along the third direction are aligned with each other and have approximately equal widths. In addition, it may also include: the width of the absorption area 180 along the third direction is smaller than the width of the avalanche area along the third direction.
  • the lower surface of the first epitaxial growth layer 120 is lower than the upper surface of the first semiconductor material region, which specifically includes: the bottom end of the first epitaxial growth layer 120 is embedded in the inside the top silicon layer 103 .
  • the first epitaxial growth layer 120 may be formed by epitaxial growth on a groove recessed in the top silicon layer 103 ; the bottom end of the first epitaxial growth layer 120 is higher than the top silicon layer 103
  • the lower surface of the first epitaxial growth layer 120 also has a part of the first semiconductor material (top silicon layer material), and the first epitaxial growth layer 120 is not in contact with the buried oxide layer 102 .
  • the upper surface of the first epitaxial growth layer 120 is higher than the upper surface of the first semiconductor material region (top silicon layer 103).
  • the material of the first epitaxial growth layer is germanium, for example, that is, the second semiconductor material is germanium.
  • the formed avalanche photodetector is a silicon germanium photodetector.
  • the light absorption surface of the absorption region is the upper surface of the first epitaxial growth layer (that is, the surface of the first epitaxial growth layer that is far from the substrate).
  • the upper surface of the first epitaxial growth layer 120 is used for absorbing optical signals, and the sidewalls (side surfaces or interfaces with the first semiconductor material) are used for transmitting electrical signals.
  • the size range of the first epitaxial growth layer (absorbing region) in the first direction is 150nm-1500nm
  • the size range in the second direction is 150nm-600nm
  • the size range in the third direction is 1 ⁇ m-20 ⁇ m.
  • the size difference between the upper and lower surfaces of the first epitaxial growth layer during the epitaxial growth process cannot be considered.
  • the second epitaxial growth layer 130 is formed on the substrate by using the first semiconductor material; the second epitaxial growth layer 130 at least includes a second epitaxial growth layer 130 located on both sides of the first epitaxial growth layer 120 along the first direction. A part and a second part, the first part and the second part respectively cover the two sidewalls of the first epitaxial growth layer 120 protruding above the first semiconductor material region, the first part and the second part respectively cover The second portion is formed as at least a portion of the first charge region 113 and the second charge region 114, respectively.
  • two charge regions are included on both sides of the absorption region, so that the electric field intensity in the absorption region can be independently adjusted, which is beneficial to reduce the dark current of the avalanche photodetector.
  • the first charge region and the second charge region are separately disposed on two sides of the absorption region and are not connected to each other.
  • the direction in which the first charge region, the absorption region and the second charge region are arranged in sequence is the transmission direction of the photocurrent, and the photocurrent flows through the second charge in sequence during transmission region, the absorption region and the first charge region.
  • the material of the first charge region and the second charge region may be a first semiconductor material; the first charge region and the second charge region have P-type doping, for example, a P+ doping region.
  • the first charge region and the second charge region are two P+ doped silicon charge regions located on two sides of the germanium absorption region, respectively.
  • ion implantation may be performed on the first charge region and the second charge region respectively according to the adjustment requirements of the electric field strength on both sides of the absorption region.
  • the ion doping concentrations of the first charge region and the second charge region are different.
  • the size of the first charge region and the second charge region in the first direction is in the range of 50 nm to 400 nm, and the size in the second direction is in the range of 100 nm to 500 nm (specifically, the size of the structure at the location and the doping range can be determined.
  • the impurity depth is jointly determined), and the size range in the third direction is 1 ⁇ m to 20 ⁇ m. Dimensions of the first charge region, the second charge region, and the first epitaxial growth layer in the third direction may be equal.
  • the upper surface of the second epitaxial growth layer 130 is at least partially coplanar with the upper surface of the first epitaxial growth layer 120 .
  • the first portion and the second portion of the second epitaxial growth layer 130 are formed as at least a portion of the first charge region 113 and the second charge region 114, respectively, and it should be understood that the first portion and the second portion
  • the first charge region 113 and the second charge region 114 are completely formed, respectively, or a part of the first charge region 113 and a part of the second charge region 114 are respectively formed.
  • the second epitaxial growth layer 130 is located between the first semiconductor material region and the first epitaxial growth layer 120, and one side of the second epitaxial growth layer 130 is connected to the first epitaxial growth layer 130.
  • a semiconductor material region is in contact, and the other side is in contact with the sidewall of the first epitaxial growth layer 120 .
  • the second epitaxial growth layer has P-type doping.
  • the upper surface of the second epitaxial growth layer is at least partially coplanar with the upper surface of the first epitaxial growth layer; the second epitaxial growth layer covers the sidewalls of the first epitaxial growth layer. Understandably, the upper surface of the second epitaxial growth layer is at least partially coplanar with the upper surface of the first epitaxial growth layer, which can be achieved by a planarization process; specifically, a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the second epitaxial growth layer covers the sidewall of the first epitaxial growth layer, specifically: the sidewall of the first epitaxial growth layer is completely covered by the second epitaxial growth layer; the first epitaxial growth layer No exposed sidewall area.
  • the material of the second epitaxial growth layer is the same as the material of the first semiconductor material region on the substrate. Therefore, the second epitaxial growth layer and the first semiconductor material region can be used as indistinguishable materials in the future. Material areas, the boundaries between the two may not be clearly demarcated.
  • Figures 2a to 2e show structural cross-sectional views of different embodiments of the second epitaxially grown layer in an avalanche photodetector.
  • the first charge region and the second charge region are shown with solid boundary lines, respectively, and the dashed line in the solid boundary line indicates the first charge region or the second charge region inside the first charge region or the second charge region.
  • the lower surface of the second epitaxial growth layer may be in contact with the top silicon layer, and the lower surface is substantially parallel to the upper surface of the top silicon layer; the upper surface of the second epitaxial growth layer may be coplanar with the upper surface of the first epitaxial growth layer; the sidewalls close to the first epitaxial growth layer are in contact with the first epitaxial growth layer (that is, the second epitaxial growth layer covers the sidewalls of the first epitaxial growth layer); A part of the sidewall away from the first epitaxial growth layer is in contact with the top silicon layer (dotted line in the figure), and the other part protrudes above the upper surface of the top silicon layer; the cross section of the second epitaxial growth layer has a pentagon shape.
  • the lower surface of the second epitaxial growth layer may be in contact with the top silicon layer, and the lower surface is substantially parallel to the upper surface of the top silicon layer; the upper surface of the second epitaxial growth layer may coplanar with the upper surface of the first epitaxial growth layer; the sidewalls close to the first epitaxial growth layer are in contact with the first epitaxial growth layer (that is, the second epitaxial growth layer covers the sidewalls of the first epitaxial growth layer); A part of the sidewall away from the first epitaxial growth layer is in contact with the top silicon layer (dotted line in the figure), and the other part protrudes above the upper surface of the top silicon layer; the second epitaxial growth layer also includes a part located on the top silicon layer part above.
  • the second epitaxial growth layer does not include a lower surface substantially parallel to the upper surface of the top silicon layer, and the lower half of the second epitaxial growth layer is interposed between the first epitaxial layers in an inverted triangle shape. between the growth layer and the top silicon layer; the second epitaxial growth layer also includes a portion above the top silicon layer.
  • the difference between the second epitaxial growth layer and the second epitaxial growth layer in the embodiment shown in FIG. 2c is that the second epitaxial growth layer in FIG.
  • the cross section of the second epitaxial growth layer has a quadrangular shape; the upper surface of the second epitaxial growth layer may be coplanar with the upper surface of the first epitaxial growth layer; close to the first epitaxial growth layer
  • the sidewall of the growth layer is in contact with the first epitaxial growth layer (that is, the second epitaxial growth layer covers the sidewall of the first epitaxial growth layer); a part of the sidewall away from the first epitaxial growth layer and the side of the top silicon layer
  • a portion of the top silicon layer and the second epitaxial growth layer are doped to form the charge region, so that the second epitaxial growth layer can be formed as the charge region (the first part and the second part are formed as part of the first charge region and the second charge region, respectively); in the embodiment shown in FIG. 2e, the second epitaxial growth layer is doped to forming the charge region so that the second epitaxial growth layer can be formed as the whole of the charge region (the first portion and the second portion are formed as the first charge region and the second charge region, respectively); the first A portion within the semiconductor material region in contact with the second epitaxial growth layer may be the avalanche region; the first epitaxial growth layer is formed as an absorption region.
  • the above embodiments can be implemented by adjusting the size and position of the mask during the formation of each structure.
  • a first contact region 111 and a second contact region 117 with opposite doping types are also formed in the first semiconductor material region (top silicon layer 103), the first charge region 113, the The absorption region 180 , the second charge region 114 and the avalanche region (refer to 115 in the drawing) are located between the first contact region 111 and the second contact region 117 in the first direction.
  • the first contact region 111 is, for example, a P++ contact region
  • the second contact region 117 is, for example, an N++ contact region.
  • a first I-intrinsic region 112 may also be included between the first contact region 111 and the first charge region 113 .
  • the first contact region 111 , the first I-intrinsic region 112 , and the first charge are sequentially formed along the first direction (ie, the moving direction of the photocurrent).
  • the absorption region 180 (the first epitaxial growth layer 120 ) is located between the first charge region 113 and the second charge region 114 .
  • the first I-intrinsic region 112 is located between the first contact region 111 and the first charge region 113; the second I-intrinsic region 115 is located between the second charge region 114 and the N+ doped region between the miscellaneous areas 116 .
  • the size of the first I-intrinsic region 112 and the second I-intrinsic region 115 in the first direction ranges from 60 nm to 600 nm; the size in the third direction may be equal to one of the following: the first charge region, the dimension of the second charge region or the first epitaxial growth layer in the third direction.
  • the doping concentration range of the P++ contact region and the N++ contact region is 1 ⁇ 10 20 /cm 3 to 5 ⁇ 10 20 /cm 3 , and the doping concentration of the P+ doping region and the N+ doping region The range is 2 ⁇ 10 17 /cm 3 to 5 ⁇ 10 18 /cm 3 , the concentration of the I-intrinsic region is less than or equal to 1 ⁇ 10 17 /cm 3 , and the doping concentration of the absorption region is less than or equal to 5 ⁇ 10 17 / cm 3 .
  • the absorption region may be an intrinsic region, or may be a lightly doped region.
  • Any one of the P++ contact region and the N++ contact region is ⁇ 1.5 ⁇ m from the absorption region in the first direction.
  • the first epitaxial growth layer absorbs light signals through the upper surface
  • the avalanche photodetector may further include a light signal located on the first epitaxial growth layer and connected to the first epitaxial growth layer.
  • the avalanche photodetector further includes: an optical waveguide 150 extending above the first epitaxial growth layer 120 and separated from the upper surface of the first epitaxial growth layer 120 by a predetermined distance set a distance; the optical waveguide 150 includes at least a first waveguide portion 151 and a second waveguide portion 152; wherein, the first waveguide portion 151 is used for coupling optical signals to the first epitaxial growth layer 120, and the first waveguide portion 151 A waveguide portion 151 includes a first end for inputting an optical signal, and a second end opposite to the first end along the propagation direction of the optical signal (the third direction in the figure); the second waveguide portion 152 is along the The propagation direction of the optical signal is arranged outside the second end, and the second waveguide portion 152 is formed as a distributed Bragg reflector structure.
  • an independent optical waveguide structure to transmit optical signals can avoid the absorption loss caused by simultaneous P or N-type doping by using a silicon slab waveguide; on the other hand, a distributed Bragg is formed through a part of the optical waveguide.
  • the reflector structure can improve the quantum efficiency of the detector without increasing the length of the active region.
  • the material of the optical waveguide may be silicon nitride, that is, the optical waveguide may be a silicon nitride optical waveguide. In some other embodiments, the material of the optical waveguide can also be silicon.
  • the period width of the distributed Bragg reflector structure is 200nm-500nm; wherein, the duty ratio of the optical waveguide material is 30-70%; the material of the optical waveguide is silicon nitride or In the silicon embodiment, the duty ratio of the silicon nitride material or the silicon material in the distributed Bragg reflector structure is 30-70%. As shown in Fig. 1b, within one period width ⁇ , 30-70% is the optical waveguide material, and the other 70-30% is other material different from the optical waveguide, such as silicon dioxide.
  • the predetermined distance between the optical waveguide 150 and the upper surface of the first epitaxial growth layer 120 ranges from 100 nm to 1000 nm.
  • the size of the first waveguide portion 151 in the first direction is 300 nm to 2000 nm, the size in the second direction is in the range of 80 nm to 800 nm, and the size in the third direction is in the range of 1 ⁇ m to 35 ⁇ m. Wherein, the size of the first waveguide portion 151 in the first direction should be larger than the size of the first epitaxial growth layer 120 in the first direction.
  • the vertical projection of the first end of the first waveguide portion 151 on the substrate may fall outside the range of the vertical projection of the first epitaxial growth layer 120 on the substrate;
  • the vertical projection of the second end on the substrate may fall outside the range of the vertical projection of the first epitaxial growth layer 120 on the substrate, or the vertical projection of the second end on the substrate may be the same as the vertical projection of the second end on the substrate.
  • the corresponding boundaries of the vertical projection of the first epitaxial growth layer 120 on the substrate are aligned.
  • the avalanche photodetector further includes: a first metal electrode 161 and a second metal electrode 162, the first metal electrode 161 and the second metal electrode 162 are both arranged in a direction perpendicular to the plane of the substrate; the A first contact region 111 and a second contact region 117 with opposite doping types are also formed in the first semiconductor material region, and the first metal electrode 161 and the second metal electrode 162 are respectively connected to the first contact region. 111 is in contact with the second contact area 117 .
  • the doping types of the first contact region 111 and the second contact region 117 are opposite, and accordingly, the electrical properties of the first metal electrode 161 and the second metal electrode 162 are opposite, that is, the two One is the positive electrode and the other is the negative electrode; thus in the first contact region 111, the first I-intrinsic region 112, the first charge region 113, the absorption region 180, the second charge region 114, the second I - applying a lateral electric field between the intrinsic region 115 , the N+ doped region 116 and the second contact region 117 .
  • the distance between any one of the first metal electrode 161 and the second metal electrode 162 and the optical waveguide 150 is greater than or equal to 500 nm. In this way, it is avoided that the first metal electrode 161 or the second metal electrode 162 absorbs the optical signal and generates heat energy to cause loss.
  • the avalanche photodetector may include: a silicon substrate (eg, bottom silicon layer 101 ), a silicon dioxide material region (eg, buried oxide layer 102 ), a silicon material region (eg, top silicon layer 103 ), a germanium material absorption region (such as the first epitaxial growth layer 120/absorbing region 180), the silicon nitride optical waveguide region (such as the optical waveguide 150), the input optical port, two metal electrode regions (such as the first metal electrode 161 and the second metal electrode 162); in,
  • the silicon material region includes: a P++ doped region (eg, the first contact region 111 ) connected to the first metal electrode 161 , a P+ doped charge region (eg, the first charge region 113 and the second charge region 114 ), a first charge region 113 and a second charge region 114 .
  • the silicon nitride optical waveguide region includes: a strip-shaped optical waveguide (eg, the first waveguide portion 151 ) and a distributed Bragg reflector (eg, the second waveguide portion 152 );
  • the germanium material absorption region is embedded in the P+ doped charge region
  • the strip-shaped optical waveguide in the silicon nitride optical waveguide region is located above the germanium material absorption region with a certain interval;
  • the two metal electrodes are respectively connected to the P++ doped region and the N++ doped region in the silicon material region to form a lateral electric field applied to the germanium material absorption region and the silicon material region.
  • the avalanche photodetector in this embodiment is a germanium-silicon embedded lateral (or "lateral") avalanche photo-detector, which benefits from the fact that the absorption region of germanium material is embedded in the region of silicon material and the The slow and high-efficiency coupling of germanium enables high-gain, large-bandwidth, and high-quantum-efficiency avalanche photodetection.
  • Embodiments of the present application also provide a method for fabricating a lateral structure avalanche photodetector; for details, please refer to FIG. 3 . As shown in the figure, the method includes the following steps:
  • Step 201 providing a substrate, the substrate including a first semiconductor material region
  • Step 202 performing an etching process on the first semiconductor material region to form a groove deep inside the first semiconductor material region
  • Step 203 performing a selective epitaxial growth process, forming a first epitaxial growth layer in the groove, and the material of the first epitaxial growth layer is a second semiconductor material different from the first semiconductor material;
  • the first epitaxial growth layer is formed as an absorption region of the avalanche photodetector; the upper surface of the first epitaxial growth layer is a light absorption surface, and the light absorption surface protrudes from the upper surface of the first semiconductor material region ;
  • Step 204 performing the selective epitaxial growth process again, and using the first semiconductor material to form a second epitaxial growth layer
  • the second epitaxial growth layer at least includes a first part and a second part located on both sides of the first epitaxial growth layer along a first direction parallel to the plane of the substrate, the first part and the second part respectively cover the two sidewalls of the first epitaxial growth layer protruding above the first semiconductor material region;
  • Step 205 performing a selective doping process to form an avalanche region in the first semiconductor material region, and forming the first portion and the second portion of the second epitaxial growth layer as first charge regions respectively and at least a portion of the second charge region;
  • the first charge region, the absorption region, the second charge region, and the avalanche region at least partially overlap along the first direction.
  • step 201 is performed.
  • a substrate is provided, the substrate including a region of a first semiconductor material.
  • a substrate is provided; the substrate may be an elemental semiconductor material substrate (eg, silicon (Si) substrate, germanium (Ge) substrate, etc.), a compound semiconductor material substrate (eg, germanium silicon ( SiGe) substrate, etc.), or silicon-on-insulator (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.
  • elemental semiconductor material substrate eg, silicon (Si) substrate, germanium (Ge) substrate, etc.
  • a compound semiconductor material substrate eg, germanium silicon ( SiGe) substrate, etc.
  • SOI silicon-on-insulator
  • GeOI germanium-on-insulator
  • the embodiments of the present application are described by taking the substrate as an SOI substrate as an example, and the first semiconductor material region is the region where the top silicon layer 103 of the SOI substrate is located.
  • the substrate further includes a buried oxide layer 102 under the top silicon layer 103 and a bottom silicon layer 101 .
  • the buried oxide layer 102 is, for example, a silicon dioxide layer.
  • the bottom silicon layer 101 may have a thicker thickness than the top silicon layer 103 .
  • the substrate is an elemental semiconductor material substrate
  • the first semiconductor material region is a partial region of the substrate close to the upper surface layer.
  • step 202 is performed.
  • An etching process is performed on the first region of semiconductor material to form a recess deep inside the first region of semiconductor material.
  • the performing an etching process on the first semiconductor material region specifically includes: forming a bottom end located on the top silicon layer grooves in 103.
  • the lower surface of the groove may be higher than the lower surface of the top silicon layer 103 so that the buried oxide layer 102 is not exposed.
  • the regions that need to be etched to form grooves can be defined by patterning, and then the etching process can be performed; specifically, processes such as photolithography or electron beam exposure and etching (such as inductive plasma etching) can be used , removing a certain thickness of silicon, thereby forming the groove.
  • processes such as photolithography or electron beam exposure and etching (such as inductive plasma etching) can be used , removing a certain thickness of silicon, thereby forming the groove.
  • step 203 is performed.
  • a selective epitaxial growth process is performed to form a first epitaxial growth layer in the groove, and the material of the first epitaxial growth layer is a second semiconductor material different from the first semiconductor material.
  • a first epitaxial growth layer 120 is formed on the top silicon layer 103 exposed by the groove, and the material of the first epitaxial growth layer 120 is a second semiconductor material different from the first semiconductor material.
  • the second semiconductor material is germanium
  • a high-quality polycrystalline germanium material can be selectively grown in the groove region by a process such as molecular beam epitaxy.
  • the lower surface of the first epitaxial growth layer covers only a part of the lower surface of the groove, or covers the recess. the entire area of the lower surface of the groove.
  • the forming of the first epitaxial growth layer 120 includes: forming a first epitaxial growth layer 120 with an upper surface higher than the upper surface of the first semiconductor material region (refer to 103 in the figure).
  • a step of planarizing the upper surface of the second semiconductor material may also be included, which may be specifically performed by a CMP process, so that the first epitaxial growth layer has a substantially flat upper surface.
  • step 204 is performed.
  • the selective epitaxial growth process is performed again to form a second epitaxial growth layer using the first semiconductor material.
  • the first epitaxial growth layer 120 does not fill the groove; the selective epitaxial growth process is performed again, and the groove and the first epitaxial growth layer 120 are formed in the groove and the first epitaxial growth layer 120.
  • a first semiconductor material such as polysilicon material, is selectively grown thereon to form a second epitaxial growth layer 130 filling the groove and covering the sidewalls of the first epitaxial growth layer 120 .
  • the second epitaxial growth layer 130 may firstly cover the entire first epitaxial growth layer 120 .
  • the second epitaxial growth layer is entirely located in the groove, or partially located in the groove and partially located in the groove. on the upper surface of the first region of semiconductor material. And, corresponding to the first epitaxial growth layer in the groove, only covers a part of the lower surface of the groove, or covers the entire area of the lower surface of the groove; the second epitaxial growth layer
  • the lower surface of the layer may be in contact with the upper surface and the side surfaces of the first semiconductor material region exposed by the groove, or only the side surface of the first semiconductor material region exposed by the groove.
  • a planarization process is performed to make the upper surface of the second epitaxial growth layer 130 at least partially coplanar with the upper surface of the first epitaxial growth layer 120 .
  • the CMP process can be used to process the polysilicon material above the germanium material, and only the polysilicon on both sides of the germanium material is retained.
  • the second epitaxial growth layer Since the material of the second epitaxial growth layer is the same as the material of the first semiconductor material region on the substrate, the second epitaxial growth layer and the first semiconductor material region can be treated as no difference in the subsequent material area, the boundaries between the two may not be clearly demarcated.
  • the second epitaxial growth layer at least includes a first part and a second part located on both sides of the first epitaxial growth layer along the first direction, and the first part and the second part respectively cover the first part
  • the two sidewalls of the epitaxial growth layer protrude above the first semiconductor material region.
  • the second epitaxial growth layer is located between the first semiconductor material region and the first epitaxial growth layer, one side of the second epitaxial growth layer is in contact with the first semiconductor material region, and the other side is in contact with the first semiconductor material region.
  • the sidewalls of the first epitaxial growth layer are in contact.
  • step 205 is performed. performing a selective doping process to form an avalanche region within the first semiconductor material region, forming the first portion and the second portion of the second epitaxially grown layer as a first charge region and a second charge region, respectively at least a portion of the charge region.
  • the performing the selective doping process may include: performing P-type doping on the second epitaxial growth layer 130 .
  • the P-type doping may also be partially performed in the first semiconductor material region with the second epitaxy on the partial area where the growth layer 130 is in contact.
  • a P+ doped charge region immediately adjacent to the absorption region is formed.
  • the charge region may be part of the multiplication region.
  • the P-type doping may be performed on both sides of the absorption region, so that the two sides of the absorption region include two charge regions; that is, the selective doping process is performed, It may further include: forming a first charge region 113 and a second charge region 114 on both sides of the first epitaxial growth layer 120 respectively.
  • the performing the selective doping process may further include: forming a first contact region 111 and a second contact region 117 with opposite doping types in the first semiconductor material region; the first charge region 113, The absorption region 180 , the second charge region 114 and the avalanche region (refer to 115 in the drawing) are located between the first contact region 111 and the second contact region 117 in the first direction.
  • the first contact region 111 is, for example, a P++ contact region
  • the second contact region 117 is, for example, an N++ contact region.
  • the performing the selective doping process may further include: between the first epitaxial growth layer 120 and the second contact region 117 , specifically the charge region (the second charge region 114 ) and the second contact region 117 . Between the two contact regions 117, an N+ contact region 116 is formed.
  • the P+ doped region (charge region), the I-intrinsic region (avalanche region) and the N+ doped region sequentially arranged in the direction of layer 120) constitute the multiplication region.
  • a first I-intrinsic region 112 may be further included between the first contact region 111 and the first charge region 113 .
  • the first contact region 111 , the first I-intrinsic region 112 , the first charge region 113 and the second charge region 114 are sequentially formed , a second I-intrinsic region 115 , an N+ doped region 116 and a second contact region 117 .
  • the absorption region 180 (the first epitaxial growth layer 120 ) is located between the first charge region 113 and the second charge region 114 .
  • the first I-intrinsic region 112 is located between the first contact region 111 and the first charge region 113; the second I-intrinsic region 115 is located between the second charge region 114 and the N+ doped region between the miscellaneous areas 116 .
  • a filling layer 140 is formed on the substrate, specifically on the first semiconductor material region and the first epitaxial growth layer and the second epitaxial growth layer.
  • the material of the filling layer 140 may include silicon dioxide.
  • the filling layer 140 may be formed by depositing a certain thickness of silicon dioxide material and performing a planarization process.
  • the method further includes: forming an optical waveguide, the optical waveguide extending above the first epitaxial growth layer and separated from the upper surface of the first epitaxial growth layer by a preset distance; the optical waveguide It includes at least a first waveguide portion and a second waveguide portion; wherein the first waveguide portion is used for coupling an optical signal to the first epitaxial growth layer, and the first waveguide portion includes a first end for inputting an optical signal , and a second end opposite to the first end along the propagation direction of the optical signal; the second waveguide portion is arranged outside the second end along the propagation direction of the optical signal, the second waveguide portion Formed as a distributed Bragg reflector structure.
  • the optical waveguide 150 is formed.
  • a patterned mask layer (not shown in the figure) can be used to define a region where an optical waveguide needs to be formed on the filling layer 140 above the first epitaxial growth layer 120; grow light in the region
  • the waveguide material is, for example, deposited silicon nitride material or grown silicon material to form the optical waveguide 150 .
  • the specific structure of the formed optical waveguide 150 can be referred to FIG. 1b.
  • the period width of the distributed Bragg reflector structure is 200nm-500nm; the duty ratio of the optical waveguide material is 30-70%.
  • the method further includes: forming a first metal electrode 161 and a second metal electrode 162 arranged perpendicular to the plane direction of the substrate (ie, the second direction); the first metal electrode 161 and the second metal electrode 162 Contact with the first contact area 111 and the second contact area 117 respectively; wherein, the distance between any one of the first metal electrode 161 and the second metal electrode 162 and the optical waveguide 150 Greater than or equal to 500nm.
  • the above two metal electrodes can be fabricated by using processes such as photolithography and inductive plasma etching to open windows, and magnetron sputtering to deposit metal materials.
  • the upper surfaces of the first metal electrode 161 and the second metal electrode 162 should be higher than the upper surface of the optical waveguide 150 .
  • it also includes forming a filling layer on the optical waveguide 150, and using photolithography and etching (eg, inductive plasma etching) and other processes to form and expose the first contact region 111 and the second contact in the filling layer.
  • a window of the region 117 ; electrode material eg, a metal material deposited by magnetron sputtering is filled in the window to form the first metal electrode 161 and the second metal electrode 162 .
  • the avalanche photodetectors provided in the embodiments of the present application can already solve the technical problems to be solved by the present application by combining their technical features; therefore, the avalanche photodetectors provided by the embodiments of the present application can be affected by
  • the avalanche photodetector prepared by the preparation method of the avalanche photodetector provided by the embodiment of the present application is limited, and any avalanche photodetector prepared by the preparation method of the avalanche photodetector structure provided by the embodiment of the present application is within the scope of protection of the present application. .

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Abstract

一种侧向结构雪崩光电探测器及其制备方法，其中，侧向结构雪崩光电探测器包括：衬底，包括一第一半导体材料区（103）；在第一半导体材料区（103）内形成有雪崩区（115）；第一外延生长层（120），形成为吸收区（180）；第一外延生长层（120）的上表面为吸光面且凸出于第一半导体材料区（103）的上表面；第一外延生长层（120）的下表面低于第一半导体材料区（103）的上表面；第二外延生长层（130），至少包括沿第一方向上位于第一外延生长层（120）两侧的第一部分和第二部分，第一部分和第二部分分别覆盖第一外延生长层（120）的凸出于第一半导体材料区（103）之上的两侧壁，第一部分和第二部分分别形成为第一电荷区（113）和第二电荷区（114）的至少一部分；第一电荷区（113）、吸收区（180）、第二电荷区（114）和雪崩区（115）在第一方向上至少部分交叠。

Description

一种侧向结构雪崩光电探测器及其制备方法
相关申请的交叉引用
本申请基于申请号为202010753430.6、申请日为2020年7月30日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及光子集成芯片探测技术领域，尤其涉及一种侧向结构雪崩光电探测器及其制备方法。
背景技术
光电探测器是光通信、光互连和光电集成技术中关键的光电器件之一，目前在军事和国民经济的各个领域都有广泛的用途，而雪崩光电探测器又以高响应度和灵敏度受到市场欢迎。
然而，目前的雪崩光电探测器具有增益带宽积不理想且吸收区内电场分布不均匀等缺点，因此有待进一步的改进。
发明内容
有鉴于此，本申请实施例为解决背景技术中存在的至少一个问题而提供一种侧向结构雪崩光电探测器及其制备方法。
为达到上述目的，本申请实施例的技术方案是这样实现的：
本申请实施例一方面提供了一种侧向结构雪崩光电探测器，包括：
衬底，所述衬底包括一第一半导体材料区；在所述第一半导体材料区内形成有所述雪崩光电探测器的雪崩区；
第一外延生长层，采用不同于第一半导体材料的第二半导体材料形成在所述衬底上；所述第一外延生长层形成为所述雪崩光电探测器的吸收区；所述第一外延生长层的上表面为吸光面，所述吸光面凸出于所述第一半导体材料区的上表面；所述第一外延生长层的下表面低于所述第一半导体材料区的上表面；所述吸收区和所述雪崩区沿平行衬底平面的第一方向上间隔设置；
第二外延生长层，采用第一半导体材料形成在所述衬底上；所述第二外延生长层至少包括沿所述第一方向上位于所述第一外延生长层两侧的第一部分和第二部分，所述第一部分和所述第二部分分别覆盖所述第一外延生长层的凸出于所述第一半导体材料区之上的两侧壁，所述第一部分和所述第二部分分别形成为第一电荷区和第二电荷区的至少一部分；
所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在所述第一方向上至少部分交叠。
在本申请的一种可选实施例中，所述衬底为绝缘体上硅衬底，所述第一半导体材料区为所述绝缘体上硅衬底的顶硅层所在的区域；
所述第一外延生长层的下表面低于所述第一半导体材料区的上表面，具体包括：所述第一外延生长层的底端嵌于所述顶硅层内。
在本申请的一种可选实施例中，所述第二外延生长层位于所述第一半导体材料区与所述第一外延生长层之间，所述第二外延生长层的一侧与所述第一半导体材料区接触，另一侧与所述第一外延生长层的侧壁接触。
在本申请的一种可选实施例中，所述第二外延生长层内具有P型掺杂。
在本申请的一种可选实施例中，所述第一半导体材料为硅；所述第二半导体材料为锗。
在本申请的一种可选实施例中，还包括：
光波导，在所述第一外延生长层上方延伸，并与所述第一外延生长层 的上表面相隔一预设距离；
所述光波导至少包括第一波导部和第二波导部；其中，
所述第一波导部用于将光信号耦合至所述第一外延生长层，所述第一波导部包括供光信号输入的第一端，以及沿光信号的传播方向上与所述第一端相对的第二端；
所述第二波导部沿所述光信号的传播方向布置在所述第二端的外侧，所述第二波导部形成为分布式布拉格反射器结构。
在本申请的一种可选实施例中，所述分布式布拉格反射器结构的周期宽度为200nm～500nm；其中，光波导材料的占空比为30～70％。
在本申请的一种可选实施例中，还包括：
第一金属电极和第二金属电极，所述第一金属电极和所述第二金属电极均沿垂直所述衬底平面方向而设置；
所述第一半导体材料区内还形成有掺杂类型相反的第一接触区和第二接触区，所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在所述第一方向上位于所述第一接触区和所述第二接触区之间；所述第一金属电极和所述第二金属电极分别与所述第一接触区和所述第二接触区接触；
所述第一金属电极和所述第二金属电极中任意一者与所述光波导之间的距离大于等于500nm。
本申请实施例还提供了一种侧向结构雪崩光电探测器的制备方法，所述方法包括以下步骤：
提供衬底，所述衬底包括一第一半导体材料区；
在所述第一半导体材料区上执行刻蚀工艺，以形成一深入所述第一半导体材料区内部的凹槽；
执行选择性外延生长工艺，在所述凹槽内形成第一外延生长层，所述 第一外延生长层的材料为不同于第一半导体材料的第二半导体材料；所述第一外延生长层形成为所述雪崩光电探测器的吸收区；所述第一外延生长层的上表面为吸光面，所述吸光面凸出于所述第一半导体材料区的上表面；
再次执行选择性外延生长工艺，采用第一半导体材料形成第二外延生长层；所述第二外延生长层至少包括沿平行衬底平面的第一方向上位于所述第一外延生长层两侧的第一部分和第二部分，所述第一部分和所述第二部分分别覆盖所述第一外延生长层的凸出于所述第一半导体材料区之上的两侧壁；
执行选择性掺杂工艺，以在所述第一半导体材料区内形成雪崩区，将所述第二外延生长层的所述第一部分和所述第二部分分别形成为第一电荷区和第二电荷区的至少一部分；所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在沿所述第一方向上至少部分交叠。
在本申请的一种可选实施例中，所述衬底为绝缘体上硅衬底，所述第一半导体材料区为所述绝缘体上硅衬底的顶硅层所在的区域；
所述在所述第一半导体材料区上执行刻蚀工艺，具体包括：形成一底端位于所述顶硅层内的凹槽。
在本申请的一种可选实施例中，所述第一外延生长层未填满所述凹槽；形成所述第二外延生长层，包括：
形成填充所述凹槽并覆盖所述第一外延生长层侧壁的第二外延生长层，所述第二外延生长层位于所述第一半导体材料区与所述第一外延生长层之间，所述第二外延生长层的一侧与所述第一半导体材料区接触，另一侧与所述第一外延生长层的侧壁接触。
在本申请的一种可选实施例中，所述执行选择性掺杂工艺，包括：对所述第二外延生长层进行P型掺杂。
在本申请的一种可选实施例中，所述第一半导体材料为硅；所述第二 半导体材料为锗。
在本申请的一种可选实施例中，所述方法还包括：
形成光波导，所述光波导在所述第一外延生长层上方延伸，并与所述第一外延生长层的上表面相隔一预设距离；
所述光波导至少包括第一波导部和第二波导部；其中，
所述第一波导部用于将光信号耦合至所述第一外延生长层，所述第一波导部包括供光信号输入的第一端，以及沿光信号的传播方向上与所述第一端相对的第二端；
所述第二波导部沿所述光信号的传播方向布置在所述第二端的外侧，所述第二波导部形成为分布式布拉格反射器结构。
在本申请的一种可选实施例中，所述分布式布拉格反射器结构的周期宽度为200nm～500nm；其中，光波导材料的占空比为30～70％。
在本申请的一种可选实施例中，所述执行选择性掺杂工艺，还包括：在所述第一半导体材料区内形成掺杂类型相反的第一接触区和第二接触区；所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在所述第一方向上位于所述第一接触区和所述第二接触区之间；
所述方法还包括：形成垂直所述衬底平面方向而设置的第一金属电极和第二金属电极；所述第一金属电极和所述第二金属电极分别与所述第一接触区和所述第二接触区接触；
其中，所述第一金属电极和所述第二金属电极中任意一者与所述光波导之间的距离大于等于500nm。
本申请实施例所提供的侧向结构雪崩光电探测器及其制备方法，其中，所述侧向结构雪崩光电探测器包括：衬底，所述衬底包括一第一半导体材料区；在所述第一半导体材料区内形成有所述雪崩光电探测器的雪崩区；第一外延生长层，采用不同于第一半导体材料的第二半导体材料形成在所 述衬底上；所述第一外延生长层形成为所述雪崩光电探测器的吸收区；所述第一外延生长层的上表面为吸光面，所述吸光面凸出于所述第一半导体材料区的上表面；所述第一外延生长层的下表面低于所述第一半导体材料区的上表面；所述吸收区和所述雪崩区沿平行衬底平面的第一方向上间隔设置；第二外延生长层，采用第一半导体材料形成在所述衬底上；所述第二外延生长层至少包括沿所述第一方向上位于所述第一外延生长层两侧的第一部分和第二部分，所述第一部分和所述第二部分分别覆盖所述第一外延生长层的凸出于所述第一半导体材料区之上的两侧壁，所述第一部分和所述第二部分分别形成为第一电荷区和第二电荷区的至少一部分；所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在所述第一方向上至少部分交叠。如此，本申请实施例不仅通过将第一外延生长层设置为下表面低于所述第一半导体材料区的上表面，从而实现所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在所述第一方向上至少部分交叠，使得所述吸收区内的电场分布更加均匀，易于光生载流子的输运，有助于提高增益带宽积；而且，通过所述第一外延生长层的上表面(即吸光面)凸出于所述第一半导体材料区的上表面，所述第一外延生长层的凸出于所述第一半导体材料区之上的两侧壁被所述第二外延生长层覆盖，即被所述第一电荷区和所述第二电荷区覆盖，从而所述第一外延生长层在上表面处吸收光信号、在第一方向上的侧壁处传递电信号，有利于光信号的耦合同时有利于光生载流子的抽运；同时，通过第二外延生长层形成第一电荷区和第二电荷区，使得吸收区内的电场强度可以独立调节，降低了所述雪崩光电探测器的暗电流。
本申请实施例附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请实施例的实践了解到。
附图说明
图1a和图1b分别为本申请实施例提供的侧向结构雪崩光电探测器的结构剖视图和俯视图；
图2a至2e为雪崩光电探测器中第二外延生长层的不同实施方式的结构剖视图；
图3为本申请实施例提供的侧向结构雪崩光电探测器的制备方法的流程示意图；
图4a至4i为本申请实施例提供的侧向结构雪崩光电探测器的制备过程中的器件结构剖视图。
附图标记说明：
101-底硅层；102-埋氧层；103-顶硅层；
111-第一接触区；112-第一I-本征区；113-第一电荷区；114-第二电荷区；115-第二I-本征区；116-N+掺杂区；117-第二接触区；
120-第一外延生长层；
130-第二外延生长层；
140-填充层；
150-光波导；151-第一波导部；152-第二波导部；
161-第一金属电极；162-第二金属电极；
180-吸收区；185-倍增区。
具体实施方式
下面将参照附图更详细地描述本申请公开的示例性实施方式。虽然附图中显示了本申请的示例性实施方式，然而应当理解，可以以各种形式实现本申请，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本申请，并且能够将本申请实施例公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本申请实施例更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请实施例可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请实施例发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请实施例教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本申请实施例必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特 征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请实施例的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本申请实施例，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本申请实施例的技术方案。本申请的可选实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
硅光子技术是基于硅和硅基衬底材料(如SiGe/Si、绝缘体上硅等)，利用现有互补金属氧化物半导体(CMOS)工艺进行光器件开发和集成的新一代技术。硅光子技术结合了集成电路技术的超大规模、超高精度制造的特性和光子技术超高速率、超低功耗的优势，是应对摩尔定律失效的颠覆性技术。这种结合得力于半导体晶圆制造的可扩展性，因而能够降低成本。光电探测器作为硅光子架构的核心器件之一，具有实现光信号到电信号转换的功能。但晶体硅材料的能带结构决定其在光通信波段探测效率很低，虽然III-V族半导体材料更适合用于光电探测器，但是III-V族半导体材料与硅工艺不兼容，无法与硅进行有效的单片集成；考虑到锗材料与CMOS工艺的兼容性，本领域提出了采用锗材料作为光吸收层材料而形成锗硅光电探测器的技术。
硅光子集成芯片中可采用兼容CMOS工艺的锗硅材料实现雪崩光电探 测，它是利用硅材料作为光波导，同时作为雪崩增益区，锗材料吸收光子。
目前的雪崩光电探测器结构存在以下不足：雪崩光电探测器的吸收区电场分布不均匀，导致响应度降低；吸收区域尺寸过大，容易导致增益带宽积不理想。
此外，对于利用硅平板波导将光信号传导入结构内部、继而将携带信号的光耦合至锗层内的雪崩光电探测器结构，其中的硅材料一方面作为传输光的波导，另一方面还会被P或N型掺杂以便形成电场抽取光生载流子，锗材料吸收区也会被P或N型掺杂，而这些掺杂都会造成光吸收损耗，继而降低探测器量子效率。
基于此，提出了本申请实施例的以下技术方案。
本申请一实施例提供了一种侧向结构雪崩光电探测器，包括：衬底，所述衬底包括一第一半导体材料区；在所述第一半导体材料区内形成有所述雪崩光电探测器的雪崩区；第一外延生长层，采用不同于第一半导体材料的第二半导体材料形成在所述衬底上；所述第一外延生长层形成为所述雪崩光电探测器的吸收区；所述第一外延生长层的上表面为吸光面，所述吸光面凸出于所述第一半导体材料区的上表面；所述第一外延生长层的下表面低于所述第一半导体材料区的上表面；所述吸收区和所述雪崩区沿平行衬底平面的第一方向上间隔设置；第二外延生长层，采用第一半导体材料形成在所述衬底上；所述第二外延生长层至少包括沿所述第一方向上位于所述吸收区两侧的第一部分和第二部分，所述第一部分和所述第二部分分别覆盖所述第一外延生长层的凸出于所述第一半导体材料区之上的两侧壁，所述第一部分和所述第二部分分别形成为第一电荷区和第二电荷区的至少一部分；所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在所述第一方向上至少部分交叠。
下面，请具体参见图1a至1b。如图所示，所述雪崩光电探测器包括： 衬底，所述衬底包括一第一半导体材料区。
这里，所述衬底可以为单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)，或绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。本申请实施例以所述衬底为SOI衬底为例进行说明，所述第一半导体材料区为所述SOI衬底的顶硅层103所在的区域。所述衬底还包括位于所述顶硅层103下的埋氧层102以及底硅层101。所述埋氧层102例如为二氧化硅层。所述底硅层101与所述顶硅层103相比可以具有更厚的厚度。应当理解，图中为了使得各层结构均能被清晰示出，可能造成各层结构的尺寸比例关系与实际结构不符。
在所述衬底为单质半导体材料衬底的实施例中，所述第一半导体材料区为所述衬底的靠近上表面层的部分区域。
在所述第一半导体材料区内形成有所述雪崩光电探测器的倍增区185。这里，所述雪崩光电探测器的倍增区是指发生载流子倍增的区域。雪崩光电探测器的吸收区能够将入射的光信号转换成多个电子-空穴对，这些空穴-电子对在电场作用下流向电极从而形成光电流；倍增区能够通过雪崩倍增的作用将吸收区形成的光电流进一步放大；进而通过一对金属电极传导光电流，实现光电探测。
由于理论上，在倍增区中可采用任何半导体材料，因此这里并不对第一半导体材料进行严格限定。在所述衬底为单质Si衬底或为SOI衬底的实施例中，所述第一半导体材料为Si。
本申请实施例中，所述雪崩光电探测器的倍增区是一个广义上的概念，可以作为发生载流子倍增的区域的统称；作为一种具体的实施方式，所述倍增区可以包括从靠近所述吸收区到远离所述吸收区方向上依次布置的P+掺杂区、I-本征区以及N+掺杂区；其中，I-本征区是具体发生碰撞电离从而 产生电子-空穴对的区域，而P+掺杂区又可以称为电荷区。本申请实施例中为了与电荷区进行区分说明，因而将具体发生碰撞电离、产生电子-空穴对的区域称为雪崩区；应当理解，这并不与本领域中常用的术语名称相违背，而是采用了本领域中一种通用的狭义的概念。所述雪崩区可以具体为I-本征区。进一步参考图1a，所述倍增区185包括第二电荷区114、第二I-本征区(雪崩区)115以及N+掺杂区116。
如此，在本申请实施例中，在所述第一半导体材料区内形成有所述雪崩光电探测器的雪崩区(具体可以参考图1a中第二I-本征区115)。
第一外延生长层120，采用不同于第一半导体材料的第二半导体材料形成在所述衬底上；所述第一外延生长层120形成为所述雪崩光电探测器的吸收区180。所述第一外延生长层120的上表面为吸光面，所述吸光面凸出于所述第一半导体材料区的上表面；也即，所述第一外延生长层120的上表面高于所述第一半导体材料区(参考图中103)的上表面。所述第一外延生长层120的下表面低于所述第一半导体材料区(参考图中103)的上表面；如此，所述吸收区180和所述倍增区185在沿衬底平面方向上至少部分交叠。
这里，衬底可以包括处于正面的顶表面以及处于与正面相对的背面的底表面；在忽略顶表面和底表面的平整度的情况下，定义垂直衬底顶表面和底表面的方向为第二方向。第二方向也为后续在衬底上沉积各层结构的层叠方向，或称器件的高度方向。而衬底顶表面和底表面所在的面，或者严格意义上讲衬底厚度方向上的中心面，即确定为衬底平面；平行衬底平面的方向即为沿衬底平面方向。在所述衬底平面方向上定义两彼此相交的第一方向和第三方向；所述第一方向和所述第三方向例如为彼此垂直的两个方向。在本实施例中，所述第一方向为所述吸收区和所述倍增区依次布置的方向/器件宽度方向，或为电流移动的方向；所述第三方向为光信号的 传播方向。
应当理解，侧向结构雪崩光电探测器指的是基于侧向电场在吸收区和雪崩区上施加电压，从而通过侧向电场抽取光生载流子、形成电流的雪崩光电探测器。这里的“侧向”在本申请实施例中可以具体指所述第一方向。换言之，在所述第一方向上，所述吸收区和所述雪崩区的两端(具体为所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区的两端)施加电压，实现光电探测。
所述吸收区和所述雪崩区沿平行衬底平面的第一方向上间隔设置。
在本实施例中，所述第一外延生长层的下表面低于所述顶硅层的上表面，以使形成的所述吸收区和所述倍增区在沿衬底平面方向上至少部分交叠，并具体使得形成的所述吸收区和所述雪崩区在沿衬底平面方向上至少部分交叠；即所述吸收区和所述雪崩区在垂直所述衬底平面方向上的平面(如由第二方向和第三方向确定的平面)内的投影至少部分重叠。如此，产生的光电流可以沿大致平行衬底平面的直线方向(如第一方向)移动，使得所述吸收区内的电场分布更加均匀，易于光生载流子的输运，有助于提高增益带宽积。
其中，如图1b所示，所述吸收区180和所述倍增区185在沿衬底平面方向上至少部分交叠，包括：所述吸收区180和所述倍增区185在沿第三方向上的边界彼此对齐、宽度大致相等。具体地，包括：吸收区180和所述雪崩区在沿第三方向上的边界彼此对齐、宽度大致相等。此外，也可以包括：所述吸收区180沿第三方向上的宽度小于所述雪崩区沿第三方向上的宽度。
如图1a，在本实施例中，所述第一外延生长层120的下表面低于所述第一半导体材料区的上表面，具体包括：所述第一外延生长层120的底端嵌于所述顶硅层103内。这里，所述第一外延生长层120可以通过在凹陷 于所述顶硅层103内的凹槽上外延生长而形成；所述第一外延生长层120的底端高于所述顶硅层103的下表面，即所述第一外延生长层120下方还有部分第一半导体材料(顶硅层材料)，所述第一外延生长层120不与所述埋氧层102接触。
请继续参考图1a，所述第一外延生长层120的上表面高于所述第一半导体材料区(顶硅层103)的上表面。
这里，所述第一外延生长层的材料例如为锗，即所述第二半导体材料为锗。如此，形成的所述雪崩光电探测器为锗硅光电探测器。
在本申请实施例中，所述吸收区的吸光面为所述第一外延生长层的上表面(即所述第一外延生长层上远离所述衬底的表面)。请参考图1a，所述第一外延生长层120的上表面用于吸收光信号，侧壁(侧表面或与所述第一半导体材料之间的界面)用于传递电信号。
所述第一外延生长层(吸收区)在第一方向上的尺寸范围为150nm～1500nm，在第二方向上的尺寸范围为150nm～600nm，在第三方向上的尺寸范围为1μm～20μm。这里，在描述第一外延生长层的尺寸时，并不可以考虑第一外延生长层在外延生长过程中的上下表面的尺寸差异。
第二外延生长层130，采用第一半导体材料形成在所述衬底上；所述第二外延生长层130至少包括沿所述第一方向上位于所述第一外延生长层120两侧的第一部分和第二部分，所述第一部分和所述第二部分分别覆盖所述第一外延生长层120的凸出于所述第一半导体材料区之上的两侧壁，所述第一部分和所述第二部分分别形成为第一电荷区113和第二电荷区114的至少一部分。
在本实施例中，所述吸收区的两侧包括两个电荷区，如此，可以独立调节吸收区内的电场强度，有利于降低所述雪崩光电探测器的暗电流。
所述第一电荷区和所述第二电荷区分立设置于所述吸收区的两侧，彼 此不连接。所述第一电荷区、所述吸收区和所述第二电荷区依次设置的方向(即所述第一方向)为光电流的传输方向，光电流在传输时依次流经所述第二电荷区、所述吸收区和所述第一电荷区。
所述第一电荷区和所述第二电荷区的材料可以为第一半导体材料；所述第一电荷区和所述第二电荷区内具有P型掺杂，具体例如为P+掺杂区。在一具体实施例中，所述第一电荷区和所述第二电荷区为分别位于锗吸收区两侧的两个P+掺杂硅电荷区。
在一具体实施例中，可以根据吸收区两侧电场强度的调节需求，对所述第一电荷区和所述第二电荷区分别进行离子注入。所述第一电荷区和所述第二电荷区的离子掺杂浓度不同。
所述第一电荷区和所述第二电荷区在第一方向上的尺寸范围为50nm～400nm，在第二方向上的尺寸范围为100nm～500nm(具体可以由所处位置的结构尺寸和掺杂深度共同决定)，在第三方向上的尺寸范围为1μm～20μm。所述第一电荷区、所述第二电荷区和所述第一外延生长层在第三方向上的尺寸可以相等。
参考图1a，所述第二外延生长层130的上表面至少部分与所述第一外延生长层120的上表面共面。所述第二外延生长层130的所述第一部分和所述第二部分分别形成为第一电荷区113和第二电荷区114的至少一部分应当理解为，所述第一部分和所述第二部分分别形成为完整的第一电荷区113和完整的第二电荷区114，或分别形成为第一电荷区113的一部分和第二电荷区114的一部分。
在一具体实施例中，所述第二外延生长层130位于所述第一半导体材料区与所述第一外延生长层120之间，所述第二外延生长层130的一侧与所述第一半导体材料区接触，另一侧与所述第一外延生长层120的侧壁接触。
所述第二外延生长层内具有P型掺杂。
所述第二外延生长层的上表面至少部分与所述第一外延生长层的上表面共面；所述第二外延生长层覆盖所述第一外延生长层的侧壁。可以理解地，所述第二外延生长层的上表面至少部分与所述第一外延生长层的上表面共面，可以通过平坦化工艺实现；具体例如通过化学机械研磨(CMP)工艺实现。所述第二外延生长层覆盖所述第一外延生长层的侧壁，具体为：所述第一外延生长层的侧壁完全被所述第二外延生长层覆盖；所述第一外延生长层不具有外露的侧壁区域。
所述第二外延生长层的材料与所述衬底上所述第一半导体材料区的材料相同，因此，所述第二外延生长层和所述第一半导体材料区在后续可以作为无差别的材料区，二者之间的界限可能不会被清楚的划分。
如图2a至2e示出了雪崩光电探测器中第二外延生长层的不同实施方式的结构剖视图。在图2a至2e的各图中，第一电荷区和第二电荷区分别以实线边界线示出，在实线边界线中的虚线指示出在第一电荷区或第二电荷区内部第二外延生长层(具体为所述第一部分和所述第二部分)和衬底(具体为顶硅层)之间的分界面。在图2a所示的实施例中，第二外延生长层的下表面可以与顶硅层接触，所述下表面与所述顶硅层的上表面基本平行；第二外延生长层的上表面可以与第一外延生长层的上表面共面；靠近所述第一外延生长层的侧壁与所述第一外延生长层接触(即第二外延生长层覆盖第一外延生长层的侧壁)；远离所述第一外延生长层的侧壁一部分与顶硅层接触(图中虚线)，另一部分凸出于顶硅层的上表面之上；第二外延生长层的剖面具有五边形形状。在图2b所示的实施例中，第二外延生长层的下表面可以与顶硅层接触，所述下表面与所述顶硅层的上表面基本平行；第二外延生长层的上表面可以与第一外延生长层的上表面共面；靠近所述第一外延生长层的侧壁与所述第一外延生长层接触(即第二外延生长层覆盖 第一外延生长层的侧壁)；远离所述第一外延生长层的侧壁一部分与顶硅层接触(图中虚线)，另一部分凸出于顶硅层的上表面之上；所述第二外延生长层还包括位于顶硅层之上的部分。在图2c所示的实施例中，第二外延生长层不包括与顶硅层的上表面基本平行的下表面，所述第二外延生长层的下半部呈倒三角形间插于第一外延生长层和顶硅层之间；所述第二外延生长层还包括位于顶硅层之上的部分。在图2d所示的实施例中，第二外延生长层与图2c所示的实施例中所述第二外延生长层之间的区别在于，图2d中的第二外延生长层不包括覆盖于顶硅层之上的部分；所述第二外延生长层的剖面具有四边形形状；所述第二外延生长层的上表面可以与第一外延生长层的上表面共面；靠近所述第一外延生长层的侧壁与所述第一外延生长层接触(即第二外延生长层覆盖第一外延生长层的侧壁)；远离所述第一外延生长层的侧壁一部分与顶硅层的侧壁接触(图中虚线)，另一部分凸出于顶硅层的上表面之上；所述第二外延生长层的下半部呈倒三角形间插于第一外延生长层和顶硅层之间。在图2a至2d所示的实施例中，对顶硅层的一部分和第二外延生长层进行掺杂，以形成所述电荷区，从而所述第二外延生长层可以形成为所述电荷区的一部分(所述第一部分和所述第二部分分别形成为第一电荷区和第二电荷区的一部分)；在图2e所示的实施例中，对第二外延生长层进行掺杂，以形成所述电荷区，从而所述第二外延生长层可以形成为所述电荷区的全部(所述第一部分和所述第二部分分别形成为第一电荷区和第二电荷区)；第一半导体材料区内与所述第二外延生长层接触的部分可以为所述雪崩区；第一外延生长层形成为吸收区。可以理解地，上述各实施例可以通过调整各结构形成过程中掩膜的尺寸和位置得以实现。
请继续参考图1a，所述第一半导体材料区(顶硅层103)内还形成有掺杂类型相反的第一接触区111和第二接触区117，所述第一电荷区113、 所述吸收区180、所述第二电荷区114和所述雪崩区(参考图中115)在所述第一方向上位于所述第一接触区111和所述第二接触区117之间。所述第一接触区111例如为P++接触区，所述第二接触区117例如为N++接触区。所述第一接触区111与所述第一电荷区113之间还可以包括第一I-本征区112。如此，在所述第一半导体材料区上，沿所述第一方向(即光电流的移动方向)，依次形成有所述第一接触区111、第一I-本征区112、第一电荷区113、第二电荷区114、第二I-本征区115、N+掺杂区116以及第二接触区117。所述吸收区180(第一外延生长层120)位于所述第一电荷区113和所述第二电荷区114之间。
这里，第一I-本征区112位于所述第一接触区111和所述第一电荷区113之间；第二I-本征区115位于所述第二电荷区114和所述N+掺杂区116之间。第一I-本征区112和第二I-本征区115在第一方向上的尺寸范围为60nm～600nm；在第三方向上的尺寸可以与以下之一相等：所述第一电荷区、所述第二电荷区或所述第一外延生长层在第三方向上的尺寸。
所述P++接触区和所述N++接触区的掺杂浓度范围为1×10 20/cm 3～5×10 20/cm 3，所述P+掺杂区和所述N+掺杂区的掺杂浓度范围为2×10 17/cm 3～5×10 18/cm 3，所述I-本征区的浓度≤1×10 17/cm 3，所述吸收区的掺杂浓度≤5×10 17/cm 3。其中，所述吸收区可以为本征区，或者可以为轻掺杂区。
所述P++接触区和所述N++接触区中的任意一者在第一方向上距离所述吸收区≥1.5μm。
在一实施例中，所述雪崩光电探测器中所述第一外延生长层通过上表面吸收光信号，所述雪崩光电探测器还可以包括位于所述第一外延生长层上且与所述第一外延生长层间隔一预设距离而设置的光波导；所述光波导将光信号耦合至所述第一外延生长层的耦合方向基本与所述衬底平面方向 相垂直。
请继续参考图1a和1b，所述雪崩光电探测器，还包括：光波导150，在所述第一外延生长层120上方延伸，并与所述第一外延生长层120的上表面相隔一预设距离；所述光波导150至少包括第一波导部151和第二波导部152；其中，所述第一波导部151用于将光信号耦合至所述第一外延生长层120，所述第一波导部151包括供光信号输入的第一端，以及沿光信号的传播方向(图中第三方向)上与所述第一端相对的第二端；所述第二波导部152沿所述光信号的传播方向布置在所述第二端的外侧，所述第二波导部152形成为分布式布拉格反射器结构。
可以理解地，一方面，采用独立的光波导结构传输光信号，可以避免利用硅平板波导同时进行P或N型掺杂所造成的吸收损耗；另一方面，通过光波导的一部分形成分布式布拉格反射器结构，可以在不增加有源区长度的情况下提高探测器量子效率。
所述光波导的材料具体可以为氮化硅，即所述光波导可以为氮化硅光波导。在其他一些实施例中，所述光波导的材料还可以为硅。
在一具体实施例中，所述分布式布拉格反射器结构的周期宽度为200nm～500nm；其中，光波导材料的占空比为30～70％；在所述光波导的材料为氮化硅或硅的实施例中，所述分布式布拉格反射器结构中的氮化硅材料或硅材料的占空比为30～70％。如图1b所示，一个周期宽度Δ内30～70％为光波导材料，另外70～30％为不同与光波导的其它材料，例如为二氧化硅。
所述光波导150与所述第一外延生长层120的上表面相隔的所述预设距离的范围为100nm～1000nm。
所述第一波导部151在第一方向上的尺寸范围为300nm～2000nm，在第二方向上的尺寸范围为80nm～800nm，在第三方向上的尺寸范围为1μm～35μm。其中，所述第一波导部151在第一方向上的尺寸应当大于所述 第一外延生长层120在第一方向上的尺寸。所述第一波导部151的所述第一端在衬底上的垂直投影可以落在所述第一外延生长层120在衬底上的垂直投影的范围以外；所述第一波导部151的所述第二端在衬底上的垂直投影可以落在所述第一外延生长层120在衬底上的垂直投影的范围以外，或者所述第二端在衬底上的垂直投影与所述第一外延生长层120在衬底上的垂直投影的相应边界对齐。
所述雪崩光电探测器，还包括：第一金属电极161和第二金属电极162，所述第一金属电极161和所述第二金属电极162均沿垂直所述衬底平面方向而设置；所述第一半导体材料区内还形成有掺杂类型相反的第一接触区111和第二接触区117，所述第一金属电极161和所述第二金属电极162分别与所述第一接触区111和所述第二接触区117接触。
应当理解，所述第一接触区111和所述第二接触区117的掺杂类型相反，相应地，所述第一金属电极161和所述第二金属电极162的电性相反，即二者之一为正极、另一为负极；从而在所述第一接触区111、第一I-本征区112、第一电荷区113、所述吸收区180、第二电荷区114、第二I-本征区115、N+掺杂区116以及第二接触区117的之间施加侧向电场。
所述第一金属电极161和所述第二金属电极162中任意一者与所述光波导150之间的距离大于等于500nm。如此，避免第一金属电极161或第二金属电极162吸收光信号，产生热能造成损耗。
下面，介绍所述雪崩光电探测器的一种具体实施方式。
所述雪崩光电探测器，可以包括：硅衬底(如底硅层101)、二氧化硅材料区(如埋氧层102)、硅材料区(如顶硅层103)、锗材料吸收区(如第一外延生长层120/吸收区180)、氮化硅光波导区(如光波导150)、输入光端口、两个金属电极区(如第一金属电极161和第二金属电极162)；其中，
所述硅材料区包括：与第一金属电极161连接的P++掺杂区(如第一 接触区111)、P+掺杂电荷区(如第一电荷区113和第二电荷区114)、第一I-本征区112、第二I-本征区115、N+掺杂区116、与第二金属电极162连接的N++掺杂区(如第二接触区117)；
所述氮化硅光波导区包括：条形光波导(如第一波导部151)和分布式布拉格反射器(如第二波导部152)；
所述锗材料吸收区嵌入在P+掺杂电荷区内部；
所述氮化硅光波导区的所述条形光波导位于所述锗材料吸收区的上方，两者具有一定间隔；
两个金属电极分别连接硅材料区中的P++掺杂区和N++掺杂区，形成侧向电场施加在锗材料吸收区和硅材料区。
如此，光通过氮化硅光波导区，通过倏逝波耦合缓慢进入锗材料吸收区，锗材料吸收光子产生载流子；外部施加的电场抽取光生载流子，形成电流，实现光电信号转换。本实施方式中的雪崩光电探测器为一种锗硅嵌入式侧向(或称“横向”)雪崩光-电探测器，得益于锗材料吸收区嵌入在硅材料区内以及氮化硅与锗的缓慢高效率耦合，能够实现高增益、大带宽、高量子效率雪崩光电探测。
本申请实施例还提供了一种侧向结构雪崩光电探测器的制备方法；具体请参见附图3。如图所示，所述方法包括以下步骤：
步骤201、提供衬底，所述衬底包括一第一半导体材料区；
步骤202、在所述第一半导体材料区上执行刻蚀工艺，以形成一深入所述第一半导体材料区内部的凹槽；
步骤203、执行选择性外延生长工艺，在所述凹槽内形成第一外延生长层，所述第一外延生长层的材料为不同于第一半导体材料的第二半导体材料；
所述第一外延生长层形成为所述雪崩光电探测器的吸收区；所述第一 外延生长层的上表面为吸光面，所述吸光面凸出于所述第一半导体材料区的上表面；
步骤204、再次执行选择性外延生长工艺，采用第一半导体材料形成第二外延生长层；
所述第二外延生长层至少包括沿平行衬底平面的第一方向上位于所述第一外延生长层两侧的第一部分和第二部分，所述第一部分和所述第二部分分别覆盖所述第一外延生长层的凸出于所述第一半导体材料区之上的两侧壁；
步骤205、执行选择性掺杂工艺，以在所述第一半导体材料区内形成雪崩区，将所述第二外延生长层的所述第一部分和所述第二部分分别形成为第一电荷区和第二电荷区的至少一部分；
所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在沿所述第一方向上至少部分交叠。
下面，结合图4a至4i中雪崩光电探测器的制备过程中的器件结构剖视图，对本申请实施例提供的雪崩光电探测器及其制备方法再作进一步详细的说明。
首先，执行步骤201。提供衬底，所述衬底包括一第一半导体材料区。
请参考图4a，提供衬底；所述衬底可以为单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)，或绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。
本申请实施例以所述衬底为SOI衬底为例进行说明，所述第一半导体材料区为所述SOI衬底的顶硅层103所在的区域。所述衬底还包括位于所述顶硅层103下的埋氧层102以及底硅层101。所述埋氧层102例如为二氧化硅层。所述底硅层101与所述顶硅层103相比可以具有更厚的厚度。
在一实施例中，所述衬底为单质半导体材料衬底，所述第一半导体材 料区为所述衬底的靠近上表面层的部分区域。
接下来，执行步骤202。在所述第一半导体材料区上执行刻蚀工艺，以形成一深入所述第一半导体材料区内部的凹槽。
请参考图4b，在所述衬底为绝缘体上硅衬底的实施例中，所述在所述第一半导体材料区上执行刻蚀工艺，具体包括：形成一底端位于所述顶硅层103内的凹槽。具体地，所述凹槽的下表面可以高于所述顶硅层103的下表面，从而不暴露出所述埋氧层102。
在实际工艺中，可以先通过图案化定义出需要刻蚀形成凹槽的区域，在执行所述刻蚀工艺；具体可以利用光刻或电子束曝光及刻蚀(如电感等离子刻蚀)等工艺，去除一定厚度的硅，从而形成所述凹槽。
接下来，进行步骤203。执行选择性外延生长工艺，在所述凹槽内形成第一外延生长层，所述第一外延生长层的材料为不同于第一半导体材料的第二半导体材料。
请参考图4c。在所述凹槽暴露出的所述顶硅层103上形成第一外延生长层120，所述第一外延生长层120的材料为不同于第一半导体材料的第二半导体材料。
在所述第一半导体材料为硅的实施例中，所述第二半导体材料为锗。
在实际工艺中，可以在所述凹槽区域内，利用分子束外延生长等工艺选择性生长高质量多晶锗材料。
可以通过控制定义所述第一外延生长层形成区域的掩膜的尺寸和位置，实现所述第一外延生长层的下表面仅覆盖所述凹槽的下表面的部分区域，或者覆盖所述凹槽的下表面的全部区域。
请继续参考图4c。所述形成第一外延生长层120，包括：形成一上表面高于所述第一半导体材料区(可参考图中103)的上表面的第一外延生长层120。
在实际工艺中，在执行外延生长工艺以生长第二半导体材料的第一外延生长层后，还可以包括对所述第二半导体材料的上表面进行平坦化的步骤，具体可以采用CMP工艺进行，以使所述第一外延生长层具有基本平坦的上表面。
接下来，执行步骤204。再次执行选择性外延生长工艺，采用第一半导体材料形成第二外延生长层。
这里，请参考图4d及4e。首先，参考图4d，在本实施例中，所述第一外延生长层120未填满所述凹槽；再次执行选择性外延生长工艺，在所述凹槽及所述第一外延生长层120上选择性生长第一半导体材料，如多晶硅材料；以形成填充所述凹槽并覆盖所述第一外延生长层120侧壁的第二外延生长层130。所述第二外延生长层130可以首先覆盖整个所述第一外延生长层120。
可以通过控制定义所述第二外延生长层形成区域的掩膜的尺寸和位置，实现所述第二外延生长层全部位于所述凹槽内，或者部分位于所述凹槽内、部分位于所述第一半导体材料区的上表面上。并且，对应于所述第一外延生长层在所述凹槽内，仅覆盖所述凹槽的下表面的部分区域，或者覆盖所述凹槽的下表面的全部区域；所述第二外延生长层的下表面可以与所述凹槽暴露出的所述第一半导体材料区的上表面以及侧表面接触，或者仅与所述凹槽暴露出的所述第一半导体材料区侧表面接触。这里，形成的具体结构可以参考图2a至2e及上述雪崩光电探测器的实施例中的相关描述，此处不再赘述。
接下来，请参考图4e。执行平坦化工艺，以使所述第二外延生长层130的上表面至少部分与所述第一外延生长层120的上表面共面。
在实际工艺中，可以利用CMP工艺，对锗材料上方的多晶硅材料处理，只保留锗材料两侧的多晶硅。
由于所述第二外延生长层的材料与所述衬底上所述第一半导体材料区的材料相同，因此，所述第二外延生长层和所述第一半导体材料区在后续可以作为无差别的材料区，二者之间的界限可能不会被清楚的划分。
所述第二外延生长层至少包括沿所述第一方向上位于所述第一外延生长层两侧的第一部分和第二部分，所述第一部分和所述第二部分分别覆盖所述第一外延生长层的凸出于所述第一半导体材料区之上的两侧壁。
所述第二外延生长层位于所述第一半导体材料区与所述第一外延生长层之间，所述第二外延生长层的一侧与所述第一半导体材料区接触，另一侧与所述第一外延生长层的侧壁接触。
接下来，进行步骤205。执行选择性掺杂工艺，以在所述第一半导体材料区内形成雪崩区，将所述第二外延生长层的所述第一部分和所述第二部分分别形成为第一电荷区和第二电荷区的至少一部分。
请参考图4f。所述执行选择性掺杂工艺，可以包括：对所述第二外延生长层130进行P型掺杂。这里，由于不对所述第二外延生长层130和所述第一半导体材料区进行清除划分，因此所述P型掺杂也可能部分进行在所述第一半导体材料区的与所述第二外延生长层130相接触的部分区域上。
通过进行P型掺杂，形成了与所述吸收区紧邻的P+掺杂电荷区。所述电荷区可以作为所述倍增区的一部分。
在一实施例中，所述P型掺杂可以在所述吸收区的两侧进行，以使所述吸收区的两侧包括两个电荷区；也即，所述执行选择性掺杂工艺，还可以包括：在所述第一外延生长层120的两侧分别形成第一电荷区113和第二电荷区114。
此外，所述执行选择性掺杂工艺，还可以包括：在所述第一半导体材料区内形成掺杂类型相反的第一接触区111和第二接触区117；所述第一电荷区113、所述吸收区180、所述第二电荷区114和所述雪崩区(参考图中 115)在所述第一方向上位于所述第一接触区111和所述第二接触区117之间。所述第一接触区111例如为P++接触区，所述第二接触区117例如为N++接触区。
所述执行选择性掺杂工艺，还可以包括：在所述第一外延生长层120和所述第二接触区117之间，具体为所述电荷区(第二电荷区114)和所述第二接触区117之间，形成N+接触区116。
所述电荷区和所述第二接触区117之间至少包括未被掺杂的I-本征区(第二I-本征区115)；如此，沿远离所述吸收区(第一外延生长层120)方向上依次布置的P+掺杂区(电荷区)、I-本征区(雪崩区)以及N+掺杂区组成所述倍增区。
在本实施例中，所述第一接触区111与所述第一电荷区113之间还可以包括第一I-本征区112。如此，在所述第一半导体材料区上，沿所述第一方向，依次形成有所述第一接触区111、第一I-本征区112、第一电荷区113、第二电荷区114、第二I-本征区115、N+掺杂区116以及第二接触区117。所述吸收区180(第一外延生长层120)位于所述第一电荷区113和所述第二电荷区114之间。
这里，第一I-本征区112位于所述第一接触区111和所述第一电荷区113之间；第二I-本征区115位于所述第二电荷区114和所述N+掺杂区116之间。
接下来，请参考图4g。在所述衬底上，具体在所述第一半导体材料区和所述第一外延生长层、所述第二外延生长层上，形成填充层140。
所述填充层140的材料可以包括二氧化硅。
在实际工艺中，可以通过沉积一定厚度的二氧化硅材料，并进行平坦化处理，以形成所述填充层140。
接下来，所述方法还包括：形成光波导，所述光波导在所述第一外延 生长层上方延伸，并与所述第一外延生长层的上表面相隔一预设距离；所述光波导至少包括第一波导部和第二波导部；其中，所述第一波导部用于将光信号耦合至所述第一外延生长层，所述第一波导部包括供光信号输入的第一端，以及沿光信号的传播方向上与所述第一端相对的第二端；所述第二波导部沿所述光信号的传播方向布置在所述第二端的外侧，所述第二波导部形成为分布式布拉格反射器结构。
请参考图4h，形成光波导150。
在实际工艺中，可以通过图案化的掩膜层(图中未示出)，在第一外延生长层120上方的填充层140上定义出需要形成光波导的区域；在所述区域内生长光波导材料，具体例如为沉积氮化硅材料或者生长硅材料，以形成所述光波导150。
形成的所述光波导150的具体结构可以参考图1b。其中，所述分布式布拉格反射器结构的周期宽度为200nm～500nm；光波导材料的占空比为30～70％。
接下来，请参考图4i。所述方法还包括：形成垂直所述衬底平面方向(即第二方向)而设置的第一金属电极161和第二金属电极162；所述第一金属电极161和所述第二金属电极162分别与所述第一接触区111和所述第二接触区117接触；其中，所述第一金属电极161和所述第二金属电极162中任意一者与所述光波导150之间的距离大于等于500nm。
具体可以利用光刻与电感等离子刻蚀开窗口、磁控溅射沉积金属材料等工艺制作上述两个金属电极。
所述第一金属电极161和所述第二金属电极162的上表面应当高于所述光波导150的上表面。具体地，还包括在所述光波导150上形成填充层，利用光刻与刻蚀(如电感等离子刻蚀)等工艺在填充层内形成暴露所述第一接触区111和所述第二接触区117的窗口；在所述窗口内填充电极材料(如 磁控溅射沉积金属材料)，以形成所述第一金属电极161和所述第二金属电极162。
如此，基本完成了所述雪崩光电探测器的制备。后续可能还会涉及到一些互连工艺，这里不再展开论述。
需要说明的是，本申请实施例提供的雪崩光电探测器实施例与雪崩光电探测器的制备方法实施例属于同一构思；各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。但需要进一步说明的是，本申请实施例提供的雪崩光电探测器，其各技术特征组合已经可以解决本申请所要解决的技术问题；因而，本申请实施例所提供的雪崩光电探测器可以不受本申请实施例提供的雪崩光电探测器的制备方法的限制，任何能够形成本申请实施例所提供的雪崩光电探测器结构的制备方法所制备的雪崩光电探测器均在本申请保护的范围之内。
以上所述，仅为本申请的可选实施例而已，并非用于限定本申请的保护范围，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (16)

  1. 一种侧向结构雪崩光电探测器，包括：
    衬底，所述衬底包括一第一半导体材料区；在所述第一半导体材料区内形成有所述雪崩光电探测器的雪崩区；
    第一外延生长层，采用不同于第一半导体材料的第二半导体材料形成在所述衬底上；所述第一外延生长层形成为所述雪崩光电探测器的吸收区；所述第一外延生长层的上表面为吸光面，所述吸光面凸出于所述第一半导体材料区的上表面；所述第一外延生长层的下表面低于所述第一半导体材料区的上表面；所述吸收区和所述雪崩区沿平行衬底平面的第一方向上间隔设置；
    第二外延生长层，采用第一半导体材料形成在所述衬底上；所述第二外延生长层至少包括沿所述第一方向上位于所述第一外延生长层两侧的第一部分和第二部分，所述第一部分和所述第二部分分别覆盖所述第一外延生长层的凸出于所述第一半导体材料区之上的两侧壁，所述第一部分和所述第二部分分别形成为第一电荷区和第二电荷区的至少一部分；
    所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在所述第一方向上至少部分交叠。
  2. 根据权利要求1所述的侧向结构雪崩光电探测器，其中，
    所述衬底为绝缘体上硅衬底，所述第一半导体材料区为所述绝缘体上硅衬底的顶硅层所在的区域；
    所述第一外延生长层的下表面低于所述第一半导体材料区的上表面，具体包括：所述第一外延生长层的底端嵌于所述顶硅层内。
  3. 根据权利要求1所述的侧向结构雪崩光电探测器，其中，所述第二外延生长层位于所述第一半导体材料区与所述第一外延生长层之间，所述第二外延生长层的一侧与所述第一半导体材料区接触，另一侧与所述第一 外延生长层的侧壁接触。
  4. 根据权利要求1所述的侧向结构雪崩光电探测器，其中，所述第二外延生长层内具有P型掺杂。
  5. 根据权利要求1至4中任意一项所述的侧向结构雪崩光电探测器，其中，所述第一半导体材料为硅；所述第二半导体材料为锗。
  6. 根据权利要求1所述的侧向结构雪崩光电探测器，其中，还包括：
    光波导，在所述第一外延生长层上方延伸，并与所述第一外延生长层的上表面相隔一预设距离；
    所述光波导至少包括第一波导部和第二波导部；其中，
    所述第一波导部用于将光信号耦合至所述第一外延生长层，所述第一波导部包括供光信号输入的第一端，以及沿光信号的传播方向上与所述第一端相对的第二端；
    所述第二波导部沿所述光信号的传播方向布置在所述第二端的外侧，所述第二波导部形成为分布式布拉格反射器结构。
  7. 根据权利要求6所述的侧向结构雪崩光电探测器，其中，所述分布式布拉格反射器结构的周期宽度为200nm～500nm；其中，光波导材料的占空比为30～70％。
  8. 根据权利要求6所述的侧向结构雪崩光电探测器，其中，还包括：
    第一金属电极和第二金属电极，所述第一金属电极和所述第二金属电极均沿垂直所述衬底平面方向而设置；
    所述第一半导体材料区内还形成有掺杂类型相反的第一接触区和第二接触区，所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在所述第一方向上位于所述第一接触区和所述第二接触区之间；所述第一金属电极和所述第二金属电极分别与所述第一接触区和所述第二接触区接触；
    所述第一金属电极和所述第二金属电极中任意一者与所述光波导之间的距离大于等于500nm。
  9. 一种侧向结构雪崩光电探测器的制备方法，所述方法包括以下步骤：
    提供衬底，所述衬底包括一第一半导体材料区；
    在所述第一半导体材料区上执行刻蚀工艺，以形成一深入所述第一半导体材料区内部的凹槽；
    执行选择性外延生长工艺，在所述凹槽内形成第一外延生长层，所述第一外延生长层的材料为不同于第一半导体材料的第二半导体材料；所述第一外延生长层形成为所述雪崩光电探测器的吸收区；所述第一外延生长层的上表面为吸光面，所述吸光面凸出于所述第一半导体材料区的上表面；
    再次执行选择性外延生长工艺，采用第一半导体材料形成第二外延生长层；所述第二外延生长层至少包括沿平行衬底平面的第一方向上位于所述第一外延生长层两侧的第一部分和第二部分，所述第一部分和所述第二部分分别覆盖所述第一外延生长层的凸出于所述第一半导体材料区之上的两侧壁；
    执行选择性掺杂工艺，以在所述第一半导体材料区内形成雪崩区，将所述第二外延生长层的所述第一部分和所述第二部分分别形成为第一电荷区和第二电荷区的至少一部分；所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在沿所述第一方向上至少部分交叠。
  10. 根据权利要求9所述的侧向结构雪崩光电探测器的制备方法，其中，所述衬底为绝缘体上硅衬底，所述第一半导体材料区为所述绝缘体上硅衬底的顶硅层所在的区域；
    所述在所述第一半导体材料区上执行刻蚀工艺，具体包括：形成一底端位于所述顶硅层内的凹槽。
  11. 根据权利要求9所述的侧向结构雪崩光电探测器的制备方法，其 中，所述第一外延生长层未填满所述凹槽；形成所述第二外延生长层，包括：
    形成填充所述凹槽并覆盖所述第一外延生长层侧壁的第二外延生长层，所述第二外延生长层位于所述第一半导体材料区与所述第一外延生长层之间，所述第二外延生长层的一侧与所述第一半导体材料区接触，另一侧与所述第一外延生长层的侧壁接触。
  12. 根据权利要求9所述的侧向结构雪崩光电探测器的制备方法，其中，所述执行选择性掺杂工艺，包括：对所述第二外延生长层进行P型掺杂。
  13. 根据权利要求9至12中任意一项所述的侧向结构雪崩光电探测器的制备方法，其中，所述第一半导体材料为硅；所述第二半导体材料为锗。
  14. 根据权利要求9所述的侧向结构雪崩光电探测器的制备方法，其中，所述方法还包括：
    形成光波导，所述光波导在所述第一外延生长层上方延伸，并与所述第一外延生长层的上表面相隔一预设距离；
    所述光波导至少包括第一波导部和第二波导部；其中，
    所述第一波导部用于将光信号耦合至所述第一外延生长层，所述第一波导部包括供光信号输入的第一端，以及沿光信号的传播方向上与所述第一端相对的第二端；
    所述第二波导部沿所述光信号的传播方向布置在所述第二端的外侧，所述第二波导部形成为分布式布拉格反射器结构。
  15. 根据权利要求14所述的侧向结构雪崩光电探测器的制备方法，其中，所述分布式布拉格反射器结构的周期宽度为200nm～500nm；其中，光波导材料的占空比为30～70％。
  16. 根据权利要求14所述的侧向结构雪崩光电探测器的制备方法，其 中，
    所述执行选择性掺杂工艺，还包括：在所述第一半导体材料区内形成掺杂类型相反的第一接触区和第二接触区；所述第一电荷区、所述吸收区、所述第二电荷区和所述雪崩区在所述第一方向上位于所述第一接触区和所述第二接触区之间；
    所述方法还包括：形成垂直所述衬底平面方向而设置的第一金属电极和第二金属电极；所述第一金属电极和所述第二金属电极分别与所述第一接触区和所述第二接触区接触；
    其中，所述第一金属电极和所述第二金属电极中任意一者与所述光波导之间的距离大于等于500nm。
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