WO2023125283A1 - 雪崩光电探测器及其制备方法 - Google Patents

雪崩光电探测器及其制备方法 Download PDF

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WO2023125283A1
WO2023125283A1 PCT/CN2022/141400 CN2022141400W WO2023125283A1 WO 2023125283 A1 WO2023125283 A1 WO 2023125283A1 CN 2022141400 W CN2022141400 W CN 2022141400W WO 2023125283 A1 WO2023125283 A1 WO 2023125283A1
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type doped
doped region
region
semiconductor layer
electrode
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PCT/CN2022/141400
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English (en)
French (fr)
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胡晓
陈代高
张宇光
王磊
肖希
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武汉光谷信息光电子创新中心有限公司
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Priority claimed from CN202111633446.4A external-priority patent/CN114256375B/zh
Priority claimed from CN202111643459.XA external-priority patent/CN114256376B/zh
Priority claimed from CN202111633301.4A external-priority patent/CN114256374B/zh
Application filed by 武汉光谷信息光电子创新中心有限公司 filed Critical 武汉光谷信息光电子创新中心有限公司
Publication of WO2023125283A1 publication Critical patent/WO2023125283A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Definitions

  • Embodiments of the present disclosure relate to but are not limited to an avalanche photodetector and a preparation method thereof.
  • the avalanche photodetector has the function of converting low-power optical signals to electrical signals.
  • the region is rapidly accelerated during the movement, and one or more collisions may occur during the movement, and secondary and three new hole-electron pairs are generated through the impact ionization effect, resulting in an avalanche multiplication effect, which rapidly increases the number of carriers, thus forming a comparative large optical signal current.
  • silicon germanium materials compatible with CMOS technology are widely used in silicon photonic integrated chips to realize avalanche photodetection. It uses silicon materials as optical waveguides and at the same time as avalanche gain regions (also known as multiplication regions), while germanium materials absorb photons.
  • the disadvantages of the silicon-germanium avalanche photodetector structure are as follows: first, the epitaxial single-crystal silicon process is required, and the fabrication is relatively complicated; Reduce the quantum efficiency of the detector; the third is that the absorption region and the multiplication region are not easy to adjust independently, the concentration accuracy of the doping region is too high, the process tolerance is low, and the gain bandwidth is likely to be unsatisfactory. Therefore, the avalanche photodetector using germanium silicon material needs to be further improved.
  • An embodiment of the present disclosure provides an avalanche photodetector, including:
  • a substrate the surface of which includes a first semiconductor layer
  • the first semiconductor layer includes a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, and a third P-type doped region arranged in sequence in the first direction.
  • impurity region, second intrinsic region, second N-type doped region, and first N-type doped region, the dopant concentrations of the first to third P-type doped regions decrease sequentially, and the first The dopant concentration to the third N-type doped region decreases sequentially, and the first direction is the electron flow direction of the avalanche photodetector;
  • the second semiconductor layer sequentially covers part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region along the first direction. district;
  • the first N-type doped region is connected to a first electrode; the third P-type doped region is connected to a second electrode; and the first P-type doped region is connected to a third electrode.
  • the first intrinsic region, the third N-type doped region, the part of the second P-type doped region next to the third N-type doped region in the first semiconductor layer, the next to A part of the third P-type doped region of the first intrinsic region has a first height H 1 in a direction perpendicular to the substrate, and other regions in the first semiconductor layer have a second height H 2 ; H 1 is not equal to H 2 ;
  • the second semiconductor layer sequentially covers a part of the region where the second P-type doped region has a second height H2 along the first direction, and the second P-type doped region has a first height H1 region, the third N-type doped region, the first intrinsic region, the third P-type doped region has a first height H1 and the third P-type doped region has a second Part of the area at height H2 .
  • H 1 is greater than H 2 .
  • H 1 is less than H 2 .
  • the avalanche photodetector also includes:
  • an optical waveguide located on the first semiconductor layer, including a front end close to the light incident end and an end far away from the light incident end;
  • the third height H3 of the partial region of the second P-type doped region in the first semiconductor layer immediately adjacent to the first P-type doped region is lower than the fourth height H3 of other regions in the first semiconductor layer.
  • the second semiconductor layer sequentially covers a partial region of the fourth height H4 of the second P-type doped region, the third N-type doped region, and the first intrinsic region along the first direction. and a partial region of the third P-type doped region;
  • the optical waveguide is located in the groove and arranged to extend generally along the second direction and form a preset angle with the second direction, so that its front end is close to the first P-type doped region and its end is close to the second Part of the fourth height H4 of the P-type doped region.
  • the optical waveguide is undoped or lightly doped.
  • a first reverse bias voltage V 1 is set between the first electrode and the third electrode, and a second reverse bias voltage is set between the first electrode and the second electrode V 2 .
  • the material of the first semiconductor layer is silicon
  • the material of the second semiconductor layer is germanium, germanium-silicon alloys, III-V materials and alloys thereof.
  • the dopant concentration of the first P-type doped region or the first N-type doped region is 1 ⁇ 10 20 /cm 3 to 5 ⁇ 10 20 /cm 3
  • the first The dopant concentration of the second P-type doped region or the second N-type doped region is 2 ⁇ 10 17 /cm 3 to 5 ⁇ 10 18 /cm 3
  • the third P-type doped region or the The dopant concentration of the third N-type doped region is 1.2 ⁇ 10 17 -4 ⁇ 10 17 /cm 3 .
  • the size of the second intrinsic region in the first direction is 50 nm to 800 nm.
  • the size of the second semiconductor layer in the first direction is 150 nm to 1500 nm
  • the size in the second direction is 1 ⁇ m to 100 ⁇ m
  • the size in the third direction is 150 nm to 600 nm
  • the third direction is a direction perpendicular to the substrate
  • the second direction is perpendicular to the third direction and perpendicular to the first direction.
  • An embodiment of the present disclosure also provides a method for preparing an avalanche photodetector, including:
  • first P-type doped region a first P-type doped region, a second P-type doped region, a third N-type doped region, a first An intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region, and a first N-type doped region, the doping of the first to third P-type doped regions
  • the dopant concentration decreases sequentially, and the dopant concentrations of the first to third N-type doped regions decrease sequentially;
  • the material of the second semiconductor layer is different from the material of the first semiconductor layer, and sequentially covering part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region;
  • first electrode is electrically connected to the first N-type doped region
  • second electrode is connected to the first
  • the three P-type doped regions are electrically connected
  • the third electrode is electrically connected to the first P-type doped region
  • the first direction is the electron flow direction of the avalanche photodetector.
  • the method also includes:
  • a height different from that of other regions in the first semiconductor layer in a direction perpendicular to the substrate is formed in a direction perpendicular to the substrate.
  • the partial region of the second P-type doped region, the partial region of the third P-type doped region, the first intrinsic region and the third In the region of the N-type doped region a different height is formed in the direction perpendicular to the substrate than in other regions of the first semiconductor layer in the direction perpendicular to the substrate, including:
  • the formed height H 1 is greater than the height H 2 formed in the direction perpendicular to the substrate in other regions of the first semiconductor layer.
  • the partial region of the second P-type doped region, the partial region of the third P-type doped region, the first intrinsic region and the third In the region of the N-type doped region a different height is formed in the direction perpendicular to the substrate than in other regions of the first semiconductor layer in the direction perpendicular to the substrate, including:
  • the formed height H 1 is smaller than the height H 2 formed in the direction perpendicular to the substrate in other regions of the first semiconductor layer.
  • the method also includes:
  • two wedge-shaped grooves are formed on a partial region of the second P-type doped region to be formed that is adjacent to the first P-type doped region, so as to form two wedge-shaped grooves in the two wedge-shaped grooves. A portion of the first semiconductor layer remains between them.
  • the remaining part of the first semiconductor layer is undoped or lightly doped.
  • the material of the first semiconductor layer is silicon
  • the material of the second semiconductor layer is germanium, germanium-silicon alloys, III-V materials and alloys thereof.
  • the dopant concentration of the first P-type doped region or the first N-type doped region is 1 ⁇ 10 20 /cm 3 to 5 ⁇ 10 20 /cm 3
  • the first The dopant concentration of the second P-type doped region or the second N-type doped region is 2 ⁇ 10 17 /cm 3 to 5 ⁇ 10 18 /cm 3
  • the third P-type doped region or the The dopant concentration of the third N-type doped region is 1.2 ⁇ 10 17 -4 ⁇ 10 17 /cm 3 .
  • the formation of the first electrode, the second electrode and the third electrode arranged perpendicular to the direction of the substrate plane includes:
  • first window, a second window, and a third window in the first N-type doped region, the third P-type doped region, and one end of the first P-type doped region along the second direction, respectively , to expose part of the surface of the first P-type doped region, the third P-type doped region and the first N-type doped region;
  • the second direction is perpendicular to the first direction and parallel to in the direction of the substrate;
  • FIGS. 1 to 3 are schematic structural diagrams of an avalanche photodetector provided by an embodiment of the present disclosure
  • FIGS. 4 to 6 are structural schematic diagrams of another avalanche photodetector provided by an embodiment of the present disclosure.
  • FIG. 7 to 9 are structural schematic diagrams of another avalanche photodetector provided by an embodiment of the present disclosure.
  • FIG. 10 to FIG. 13 are structural schematic diagrams of another avalanche photodetector provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic flowchart of a method for preparing an avalanche photodetector provided by an embodiment of the present disclosure
  • 15a to 15e are cross-sectional views of the device structure during the preparation process of an avalanche photodetector provided by an embodiment of the present disclosure
  • 16a to 16g are cross-sectional views of the device structure during the preparation process of another avalanche photodetector provided by an embodiment of the present disclosure.
  • the "upper” or “lower” relationship between two layers in a semiconductor structure may be direct contact between the two layers, or indirect contact between the two layers through an intermediate layer .
  • the term "layer" refers to a portion of material comprising a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure.
  • a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along sloped surfaces.
  • a layer may include a plurality of sublayers.
  • spatially relative terms such as “below”, “below”, “under”, “above”, “upper”, “upward”, “downward”, etc. may be used herein for the convenience of description Describes the relationship of an element or feature to another element or feature(s), as shown in the figure. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • Silicon photonics technology is a new generation technology based on silicon and silicon-based substrate materials (such as SiGe/Si, silicon-on-insulator, etc.), using the existing complementary metal oxide semiconductor (CMOS) process for optical device development and integration.
  • CMOS complementary metal oxide semiconductor
  • Silicon photonics technology combines the characteristics of ultra-large-scale and ultra-high-precision manufacturing of integrated circuit technology with the advantages of ultra-high speed and ultra-low power consumption of photonic technology. It is a disruptive technology to cope with the failure of Moore's Law. This combination benefits from the scalability of semiconductor wafer fabrication, thereby reducing costs.
  • photodetector has the function of converting optical signal to electrical signal.
  • the disadvantages of the silicon-germanium avalanche photodetector structure are as follows: first, the epitaxial single-crystal silicon process is required, and the fabrication is relatively complicated; Reduce the quantum efficiency of the detector; the third is that the absorption region and the avalanche region (also known as the multiplication region) are not easy to adjust independently, the concentration accuracy of the doping region is too high, the process tolerance is low, and the gain bandwidth is likely to be unsatisfactory.
  • An embodiment of the present disclosure provides an avalanche photodetector, including:
  • a substrate the surface of which includes a first semiconductor layer
  • the first semiconductor layer includes a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, and a third P-type doped region arranged in sequence in the first direction.
  • impurity region, second intrinsic region, second N-type doped region, and first N-type doped region, the dopant concentrations of the first to third P-type doped regions decrease sequentially, and the first The dopant concentration to the third N-type doped region decreases sequentially, and the first direction is the electron flow direction of the avalanche photodetector;
  • the second semiconductor layer sequentially covers part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region along the first direction. district,
  • the first N-type doped region is connected to a first electrode; the third P-type doped region is connected to a second electrode; and the first P-type doped region is connected to a third electrode.
  • FIG. 1 is a schematic axonometric view of an avalanche photodetector provided by an embodiment of the present disclosure
  • FIG. 2 is a top view of an avalanche photodetector provided by an embodiment of the present disclosure Schematic diagram
  • FIG. 3 is a schematic diagram along the Y direction of an avalanche photodetector provided by an embodiment of the present disclosure.
  • the avalanche photodetector includes:
  • a substrate 10 which includes a first semiconductor layer 300; an avalanche region of the avalanche photodetector is formed in the first semiconductor layer 300 to achieve an avalanche effect;
  • the second semiconductor layer 400 uses a material different from that of the first semiconductor layer 300 .
  • the substrate may be a multi-layer structure, wherein the top of the substrate is the first semiconductor layer, and the bottom layer may include a single semiconductor material (such as silicon (Si), germanium (Ge), etc.), a compound semiconductor material (such as Silicon germanium (SiGe) etc.) and insulating layers made of oxides.
  • the substrate 10 may be silicon-on-insulator (SOI), germanium-on-insulator (GeOI), or the like.
  • the layer below the surface of the substrate is SOI as an example for illustration. It can be understood that the first semiconductor layer 300 is located on the top of the substrate 10 of the present disclosure.
  • the material of the first semiconductor layer 300 includes silicon.
  • Layers under the first semiconductor layer 300 include an insulating layer 200 and a bottom layer 100 in sequence.
  • the bottom layer 100 may be a silicon wafer, or a wafer formed of other materials. Therefore, the material of the bottom layer 100 may be silicon, germanium, or sapphire.
  • the material of the bottom layer 100 is silicon, and correspondingly, the material of the insulating layer 200 can be an oxide of silicon, such as silicon dioxide.
  • the bottom layer 100 may have a thicker thickness than the first semiconductor layer 300 . It should be understood that in order to clearly show each layer structure in the figure, the size ratio relationship of each layer structure may not match the actual structure.
  • FIG. 1 the embodiments of the present disclosure are described by means of a first direction (X), a second direction (Y) and a third direction (Z) (see FIG. 1 ) .
  • the substrate 10 may include a top surface on the front side and a bottom surface on the back side opposite to the front side; under the condition of ignoring the flatness of the top surface and the bottom surface, the direction perpendicular to the top surface and the bottom surface of the substrate is defined as Three directions (Z).
  • the third direction Z is also the lamination direction of subsequent deposition of various layer structures on the substrate, or called the height direction of the device.
  • the plane where the top and bottom surfaces of the substrate are located, or strictly speaking, the center plane in the thickness direction of the substrate, is determined as the substrate plane.
  • Two intersecting (for example, perpendicular to each other) first directions (X) and second directions (Y) are defined in the substrate plane direction.
  • the first direction X is the electron flow direction
  • the second direction Y is the propagation direction of the optical signal.
  • any semiconductor material can be used as the material of the first semiconductor layer 300 in the avalanche photodetector, so the first semiconductor material is not strictly limited here.
  • the first semiconductor material is Si.
  • the different regions formed in the first semiconductor layer 300 of the avalanche photodetector have different doping regions, including doping with different concentrations of P-type dopants, N-type dopant, and the undoped region (intrinsic region).
  • the first semiconductor layer 300 in the avalanche photodetector includes a first P-type doped region 301, a second P-type doped region 302, and a third N-type doped region arranged in sequence in the first direction X. region 303 , a first intrinsic region 304 , a third P-type doped region 305 , a second intrinsic region 306 , a second N-type doped region 307 and a first N-type doped region 308 .
  • the P-type dopant concentrations in the first P-type doped region, the second P-type doped region, and the third P-type doped region decrease sequentially, and the first N-type doped region, the second N-type doped region, The N-type dopant concentration of the third N-type doped region decreases successively.
  • the first intrinsic region, the third N-type doped region, the part of the second P-type doped region next to the third N-type doped region in the first semiconductor layer, the next to A part of the third P-type doped region of the first intrinsic region has a first height H 1 in a direction perpendicular to the substrate, and other regions in the first semiconductor layer have a second height H 2 ; H 1 is not equal to H 2 ;
  • the second semiconductor layer sequentially covers a part of the region where the second P-type doped region has a second height H2 along the first direction, and the second P-type doped region has a first height H1 region, the third N-type doped region, the first intrinsic region, the third P-type doped region has a first height H1 and the third P-type doped region has a second Part of the area at height H2 .
  • FIG. 4 to 6 are schematic diagrams of another avalanche photodetector provided by an embodiment of the present disclosure; wherein, FIG. 4 is a schematic isometric view; FIG. 5 is a schematic top view; and FIG. 6 is a schematic view along the Y direction.
  • part of the second P-type doped region, part of the third P-type doped region, the first intrinsic region, and the third N-type doped region in the first semiconductor layer are arranged in a direction perpendicular to the substrate The height H 1 of the top is greater than the height H 2 of other regions in the first semiconductor layer.
  • part of the second P-type doped region 302 part of the third P-type doped region 305, first intrinsic region 304, third N-type doped region 300 in the first semiconductor layer 300
  • the height H 1 of the doped region 303 in the direction perpendicular to the substrate (Z direction) is greater than the height H 2 of other regions in the first semiconductor layer.
  • part of the second P-type doped region 302 part of the third P-type doped region 305, the first intrinsic region 304, and the third N-type doped region 303 is protruding. Viewed from the Y direction, part of the second P-type doped region 302 , part of the third P-type doped region 305 , the first intrinsic region 304 and the third N-type doped region 303 are in an inverted U shape.
  • FIG. 7 to 9 are schematic diagrams of another avalanche photodetector provided by an embodiment of the present disclosure; wherein, FIG. 7 is a schematic isometric view; FIG. 8 is a schematic top view; and FIG. 9 is a schematic view along the Y direction.
  • part of the second P-type doped region, part of the third P-type doped region, first intrinsic region, third N-type doped is smaller than the height H 2 of other regions in the first semiconductor layer.
  • part of the second P-type doped region 302 part of the third P-type doped region 305, first intrinsic region 304, third N-type doped region in the first semiconductor layer 300
  • the height H 1 of the doped region 303 in the direction perpendicular to the substrate (Z direction) is smaller than the height H 2 of other regions in the first semiconductor layer 300 .
  • part of the second P-type doped region 302 part of the third P-type doped region 305, the first intrinsic region 304, and the third N-type doped region 303 is sunken. Viewed from the Y direction, part of the second P-type doped region 302 , part of the third P-type doped region 305 , the first intrinsic region 304 and the third N-type doped region 303 are in an inverted U shape.
  • the avalanche photodetector also includes:
  • an optical waveguide located on the first semiconductor layer, including a front end close to the light incident end and an end far away from the light incident end;
  • the third height H3 of the partial region of the second P-type doped region in the first semiconductor layer immediately adjacent to the first P-type doped region is lower than the fourth height H3 of other regions in the first semiconductor layer.
  • the second semiconductor layer sequentially covers a partial region of the fourth height H4 of the second P-type doped region, the third N-type doped region, and the first intrinsic region along the first direction. and a partial region of the third P-type doped region;
  • the optical waveguide is located in the groove and arranged to extend generally along the second direction and form a preset angle with the second direction, so that its front end is close to the first P-type doped region and its end is close to the second Part of the fourth height H4 of the P-type doped region.
  • FIG. 10 to 13 are schematic diagrams of another avalanche photodetector provided by an embodiment of the present disclosure; wherein, FIG. 10 is an axonometric schematic diagram; FIG. 11 is a schematic top view; FIG. 12 is a schematic diagram along the Y direction, and FIG. 13 is a diagram Schematic illustration of a local enlargement in 12.
  • the avalanche photodetector further includes an optical waveguide G located on the first semiconductor layer 300 , which includes a front end close to the light incident end and an end far away from the light incident end.
  • a portion of the second P-type doped region 302 adjacent to the first P-type doped region 301 along the second direction (Y) has a groove. That is, the second P-type doped region 302 is composed of two parts: the second P-type doped I region 3021 and the second P-type doped II region 3022 , refer to FIG. 11 to FIG. 13 .
  • the second P-type doped I region 3021 that is, the groove portion, has a height smaller than other regions in the first semiconductor layer 300 in the third direction (Z); the rest of the second P-type doped region 302 is part of the second The P-type doped II region 3022 , which is adjacent to the third N-type doped region 303 , has the same height as other regions in the first semiconductor layer 300 along the third direction (Z). It should be noted that the dopant concentrations of the two parts of the second P-type doped region 302, the second P-type doped I region 3021 and the second P-type doped II region 3022, are the same, the difference is only that the two different heights.
  • the P-type dopant may be boron (B), and the N-type dopant may be phosphorous (P) or arsenic (As).
  • the dopant concentration of the first P-type doped region 301 or the first N-type doped region 308 is 1 ⁇ 10 20 /cm 3 to 5 ⁇ 10 20 /cm 3
  • the second P-type doped region The dopant concentration of the impurity region 302 or the second N-type doped region 307 is 2 ⁇ 10 17 /cm 3 to 5 ⁇ 10 18 /cm 3
  • the dopant concentration of 303 is 1.2 ⁇ 10 17 -4 ⁇ 10 17 /cm 3 .
  • the intrinsic region is undoped or lightly doped, its concentration is generally less than a predetermined value, for example, less than 1 ⁇ 10 17 /cm 3 .
  • the dopant concentrations of the first P-type doped region and the first N-type doped region may be the same or different, as long as their doping concentrations are within the above-mentioned range.
  • the dopant concentrations of the second P-type doped region and the second N-type doped region, and the third P-type doped region and the third N-type doped region may be the same or different.
  • the intrinsic region it may be the undoped or lightly doped first semiconductor material.
  • the intrinsic region is a region where impact ionization specifically occurs to generate electron-hole pairs.
  • the avalanche region may be the second intrinsic region 306 .
  • the avalanche photodetector is based on applying a voltage between the avalanche regions to generate an electric field, thereby extracting photo-generated carriers through the electric field to form a current. Specifically, a bias voltage is applied to both sides of the avalanche region along the first direction to realize photodetection.
  • the first semiconductor layer 300 includes a second semiconductor layer 400 whose material is different from that of the first semiconductor layer.
  • the material of the first semiconductor layer 300 is silicon
  • the material of the second semiconductor layer 400 is germanium, germanium-silicon alloys, III-V materials and alloys thereof.
  • the material of the first semiconductor layer 300 is silicon
  • the material of the second semiconductor layer is germanium.
  • the resulting avalanche photodetector is a silicon germanium photodetector.
  • the second semiconductor layer 400 used as the absorption region in the avalanche photodetector provided by the present disclosure is not doped by P or N type and does not involve ohmic contact, the light absorption loss can be reduced as much as possible, which is beneficial to improve the quantum absorption efficiency.
  • the second semiconductor layer 400 of the avalanche photodetector in this embodiment sequentially covers part of the second P-type doped region 302, the third N-type doped region 303, the first intrinsic region 304 and part of the second doped region along the first direction. Three P-type doped regions 305 .
  • the second semiconductor layer 400 is formed as an absorption region of the avalanche photodetector.
  • the second semiconductor layer 400 of the avalanche photodetector of the present disclosure sequentially covers part of the second P-type doped region 302 and the third N-type doped region along the first direction X.
  • the second semiconductor layer 400 is formed as an absorption region of the avalanche photodetector.
  • the second semiconductor layer 400 of the avalanche photodetector of this embodiment sequentially covers part of the second P-type doped region 302 and the third N-type doped region 302 along the first direction X.
  • the second semiconductor layer 400 is in the relationship of space and complement to them.
  • the second semiconductor layer 400 is formed as an absorption region of the avalanche photodetector.
  • the second semiconductor layer since part of the second P-type doped region, part of the third P-type doped region, the first intrinsic region, and the third N-type doped region have the same The heights of other regions in a semiconductor layer are different, and the second semiconductor layer sequentially covers a part of the region of the second height H of the second P-type doped region along the first direction, and the first height of the second P-type doped region The region of H1 , the third N-type doped region, the first intrinsic region and the region of the first height H1 of the third P-type doped region and the region of the second height H2 of the third P-type doped region Therefore, the second semiconductor layer has a larger contact area with the second P-type doped region and the third P-type doped region, which can improve the subsequent transmission efficiency of electrons participating in the avalanche effect.
  • the second P-type doped region 302 not covered by the second semiconductor layer has a groove in it, and the optical waveguide G is in the groove.
  • the optical waveguide G is located on the surface of the second P-type doped I region 3021 , that is, located in the groove of the second P-type doped region 302 , please refer to FIG. 11 to FIG. 13 .
  • the optical waveguide G has a front end and an end, and extends generally in the second direction (Y) from the front end to the end thereof.
  • the extending direction of the optical waveguide G from its front end to the end forms a certain angle with the second direction (Y), so that there is a space between its front end and the front end of the second P-type doped II region 3022, and its end
  • the ends of the second P-type doped II region 3022 are close to each other.
  • the front end of the optical waveguide G is close to the first P-type doped region 301 and the end is close to the part of the fourth height H4 of the second P-type doped region 302 .
  • the close means that the two are in contact with each other, or the two are separated by a small distance.
  • the front end of the optical waveguide G is preferably spaced from the first P-type doped region 301 at a certain distance, for example, 800nm, so as to prevent the dopant in the first P-type doped region 301 from producing an effect on the light in the optical waveguide. Influence.
  • the end of the optical waveguide G is in contact with the part of the fourth height H4 of the second P-type doped region 302 .
  • the end of the optical waveguide G is close to the second semiconductor layer 400 .
  • Light is incident into the optical waveguide G along the Y direction, and then passes through the second P-type doped II region 3022 of the second P-type doped region 302 and is absorbed by the second semiconductor layer 400 .
  • the second P-type doped II region 3022 not only serves as a channel for electron transmission, but also serves as a medium for light waves to propagate to the second semiconductor layer.
  • the optical waveguide is undoped or lightly doped. Since the second P-type doped I region 3021 of the second P-type doped region 302 below the optical waveguide is P-type doped, therefore, in the actual process, ion implantation is physically blocked by the optical waveguide. By setting appropriate doping conditions, the second P-type doped I region 3021 can achieve P-type doping and at the same time make the optical waveguide close to the intrinsic state.
  • the incident light can be limited to propagate therein, reducing the light propagation loss and improving the light propagation efficiency.
  • the P-type doped II region 3022 is coupled to the second semiconductor, and this process is relatively slow and thus relatively stable.
  • the optical waveguide G transfers the energy of the light to the second semiconductor layer via the second P-type doped II region 3022 of the second P-type doped region 302 400.
  • the second semiconductor layer 400 is capable of absorbing photons in an optical signal. According to the photoelectric effect proposed by Einstein, one photon generates one photogenerated electron. Therefore, the second semiconductor layer 400 absorbs photons and generates electrons, which are photo-generated electrons.
  • the second semiconductor layer 400 covers part of the second P-type doped region 302 and part of the third P-type doped region 305, so that the second P-type doped region 302 and the third P-type doped region
  • the impurity regions 305 are bridged to form a path for carriers.
  • the above-mentioned photo-generated electrons can move from the second P-type doped region 302 to the third P-type doped region 305 under the action of the electric field.
  • the avalanche photodetector of this embodiment further includes a first electrode 501 , a second electrode 502 and a third electrode 503 .
  • the first electrode 501 is electrically connected to the first N-type doped region 308; the second electrode 502 is electrically connected to the third P-type doped region 305, and the third electrode 503 is electrically connected to the The first P-type doped region 301 is electrically connected.
  • the first electrode 501, the second electrode 502 and the third electrode 503 electrically connected to the first N-type doped region 308, the third P-type doped region 305 and the first P-type doped region 301 can pass through the first
  • the first bias voltage V 1 is provided between the electrode 501 and the third electrode 503 so as to provide the first bias voltage V 1 between the first N-type doped region 308 and the first P-type doped region 301 .
  • a second bias voltage V 2 is provided between the first electrode 501 and the second electrode 502 so as to provide an external second bias voltage V 2 between the first N-type doped region 308 and the third P-type doped region 305 .
  • the second semiconductor layer 400 serving as an absorption region connects the second P-type doped region 302 and the third P-type doped region 305 to form a path for carriers. Therefore, when an electric field is applied between the first N-type doped region 308 and the first P-type doped region 301 (ie, through the first bias voltage V 1 ), it can be used to adjust the energy of the above-mentioned photogenerated electrons.
  • the second intrinsic The region 306 is used as an avalanche region, so the second bias voltage V 2 can regulate the electric field distribution of the avalanche region.
  • the avalanche region of the avalanche photodetector refers to the region where the multiplication of carriers (here, electrons) occurs, so it can also be called the multiplication region.
  • the absorption region of the avalanche photodetector can convert the incident light signal into multiple electrons, and these electron pairs flow under the action of an electric field to form a photocurrent; the avalanche region can further excite a small amount of electrons formed in the absorption region through the avalanche effect, forming A large number of electrons are used to achieve amplification; finally, photoelectric current is conducted through a pair of metal electrodes to realize photodetection.
  • the photogenerated electrons are accelerated to the second intrinsic region 306 for multiplication.
  • the photogenerated electrons collide with other carriers incorporated in the semiconductor atomic lattice, thereby generating more free carriers through a process called "impact ionization.” These new free carriers are also accelerated by the applied electric field and generate more free carriers.
  • the arrangement of the third N-doped region 303, the first intrinsic region 304, and the third P-doped region 305 of the avalanche photodetector in the embodiment of the present disclosure, and the third N-doped region are favorable for the electric field distribution in the second semiconductor layer 400 as an absorption region. Due to the existence of the first intrinsic region 304 , electrons cannot pass through the first intrinsic region 304 even under the action of the first bias voltage V 1 , and the first intrinsic region 304 plays a certain blocking role.
  • Electrons from the direction of the second P-doped region 302 can pass through the third N-doped region 303 , pass through the second semiconductor layer 400 , and then go to the avalanche region through the third P-doped region 305 .
  • the existing avalanche photodetectors only apply a bias voltage across the avalanche region, which has some disadvantages, for example, the absorption region and the avalanche region (also known as the multiplication region) are not easy to adjust independently, The concentration accuracy of the doped region is too high, and the process tolerance is low, which easily leads to unsatisfactory gain bandwidth.
  • the present disclosure simultaneously sets a bias voltage at both ends of the absorption region and the avalanche region of the avalanche photodetector, that is, a first bias voltage is provided between the first P-doped region 301 and the first N-doped region 308 .
  • the voltage V 1 is set, and a second bias voltage V 2 is provided between the first N-doped region 308 and the third P-type doped region 305 .
  • V 2 is provided between the first N-doped region 308 and the third P-type doped region 305 .
  • first bias voltage V 1 and the bias voltage V 2 are relatively independent, and the first bias voltage V 1 acts on the absorption region, and its value may be 1 to 4 volts. And the second bias voltage V 2 acts on the avalanche region, and its value can be 3 to 20 volts.
  • the size of the second intrinsic region 306 in the first direction X is 50 nm to 800 nm, that is to say, the width of the second intrinsic region 306 is within the above range.
  • the second intrinsic region 306 is the avalanche region of the avalanche photodetector in the embodiment of the present disclosure
  • the size of the second intrinsic region 306 in the first direction X should not be too small. For example, when it is smaller than 50nm, the electrons moving from the absorption region do not have sufficient avalanche space, cannot be absorbed effectively, and the multiplication effect is poor. Its size should not be too large, otherwise the voltage required at both ends of the avalanche area is too high, and the time for electrons to avalanche is too long, the response will be reduced, and the detection effect will be affected.
  • the size of the second semiconductor layer in the first direction X is 150 nm to 1500 nm
  • the size in the second direction Y is 1 ⁇ m to 100 ⁇ m
  • the size in the third direction Z is 150 nm to 150 nm. 600nm.
  • the size of the second semiconductor layer in the embodiments of the present disclosure is limited within the above range, which can reduce the generation of dark current while reducing noise.
  • the difference in size between the upper and lower surfaces of the second semiconductor layer during the epitaxial growth process may not be considered.
  • the shape of the second semiconductor layer 400 parallel to the substrate 10 can be a regular rectangle, see FIG. 4 or FIG. 7 or FIG. Dimensions of the chamfered trapezoid, see Figure 1.
  • the avalanche photodetector of the present disclosure may also include a covering layer covering the first semiconductor layer 300, the second semiconductor layer 400, the first electrode 501, the second electrode 502 and the third electrode 503 (see FIG. 15e or FIG. 16g) .
  • the structure of the avalanche photodetector of the present disclosure can also be its own mirror structure.
  • One direction X' is from left to right. Therefore, the avalanche photodetector and its mirror image structure provided by the embodiments of the present disclosure are within the protection scope of the present disclosure.
  • the avalanche photodetector provided by the embodiment of the present disclosure includes: a substrate, the surface of which includes a first semiconductor layer; a second semiconductor layer located on the first semiconductor layer, and the material of the second semiconductor layer A material different from the first semiconductor layer; wherein, the first semiconductor layer includes a first P-type doped region, a second P-type doped region, and a third N-type doped region arranged in sequence in the first direction.
  • the first to third P-type doped regions are sequentially decreased, and the dopant concentrations in the first to third N-type doped regions are sequentially decreased, the first direction is the electron flow direction of the avalanche photodetector; the second The semiconductor layer sequentially covers part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region along the first direction, the The first N-type doped region is connected with the first electrode; the third P-type doped region is connected with the second electrode; the first P-type doped region is connected with the third electrode.
  • the fabrication is relatively simple, which is beneficial to reduce costs; in addition, due to the first
  • the N-type doped region is connected to the first electrode, the third P-type doped region is connected to the second electrode, and the first P-type doped region is connected to the third electrode. Subsequent biases can be independently applied to the three electrodes. Therefore, the electric field located in the second semiconductor layer as the absorption region and the second intrinsic region as the avalanche region can be independently adjusted, and the tolerance to the concentration accuracy of the doped region is better, which is conducive to realizing low noise and high gain bandwidth.
  • the embodiment of the present disclosure also provides a method for manufacturing an avalanche photodetector, please refer to FIG. 14 for details. As shown in Figure 14, the method includes the following steps:
  • Step 201 providing a substrate, the surface of which includes a first semiconductor layer;
  • Step 202 Perform a selective doping process to form sequentially arranged first P-type doped regions, second P-type doped regions, and third N-type doped regions on the first semiconductor layer along the first direction. region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region, and a first N-type doped region;
  • Step 203 forming a second semiconductor layer, the material of the second semiconductor layer is different from the material of the first semiconductor layer, and sequentially covering part of the second P-type doped region, the second semiconductor layer in the first direction Three N-type doped regions, the first intrinsic region and part of the third P-type doped region;
  • Step 204 forming a first electrode, a second electrode and a third electrode arranged perpendicular to the direction of the substrate plane, the first electrode is electrically connected to the first N-type doped region; the second electrode is electrically connected to the first N-type doped region; The third P-type doped region is electrically connected, and the third electrode is electrically connected to the first P-type doped region.
  • the above-mentioned first direction is the electron flow direction of the avalanche photodetector.
  • Figure 15a- Figure 15e is a cross-sectional view of the device structure during the preparation process of an avalanche photodetector provided by an embodiment of the present disclosure
  • Figure 16a- Figure 16g is a preparation process of another avalanche photodetector provided by an embodiment of the present disclosure
  • Cross-sectional view of the device structure is a cross-sectional view of the device structure.
  • the avalanche photodetector provided by the embodiments of the present disclosure and its preparation method will be further described in detail in conjunction with the cross-sectional view of the device structure during the preparation process of the avalanche photodetector in FIG. 15a-FIG. 15e.
  • step 201 is executed.
  • a substrate is provided that includes a first semiconductor layer.
  • a substrate 10 is provided; the substrate 10 may include a multilayer structure, and a functional layer is further grown on the multilayer structure. Therefore, the substrate 10 of the present disclosure may include a multilayer structure, wherein the surface of the substrate 10 includes the first semiconductor layer 300, and the layer located below the surface may include a single semiconductor material (such as silicon (Si), germanium ( Ge) etc.), compound semiconductor materials (such as silicon germanium (SiGe) etc.)
  • a single semiconductor material such as silicon (Si), germanium ( Ge) etc.
  • compound semiconductor materials such as silicon germanium (SiGe) etc.
  • the embodiment of the present application is described by taking the substrate 10 as an example of SOI. It can be understood that the first semiconductor layer 300 is located on the surface of the substrate 10 of the present disclosure.
  • the substrate 10 further includes an intermediate layer 200 (which may be an insulating layer in practical application) and a bottom layer 100 (which may be a silicon layer in practical application) located under the first semiconductor layer 300 .
  • the insulating layer 200 is, for example, a silicon dioxide layer, which can be directly obtained by thermally oxidizing the bottom layer 100 .
  • the bottom layer 100 may have a thicker thickness than the first semiconductor layer 300 .
  • step 202 is executed.
  • Fig. 15b Executing a selective doping process to form a first P-type doped region 301, a second P-type doped region 302, and a third N-type doped region arranged in sequence along the first direction on the first semiconductor layer 300.
  • region 303 a first intrinsic region 304 , a third P-type doped region 305 , a second intrinsic region 306 , a second N-type doped region 307 and a first N-type doped region 308 .
  • the mask photolithography process can be used to sequentially open windows in the regions to be doped. Subsequently, ion implantation is performed in the window to form the aforementioned doped regions with different doping concentrations.
  • the doping concentration of the first P-type doped region or the first N-type doped region is 1 ⁇ 10 20 /cm 3 to 5 ⁇ 10 20 /cm 3
  • the second P-type The doping concentration of the doped region or the second N-type doped region is 2 ⁇ 10 17 /cm 3 to 5 ⁇ 10 18 /cm 3
  • the third P-type doped region or the third N-type doped region The doping concentration of the doped region is 1.2 ⁇ 10 17 -4 ⁇ 10 17 /cm 3 .
  • the dopant in the first P-type doped region 301, the second P-type doped region 302, and the third P-type doped region 305 is boron (B) element; and the first N-type doped region
  • the dopant of the impurity region 308 , the second N-type doped region 307 and the third N-type doped region 303 is phosphorus (P) or arsenic (As).
  • the method also includes:
  • a height different from that of other regions in the first semiconductor layer in a direction perpendicular to the substrate is formed in a direction perpendicular to the substrate.
  • the partial region of the second P-type doped region, the partial region of the third P-type doped region, the first intrinsic region and the third In the region of the N-type doped region a different height is formed in the direction perpendicular to the substrate than in other regions of the first semiconductor layer in the direction perpendicular to the substrate, including:
  • the formed height H 1 is greater than the height H 2 formed in the direction perpendicular to the substrate in other regions of the first semiconductor layer.
  • the partial region of the second P-type doped region, the partial region of the third P-type doped region, the first intrinsic region and the second P-type doped region are to be formed.
  • a different height is formed in the direction perpendicular to the substrate than in other regions of the first semiconductor layer in the direction perpendicular to the substrate, including:
  • the formed height H 1 is smaller than the height H 2 formed in the direction perpendicular to the substrate in other regions of the first semiconductor layer.
  • the impurity region has a height different from that of other regions in the first semiconductor layer in a direction perpendicular to the substrate, and correspondingly covers part of the second P-type doped region, part of the third P-type doped region, the first The height of the second semiconductor layer in the constitutive region and the third N-type doped region is also different accordingly.
  • the other parts of the two avalanche photodetectors are the same.
  • this paper will representatively use Height H of part of the second P-type doped region, part of the third P-type doped region, first intrinsic region, and third N-type doped region in the direction perpendicular to the substrate in the first semiconductor layer 1 is greater than the height H 2 of other regions in the first semiconductor layer to illustrate the preparation method of the avalanche photodetector provided by the embodiments of the present disclosure.
  • the partial region of the second P-type doped region 302, the partial region of the third P-type doped region 303, the first intrinsic region 304 and the third N-type doped region are to be formed.
  • a height different from that of other regions in the first semiconductor layer 300 is formed in the direction (Z direction) perpendicular to the substrate.
  • a combination of processes such as photolithography and etching can be used to achieve Different heights for different areas.
  • the method includes: vertically The height H 1 formed in the direction of the substrate is greater than the height H 2 of other regions in the first semiconductor layer.
  • step 203 is performed.
  • the second semiconductor layer 400 is formed, and covers the first intrinsic region 304 and the third N-type doped region 303 in the first direction X, and covers part of the second P-type doped region 302 and The third P-type doped region 305 .
  • an initial second semiconductor layer 400' (not shown in FIG. 15c) covering the first semiconductor material 300 is first formed, and then the initial second semiconductor layer 400' is etched using a patterned photoresist layer. etch to form the second semiconductor layer 400, and then remove the photoresist layer.
  • the formed second semiconductor layer 400 has a rectangular shape (for its shape, refer to the second semiconductor layer 400 in FIG. 4 ), or a trapezoidal shape (for its shape, refer to the second semiconductor layer 400 in FIG. 1 ).
  • the material of the first semiconductor layer is different from the material of the second semiconductor layer.
  • the material of the first semiconductor layer is Si
  • the material of the second semiconductor layer is germanium, germanium silicon alloy, III-V group material and alloy thereof.
  • the material of the first semiconductor layer is silicon
  • the material of the second semiconductor layer is germanium.
  • the avalanche photodetector of the embodiment of the present disclosure is germanium Silicon avalanche photodetectors.
  • the high-quality polycrystalline germanium material can be epitaxially grown by molecular beam epitaxy and other techniques, that is, the second semiconductor layer can be formed.
  • step 204 proceeds to step 204 .
  • the first electrode 501 is electrically connected to the first N-type doped region 308;
  • the second The electrode 502 is electrically connected to the third P-type doped region 305 , and
  • the third electrode 503 is electrically connected to the first P-type doped region 301 .
  • the formation of the first electrode 501, the second electrode 502 and the third electrode 503 arranged perpendicular to the direction of the substrate plane includes:
  • Metal material is filled in the first window, the second window and the third window to form the first electrode 501 , the second electrode 502 and the third electrode 503 .
  • the covering layer 600 can be directly formed using insulating materials.
  • an insulating material such as silicon dioxide may be used to form a capping layer 600 to cover the doped first semiconductor layer 300 and the second semiconductor layer 400 first. Then use photolithography and inductive plasma etching to open a window on the cover layer 600 to form a first window, a second window and a third window to expose the first N-type doped region 308 in the first semiconductor layer 300 , the surface of the third P-type doped region 305 and the first P-type doped region 301, and then deposit metal materials in the first window, the second window and the third window by using, for example, a magnetron sputtering process, to respectively form and
  • the first N-type doped region 308 , the third P-type doped region 305 and the first P-type doped region 301 are electrically connected to the first electrode 501 , the second electrode 502 and the third electrode 503 .
  • a step of planarizing the upper surface of the covering layer 600 may also be performed, specifically, a chemical mechanical polishing (CMP) process may be used.
  • CMP chemical mechanical polishing
  • the avalanche photodetector provided by the embodiments of the present disclosure and the preparation method thereof will be further described in conjunction with the cross-sectional view of the device structure in FIG. 16a-FIG. 16g during the preparation process of the avalanche photodetector.
  • step 201 is executed.
  • a substrate is provided, the substrate comprising a first semiconductor layer.
  • two wedge-shaped grooves C are formed on a part of the region where the second P-type doped region is to be formed and is adjacent to the first P-type doped region; refer to FIG. 16b and FIG. 16c.
  • a part of the first semiconductor layer G remains between the two wedge-shaped grooves C, and the remaining part of the first semiconductor layer G is not doped or lightly doped; here, this part of the first semiconductor layer G No doping or light doping is used to serve as an optical waveguide in the formed photodetector to transfer light energy to subsequent parts.
  • the above two wedge-shaped grooves C may be formed by combining etching with a mask, thereby forming part of the first semiconductor layer G in the two wedge-shaped grooves C.
  • step 202 is performed.
  • step 202 is performed.
  • region 303 a first intrinsic region 304 , a third P-type doped region 305 , a second intrinsic region 306 , a second N-type doped region 307 and a first N-type doped region 308 .
  • the portion of the first semiconductor layer G remaining between the two wedge-shaped grooves C is undoped or lightly doped. Open the window in the area. Subsequently, ion implantation is performed in the window to form the aforementioned doped regions with different doping concentrations. By using a suitable ion implantation process, a part of the first semiconductor layer G is undoped or lightly doped.
  • step 203 is performed.
  • the second semiconductor layer 400 is formed, and covers the first intrinsic region 304 and the third N-type doped region 303 in the first direction X, and covers part of the second P-type doped region 302 and The third P-type doped region 305 .
  • step 204 is performed. See Figure 16f. Forming a first electrode 501, a second electrode 502 and a third electrode 503 arranged perpendicular to the direction of the substrate plane, the first electrode 501 is electrically connected to the first N-type doped region 308; the second The electrode 502 is electrically connected to the third P-type doped region 305 , and the third electrode 503 is electrically connected to the first P-type doped region 301 .
  • the formation of the first electrode 501, the second electrode 502 and the third electrode 503 arranged perpendicular to the direction of the substrate plane includes:
  • Metal material is filled in the first window, the second window and the third window to form the first electrode 501 , the second electrode 502 and the third electrode 503 .
  • the embodiment of the avalanche photodetector provided by the present disclosure and the embodiment of the preparation method of the avalanche photodetector belong to the same concept; the technical features in the technical solutions recorded in each embodiment, in the case of no conflict , can be combined arbitrarily.
  • the combination of various technical features of the avalanche photodetectors provided by the embodiments of the present disclosure can already solve the technical problems to be solved by the present disclosure; therefore, the avalanche photodetectors provided by the embodiments of the present disclosure can not
  • the limitation of the preparation method of the avalanche photodetector provided by the embodiment of the present disclosure any avalanche photodetector prepared by the preparation method capable of forming the structure of the avalanche photodetector provided by the embodiment of the present disclosure is within the protection scope of the present disclosure .

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Abstract

本公开提供了雪崩光电探测器及其制备方法。其中，雪崩光电探测器包括：衬底，其表面包括第一半导体层；位于衬底之上的第二半导体层，第一半导体层包括第一方向上依次排列的第一P型掺杂区、第二P型掺杂区、第三N型掺杂区、第一本征区、第三P型掺杂区、第二本征区、第二N型掺杂区和第一N型掺杂区，第一至第三P型掺杂区的掺杂剂浓度依次递减，第一至第三N型掺杂区的掺杂剂浓度依次递减，第一方向为电子流动方向；第二半导体层在第一方向上依次覆盖部分第二P型掺杂区、第三N型掺杂区、第一本征区和所述第三P型掺杂区；第一N型掺杂区连接第一电极；第三P型掺杂区连接第二电极；第一N型掺杂区连接第三电极。

Description

雪崩光电探测器及其制备方法
相关申请的交叉引用
本申请基于申请号为202111643459.X、202111633301.4以及202111633446.4、申请日均为2021年12月29日的三个中国专利申请提出，并要求该三个中国专利申请的优先权，该三个中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开实施例涉及但不限于一种雪崩光电探测器及其制备方法。
背景技术
雪崩光电探测器作为硅光子架构的核心器件之一，具有实现低功率光信号到电信号转换的功能，其工作原理是通过光电效应产生的光生载流子(空穴电子对)，在高电场区运动时被迅速加速，运动过程中可能发生一次或多次碰撞，通过碰撞电离效应产生二次、三次新的空穴电子对，产生雪崩倍增效应，使载流子数量迅速增加，从而形成比较大的光信号电流。
目前，在硅光子集成芯片中广泛采用兼容CMOS工艺的锗硅材料实现雪崩光电探测，它是利用硅材料作为光波导，同时作为雪崩增益区(也称为倍增区)，而锗材料吸收光子。目前该锗硅雪崩光电探测器结构的不足如下：一是需要外延单晶硅工艺，制作相对复杂；二是吸收区通常会被P或N型掺杂，这些掺杂都会造成光吸收损耗，继而降低探测器量子效率；三是吸收区和倍增区不易独立调节，对掺杂区浓度精度要过较高，工艺容忍度低，容易导致增益带宽不理想。因此采用锗硅材料的雪崩光电探测器有待进一步的改进。
发明内容
本公开实施例一方面提供了一种雪崩光电探测器，包括：
衬底，所述衬底的表面包括第一半导体层；
位于所述第一半导体层之上的第二半导体层，所述第二半导体层的材料不同于所述第一半导体层的材料；其中，
所述第一半导体层包括在第一方向上依次排列的第一P型掺杂区、第二P型掺杂区、第三N型掺杂区、第一本征区、第三P型掺杂区、第二本征区、第二N型掺杂区和第一N型掺杂区，所述第一至第三P型掺杂区的掺杂剂浓度依次递减，且所述第一至第三N型掺杂区的掺杂剂浓度依次递减，所述第一方向为所述雪崩光电探测器的电子流动方向；
所述第二半导体层沿所述第一方向依次覆盖部分所述第二P型掺杂区、第三N型掺杂区、所述第一本征区和部分所述第三P型掺杂区；
所述第一N型掺杂区连接有第一电极；所述第三P型掺杂区连接有第二电极；所述第一P型掺杂区连接有第三电极。
在一些实施例中，所述第一半导体层中的第一本征区、第三N型掺杂区、紧邻所述第三N型掺杂区的第二P型掺杂区的部分、紧邻所述第一本征区的第三P型掺杂区的部分在垂直于所述衬底的方向上具有第一高度H 1，所述第一半导体层中其他区域具有第二高度H 2；H 1不等于H 2；
所述第二半导体层沿所述第一方向依次覆盖所述第二P型掺杂区具有第二高度H 2的区域的一部分、所述第二P型掺杂区具有第一高度H 1的区域、所述第三N型掺杂区、所述第一本征区、所述第三P型掺杂区具有第一高度H 1的区域和所述第三P型掺杂区具有第二高度H 2的区域的一部分。
在一些实施例中，H 1大于H 2。
在一些实施例中，H 1小于H 2。
在一些实施例中，所述雪崩光电探测器还包括：
光波导，所述光波导位于所述第一半导体层之上，包括靠近光入射端的前端和远离所述光入射端的末端；
所述第一半导体层中的第二P型掺杂区的紧邻所述第一P型掺杂区的部分区域具有的第三高度H 3低于第一半导体层中其他区域具有的第四高度H 4以形成沿第二方向上延伸的槽，所述第二方向为垂直于所述第一方向且平行于所述衬底表面的方向；
所述第二半导体层沿所述第一方向依次覆盖所述第二P型掺杂区的第四高度H 4的部分区域、所述第三N型掺杂区、所述第一本征区和所述第三P型掺杂区的部分区域；
所述光波导位于所述槽中且布置成大体沿第二方向延伸且与第二方向成预设夹角，以使其前端靠近所述第一P型掺杂区且末端靠近所述第二P型掺杂区的第四高度H 4的部分。
在一些实施例中，所述光波导是未掺杂的或轻掺杂的。
在一些实施例中，所述第一电极和第三电极之间设置有第一反向偏置电压V 1，且所述第一电极和第二电极之间设置有第二反向偏置电压V 2。
在一些实施例中，所述第一半导体层的材料为硅，且所述第二半导体层的材料为锗、锗硅合金、III-V族材料及其合金。
在一些实施例中，所述第一P型掺杂区或所述第一N型掺杂区的掺杂剂浓度为1×10 20/cm 3～5×10 20/cm 3，所述第二P型掺杂区或所述第二N型掺杂区的掺杂剂浓度为2×10 17/cm 3～5×10 18/cm 3，所述第三P型掺杂区或所述第三N型掺杂区的掺杂剂浓度为1.2×10 17～4×10 17/cm 3。
在一些实施例中，所述第二本征区在所述第一方向上的尺寸为50nm至800nm。
在一些实施例中，所述第二半导体层在所述第一方向上的尺寸为150nm至1500nm，在第二方向上的尺寸为1μm至100μm，并且在第三方向 上的尺寸为150nm至600nm，其中，所述第三方向为垂直于所述衬底的方向，且所述第二方向垂直于所述第三方向且垂直于所述第一方向。
本公开实施例还提供了一种雪崩光电探测器的制备方法，包括：
提供衬底，所述衬底的表面上包括第一半导体层；
执行选择性掺杂工艺，以在所述第一半导体层上沿第一方向上形成依次排列的第一P型掺杂区、第二P型掺杂区、第三N型掺杂区、第一本征区、第三P型掺杂区、第二本征区、第二N型掺杂区和第一N型掺杂区，所述第一至第三P型掺杂区的掺杂剂浓度依次递减，且所述第一至第三N型掺杂区的掺杂剂浓度依次递减；
形成第二半导体层，所述第二半导体层的材料不同于所述第一半导体层的材料，且在所述第一方向上依次覆盖部分所述第二P型掺杂区、所述第三N型掺杂区、所述第一本征区和部分所述第三P型掺杂区；
形成垂直所述衬底平面方向而设置的第一电极、第二电极和第三电极，所述第一电极与所述第一N型掺杂区电连接；所述第二电极与所述第三P型掺杂区电连接，且所述第三电极与所述第一P型掺杂区电连接；
所述第一方向为所述雪崩光电探测器的电子流动方向。
在一些实施例中，所述方法还包括：
在执行选择性掺杂工艺之前，在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成与所述第一半导体层中其他区域垂直于所述衬底的方向上不同的高度。
在一些实施例中，所述在执行选择性掺杂工艺之前，在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成与所述第一半导体层中其他区域垂直于所述衬底的方向上不同的高度，包括：
在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成的高度H 1大于所述第一半导体层中其他区域垂直于所述衬底的方向上形成的高度H 2。
在一些实施例中，所述在执行选择性掺杂工艺之前，在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成与所述第一半导体层中其他区域垂直于所述衬底的方向上不同的高度，包括：
在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成的高度H 1小于所述第一半导体层中其他区域垂直于所述衬底的方向上形成的高度H 2。
在一些实施例中，所述方法还包括：
在执行选择性掺杂工艺之前，在待形成所述第二P型掺杂区的紧邻所述第一P型掺杂区的部分区域上形成两个楔形槽，以在所述两个楔形槽之间保留部分第一半导体层。
在一些实施例中，所述保留的部分第一半导体层是不掺杂或轻掺杂的。
在一些实施例中，所述第一半导体层的材料为硅，且所述第二半导体层的材料为锗、锗硅合金、III-V族材料及其合金。
在一些实施例中，所述第一P型掺杂区或所述第一N型掺杂区的掺杂剂浓度为1×10 20/cm 3～5×10 20/cm 3，所述第二P型掺杂区或所述第二N型掺杂区的掺杂剂浓度为2×10 17/cm 3～5×10 18/cm 3，所述第三P型掺杂区或所述第三N型掺杂区的掺杂剂浓度为1.2×10 17～4×10 17/cm 3。
在一些实施例中，所述形成垂直所述衬底平面方向而设置的第一电极、第二电极和第三电极包括：
形成覆盖所述第一半导体层和所述第二半导体层的覆盖层；
分别在所述第一N型掺杂区、所述第三P型掺杂区和所述第一P型掺杂区的沿第二方向的一端形成第一窗口、第二窗口和第三窗口，以暴露述第一P型掺杂区、所述第三P型掺杂区和所述第一N型掺杂区的部分表面；所述第二方向为垂直于所述第一方向且平行于所述衬底的方向；
在所述第一窗口、第二窗口和第三窗口填充金属以形成第一电极、第二电极和第三电极。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1至图3为本公开实施例提供的一种雪崩光电探测器的结构示意图；
图4至图6为本公开实施例提供的另一种雪崩光电探测器的结构示意图；
图7至图9为本公开实施例提供的又一种雪崩光电探测器的结构示意图；
图10至图13为本公开实施例提供的再一种雪崩光电探测器的结构示意图；
图14为本公开实施例提供的雪崩光电探测器的制备方法的流程示意图；
图15a至图15e为本公开实施例提供的一种雪崩光电探测器的制备过程中的器件结构剖视图；
图16a至图16g为本公开实施例提供的另一种雪崩光电探测器的制备过程中的器件结构剖视图。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚，以下结合说明书附图及具体实施例对本公开的技术方案做进一步的详细阐述。
在本公开实施例中，术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。
在本公开实施例中，除非另有明确的规定和限定，半导体结构中的两层之间的“上”或“下”关系可以是两层之间直接接触，或两层通过中间层间接接触。
在本公开实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如，层可位于连续结构的顶面和底面之间，或者层可在连续结构顶面和底面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延伸。并且，层可以包括多个子层。
在本公开实施例中，空间相对术语，例如“之下”、“下方”、“下”、“上方”、“上”、“朝上”、“朝下”等在本文中为了便于描述可以描述一个元素或特征与另一个(多个)元素或(多个)特征的关系，如图中所示。空间相对术语旨在涵盖在使用或操作中的除了图中描绘的取向之外的器件的不同取向。装置可以以其它方式取向(旋转90度或在其它取向下)，并且本文所使用的空间相对描述符也可以相应地进行解释。
硅光子技术是基于硅和硅基衬底材料(如SiGe/Si、绝缘体上硅等)，利用现有互补金属氧化物半导体(CMOS)工艺进行光器件开发和集成的新一代技术。硅光子技术结合了集成电路技术的超大规模、超高精度制造的特性和光子技术超高速率、超低功耗的优势，是应对摩尔定律失效的颠覆性技术。这种结合得益于半导体晶圆制造的可扩展性，因而能够降低成本。 光电探测器作为硅光子架构的核心器件之一，具有实现光信号到电信号转换的功能。目前该锗硅雪崩光电探测器结构的不足如下：一是需要外延单晶硅工艺，制作相对复杂；二是吸收区通常会被P或N型掺杂，这些掺杂都会造成光吸收损耗，继而降低探测器量子效率；三是吸收区和雪崩区(也称为倍增区)不易独立调节，对掺杂区浓度精度要过较高，工艺容忍度低，容易导致增益带宽不理想。
基于此，提出了本申请实施例的以下技术方案。
本公开实施例提供了一种雪崩光电探测器，包括：
衬底，所述衬底的表面包括第一半导体层；
位于所述第一半导体层之上的第二半导体层，所述第二半导体层的材料不同于所述第一半导体层的材料；其中，
所述第一半导体层包括在第一方向上依次排列的第一P型掺杂区、第二P型掺杂区、第三N型掺杂区、第一本征区、第三P型掺杂区、第二本征区、第二N型掺杂区和第一N型掺杂区，所述第一至第三P型掺杂区的掺杂剂浓度依次递减，且所述第一至第三N型掺杂区的掺杂剂浓度依次递减，所述第一方向为所述雪崩光电探测器的电子流动方向；
所述第二半导体层沿所述第一方向依次覆盖部分所述第二P型掺杂区、第三N型掺杂区、所述第一本征区和部分所述第三P型掺杂区，
所述第一N型掺杂区连接有第一电极；所述第三P型掺杂区连接有第二电极；所述第一P型掺杂区连接有第三电极。
以下，请具体参见图1至图3，其中，图1为本公开实施例提供的一种雪崩光电探测器的轴测示意图；图2为本公开实施例提供的一种雪崩光电探测器的俯视示意图；图3为本公开实施例提供的一种雪崩光电探测器沿Y方向的示意图。
结合图1至图3，所述雪崩光电探测器包括：
衬底10，所述衬底包括第一半导体层300；在所述第一半导体层300中形成有所述雪崩光电探测器的雪崩区以实现雪崩效果；
第二半导体层400，其采用不同于第一半导体层300的材料。
以下将详细介绍本公开雪崩光电探测器中各个部分的布局情况。
这里，衬底可为多层结构，其中，衬底的顶部为第一半导体层，之下可以包括单质半导体材料(例如为硅(Si)、锗(Ge)等)、复合半导体材料(例如为锗硅(SiGe)等)构成的层以及其氧化物构成的绝缘层。该实例中，衬底10可以是绝缘体上硅(SOI)或绝缘体上锗(GeOI)等。
本申请实施例以所述衬底表面下方的层为SOI为例进行说明。可以理解，所述第一半导体层300位于本公开衬底10的顶部。
在一些实施例中，第一半导体层300的材料包括硅。位于第一半导体层300下方的层依次包括绝缘层200和底层100。
实际应用中，底层100可以是硅晶圆，也可以是其他材料形成的晶圆。因此底层100的材料可以是硅、锗或蓝宝石等。
在一些实施例中，底层100的材料是硅，对应地，绝缘层200的材料则可以硅的氧化物，例如二氧化硅
所述底层100与所述第一半导体层300相比可以具有更厚的厚度。应当理解，图中为了使得各层结构均能被清晰地示出，可能造成各层结构的尺寸比例关系与实际结构不符。
需要说明的是，为了便于描述，如图1所示，本公开实施例中借助第一方向(X)、第二方向(Y)和第三方向(Z)来描述(参见图1所示)。
这里，衬底10可以包括处于正面的顶表面以及处于与正面相对的背面的底表面；在忽略顶表面和底表面的平整度的情况下，定义垂直衬底顶表面和底表面的方向为第三方向(Z)。第三方向Z也为后续在衬底上沉积各层结构的层叠方向，或称器件的高度方向。衬底顶表面和底表面所在的面， 或者严格意义上讲衬底厚度方向上的中心面，确定为衬底平面。在所述衬底平面方向上定义两彼此相交的(例如为彼此垂直的)第一方向(X)和第二方向(Y)。在本实施例中，所述第一方向X为电子流动方向；所述第二方向Y为光信号的传播方向。
由于理论上，在雪崩光电探测器中的第一半导体层300的材料可采用任何半导体材料，因此这里并不对第一半导体材料进行严格限定。在所述衬底10包括单质Si底层100的实施例中，所述第一半导体材料为Si。
为了使所述雪崩光电探测器实现雪崩效应，所述雪崩光电探测器的第一半导体层300形成的不同的区域具有不同的掺杂区域，包括掺杂不同浓度的P型掺杂剂、N型掺杂剂，以及未被掺杂的区域(本征区)。
以下将详细说明根据本公开实施例的雪崩光电探测器的第一半导体层300的结构。在一些实施例中，雪崩光电探测器中第一半导体层300包括在第一方向X上依次排列的第一P型掺杂区301、第二P型掺杂区302、第三N型掺杂区303、第一本征区304、第三P型掺杂区305、第二本征区306、第二N型掺杂区307和第一N型掺杂区308。第一P型掺杂区、第二P型掺杂区、第三P型掺杂区的P型掺杂剂浓度依次递减，且第一N型掺杂区、第二N型掺杂区、第三N型掺杂区的N型掺杂剂浓度依次递减。
在一些实施例中，所述第一半导体层中的第一本征区、第三N型掺杂区、紧邻所述第三N型掺杂区的第二P型掺杂区的部分、紧邻所述第一本征区的第三P型掺杂区的部分在垂直于所述衬底的方向上具有第一高度H 1，所述第一半导体层中其他区域具有第二高度H 2；H 1不等于H 2；
所述第二半导体层沿所述第一方向依次覆盖所述第二P型掺杂区具有第二高度H 2的区域的一部分、所述第二P型掺杂区具有第一高度H 1的区域、所述第三N型掺杂区、所述第一本征区、所述第三P型掺杂区具有第一高度H 1的区域和所述第三P型掺杂区具有第二高度H 2的区域的一部分。
图4至图6为本公开实施例提供的另一种雪崩光电探测器的示意图；其中，图4为轴测示意图；图5为俯视示意图；图6为沿Y方向的示意图。
在一些实施例中，第一半导体层中的部分第二P型掺杂区、部分第三P型掺杂区、第一本征区、第三N型掺杂区在垂直于衬底的方向上的高度H 1大于所述第一半导体层中其他区域的高度H 2。
这种情况下，结合图4和图6，第一半导体层300中的部分第二P型掺杂区302、部分第三P型掺杂区305、第一本征区304、第三N型掺杂区303在垂直于所述衬底的方向(Z方向)上的高度H 1大于所述第一半导体层中其他区域的高度H 2。
可以理解，相对于第一半导体层中其他区域而言，部分第二P型掺杂区302、部分第三P型掺杂区305、第一本征区304、第三N型掺杂区303是突起的。从Y方向的视角来看，部分第二P型掺杂区302、部分第三P型掺杂区305、第一本征区304、第三N型掺杂区303为倒U形形状。
图7至图9为本公开实施例提供的又一种雪崩光电探测器的示意图；其中，图7为轴测示意图；图8为俯视示意图；图9为沿Y方向的示意图。
在一些实施例中，如图7至图9所示，第一半导体层中的部分第二P型掺杂区、部分第三P型掺杂区、第一本征区、第三N型掺杂区在垂直于衬底的方向上的高度H 1大小于所述第一半导体层中其他区域的高度H 2。
这种情况下，结合图7和图9，第一半导体层300中的部分第二P型掺杂区302、部分第三P型掺杂区305、第一本征区304、第三N型掺杂区303在垂直于所述衬底的方向(Z方向)上的高度H 1小于所述第一半导体层300中其他区域的高度H 2。
可以理解，相对于第一半导体300中其他区域而言，部分第二P型掺杂区302、部分第三P型掺杂区305、第一本征区304、第三N型掺杂区303是凹陷的。从Y方向的视角来看，部分第二P型掺杂区302、部分第三P 型掺杂区305、第一本征区304、第三N型掺杂区303为倒U形形状。
在一些实施例中，所述雪崩光电探测器还包括：
光波导，所述光波导位于所述第一半导体层之上，包括靠近光入射端的前端和远离所述光入射端的末端；
所述第一半导体层中的第二P型掺杂区的紧邻所述第一P型掺杂区的部分区域具有的第三高度H 3低于第一半导体层中其他区域具有的第四高度H 4以形成沿第二方向上延伸的槽，所述第二方向为垂直于所述第一方向且平行于所述衬底表面的方向；
所述第二半导体层沿所述第一方向依次覆盖所述第二P型掺杂区的第四高度H 4的部分区域、所述第三N型掺杂区、所述第一本征区和所述第三P型掺杂区的部分区域；
所述光波导位于所述槽中且布置成大体沿第二方向延伸且与第二方向成预设夹角，以使其前端靠近所述第一P型掺杂区且末端靠近所述第二P型掺杂区的第四高度H 4的部分。
图10至图13为本公开实施例提供的再一种雪崩光电探测器的示意图；其中，图10为轴测示意图；图11为俯视示意图；图12为沿Y方向的示意图，图13为图12中的局部放大示意图。
在一些实施例中，如图10至图13所示，雪崩光电探测器还包括位于第一半导体层300的光波导G，其包括包括靠近光入射端的前端和远离所述光入射端的末端。
沿第二方向(Y)第二P型掺杂区302紧邻第一P型掺杂区301的部分具有一个槽。即，第二P型掺杂区302由两部分构成：第二P型掺杂I区3021和第二P型掺杂II区3022，可参考图11至图13。其中第二P型掺杂I区3021，即槽部，在第三方向(Z)上具有小于第一半导体层300中其他区域的高度；其余的第二P型掺杂区302部分为第二P型掺杂II区3022， 其紧邻第三N型掺杂区303，在沿第三方向(Z)上，具有与第一半导体层300中其他区域齐平的高度。需要说明是的，第二P型掺杂区302的两个部分第二P型掺杂I区3021和第二P型掺杂II区3022的掺杂剂浓度是相同的，区别仅在于两者的高度不同。
在一些实施例中，P型掺杂剂可为硼(B)，N型掺杂剂可为磷(P)或砷(As)。
在一些实施例中，第一P型掺杂区301或第一N型掺杂区308的掺杂剂浓度为1×10 20/cm 3～5×10 20/cm 3，第二P型掺杂区302或第二N型掺杂区307的掺杂剂浓度为2×10 17/cm 3～5×10 18/cm 3，第三P型掺杂区305或第三N型掺杂区303的掺杂剂浓度为1.2×10 17～4×10 17/cm 3。
实用应用中，由于本征区被未掺杂或者是轻掺杂的，其浓度一般小于预定值，例如，小于1×10 17/cm 3。
需要说明的是，第一P型掺杂区和第一N型掺杂区的掺杂剂浓度可以相同或不同，只要它们的掺杂浓度在上述范围即可。
同理，第二P型掺杂区和第二N型掺杂区，以及第三P型掺杂区和第三N型掺杂区的掺杂剂浓度也分别可以相同或不同。
对于本征区而言，其可以是未被掺杂或被轻掺杂的第一半导体材料。其中，本征区是具体发生碰撞电离从而产生电子-空穴对的区域。
在本公开的雪崩光电探测器中的第一半导体层300中，雪崩区可以是第二本征区306。
应当理解，雪崩光电探测器是基于在雪崩区之间施加电压，产生电场，从而通过电场抽取光生载流子而形成电流。具体地，所述雪崩区沿第一方向的两侧施加偏置电压，实现光电探测。
在本公开的实施例中，第一半导体层300之上包括第二半导体层400，所述第二半导体层400的材料不同于第一半导体层的材料。
在一些实施例中，第一半导体层300的材料为硅，且第二半导体层400的材料为锗、锗硅合金、III-V族材料及其合金。
在进一步的实施例中，第一半导体层300的材料为硅，且第二半导体层的材料为锗。由此形成的雪崩光电探测器为锗硅光电探测器。
这里，由于本公开的提供的雪崩光电探测器中的作为吸收区的第二半导体层400未被P或N型掺杂且不涉及欧姆接触，能够尽可能地降低光吸收损耗，利于提高量子吸收效率。
本实施例的雪崩光电探测器的第二半导体层400沿所述第一方向依次覆盖部分第二P型掺杂区302、第三N型掺杂区303、第一本征区304和部分第三P型掺杂区305。第二半导体层400形成为所述雪崩光电探测器的吸收区。
在一些实施例中，结合图4和图6，本公开的雪崩光电探测器的第二半导体层400沿第一方向X依次覆盖部分第二P型掺杂区302、第三N型掺杂区303、第一本征区304和部分第三P型掺杂区305，在第一半导体层300中的部分第二P型掺杂区302、部分第三P型掺杂区305、第一本征区304、第三N型掺杂区303在垂直于衬底的方向(Z方向)上的高度H 1大于第一半导体层中其他区域的高度H 2的情况下，第二半导体层400与它们呈空间与补的关系。第二半导体层400形成为雪崩光电探测器的吸收区。
在一些实施例中，结合图7和图9，本实施例的雪崩光电探测器的第二半导体层400沿第一方向X依次覆盖部分第二P型掺杂区302、第三N型掺杂区303、第一本征区304和部分第三P型掺杂区305，在第一半导体层300中的部分第二P型掺杂区302、部分第三P型掺杂区305、第一本征区304、第三N型掺杂区303在垂直于衬底的方向(Z方向)上的高度H 1小于第一半导体层300中其他区域的高度H 2的情况下，第二半导体层400与它们呈空间与补的关系。第二半导体层400形成为雪崩光电探测器的吸收 区。
在以上两种情况下，由于部分第二P型掺杂区、部分第三P型掺杂区、第一本征区、第三N型掺杂区在垂直于衬底的方向上具有与第一半导体层中其他区域不同的高度，且第二半导体层沿第一方向依次覆盖第二P型掺杂区的第二高度H 2的区域的一部分、第二P型掺杂区的第一高度H 1的区域、第三N型掺杂区、第一本征区和第三P型掺杂区的第一高度H 1的区域和第三P型掺杂区的第二高度H 2的区域的一部分，因此，第二半导体层与第二P型掺杂区以及第三P型掺杂区均具有更大的接触面积，能够提高后续参与雪崩效应的电子的传输效率。
同时，未被所述第二半导体层覆盖的所述第二P型掺杂区302中具有槽，且所述槽中具有光波导G。光波导G位于第二P型掺杂I区3021的表面，即位于第二P型掺杂区302的槽中，请参考图11至图13。光波导G具有前端和末端，从其前端至末端大体沿第二方向(Y)延伸。也就是说，光波导G从其前端至末端的延伸方向与第二方向(Y)呈一定夹角，使得其前端与第二P型掺杂II区3022的前端之间具有间隔，而其末端与第二P型掺杂II区3022的末端相互靠近。其中，光波导G的前端靠近第一P型掺杂区301且末端靠近所述第二P型掺杂区302的第四高度H 4的部分。这里，所述靠近是指两者相互接触，或者两者间隔较小的距离。在实际工艺中，光波导G的前端与第一P型掺杂区301优选间隔有一定的距离，例如，800nm，以免第一P型掺杂区301中掺杂剂对光在光波导中产生影响。在实际工艺中，光波导G的末端与所述第二P型掺杂区302的第四高度H 4的部分相接触。从而光波导G的末端靠近第二半导体层400。光沿Y方向入射进入所述光波导G，进而通过第二P型掺杂区302的第二P型掺杂II区3022被第二半导体层400吸收。这里第二P型掺杂II区3022除了作为电子传输的通道，还作为光波导向第二半导体层传播的媒介。
在一些实施例中，所述光波导是未掺杂的或轻掺杂的。由于光波导以下的第二P型掺杂区302的第二P型掺杂I区3021是P型掺杂的，因此，在实际工艺中，离子注入时受到了光波导的物理阻隔。可通过设置合适的掺杂条件，使第二P型掺杂I区3021实现P型掺杂的同时，使光波导接近于本征状态。
通过设置单独的光波导G，能够使入射光限制在其中传播，减少了光传播损失，提高光传播效率，同时，入射光经过光波导G，再经过第二P型掺杂区302的第二P型掺杂II区3022耦合至第二半导体，该过程相对缓慢，因此相对稳定。
这里，当在雪崩光电探测器的光波导G上施加光信号时，光波导G使光的能量经由第二P型掺杂区302的第二P型掺杂II区3022传递至第二半导体层400。第二半导体层400能够吸收光信号中的光子。由爱因斯坦提出的光电效应可知，一个光子产生一个光生电子。因此，第二半导体层400吸收光子并且产生电子，所产生的电子即为光生电子。
请结合图1至图3，第二半导体层400覆盖部分第二P型掺杂区302和部分第三P型掺杂区305，从而将第二P型掺杂区302和第三P型掺杂区305桥接起来，形成载流子的通路。上述光生电子在电场的作用上能够从第二P型掺杂区302移动到第三P型掺杂区305。
继续参考图1至图3，本实施例的雪崩光电探测器还包括第一电极501、第二电极502和第三电极503。所述第一电极501与所述第一N型掺杂区308电连接；所述第二电极502与所述第三P型掺杂区305电连接，且所述第三电极503与所述第一P型掺杂区301电连接。
与第一N型掺杂区308、第三P型掺杂区305和第一P型掺杂区301电连接的第一电极501、第二电极502和第三电极503，能够通过在第一电极501与第三电极503之间提供第一偏置电压V 1从而在第一N型掺杂区 308和第一P型掺杂区301之间提供第一偏置电压V 1，同时通过在第一电极501与第二电极502之间提供第二偏置电压V 2从而在第一N型掺杂区308和第三P型掺杂区305之间提供外加第二偏置电压V 2。
如上所述，作为吸收区的第二半导体层400将第二P型掺杂区302和第三P型掺杂区305连接起来，形成载流子的通路。因此，通过在第一N型掺杂区308和第一P型掺杂区301之间施加电场(即，通过第一偏置电压V 1)时，能够用于调节上述光生电子的能量。
而对于在第三P型掺杂区305和所述第一N型掺杂区308之间提供第二偏置电压V 2，由于其位于第二本征区306的两端，第二本征区306用作雪崩区，因此第二偏置电压V 2可调控雪崩区的电场分布。雪崩光电探测器的雪崩区是指发生载流子(这里为电子)倍增的区域，因此也可以称为倍增区。雪崩光电探测器的吸收区能够将入射的光信号转换成多个电子，这些电子对在电场作用下发生流动而形成光电流；雪崩区能够通过雪崩效应将吸收区形成的少量电子进一步激发，形成大量的电子以实现放大作用；最后通过一对金属电极传导光电流，实现光电探测。
上述光生电子在存在电场的情况下(由于施加到雪崩光电探测器的第一偏置电压V 1)，这些光生电子被加速去往第二本征区306进行倍增。当光生电子穿过第二本征区306时，它们与结合在半导体原子晶格中的其他载流子碰撞，从而通过称为“碰撞电离”的过程产生更多的自由载流子。这些新的自由载流子也被施加的电场加速并产生更多的自由载流子。
此外，本公开实施例中雪崩光电探测器的第三N掺杂区303、第一本征区304和第三P掺杂区305这三个区域的排布方式，以及第三N掺杂区303和第三P掺杂区305各自的掺杂剂的浓度范围，对于作为吸收区的第二半导体层400内的电场分布是有利的。由于第一本征区304的存在，即使在第一偏置电压V 1的作用下，电子也无法通过第一本征区304，第一本征 区304起到了一定的阻隔作用。来自第二P掺杂区302方向的电子可通过第三N掺杂区303，经由第二半导体层400，再经过第三P掺杂区305去往雪崩区。
为实现上述雪崩效果，现有的雪崩光电探测器仅在雪崩区的两端施加偏置电压，这种做法存在一些缺点，例如，吸收区和雪崩区(也称为倍增区)不易独立调节，对掺杂区浓度精度要过较高，工艺容忍度低，容易导致增益带宽不理想。为此，本公开在雪崩光电探测器的吸收区和雪崩区的两端同时设置偏置电压，即，在第一P掺杂区301和第一N掺杂区308之间提供有第一偏置电压V 1，且在第一N掺杂区308和第三P型掺杂区305之间提供有第二偏置电压V 2。由此，实现吸收区和雪崩区对应的电场的独立调节，并能够进一步提高增益带宽。
需要说明的是，第一偏置电压V 1和所述偏置电压V 2是相对独立的，第一偏置电压V 1作用于吸收区，其值为可为1至4伏。而第二偏置电压V 2作用于雪崩区，其值可以为3至20伏。
在一些实施例中，第二本征区306在第一方向X上的尺寸为50nm至800nm，也就是说第二本征区306的宽度在上述区间内。由此，在实现较高增益的同时实现大的带宽。由于第二本征区306为本公开实施例的雪崩光电探测器的雪崩区，因此，第二本征区306第一方向X上的尺寸不宜太小。例如，小于50nm时，从吸收区运动过来的电子没有充分的雪崩空间，不能有效地被吸收，倍增效果较差。其尺寸也不宜过大，否则雪崩区两端所需的电压要求过高，电子发生雪崩的时间过长，响应降低，影响探测效果。
在一些实施例中，所述第二半导体层在第一方向X上的尺寸为150nm至1500nm，在第二方向Y上的尺寸为1μm至100μm，并且在第三方向Z上的尺寸为150nm至600nm。本公开实施例中的第二半导体层的尺寸限定 在上述范围内，能够降低噪声的同时，减少暗电流的产生。
这里，在描述所述第二半导体层的尺寸时，可以不考虑第二半导体层在外延生长过程中的上下表面的尺寸差异。
需要说明的是，所述第二半导体层400在平行于所述衬底10的形状可以是规则的矩形，参见图4或图7或图10，也可以具有沿所述第一方向X具有一定尺寸的倒角的梯形，参见图1。
本公开的雪崩光电探测器还可以包括覆盖所述第一半导体层300、第二半导体层400、第一电极501、第二电极502和第三电极503的覆盖层(参见图15e或图16g)。
需要说明的是，本公开的雪崩光电探测器的结构也可以为其自身的镜像结构，例如，参考图3，本公开实施例中的第一方向X为从右到左，则镜像结构的第一方向X’为从左到右。因此，本公开实施例所提供的雪崩光电探测器及其镜像结构均在本公开保护的范围之内。
本公开实施例提供的雪崩光电探测器包括：衬底，所述衬底的表面包括第一半导体层；位于所述第一半导体层之上的第二半导体层，所述第二半导体层的材料不同于所述第一半导体层的材料；其中，所述第一半导体层包括在第一方向上依次排列的第一P型掺杂区、第二P型掺杂区、第三N型掺杂区、第一本征区、第三P型掺杂区、第二本征区、第二N型掺杂区和第一N型掺杂区，所述第一至第三P型掺杂区的掺杂剂浓度依次递减，且所述第一至第三N型掺杂区的掺杂剂浓度依次递减，所述第一方向为所述雪崩光电探测器的电子流动方向；所述第二半导体层沿所述第一方向依次覆盖部分所述第二P型掺杂区、第三N型掺杂区、所述第一本征区和部分所述第三P型掺杂区，所述第一N型掺杂区连接有第一电极；所述第三P型掺杂区连接有第二电极；所述第一P型掺杂区连接有第三电极。由于多个被掺杂的电荷区以及作为雪崩区的第二本征区均在第一半导体层中，因 此不需要额外外延制作单晶硅，制作相对简单，利于降低成本；此外，由于第一N型掺杂区连接有第一电极，第三P型掺杂区连接有第二电极，第一P型掺杂区连接有第三电极，后续可以通过在这三个电极上独立地施加偏置电压，因此能够使位于作为吸收区的第二半导体层和作为作为雪崩区的第二本征区的电场可以独立调节，对掺杂区浓度精度容忍度较好，有利于实现低噪声、高增益带宽。
本公开实施例还提供了一种雪崩光电探测器的制备方法，具体请参见图14。如图14所示，所述方法包括以下步骤：
步骤201：提供衬底，所述衬底的表面上包括第一半导体层；
步骤202：执行选择性掺杂工艺，以在所述第一半导体层上沿第一方向上形成依次排列的第一P型掺杂区、第二P型掺杂区、第三N型掺杂区、第一本征区、第三P型掺杂区、第二本征区、第二N型掺杂区和第一N型掺杂区；
步骤203：形成第二半导体层，所述第二半导体层的材料不同于所述第一半导体层的材料，且在所述第一方向上依次覆盖部分所述第二P型掺杂区、第三N型掺杂区、所述第一本征区和部分所述第三P型掺杂区；
步骤204：形成垂直所述衬底平面方向而设置的第一电极、第二电极和第三电极，所述第一电极与所述第一N型掺杂区电连接；所述第二电极与所述第三P型掺杂区电连接，且所述第三电极与所述第一P型掺杂区电连接。
上述第一方向为所述雪崩光电探测器的电子流动方向。
图15a-图15e为本公开实施例提供的一种雪崩光电探测器的制备过程中的器件结构剖视图；图16a-图16g为本公开实施例提供的另一种雪崩光电探测器的制备过程中的器件结构剖视图。
下面，先结合图15a-图15e中雪崩光电探测器的制备过程中的器件结 构剖视图，对本公开实施例提供的雪崩光电探测器及其制备方法再作进一步详细的说明。
首先，执行步骤201。提供衬底，所述衬底包括第一半导体层。
请参考图15a，提供衬底10；衬底10可以包括多层结构，而多层结构之上进一步生长有功能层。因此，本公开的衬底10可包括多层结构，其中，衬底10的表面包括第一半导体层300，而位于表面之下的层可以包括单质半导体材料(例如为硅(Si)、锗(Ge)等)、复合半导体材料(例如为锗硅(SiGe)等)以及其氧化物构成的绝缘层，因此，衬底10可以是或绝缘体上硅(SOI)或绝缘体上锗(GeOI)等。
本申请实施例以所述衬底10为SOI为例进行说明。可以理解，所述第一半导体层300位于本公开衬底10的表面。
衬底10还包括位于第一半导体层300下的中间层200(实际应用中可以是绝缘层)以及底层100(实际应用中可以是硅层)。所述绝缘层200例如为二氧化硅层，其可以直接通过对底层100进行热氧化而获得。底层100与所述第一半导体层300相比可以具有更厚的厚度。
接下来，执行步骤202。这里，参考图15b。执行选择性掺杂工艺，以在所述第一半导体层300上沿第一方向上形成依次排列的第一P型掺杂区301、第二P型掺杂区302、第三N型掺杂区303、第一本征区304、第三P型掺杂区305、第二本征区306、第二N型掺杂区307和第一N型掺杂区308。
在实际工艺中，可利用掩膜版光刻工艺，依次对需要掺杂的区域进行开窗口。随后在窗口中进行离子注入，以形成上述掺杂浓度不同的掺杂区。
具体地，上述所述第一P型掺杂区或所述第一N型掺杂区的掺杂浓度为1×10 20/cm 3～5×10 20/cm 3，所述第二P型掺杂区或所述第二N型掺杂区的掺杂浓度为2×10 17/cm 3～5×10 18/cm 3，所述第三P型掺杂区或所述第三N型 掺杂区的掺杂浓度为1.2×10 17～4×10 17/cm 3。在一些实施例中，以第一P型掺杂区301、第二P型掺杂区302、第三P型掺杂区305中掺杂剂为硼(B)元素；而第一N型掺杂区308、第二N型掺杂区307、第三N型掺杂区303的掺杂剂为磷(P)元素或砷(As)元素。
在一些实施例中，所述方法还包括：
在执行选择性掺杂工艺之前，在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成与所述第一半导体层中其他区域垂直于所述衬底的方向上不同的高度。
在一些实施例中，所述在执行选择性掺杂工艺之前，在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成与所述第一半导体层中其他区域垂直于所述衬底的方向上不同的高度，包括：
在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成的高度H 1大于所述第一半导体层中其他区域垂直于所述衬底的方向上形成的高度H 2。
在另一些实施例中，所述在执行选择性掺杂工艺之前，在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成与所述第一半导体层中其他区域垂直于所述衬底的方向上不同的高度，包括：
在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成的高度H 1小于所述第一半导体层中其他区域垂直于所述衬底的方向上形成的高度H 2。
这里，由于前述两种实施例中的雪崩光电探测器中第一半导体层中的部分第二P型掺杂区、部分第三P型掺杂区、第一本征区、第三N型掺杂区在垂直于所述衬底的方向上具有与第一半导体层中其他区域不同的高度，对应地，覆盖部分第二P型掺杂区、部分第三P型掺杂区、第一本征区、第三N型掺杂区的第二半导体层的高度也相应地有所差异，除此之外，两种雪崩光电探测器中其他部分是相同的，因此，本文将代表性地以第一半导体层中的部分第二P型掺杂区、部分第三P型掺杂区、第一本征区、第三N型掺杂区在垂直于所述衬底的方向上的高度H 1大于所述第一半导体层中其他区域的高度H 2的情况来说明本公开实施例提供的雪崩光电探测器的制备方法。
这里，在执行选择性掺杂工艺之前，在待形成第二P型掺杂区302的部分区域、第三P型掺杂区303的部分区域、第一本征区304以及第三N型掺杂区303的区域中垂直于所述衬底的方向(Z方向)上形成与第一半导体层300中其他区域不同的高度，在实际应用中，可以采用光刻、刻蚀等工艺组合来实现不同区域的不同高度。该方法包括：在待形成第二P型掺杂区302的部分区域、第三P型掺杂区305的部分区域、第一本征区304以及第三N型掺杂区303的区域中垂直于所述衬底的方向上形成的高度H 1大于所述第一半导体层中其他区域的高度H 2。
接下来，执行步骤203。请参考图15c，形成第二半导体层400，且在第一方向X上覆盖所述第一本征区304和第三N型掺杂区303，且覆盖部分第二P型掺杂区302和第三P型掺杂区305。
在一些实施例中，首先形成覆盖第一半导体材料300的初始第二半导体层400’(图15c中未示出)，然后利用图形化的光刻胶层对初始第二半导体层400’进行刻蚀以形成第二半导体层400，再除去光刻胶层。
这里，所形成的第二半导体层400为矩形形状(其形状可参考图4中 第二半导体层400)，也可以采用梯形形状(其形状可参考图1中第二半导体层400)。
在一些实施例中，第一半导体层的材料不同于第二半导体层的材料。例如，在第一半导体层的材料为Si的情况下，第二半导体层的材料为锗、锗硅合金、III-V族材料及其合金。
本公开实施例的雪崩光电探测器中的一个具体实施例中，第一半导体层的材料为硅，第二半导体层的材料为锗，换句话说，本公开实施例的雪崩光电探测器为锗硅雪崩光电探测器。
可利用分子束外延生长等工艺外延生长高质量多晶锗材料，即形成第二半导体层。
接下来进行步骤204。可参考图15d。形成垂直所述衬底平面方向而设置的第一电极501、第二电极502和第三电极503，所述第一电极501与所述第一N型掺杂区308电连接；所述第二电极502与所述第三P型掺杂区305电连接，且所述第三电极503与所述第一P型掺杂区301电连接。
在一些实施例中，所述形成垂直所述衬底平面方向而设置的第一电极501、第二电极502和第三电极503包括：
形成覆盖所述第一半导体层300和所述第二半导体层400的覆盖层600；
分别在第一N型掺杂区308、第三P型掺杂区305和第一N型掺杂区308上方形成第一窗口、第二窗口和第三窗口；
在所述第一窗口、第二窗口和第三窗口填充金属材料以形成第一电极501、第二电极502和第三电极503。
在一个实施例中，覆盖层600可直接采用绝缘材料形成。参考图15e，可首先利用绝缘材料，例如二氧化硅形成覆盖层600以覆盖已掺杂的第一半导体层300和第二半导体层400。然后利用光刻与电感等离子刻蚀在所述 覆盖层600上进行开窗口，形成第一窗口、第二窗口和第三窗口以暴露出第一半导体层300中的第一N型掺杂区308、第三P型掺杂区305和第一P型掺杂区301的表面，然后利用例如磁控溅射工艺在第一窗口、第二窗口和第三窗口中沉积金属材料，以分别形成与第一N型掺杂区308、第三P型掺杂区305和第一P型掺杂区301电连接的第一电极501、第二电极502和第三电极503。
在形成电极后，还可以对覆盖层600的上表面进行平坦化的步骤，具体可以采用化学机械研磨(CMP)工艺。如此，可通过外部引线在第一电极501和第二电极502之间，以及第一电极501和第三电极503之间施加不同的电压，从而在第一电极501和第三电极503之间，以及在第一电极501和第三电极503提供偏置电压。
下面，再结合图16a-图16g中雪崩光电探测器的制备过程中的器件结构剖视图，对本公开实施例提供的雪崩光电探测器及其制备方法再作进一步的说明。
首先，执行步骤201。
如图16a所示，提供衬底，所述衬底包括第一半导体层。
接下来，在待形成所述第二P型掺杂区的紧邻所述第一P型掺杂区的部分区域上形成两个楔形槽C；参考图16b和图16c。由此，在所述两个楔形槽C之间保留部分第一半导体层G，且所保留的部分第一半导体层G不进行掺杂或进行轻掺杂；这里，这部分第一半导体层G不进行掺杂或轻掺杂的是为了在所形成的光电探测器中用作光波导以传递光的能量至后续部分。
实际工艺中，可通过掩膜版结合刻蚀，以形成上述两个楔形槽C，由此在两个楔形槽C形成部分第一半导体层G。
接下来，执行步骤202。这里，参考图16d。执行选择性掺杂工艺，以 在所述第一半导体层300上沿第一方向上形成依次排列的第一P型掺杂区301、第二P型掺杂区302、第三N型掺杂区303、第一本征区304、第三P型掺杂区305、第二本征区306、第二N型掺杂区307和第一N型掺杂区308。
如上所述的，在两个楔形槽C之间保留的部分第一半导体层G是未掺杂或轻掺杂的，在实际工艺中，可利用掩膜版光刻工艺，依次对需要掺杂的区域进行开窗口。随后在窗口中进行离子注入，以形成上述掺杂浓度不同的掺杂区。通过利用合适的离子注入工艺，使部分第一半导体层G是未掺杂或轻掺杂的。
接下来，执行步骤203。请参考图16e，形成第二半导体层400，且在第一方向X上覆盖所述第一本征区304和第三N型掺杂区303，且覆盖部分第二P型掺杂区302和第三P型掺杂区305。
接下来，执行步骤204。可参考图16f。形成垂直所述衬底平面方向而设置的第一电极501、第二电极502和第三电极503，所述第一电极501与所述第一N型掺杂区308电连接；所述第二电极502与所述第三P型掺杂区305电连接，且所述第三电极503与所述第一P型掺杂区301电连接。
在一些实施例中，如图16g所示，所述形成垂直所述衬底平面方向而设置的第一电极501、第二电极502和第三电极503包括：
形成覆盖所述第一半导体层300和所述第二半导体层400的覆盖层600；
分别在第一N型掺杂区308、第三P型掺杂区305和第一N型掺杂区308上方形成第一窗口、第二窗口和第三窗口；
在所述第一窗口、第二窗口和第三窗口填充金属材料以形成第一电极501、第二电极502和第三电极503。
需要说明的是，上述介绍的图16a-图16g所示的方法中，与图15a-图 15e中方法类似的部分未做赘述。
需要说明的是，本公开提供的雪崩光电探测器实施例与雪崩光电探测器的制备方法实施例属于同一构思；各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。但需要进一步说明的是，本公开实施例提供的雪崩光电探测器，其各技术特征组合已经可以解决本公开所要解决的技术问题；因而，本公开实施例所提供的雪崩光电探测器可以不受本公开实施例提供的雪崩光电探测器的制备方法的限制，任何能够形成本公开实施例所提供的雪崩光电探测器结构的制备方法所制备的雪崩光电探测器均在本公开保护的范围之内。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种雪崩光电探测器，包括：
    衬底，所述衬底的表面包括第一半导体层；
    位于所述第一半导体层之上的第二半导体层，所述第二半导体层的材料不同于所述第一半导体层的材料；其中，
    所述第一半导体层包括在第一方向上依次排列的第一P型掺杂区、第二P型掺杂区、第三N型掺杂区、第一本征区、第三P型掺杂区、第二本征区、第二N型掺杂区和第一N型掺杂区，所述第一至第三P型掺杂区的掺杂剂浓度依次递减，且所述第一至第三N型掺杂区的掺杂剂浓度依次递减，所述第一方向为所述雪崩光电探测器的电子流动方向；
    所述第二半导体层沿所述第一方向依次覆盖部分所述第二P型掺杂区、所述第三N型掺杂区、所述第一本征区和部分所述第三P型掺杂区；
    所述第一N型掺杂区连接有第一电极；所述第三P型掺杂区连接有第二电极；所述第一P型掺杂区连接有第三电极。
  2. 根据权利要求1所述的雪崩光电探测器，其中，所述第一半导体层中的第一本征区、第三N型掺杂区、紧邻所述第三N型掺杂区的第二P型掺杂区的部分、紧邻所述第一本征区的第三P型掺杂区的部分在垂直于所述衬底的方向上具有第一高度H 1，所述第一半导体层中其他区域具有第二高度H 2；H 1不等于H 2；
    所述第二半导体层沿所述第一方向依次覆盖所述第二P型掺杂区具有第二高度H 2的区域的一部分、所述第二P型掺杂区具有第一高度H 1的区域、所述第三N型掺杂区、所述第一本征区、所述第三P型掺杂区具有第一高度H 1的区域和所述第三P型掺杂区具有第二高度H 2的区域的一部分。
  3. 根据权利要求2所述的雪崩光电探测器，其中，H 1大于H 2。
  4. 根据权利要求2所述的雪崩光电探测器，其中，H 1小于H 2。
  5. 根据权利要求1所述的雪崩光电探测器，其中，所述雪崩光电探测器还包括：
    光波导，所述光波导位于所述第一半导体层之上，包括靠近光入射端的前端和远离所述光入射端的末端；
    所述第一半导体层中的第二P型掺杂区的紧邻所述第一P型掺杂区的部分区域具有的第三高度H 3低于第一半导体层中其他区域具有的第四高度H 4以形成沿第二方向上延伸的槽，所述第二方向为垂直于所述第一方向且平行于所述衬底表面的方向；
    所述第二半导体层沿所述第一方向依次覆盖所述第二P型掺杂区的第四高度H 4的部分区域、所述第三N型掺杂区、所述第一本征区和所述第三P型掺杂区的部分区域；
    所述光波导位于所述槽中且布置成大体沿第二方向延伸且与第二方向成预设夹角，以使其前端靠近所述第一P型掺杂区且末端靠近所述第二P型掺杂区的第四高度H 4的部分。
  6. 根据权利要求5所述的雪崩光电探测器，其中，所述光波导是未掺杂的或轻掺杂的。
  7. 根据权利要求1所述的雪崩光电探测器，其中，所述第一电极和第三电极之间设置有第一反向偏置电压V 1，且所述第一电极和第二电极之间设置有第二反向偏置电压V 2。
  8. 根据权利要求1所述的雪崩光电探测器，其中，所述第一半导体层的材料为硅，且所述第二半导体层的材料为锗、锗硅合金、III-V族材料及其合金。
  9. 根据权利要求1所述的雪崩光电探测器，其中，所述第一P型掺杂区或所述第一N型掺杂区的掺杂剂浓度为1×10 20/cm 3～5×10 20/cm 3，所述第 二P型掺杂区或所述第二N型掺杂区的掺杂剂浓度为2×10 17/cm 3～5×10 18/cm 3，所述第三P型掺杂区或所述第三N型掺杂区的掺杂剂浓度为1.2×10 17～4×10 17/cm 3。
  10. 根据权利要求1所述的雪崩光电探测器，其中，所述第二本征区在所述第一方向上的尺寸为50nm至800nm。
  11. 根据权利要求1所述的雪崩光电探测器，其中，所述第二半导体层在所述第一方向上的尺寸为150nm至1500nm，在第二方向上的尺寸为1μm至100μm，并且在第三方向上的尺寸为150nm至600nm，其中，所述第三方向为垂直于所述衬底的方向，且所述第二方向垂直于所述第三方向且垂直于所述第一方向。
  12. 一种雪崩光电探测器的制备方法，包括：
    提供衬底，所述衬底的表面上包括第一半导体层；
    执行选择性掺杂工艺，以在所述第一半导体层上沿第一方向上形成依次排列的第一P型掺杂区、第二P型掺杂区、第三N型掺杂区、第一本征区、第三P型掺杂区、第二本征区、第二N型掺杂区和第一N型掺杂区，所述第一至第三P型掺杂区的掺杂剂浓度依次递减，且所述第一至第三N型掺杂区的掺杂剂浓度依次递减；
    形成第二半导体层，所述第二半导体层的材料不同于所述第一半导体层的材料，且在所述第一方向上依次覆盖部分所述第二P型掺杂区、所述第三N型掺杂区、所述第一本征区和部分所述第三P型掺杂区；
    形成垂直所述衬底平面方向而设置的第一电极、第二电极和第三电极，所述第一电极与所述第一N型掺杂区电连接；所述第二电极与所述第三P型掺杂区电连接，且所述第三电极与所述第一P型掺杂区电连接；
    所述第一方向为所述雪崩光电探测器的电子流动方向。
  13. 根据权利要求12所述的方法，其中，所述方法还包括：
    在执行选择性掺杂工艺之前，在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成与所述第一半导体层中其他区域垂直于所述衬底的方向上不同的高度。
  14. 根据权利要求13所述的方法，其中，所述在执行选择性掺杂工艺之前，在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成与所述第一半导体层中其他区域垂直于所述衬底的方向上不同的高度，包括：
    在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成的高度H 1大于所述第一半导体层中其他区域垂直于所述衬底的方向上形成的高度H 2。
  15. 根据权利要求13所述的方法，其中，所述在执行选择性掺杂工艺之前，在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成与所述第一半导体层中其他区域垂直于所述衬底的方向上不同的高度，包括：
    在待形成第二P型掺杂区的部分区域、第三P型掺杂区的部分区域、第一本征区以及第三N型掺杂区的区域中垂直于所述衬底的方向上形成的高度H 1小于所述第一半导体层中其他区域垂直于所述衬底的方向上形成的高度H 2。
  16. 根据权利要求12所述的方法，其中，所述方法还包括：
    在执行选择性掺杂工艺之前，在待形成所述第二P型掺杂区的紧邻所述第一P型掺杂区的部分区域上形成两个楔形槽，以在所述两个楔形槽之间保留部分第一半导体层。
  17. 根据权利要求16所述的方法，其中，所述保留的部分第一半导体 层是不掺杂或轻掺杂的。
  18. 根据权利要求12所述的方法，其中，所述第一半导体层的材料为硅，且所述第二半导体层的材料为锗、锗硅合金、III-V族材料及其合金。
  19. 根据权利要求12所述的方法，其中，所述第一P型掺杂区或所述第一N型掺杂区的掺杂剂浓度为1×10 20/cm 3～5×10 20/cm 3，所述第二P型掺杂区或所述第二N型掺杂区的掺杂剂浓度为2×10 17/cm 3～5×10 18/cm 3，所述第三P型掺杂区或所述第三N型掺杂区的掺杂剂浓度为1.2×10 17～4×10 17/cm 3。
  20. 根据权利要求12所述的方法，其中，所述形成垂直所述衬底平面方向而设置的第一电极、第二电极和第三电极包括：
    形成覆盖所述第一半导体层和所述第二半导体层的覆盖层；
    分别在所述第一N型掺杂区、所述第三P型掺杂区和所述第一P型掺杂区的沿第二方向的一端形成第一窗口、第二窗口和第三窗口，以暴露述第一P型掺杂区、所述第三P型掺杂区和所述第一N型掺杂区的部分表面；所述第二方向为垂直于所述第一方向且平行于所述衬底的方向；
    在所述第一窗口、第二窗口和第三窗口填充金属以形成第一电极、第二电极和第三电极。
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