WO2022018842A1 - 表示装置 - Google Patents

表示装置 Download PDF

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Publication number
WO2022018842A1
WO2022018842A1 PCT/JP2020/028372 JP2020028372W WO2022018842A1 WO 2022018842 A1 WO2022018842 A1 WO 2022018842A1 JP 2020028372 W JP2020028372 W JP 2020028372W WO 2022018842 A1 WO2022018842 A1 WO 2022018842A1
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Prior art keywords
transistor
control
terminal connected
conduction terminal
terminal
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Ceased
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PCT/JP2020/028372
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English (en)
French (fr)
Japanese (ja)
Inventor
史幸 小林
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Sharp Corp
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Sharp Corp
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Priority to JP2022538541A priority Critical patent/JP7357165B2/ja
Priority to PCT/JP2020/028372 priority patent/WO2022018842A1/ja
Priority to US18/014,767 priority patent/US11922877B2/en
Publication of WO2022018842A1 publication Critical patent/WO2022018842A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the following disclosure relates to a display device, and more particularly to a display device including a pixel circuit including a display element driven by a current such as an organic EL element.
  • the organic EL element is also called an OLED (Organic Light-Emitting Diode), and is a self-luminous display element that emits light with brightness corresponding to the current flowing through the organic EL element. Since the organic EL element is a self-luminous display element in this way, the organic EL display device is easily thinner, lower in power consumption, and higher in brightness than a liquid crystal display device that requires a backlight and a color filter. It can be changed.
  • OLED Organic Light-Emitting Diode
  • a thin film transistor (TFT) is typically adopted as a drive transistor for controlling the supply of current to the organic EL element.
  • TFT thin film transistor
  • the characteristics of the thin film transistor tend to vary. Specifically, the threshold voltage tends to vary. If the threshold voltage varies in the drive transistor provided in the display unit, the brightness varies and the display quality deteriorates. Therefore, conventionally, various processes (compensation process) for compensating for variations in the threshold voltage have been proposed.
  • Compensation processing methods include an internal compensation method in which compensation processing is performed by providing a capacitor for holding information on the threshold voltage of the drive transistor in the pixel circuit, and, for example, the magnitude of the current flowing through the drive transistor under predetermined conditions.
  • the channel types of the transistors T91 to T97 in the pixel circuit 90 are all P-type (p-channel type).
  • the transistors T91 to T97 in the pixel circuit 90 employ a thin film transistor (hereinafter, referred to as “LTPS-TFT”) in which a channel layer is formed by low-temperature polysilicon.
  • the LTPS-TFT has the advantages that it can be driven at high speed because of its high mobility and that it is easy to realize a narrow frame of the panel.
  • the gate voltage of the driving transistor (transistor T94) is initialized by turning on the transistor T91. .. After that, by turning on the transistors T92 and T93, the data signal D (m) is written to the holding capacitor C9. At that time, a current is supplied as shown by an arrow with reference numeral 92 in FIG. 29. That is, the holding capacitor C9 is charged via the drive transistor (transistor T94).
  • the current drive capability of the drive transistor is low so that high resolution can be obtained. Therefore, even if the LTPS-TFT is adopted for the drive transistor, it is difficult to shorten the charge time of the holding capacitor C9. If high-frequency drive (high-speed drive) such that the drive frequency is 120 Hz is adopted, the display quality may deteriorate due to insufficient charging.
  • the holding capacitor is connected between the node connected to the data signal line and the node connected to the control terminal (gate terminal) of the driving transistor so that the holding capacitor is charged without going through the driving transistor.
  • a channel layer is formed by an oxide semiconductor on a part of the thin film transistors in the pixel circuit in order to prevent the generation of leakage current when low frequency driving is performed. It is described that a thin film transistor (hereinafter referred to as "oxide TFT") is used. Oxide TFTs have an advantage that the leakage current (off-leakage) is extremely small, and in recent years, their adoption in thin film transistors constituting pixel circuits and drive circuits of display devices is increasing.
  • the oxide semiconductor forming the channel layer of the oxide TFT is composed of, for example, indium, gallium, zinc, and oxygen.
  • the following disclosure aims to realize a display device provided with a pixel circuit that enables both high-frequency drive and low-frequency drive without causing deterioration of display quality.
  • the display device is a display device including a pixel circuit including a display element driven by an electric current. Controls the writing of the data signal to the pixel circuit of a plurality of rows ⁇ a plurality of columns, a plurality of data signal lines for supplying a data signal to the pixel circuit of the corresponding column, and the pixel circuit of the corresponding row.
  • a plurality of scanning signal lines for controlling, a plurality of emission control lines for controlling whether or not to supply a current to the display element included in the pixel circuit of the corresponding row, and a high level power supply voltage supply.
  • a display unit including one power supply line, a second power supply line for supplying a low level power supply voltage, and a reference power supply line for supplying a reference voltage is provided.
  • the pixel circuit is The first control node and The second control node and The display element having the first terminal and the second terminal connected to the second power line, A first having a control terminal connected to one of the plurality of scanning signal lines, a first conduction terminal connected to the first power supply line, and a second conduction terminal connected to the first control node.
  • Initialization transistor and A threshold voltage compensating transistor having a control terminal connected to one of the plurality of scanning signal lines, a first conduction terminal connected to the first control node, and a second conduction terminal.
  • a control terminal connected to the first control node, a first conduction terminal connected to the second conduction terminal of the threshold voltage compensation transistor, and a second conduction terminal connected to the first terminal of the display element are provided.
  • the drive transistor A control terminal connected to one of the plurality of light emission control lines, a first conduction terminal connected to the first power supply line, and a second conduction terminal connected to the first conduction terminal of the drive transistor are provided.
  • the first light emission control transistor to have and It has a control terminal connected to one of the plurality of scanning signal lines, a first conduction terminal connected to the second control node, and a second conduction terminal connected to the first terminal of the display element.
  • the second emission control transistor and A second initialization transistor having a control terminal, a first conduction terminal connected to the first terminal of the display element, and a second conduction terminal connected to the reference power line.
  • a holding capacitor having a first electrode connected to the first control node and a second electrode connected to the second control node is included.
  • the channel layer of the first initialization transistor and the channel layer of the threshold voltage compensating transistor are formed of an oxide semiconductor.
  • the display device is a display device including a pixel circuit including a display element driven by an electric current. Controls the writing of the data signal to the pixel circuit of a plurality of rows ⁇ a plurality of columns, a plurality of data signal lines for supplying a data signal to the pixel circuit of the corresponding column, and the pixel circuit of the corresponding row.
  • a plurality of scanning signal lines for controlling, a plurality of emission control lines for controlling whether or not to supply a current to the display element included in the pixel circuit of the corresponding row, and a high level power supply voltage supply.
  • a display unit including one power supply line, a second power supply line for supplying a low level power supply voltage, and a reference power supply line for supplying a reference voltage is provided.
  • the pixel circuit is The first control node and The second control node and The display element having the first terminal and the second terminal connected to the second power line, A first having a control terminal connected to one of the plurality of scanning signal lines, a first conduction terminal connected to the first power supply line, and a second conduction terminal connected to the first control node.
  • Initialization transistor and A threshold voltage compensating transistor having a control terminal connected to one of the plurality of scanning signal lines, a first conduction terminal connected to the first control node, and a second conduction terminal.
  • a control terminal connected to the first control node, a first conduction terminal connected to the second conduction terminal of the threshold voltage compensation transistor, and a second conduction terminal connected to the first terminal of the display element are provided.
  • the drive transistor A control terminal connected to one of the plurality of light emission control lines, a first conduction terminal connected to the first power supply line, and a second conduction terminal connected to the first conduction terminal of the drive transistor are provided.
  • the first light emission control transistor to have and It has a control terminal connected to one of the plurality of scanning signal lines, a first conduction terminal connected to the second control node, and a second conduction terminal connected to the first terminal of the display element.
  • the second emission control transistor and A second initialization transistor having a control terminal, a first conduction terminal connected to the first terminal of the display element, and a second conduction terminal connected to the reference power line. It includes a holding capacitor having a first electrode connected to the first control node and a second electrode connected to the second control node.
  • the display device is a display device including a pixel circuit including a display element driven by an electric current. Controls the writing of the data signal to the pixel circuit of a plurality of rows ⁇ a plurality of columns, a plurality of data signal lines for supplying a data signal to the pixel circuit of the corresponding column, and the pixel circuit of the corresponding row. A plurality of scanning signal lines for controlling, a plurality of emission control lines for controlling whether or not to supply a current to the display element included in the pixel circuit of the corresponding row, and a high level power supply voltage supply.
  • a display unit including one power supply line, a second power supply line for supplying a low level power supply voltage, an initialization power supply line for supplying an initialization voltage, and a reference power supply line for supplying a reference voltage.
  • the pixel circuit is The first control node and The second control node and The display element having the first terminal and the second terminal connected to the second power line, A first initial stage having a control terminal connected to one of the plurality of scanning signal lines, a first conduction terminal connected to the reference power supply line, and a second conduction terminal connected to the second control node.
  • a threshold voltage compensating transistor having a control terminal connected to one of the plurality of scanning signal lines, a first conduction terminal connected to the first control node, and a second conduction terminal.
  • a write control transistor A drive having a control terminal connected to the first control node, a first conduction terminal connected to the first power supply line, and a second conduction terminal connected to the second conduction terminal of the threshold voltage compensation transistor.
  • a control terminal connected to one of the plurality of light emission control lines, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to the first terminal of the display element.
  • a first light emission control transistor having It has a control terminal connected to one of the plurality of light emission control lines, a first conduction terminal connected to the first terminal of the display element, and a second conduction terminal connected to the initialization power supply line.
  • the second emission control transistor and A second having a control terminal connected to one of the plurality of scanning signal lines, a first conduction terminal connected to the first control node, and a second conduction terminal connected to the initialization power supply line.
  • Initialization transistor and A holding capacitor having a first electrode connected to the first control node and a second electrode connected to the second control node is included.
  • the channel layer of the threshold voltage compensation transistor and the channel layer of the second initialization transistor are formed of an oxide semiconductor.
  • the second control node connected to the data signal line via the write control transistor and the first control node connected to the control terminal of the drive transistor.
  • a holding capacitor is provided between the two. With such a configuration, the holding capacitor is charged without going through the drive transistor. That is, the holding capacitor is charged quickly. Further, since the voltage of the data signal may be fixed by the time when the threshold voltage compensating transistor changes from the on state to the off state, the display quality does not deteriorate unless a large delay occurs in the waveform change of the data signal. From the above, good display quality is maintained even when high frequency drive (high speed drive) such that the drive frequency is set to 120 Hz is performed.
  • a transistor having a conduction terminal connected to the first control node (a first initialization transistor having a second conduction terminal connected to the first control node and a threshold voltage compensation having a first conduction terminal connected to the first control node).
  • the channel layer is formed of an oxide semiconductor. Therefore, the generation of leakage current in those transistors is prevented. Therefore, even if a low frequency drive (low speed drive) such that the drive frequency is set to 1 Hz is performed, the display quality does not deteriorate due to the leak current. That is, good display quality is maintained. From the above, a display device provided with a pixel circuit that enables both high-frequency drive and low-frequency drive without causing deterioration of display quality is realized.
  • the first embodiment it is a circuit diagram which shows the structure of the pixel circuit of the nth row and the mth column. It is a block diagram which shows the whole structure of the organic EL display device which concerns on the said 1st Embodiment. It is a waveform diagram for demonstrating the operation of a pixel circuit in the said 1st Embodiment. In the first embodiment, it is a figure which shows the transition of the state of each transistor in a pixel circuit. It is a figure for demonstrating operation of a pixel circuit in the said 1st Embodiment. It is a figure for demonstrating operation of a pixel circuit in the said 1st Embodiment.
  • FIG. 6C of US Pat. No. 10,304,378 It is a waveform diagram for demonstrating the operation of the pixel circuit described in US Pat. No. 10,304,378. It is a waveform diagram for demonstrating the effect of this embodiment. It is a block diagram which shows the whole structure of the organic EL display device which concerns on the modification of 1st Embodiment. It is a circuit diagram which shows the structure of the pixel circuit of the nth row and mth column in the modification of the 1st Embodiment. It is a waveform diagram for demonstrating the operation of a pixel circuit in the modification of the 1st Embodiment.
  • i and j are integers of 2 or more
  • m is an integer of 1 or more and i or less
  • n is an integer of 1 or more and j or less.
  • the voltage of each node or the like represents the potential difference from the reference potential when 0 V is used as the reference potential.
  • FIG. 2 is a block diagram showing the overall configuration of the organic EL display device according to the first embodiment.
  • this organic EL display device includes a display control circuit 100, a display unit 200, a source driver (data signal line drive circuit) 300, a gate driver (scanning signal line drive circuit) 400, and an emission driver (light emission control). It is equipped with a line drive circuit) 500.
  • the gate driver 400 and the emission driver 500 are formed in the organic EL panel 6 including the display unit 200. That is, the gate driver 400 and the emission driver 500 are monolithic. However, it is also possible to adopt a configuration in which the gate driver 400 and the emission driver 500 are not monolithic.
  • the display unit 200 is provided with i data signal lines D (1) to D (i) and (j + 1) scanning signal lines SCAN (0) to SCAN (j) orthogonal to these. Further, on the display unit 200, j light emission control lines EM ( 1) to EM (j) are arranged. The scanning signal lines SCAN (0) to SCAN (j) and the light emission control lines EM (1) to EM (j) are parallel to each other. Further, the display unit 200 is provided with i ⁇ so as to correspond to the intersection of i data signal lines D (1) to D (i) and j scanning signal lines SCAN (1) to SCAN (j). The j pixel circuits 20 are provided.
  • the scan signals given to each of the (j + 1) scan signal lines SCAN (0) to SCAN (j) may also be designated by the reference numerals SCAN (0) to SCAN (j).
  • the light emission control signals given to the light emission control lines EM (1) to EM (j) may also be designated by the reference numerals EM (1) to EM (j), and i data signal lines D (1) to D (
  • the data signals given to i) may also be assigned the reference numerals D (1) to D (i).
  • the display unit 200 is also provided with a power line (not shown) common to all the pixel circuits 20. More specifically, a power line for supplying a high-level power supply voltage EL VDD for driving an organic EL element (hereinafter referred to as "high-level power line”) and a low-level power supply voltage ELVSS for driving an organic EL element.
  • a power supply line for supplying hereinafter referred to as “low level power supply line”
  • a power supply line for supplying a reference voltage Vsus hereinafter referred to as "reference power supply line” are arranged.
  • the high level power supply voltage EL VDD, the low level power supply voltage ELVSS, and the reference voltage Vsus are supplied from a power supply circuit (not shown).
  • the high-level power supply line realizes the first power supply line
  • the low-level power supply line realizes the second power supply line.
  • the display control circuit 100 receives the image data DAT sent from the outside and the timing signal group (horizontal synchronization signal, vertical synchronization signal, etc.) TG, and receives the digital video signal DV and the source control signal SCTL that controls the operation of the source driver 300.
  • the gate control signal GCTL that controls the operation of the gate driver 400 and the emission driver control signal EMCTL that controls the operation of the emission driver 500 are output.
  • the source control signal SCTL includes a source start pulse signal, a source clock signal, a latch strobe signal, and the like.
  • the gate control signal GCTL includes a gate start pulse signal, a gate clock signal, and the like.
  • the emission driver control signal EMCTL includes an emission start pulse signal, an emission clock signal and the like.
  • the source driver 300 is connected to i data signal lines D (1) to D (i).
  • the source driver 300 receives the digital video signal DV and the source control signal SCTL output from the display control circuit 100, and applies the data signals to the i data signal lines D (1) to D (i).
  • the source driver 300 includes an i-bit shift register (not shown), a sampling circuit, a latch circuit, i D / A converters, and the like.
  • the shift register has i registers connected in cascade. The shift register sequentially transfers the pulse of the source start pulse signal supplied to the register of the first stage from the input end to the output end based on the source clock signal. A sampling pulse is output from each stage of the shift register according to the transfer of this pulse. Based on the sampling pulse, the sampling circuit stores the digital video signal DV.
  • the latch circuit captures and holds one line of digital video signal DV stored in the sampling circuit according to the latch strobe signal.
  • the D / A converter is provided so as to correspond to each data signal line D (1) to D (i).
  • the D / A converter converts the digital video signal DV held in the latch circuit into an analog voltage.
  • the converted analog voltage is simultaneously applied to all the data signal lines D (1) to D (i) as data signals.
  • the gate driver 400 is connected to (j + 1) scanning signal lines SCAN (0) to SCAN (j).
  • the gate driver 400 includes a shift register, a logic circuit, and the like.
  • the gate driver 400 drives (j + 1) scanning signal lines SCAN (0) to SCAN (j) based on the gate control signal GCTL output from the display control circuit 100.
  • the emission driver 500 is connected to j light emission control lines EM (1) to EM (j).
  • the emission driver 500 includes a shift register, a logic circuit, and the like.
  • the emission driver 500 drives j emission control lines EM (1) to EM (j) based on the emission driver control signal EMCTL output from the display control circuit 100.
  • EM (j) an image based on the image data DAT is displayed on the display unit 200.
  • FIG. 1 is a circuit diagram showing a configuration of a pixel circuit 20 in the nth row and the mth column.
  • the pixel circuit 20 includes one organic EL element (organic light emitting diode) 21 as a display element (display element driven by an electric current) and seven transistors (typically a thin film) T1 to T7 (first).
  • the holding capacitor C1 is a capacitive element composed of two electrodes (first electrode and second electrode).
  • the transistors T1 to T7 are n-channel type transistors.
  • the node is called a "first control node”.
  • the code NG is attached to the first control node.
  • a node connected to the second conduction terminal of the write control transistor T3, the first conduction terminal of the second light emission control transistor T6, and the second electrode of the holding capacitor C1 is referred to as a "second control node”.
  • the second control node is designated by the reference numeral NA.
  • the control terminal is connected to the scanning signal line SCAN (n-1) on the (n-1) line, and the first conduction terminal is the high-level power supply line and the first light emission control transistor T5. It is connected to the first conduction terminal, and the second conduction terminal is connected to the first control node NG.
  • the control terminal is connected to the scanning signal line SCAN (n) on the nth line, the first conduction terminal is connected to the first control node NG, and the second conduction terminal is the second conduction terminal of the drive transistor T4. It is connected to the 1 continuity terminal and the second continuity terminal of the first light emission control transistor T5.
  • the control terminal is connected to the scan signal line SCAN (n) in the nth row, the first conduction terminal is connected to the data signal line D (m) in the mth column, and the second conduction terminal is. It is connected to the second control node NA.
  • the control terminal is connected to the first control node NG, and the first conduction terminal is connected to the second conduction terminal of the threshold voltage compensation transistor T2 and the second conduction terminal of the first light emission control transistor T5.
  • the second conduction terminal is connected to the second conduction terminal of the second light emission control transistor T6, the first conduction terminal of the second initialization transistor T7, and the anode terminal (first terminal) of the organic EL element 21.
  • the control terminal is connected to the light emission control line EM (n) on the nth line, and the first conduction terminal is a high level power supply line and the first conduction terminal of the first initialization transistor T1.
  • the second conduction terminal is connected to the second conduction terminal of the threshold voltage compensation transistor T2 and the first conduction terminal of the drive transistor T4.
  • the control terminal is connected to the light emission control line EM (n) on the nth line, the first conduction terminal is connected to the second control node NA, and the second conduction terminal is the drive transistor T4. It is connected to the second conduction terminal, the first conduction terminal of the second initialization transistor T7, and the anode terminal of the organic EL element 21.
  • the control terminal is connected to the scanning signal line SCAN (n) on the nth line, and the first conduction terminal is the second conduction terminal of the drive transistor T4 and the second emission control transistor T6.
  • the conduction terminal is connected to the anode terminal of the organic EL element 21, and the second conduction terminal is connected to the reference power supply line.
  • the first electrode is connected to the first control node NG, and the second electrode is connected to the second control node NA.
  • the anode terminal is connected to the second conduction terminal of the drive transistor T4, the second conduction terminal of the second light emission control transistor T6, and the first conduction terminal of the second initialization transistor T7, and is connected to the cathode terminal (cathode terminal).
  • the second terminal is connected to the low level power line.
  • an oxide TFT is adopted for the first initialization transistor T1, the threshold voltage compensation transistor T2, and the second initialization transistor T7, and the write control transistor T3, the drive transistor T4, and the first light emission control transistor T5 are adopted.
  • And LTPS-TFT is adopted for the second light emission control transistor T6.
  • the oxide semiconductor forming the channel layer of the oxide TFT is composed of indium, gallium, zinc, and oxygen.
  • the present invention is not limited to this.
  • the period before the period P1 and the period after the period 5 are the light emitting periods for the organic EL element 21 in the pixel circuit 20.
  • the high level corresponds to the on level and the low level corresponds to the off level.
  • the voltage waveforms of the second control node NA and the first control node NG shown in FIG. 3 are examples. be.
  • FIG. 4 shows the transition of the state (on / off state) of each transistor (however, excluding the drive transistor T4) in the periods P1 to P5 of FIG.
  • the emission control signal EM (n) is at a high level, and the scanning signals SCAN (n) and SCAN (n-1) are at a low level.
  • the first light emission control transistor T5 and the second light emission control transistor T6 are in the ON state. Since the second light emission control transistor T6 is in the ON state, the voltage between the control terminal and the second conduction terminal of the drive transistor T4 is equal to the charge voltage of the holding capacitor C1. Further, since the first light emission control transistor T5 is in the ON state, a drive current is supplied to the organic EL element 21 according to the magnitude of the charge voltage of the holding capacitor C1. As a result, the organic EL element 21 emits light according to the magnitude of the drive current.
  • the light emission control signal EM (n) changes from a high level to a low level.
  • the first light emission control transistor T5 and the second light emission control transistor T6 are turned off.
  • the supply of the drive current to the organic EL element 21 is cut off, and the organic EL element 21 is turned off.
  • the scanning signal SCAN (n-1) changes from low level to high level.
  • the first initialization transistor T1 is turned on, and a current is supplied to the first control node NG as shown by an arrow with reference numeral 61 in FIG.
  • the holding capacitor C1 is charged, and the voltage of the first control node NG rises.
  • the voltage of the first control node NG becomes equal to the high level power supply voltage EL VDD.
  • the voltage of the first control node NG (that is, the gate voltage of the drive transistor T4) is initialized in the period P2.
  • the scanning signal SCAN (n-1) changes from high level to low level.
  • the first initialization transistor T1 is turned off, and the initialization of the voltage of the first control node NG is completed.
  • the scanning signal SCAN (n) changes from a low level to a high level.
  • the threshold voltage compensation transistor T2, the write control transistor T3, and the second initialization transistor T7 are turned on.
  • the write control transistor T3 is turned on, the data signal D (m) is given to the second control node NA via the write control transistor T3 as shown by the arrow with reference numeral 62 in FIG.
  • the voltage of the second control node NA changes according to the data signal D (m).
  • the voltage of the second control node NA may rise, fall, or be maintained.
  • a holding capacitor C1 is provided between the second control node NA and the first control node NG. Therefore, the voltage of the first control node NG also changes according to the change of the voltage of the second control node NA.
  • the threshold voltage compensation transistor T2 and the second initialization transistor T7 are turned on, a current flows from the first control node NG to the reference power supply line as shown by an arrow with reference numeral 63 in FIG. .. As a result, the voltage of the first control node NG gradually decreases.
  • the scanning signal SCAN (n) changes from high level to low level.
  • the threshold voltage compensation transistor T2, the write control transistor T3, and the second initialization transistor T7 are turned off.
  • the voltages of the first control node NG and the second control node NA are maintained at the voltage at the end of the period P3.
  • the light emission control signal EM (n) changes from a low level to a high level.
  • the second light emission control transistor T6 is turned on, and the second conduction terminal of the drive transistor T4 and the second control node NA are electrically connected. That is, the voltage of the second conduction terminal of the drive transistor T4 and the voltage of the second control node NA become equal.
  • the first light emission control transistor T5 is turned on.
  • the drive current is an organic EL as shown by the arrow with reference numeral 64 in FIG. 7, depending on the magnitude of the voltage (charging voltage of the holding capacitor C1) between the control terminal of the drive transistor T4 and the second conduction terminal. It is supplied to the element 21.
  • the organic EL element 21 emits light according to the magnitude of the drive current.
  • the anode voltage of the organic EL element 21 changes according to the magnitude of the drive current, and the voltage of the second control node NA changes so as to be equal to the anode voltage of the organic EL element 21.
  • the voltage of the first control node NG also changes according to the change of the voltage of the second control node NA.
  • the organic EL element 21 continues to emit light according to the magnitude of the drive current throughout the period until the light emission control signal EM (n) changes from the high level to the low level.
  • the high level power supply voltage EL VDD is set to 11.5V
  • the low level power supply voltage ELVSS and the reference voltage Vsus are set to 2.5V
  • the voltage on the high level side of the scanning signal SCAN and the emission control signal EM is 14.5V.
  • the voltage on the low level side of the scanning signal SCAN and the emission control signal EM is set to -3.5V.
  • the voltage of the data signal D is set within the range of 1V to 6V. In this regard, the voltage corresponding to white is 1V and the voltage corresponding to black is 6V. It is assumed that the threshold voltage of the drive transistor T4 is 4V.
  • the voltage of the data signal D corresponds to the voltage (1V) corresponding to white
  • the voltage between the anode and the cathode of the organic EL element 21 during the light emission period is 4V
  • the voltage of the data signal D corresponds to black.
  • the voltage is (6V)
  • the anode-cathode voltage Voled of the organic EL element 21 during the light emission period becomes 0V.
  • the voltage of the data signal D is the voltage (1V) corresponding to white color will be described.
  • the voltage of the first control node NG becomes 11.5V regardless of the voltage of the data signal D.
  • the voltage of the second control node NA becomes 1V. Further, as described above, the voltage of the first control node NG decreases until it becomes equal to the sum of the reference voltage Vsus and the threshold voltage Vth of the drive transistor T4. Therefore, at the end of the period P3, the voltage of the first control node NG becomes 6.5V. As described above, during the period P4, the voltages of the first control node NG and the second control node NA are maintained at the voltage at the end of the period P3. From the above, at the end of the period P4, the voltage of the second control node NA is 1V, and the voltage of the first control node NG is 6.5V.
  • the voltage of the second control node NA becomes equal to the sum of the low level power supply voltage ELVSS and the anode-cathode voltage Voled of the organic EL element 21. That is, the voltage VNA of the second control node NA in the period P5 is expressed by the following equation (1).
  • VNA ELVSS + Voled ⁇ ⁇ ⁇ (1) Therefore, during the period P5, the voltage VNA of the second control node NA becomes 6.5V.
  • the change ⁇ VNA of the voltage of the second control node NA from the period P4 to the period P5 is expressed by the following equation (2).
  • ⁇ VNA ELVSS + Voled-Vdata ... (2)
  • the voltage change ⁇ VNA of the second control node NA is 5.5V.
  • the voltage Vgs between the first conduction terminal and the second conduction terminal of the drive transistor T4 is 5.5V.
  • the current Ioled flowing through the organic EL element 21 in the period after the period P5 is expressed by the following equation (5) when “Vgs ⁇ Vth” is established, and is expressed by the following equation (6) when “Vgs ⁇ Vth” is established. It is represented by. Since the surface potential can be approximated by "VNG-Vth" when “Vgs ⁇ Vth” is established, Ioled is proportional to exp (q (VNG-Vth) / kT). That is, when "Vgs ⁇ Vth" is established, Ioled decreases exponentially as VNG becomes smaller.
  • the voltage of the data signal D is the voltage (6V) corresponding to the black color.
  • the voltage of the first control node NG becomes 11.5 V regardless of the voltage of the data signal D.
  • the voltage of the second control node NA becomes 6V. Further, as described above, at the end of the period P3, the voltage of the first control node NG becomes 6.5V, and in the period P4, the voltages of the first control node NG and the second control node NA are the period P3. The voltage at the end of is maintained. From the above, at the end of the period P4, the voltage of the second control node NA is 6V, and the voltage of the first control node NG is 6.5V.
  • the voltage VNA of the second control node NA is 2.5V from the above equation (1).
  • the voltage change ⁇ VNA of the second control node NA from the period P4 to the period P5 is ⁇ 3.5 V from the above equation (2).
  • the voltage VNG of the first control node NG becomes 3V from the above equation (3).
  • the voltage Vgs between the first conduction terminal and the second conduction terminal of the drive transistor T4 in the period P5 is 0.5V from the above equation (4).
  • the current Ioled flowing through the organic EL element 21 in the period P5 or later is expressed by the same equation as in the case where the voltage of the data signal D is the voltage (1 V) corresponding to white (the above equation (5) and the above equation (upper equation (5)). See equation (6)).
  • the period from the start of the voltage change of the data signal Vdata to the end of the compensation process (the time when the voltage of the Node 2 becomes large according to the threshold voltage of the drive transistor) is relatively long.
  • the current path for writing the data signal D and the current path for compensation processing are completely different paths.
  • the operation of the compensation process can be started at the time when the voltage of the data signal D starts to change. That is, as shown by the period indicated by the arrow with reference numeral 79 in FIG. 10, from the time when the voltage of the data signal D starts to change to the time when the compensation process ends (the voltage of the first control node NG becomes the threshold voltage of the drive transistor).
  • the period until the corresponding size is reached) is relatively short.
  • the length of one horizontal period (1H) is at least designated by reference numeral 77 in FIG. 9 as compared with the configuration according to the present embodiment. It will be longer by the period indicated by the arrow. In other words, according to the present embodiment, the length of one horizontal period (1H) can be shortened, so that high-speed driving becomes possible as compared with the conventional case.
  • a holding capacitor C1 is provided between the two. With such a configuration, the holding capacitor C1 is charged without going through the drive transistor T4. That is, the holding capacitor C1 is charged quickly. Further, since the voltage of the data signal D only needs to be fixed by the time when the threshold voltage compensation transistor T2 changes from the on state to the off state (time point ta in FIG. 10), there is a large delay in the waveform change of the data signal D. The display quality does not deteriorate unless it occurs.
  • the LTPS-TFT is adopted for the drive transistor T4, the first control node NG is quickly charged during the period P3 (see FIG. 3) in which the compensation process for compensating the threshold voltage of the drive transistor T4 is performed. It is done in. From the above, good display quality is maintained even when high frequency drive (high speed drive) such that the drive frequency is set to 120 Hz is performed.
  • a transistor having a conduction terminal connected to the first control node NG (specifically, a first conduction terminal connected to the first initialization transistor T1 to which the second conduction terminal is connected to the first control node NG and the first control node NG).
  • An oxide TFT is used for the threshold voltage compensating transistor T2) to which the is connected.
  • an organic EL display device including a pixel circuit 20 that enables both high-frequency drive and low-frequency drive without causing deterioration of display quality is realized.
  • FIG. 11 is a block diagram showing the overall configuration of the organic EL display device according to the modified example of the first embodiment.
  • a signal wiring (hereinafter, referred to as “reset control line”) for transmitting the logic inversion signal of the light emission control signal EM is arranged in the display unit 200.
  • reset control line a signal wiring for transmitting the logic inversion signal of the light emission control signal EM is arranged in the display unit 200.
  • j reset control lines EMB (1) to EMB (j) are arranged on the display unit 200 so as to have a one-to-one correspondence with j light emission control lines EM (1) to EM (j).
  • i data signal lines D (1) to D (i) and (j + 1) scanning signal lines SCAN (0) to SCAN (j) are displayed on the display unit 200.
  • j reset control lines EMB (1) to EMB (j) are arranged.
  • the reset control signals (logical inversion signals of the light emission control signal EM) transmitted by the j reset control lines EMB (1) to EMB (j) are also represented by the codes EMB (1) to EMB (j). May be attached.
  • FIG. 12 is a circuit diagram showing the configuration of the pixel circuit 20 in the nth row and the mth column. Similar to the first embodiment (see FIG. 1), the pixel circuit 20 includes one organic EL element 21 and seven transistors (typically thin film transistors) T1 to T7 (first initialization transistor T1, It includes a threshold voltage compensation transistor T2, a write control transistor T3, a drive transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a second initialization transistor T7), and one holding capacitor C1.
  • the control terminal of the second initialization transistor T7 is connected to the reset control line EMB (n) on the nth line. Other than that, it is the same as that of the first embodiment.
  • the reset control line EMB is a signal wiring for initializing the state of the anode terminal of the organic EL element 21.
  • an oxide TFT is adopted for the first initialization transistor T1, the threshold voltage compensation transistor T2, and the second initialization transistor T7, and the write control transistor T3, the drive transistor T4, and the first light emission control are used.
  • LTPS-TFT is adopted for the transistor T5 and the second light emission control transistor T6.
  • FIG. 14 shows the transition of the state (on / off state) of each transistor (however, excluding the drive transistor T4) in the periods P1 to P5 of FIG.
  • the period before the period P1 is the same as that of the first embodiment.
  • the reset control signal EMB (n) is at a low level.
  • the organic EL element 21 is turned off as in the first embodiment.
  • the reset control signal EMB (n) changes from a low level to a high level.
  • the second initialization transistor T7 is turned on, a current is generated as shown by an arrow with reference numeral 65 in FIG. 15, and the anode voltage of the organic EL element 21 is initialized based on the reference voltage Vsus.
  • the voltage of the first control node NG (that is, the gate voltage of the drive transistor T4) is initialized by turning on the first initialization transistor T1 as in the first embodiment.
  • the reset control signal EMB (n) is maintained at a high level, and the scanning signal SCAN (n) changes from a low level to a high level.
  • the second initialization transistor T7 is maintained in the ON state, and the threshold voltage compensation transistor T2 and the write control transistor T3 are in the ON state.
  • the data signal D (m) is given to the second control node NA via the write control transistor T3 as shown by the arrow with reference numeral 66 in FIG.
  • the voltage of the second control node NA changes according to the data signal D (m), and the voltage of the first control node NG becomes equal to the sum of the reference voltage Vsus and the threshold voltage Vth of the drive transistor T4. ..
  • the voltage of the first control node NG and the second control node NA is maintained at the end of the period P3, as in the first embodiment.
  • the reset control signal EMB (n) changes from high level to low level.
  • the second initialization transistor T7 is turned off.
  • the light emission control signal EM (n) changes from a low level to a high level.
  • the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the voltage between the control terminal and the second conduction terminal of the drive transistor T4 (the charging voltage of the holding capacitor C1) is the same as in the first embodiment. ),
  • the drive current is supplied to the organic EL element 21 as shown by the arrow with reference numeral 68 in FIG. As a result, the organic EL element 21 emits light according to the magnitude of the drive current.
  • the organic EL element 21 continues to emit light according to the magnitude of the drive current throughout the period until the light emission control signal EM (n) changes from the high level to the low level.
  • FIG. 18 is a waveform diagram for explaining the operation at the time of low frequency driving in the first embodiment
  • FIG. 19 is a waveform diagram for explaining the operation at the time of low frequency driving in this modification.
  • the white display is performed by paying attention to the pixel circuit 20 on the nth row.
  • a refresh frame which is a frame period in which the display screen is updated (writing of the data signal D into the pixel circuit 20), is represented by a code RF, and is a frame period in which the display screen is not updated.
  • a non-refresh frame is represented by the code NRF.
  • the period in which the light emission control signal EM (n) is at a high level is the light emission period, and the period in which the light emission control signal EM (n) is at a low level is a non-light emission period.
  • the scan signal SCAN (n) has a high level during the non-emission period of the refresh frame RF
  • the anode voltage of the organic EL element 21 drops rapidly when the second initialization transistor T7 is turned on. do. Therefore, the brightness drops rapidly.
  • the anode voltage of the organic EL element 21 is initialized in this way, the brightness gradually increases when the non-light emission period is changed to the light emission period in the refresh frame RF. Since the second initialization transistor T7 is maintained in the off state during the non-emission period of the non-refresh frame NRF, the anode voltage of the organic EL element 21 is maintained as it is. Then, the brightness is lowered only by turning off the first light emission control transistor T5.
  • the refresh frame RF and the non-refresh frame NRF differ in the length of the period during which the luminance is below a predetermined level. More specifically, the period during which the luminance is below a predetermined level is relatively long in the refresh frame RF as indicated by the arrow with the reference numeral 81 in FIG. 18, whereas in the non-refresh frame NRF, the figure is shown. It is relatively short, as indicated by the arrow with reference numeral 82 at 18.
  • the reset control signal EMB (n) becomes high level during the non-light emission period, so that the second initialization transistor T7 is turned on. Therefore, in both the refresh frame RF and the non-refresh frame NRF, the brightness decreases rapidly when transitioning from the light emission period to the non-light emission period, and the brightness gradually decreases when transitioning from the non-light emission period to the light emission period. Rise. That is, the luminance changes in the same manner between the refresh frame RF and the non-refresh frame NRF.
  • the length of the period during which the luminance is below the predetermined level is equal in the refresh frame RF and the non-refresh frame NRF. Further, unlike the first embodiment, on-bias stress is applied to the drive transistor T4 every one frame period, so that the influence of the hysteresis of the drive transistor T4 can be eliminated. From the above, according to this modification, the generation of low frequency flicker is suppressed.
  • FIG. 20 is a block diagram showing the overall configuration of the organic EL display device according to the second embodiment.
  • the overall configuration in the present embodiment is substantially the same as the overall configuration in the first embodiment (see FIG. 2).
  • a power supply line for supplying the initialization voltage Vini (hereinafter referred to as “initialization power supply line”) is arranged on the display unit 200.
  • the initialization voltage Vini is supplied from a power supply circuit (not shown).
  • FIG. 21 is a circuit diagram showing the configuration of the pixel circuit 20 in the nth row and the mth column.
  • the pixel circuit 20 includes one organic EL element (organic light emitting diode) 22 as a display element (display element driven by an electric current) and seven transistors (typically a thin film) M1 to M7 (first).
  • the holding capacitor C2 is a capacitive element composed of two electrodes (first electrode and second electrode).
  • the threshold voltage compensation transistor M2, the write control transistor M3, the second light emission control transistor M6, and the second initialization transistor M7 are n-channel type transistors.
  • the first initialization transistor M1, the drive transistor M4, and the first light emission control transistor M5 are p-channel type transistors.
  • the node is called a "first control node”.
  • a node connected to the second conduction terminal of the first initialization transistor M1, the second conduction terminal of the write control transistor M3, and the second electrode of the holding capacitor C2 is referred to as a "second control node”.
  • the first control node is designated by the reference numeral NG
  • the second control node is designated by the reference numeral NA.
  • the control terminal is connected to the scan signal line SCAN (n) on the nth line, the first conduction terminal is connected to the reference power supply line, and the second conduction terminal is connected to the second control node NA. It is connected.
  • the control terminal is connected to the scanning signal line SCAN (n) on the nth line, the first conduction terminal is connected to the first control node NG, and the second conduction terminal is the second conduction terminal of the drive transistor M4.
  • the two conduction terminals are connected to the first continuity terminal of the first light emission control transistor M5.
  • the control terminal is connected to the scan signal line SCAN (n) in the nth row, the first conduction terminal is connected to the data signal line D (m) in the mth column, and the second conduction terminal is. It is connected to the second control node NA.
  • the control terminal is connected to the first control node NG, the first conduction terminal is connected to the high level power supply line, and the second conduction terminal is the second conduction terminal of the threshold voltage compensation transistor M2 and the first light emission. It is connected to the first conduction terminal of the control transistor M5.
  • the control terminal is connected to the light emission control line EM (n) on the nth line, and the first conduction terminal is the second conduction terminal of the threshold voltage compensation transistor M2 and the second conduction terminal of the drive transistor M4. It is connected to a terminal, and the second conduction terminal is connected to the first conduction terminal of the second light emission control transistor M6 and the anode terminal (first terminal) of the organic EL element 21.
  • the control terminal is connected to the light emission control line EM (n) on the nth line, and the first conduction terminal is the second conduction terminal of the first light emission control transistor M5 and the anode of the organic EL element 21.
  • the second conduction terminal is connected to the second conduction terminal of the second initialization transistor M7 and the initialization power supply line.
  • the control terminal is connected to the scanning signal line SCAN (n-1) on the (n-1) line
  • the first conduction terminal is connected to the first control node NG
  • the second conduction terminal is connected.
  • the terminal is connected to the second conduction terminal of the second light emission control transistor M6 and the initialization power supply line.
  • the first electrode is connected to the first control node NG, and the second electrode is connected to the second control node NA.
  • the anode terminal is connected to the second conduction terminal of the first light emission control transistor M5 and the first conduction terminal of the second light emission control transistor M6, and the cathode terminal (second terminal) is a low level power supply line. It is connected to the.
  • an oxide TFT is adopted for the threshold voltage compensation transistor M2, the write control transistor M3, the second light emission control transistor M6, and the second initialization transistor M7, and the first initialization transistor M1 and the drive transistor M4 are adopted.
  • LTPS-TFT is adopted as the first light emission control transistor M5.
  • FIG. 23 shows the transition of the state (on / off state) of each transistor (however, excluding the drive transistor M4) in the periods P11 to P15 of FIG. 22.
  • the light emission control signal EM (n), the scanning signal SCAN (n), and the scanning signal SCAN (n-1) are at low levels.
  • the threshold voltage compensation transistor M2, the second light emission control transistor M6, and the second initialization transistor M7 are in the off state, and the first light emission control transistor M5 is in the on state. Therefore, the drive current is supplied to the organic EL element 22 according to the magnitude of the voltage between the control terminal and the second conduction terminal of the drive transistor M4. As a result, the organic EL element 22 emits light according to the magnitude of the drive current. Since the write control transistor M3 is in the off state and the first initialization transistor M1 is in the on state, the voltage of the second control node NA is equal to the reference voltage Vsus.
  • the light emission control signal EM (n) changes from a low level to a high level.
  • the first light emission control transistor M5 is turned off and the second light emission control transistor M6 is turned on.
  • the supply of the drive current to the organic EL element 22 is cut off, and the organic EL element 22 is turned off.
  • the second light emission control transistor M6 is turned on, the anode voltage of the organic EL element 22 is initialized based on the initialization voltage Vini.
  • the scanning signal SCAN (n-1) changes from low level to high level.
  • the second initialization transistor M7 is turned on, and a current flows from the first control node NG to the initialization power line as shown by the arrow with reference numeral 71 in FIG. 24.
  • the voltage of the first control node NG becomes equal to the initialization voltage Vini.
  • the voltage of the first control node NG (that is, the gate voltage of the drive transistor M4) is initialized in the period P12.
  • the scanning signal SCAN (n-1) changes from high level to low level.
  • the second initialization transistor M7 is turned off, and the initialization of the voltage of the first control node NG is completed.
  • the scanning signal SCAN (n) changes from a low level to a high level.
  • the first initialization transistor M1 is turned off, and the threshold voltage compensation transistor M2 and the write control transistor M3 are turned on.
  • the data signal D (m) is transmitted via the write control transistor M3 as shown by the arrow with reference numeral 72 in FIG. It is given to the second control node NA.
  • the voltage of the second control node NA rises according to the data signal D (m).
  • a holding capacitor C2 is provided between the second control node NA and the first control node NG. Therefore, as the voltage of the second control node NA rises, the voltage of the first control node NG also rises.
  • the threshold voltage compensation transistor M2 is turned on, a current flows from the high level power supply line to the first control node NG as shown by an arrow with reference numeral 73 in FIG. 25. As a result, the voltage of the first control node NG gradually rises.
  • the scanning signal SCAN (n) changes from high level to low level.
  • the threshold voltage compensation transistor M2 and the write control transistor M3 are turned off, and the first initialization transistor M1 is turned on.
  • the write control transistor M3 is in the off state and the first initialization transistor M1 is in the on state, a current flows from the second control node NA to the reference power line as shown by the arrow with reference numeral 74 in FIG. ..
  • the voltage of the second control node NA drops until it becomes equal to the reference voltage Vsus.
  • the voltage of the first control node NG also drops due to the presence of the holding capacitor C2.
  • the light emission control signal EM (n) changes from high level to low level.
  • the second light emission control transistor M6 is turned off, and the first light emission control transistor M5 is turned on.
  • a drive current is supplied to the organic EL element 22 as shown by an arrow with reference numeral 75 in FIG. 27 according to the magnitude of the voltage between the control terminal and the second conduction terminal of the drive transistor M4.
  • the organic EL element 22 emits light according to the magnitude of the drive current.
  • the organic EL element 22 continues to emit light according to the magnitude of the drive current throughout the period until the light emission control signal EM (n) changes from the high level to the low level.
  • a holding capacitor C2 is provided between the two. With such a configuration, the holding capacitor C2 is charged without going through the drive transistor M4. That is, the holding capacitor C2 is charged quickly. Further, since the voltage of the data signal D only needs to be fixed by the time when the threshold voltage compensation transistor M2 changes from the on state to the off state, the display quality deteriorates unless a large delay occurs in the waveform change of the data signal D. do not do.
  • the first control node NG is quickly charged during the period P13 (see FIG. 22) in which the compensation process for compensating the threshold voltage of the drive transistor M4 is performed. It is done in. From the above, good display quality is maintained even when high frequency drive (high speed drive) such that the drive frequency is set to 120 Hz is performed. Further, a transistor in which a conduction terminal is connected to the first control node NG (specifically, a threshold voltage compensation transistor M2 in which the first conduction terminal is connected to the first control node NG and a first conduction terminal are connected to the first control node NG. An oxide TFT is used for the connected second initialization transistor M7).
  • an organic EL display device provided with a pixel circuit 20 that enables both high frequency drive and low frequency drive without causing deterioration of display quality is realized. Will be done.
  • the organic EL display device has been described as an example, but the present invention is not limited to this, and the present invention can be applied to an inorganic EL display device, a QLED display device, and the like.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)
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