WO2022017058A1 - 柔性阵列基板和显示装置 - Google Patents

柔性阵列基板和显示装置 Download PDF

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Publication number
WO2022017058A1
WO2022017058A1 PCT/CN2021/099842 CN2021099842W WO2022017058A1 WO 2022017058 A1 WO2022017058 A1 WO 2022017058A1 CN 2021099842 W CN2021099842 W CN 2021099842W WO 2022017058 A1 WO2022017058 A1 WO 2022017058A1
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WIPO (PCT)
Prior art keywords
source
drain
pixel
lead
leads
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PCT/CN2021/099842
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English (en)
French (fr)
Inventor
钱昱翰
刘利宾
韩龙
曹方旭
王品凡
于洋
李文强
吕祖彬
贾立
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/788,755 priority Critical patent/US20230031474A1/en
Publication of WO2022017058A1 publication Critical patent/WO2022017058A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a flexible array substrate and a display device.
  • the stretchable area may be designed with a hole cut to form an island bridge area composed of a pixel island area and a bridge area. Isolation grooves may be arranged around the island and bridge areas to prevent water vapor from invading the pixel island and bridge areas.
  • the arrangement of the isolation trench increases the density of signal leads in the bridging region and makes the distance between the signal leads and the isolation trench smaller, and moisture easily penetrates into the signal leads from the isolation trench, thereby reducing the electrical performance of the bridging region.
  • the purpose of the present disclosure is to provide a flexible array substrate and a display device to improve the encapsulation effect of the stretchable area.
  • a flexible array substrate comprising at least one stretchable area; the flexible array substrate is provided with a plurality of through holes in the stretchable area, and a plurality of the through holes
  • the stretchable area is divided into a pixel island area for display and a bridge area for signal transmission; the bridge area includes a source-drain bridge area, and the flexible array substrate is in any one of the source and drain areas.
  • the bridge area includes:
  • first source-drain metal layer disposed on one side of the base substrate, and comprising a plurality of first source-drain leads
  • a first insulating material layer disposed on the side of the first source-drain metal layer away from the base substrate;
  • a second source-drain metal layer is disposed on the side of the first insulating material layer away from the base substrate; the second source-drain metal layer includes a plurality of second source-drain leads, and the second source-drain The number of leads is less than the number of the first source-drain leads;
  • the second insulating material layer is provided on the side of the second source-drain metal layer away from the base substrate; the second insulating material layer is provided with a plurality of isolation grooves, and the isolation grooves are located on the second source and drain.
  • the orthographic projection on the drain metal layer isolates the second source-drain lead and the through hole;
  • the encapsulation layer is arranged on the side of the second insulating material layer away from the base substrate.
  • the distance between the orthographic projection of the second source-drain lead on the second insulating material layer and the isolation trench is not less than the distance between two adjacent second source-drain leads.
  • the width of the isolation trench is not greater than twice the distance between two adjacent second source-drain leads.
  • the width of the isolation trench is equal to 0.9-1.1 times the distance between two adjacent second source-drain leads; Between the second source-drain lead and an adjacent through hole, the number of the isolation trenches is multiple, and the distance between two adjacent isolation trenches is equal to the distance between two adjacent isolation trenches. 0.9 to 1.1 times the spacing between the second source and drain leads.
  • the distance between two adjacent second source-drain leads is not greater than 2 times the width of the second source-drain leads times.
  • a plurality of the second source-drain leads are arranged at equal intervals;
  • the hole is equal to the minimum distance between the second source and drain leads.
  • a distance between two adjacent first source-drain leads is no greater than two adjacent second source-drain leads spacing between.
  • the distance between the orthographic projection of the first source-drain lead on the second insulating material layer and the isolation trench is not greater than the minimum value of the distance between the orthographic projection of the second source-drain lead on the second insulating material layer and the isolation trench.
  • an orthographic projection of the first source-drain lead on the second insulating material layer at least partially overlaps the isolation trench .
  • the distance between the orthographic projection of the first source-drain lead on the second insulating material layer and the isolation trench The minimum value is 1.5-2.7 microns; the minimum value of the distance between the orthographic projection of the second source-drain lead on the second insulating material layer and the isolation trench is 4.5-6.0 microns.
  • the number of the first source-drain leads is 1 or 2 greater than the number of the second source-drain leads.
  • a width of an end of the isolation trench away from the base substrate is smaller than a width of an end of the isolation trench close to the base substrate.
  • the extending direction of the first source-drain lead is parallel or perpendicular to the extending direction of the through hole; the second source-drain lead The extending direction of the through hole is parallel or perpendicular to the extending direction of the through hole.
  • the pixel island region includes a plurality of sub-pixels, and the size of any one of the sub-pixels along the row direction is the first size; in the source-drain bridge region, adjacent two The spacing between the second source-drain leads is equal to the second size; the first size is larger than the second size.
  • the through hole includes a first elongated hole extending in a row direction and a second elongated hole extending in a column direction; the source-drain bridge region is located in the second elongated hole. Between the end of one elongated hole and the side edge of the second elongated hole.
  • any one of the pixel island regions is located between two adjacent first elongated holes and between two adjacent second elongated holes
  • Any one of the pixel island regions includes four pixels, and any one of the pixels includes a red sub-pixel, a green sub-pixel and a blue sub-pixel.
  • any one of the pixel island regions four of the pixels form two pixel rows, and any one of the pixel rows includes two of the pixel rows arranged along the row direction. pixel;
  • the pixel electrodes of the blue sub-pixels and the pixel electrodes of the red sub-pixels are arranged along the row direction, and the pixel electrodes of the green sub-pixels are far away from the other pixel electrodes. side of the pixel row.
  • the flexible array substrate includes a plurality of sub-pixels arranged in an array in any one of the pixel island regions, and any one of the sub-pixels includes a pixel driving circuit and a connection with the pixel driving circuit Electrically connected pixel electrodes; any one of the pixel driving circuits includes a storage capacitor, a first thin film transistor to a seventh thin film transistor; wherein,
  • the first end of the first thin film transistor is used for loading an initial signal
  • the second end of the first thin film transistor is electrically connected to the first electrode plate of the storage capacitor, and the control end of the first thin film transistor is used for load reset signal;
  • the first end of the second thin film transistor is electrically connected to the second end of the third thin film transistor and the first end of the sixth thin film transistor, and the second end of the second thin film transistor is electrically connected to the storage capacitor
  • the first electrode plate is electrically connected, and the control terminal of the second thin film transistor is used to load the scanning signal
  • the first end of the third thin film transistor is electrically connected to the second end of the fourth thin film transistor and the second end of the fifth thin film transistor, and the control end of the third thin film transistor is connected to the storage capacitor.
  • the first electrode plate is electrically connected;
  • the first end of the fourth thin film transistor is used to load the data signal, and the control end of the fourth thin film transistor is used to load the scan signal;
  • the first end of the fifth thin film transistor is used to load the power supply voltage, and the control end of the fifth thin film transistor is used to load the enable signal;
  • the second end of the sixth thin film transistor is used for electrical connection with the pixel electrode, and the control end of the sixth thin film transistor is used for loading the enable signal;
  • the first end of the seventh thin film transistor is used for loading the initial signal
  • the second end of the seventh thin film transistor is used for electrical connection with the pixel electrode
  • the control end of the seventh thin film transistor is used for loading the reset signal
  • the second electrode plate of the storage capacitor is used for loading the power supply voltage.
  • any one of the pixel island regions includes a first column of pixel driving circuits to a sixth column of pixel driving circuits arranged in sequence along a set direction, and any one column of pixel driving circuits includes a pixel driving circuit along the column direction.
  • the number of the first source-drain leads is five; the first first source-drain lead along the set direction is used for driving the circuit to the first column of pixels Loading the data signal; the second first source-drain wire along the setting direction is used to load the data signal to the second column pixel driving circuit; the fourth one along the setting direction The first source-drain lead is used for loading the data signal to the fifth column pixel driving circuit.
  • the number of the second source-drain leads is four; the first one of the second source-drain leads along the set direction The lead wires are used to load the power supply voltage to the pixel drive circuits of the first column to the pixel drive circuits of the sixth column; Three-column pixel driving circuits load the data signals; the third second source-drain leads along the setting direction are used to load the data signals to the fourth-column pixel driving circuits; The fourth and second source-drain leads in the direction are used to load the data signal to the pixel driving circuit of the sixth column.
  • a display device including the above-mentioned flexible array substrate.
  • two source-drain metal layers are arranged in the source-drain bridge region, which can increase the width of each source-drain lead formed by the source-drain metal layer and the distance between the source-drain leads, and reduce the The crosstalk between the source-drain leads reduces the impedance of the source-drain leads, improves the bendability of the source-drain leads, and further improves the tensile properties and electrical stability of the stretchable region.
  • the number of the second source-drain leads is less than the number of the first source-drain leads, which can increase the distance between the second source-drain lead and the isolation trench and reduce the risk of water vapor invading the second source-drain lead through the isolation trench. , improve the reliability of the encapsulation of the stretchable region, and further improve the electrical stability of the stretchable region.
  • FIG. 1 is a schematic structural diagram of a stretchable region according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a flexible array substrate in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a flexible array substrate in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a flexible array substrate in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a flexible array substrate in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic top-view structure diagram of a flexible array substrate in a source-drain bridge region according to an embodiment of the present disclosure; wherein, FIG. 6 only shows the through holes, the first source-drain leads, the second source-drain leads, and the isolation trenches. relative positional relationship.
  • FIG. 7 is a schematic structural diagram of forming a first source-drain lead in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of forming a first insulating material layer in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of forming a second source-drain lead in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of forming a second planarization layer in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of forming a second passivation layer in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of forming an isolation trench in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of forming an encapsulation layer in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of forming an organic light-emitting layer and a common electrode layer in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of forming an encapsulation layer in a source-drain bridge region according to an embodiment of the present disclosure.
  • FIG. 16 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of a semiconductor layer of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a first gate layer of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of a second gate layer of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic structural diagram of a first source-drain metal layer of a pixel driving circuit according to an embodiment of the present disclosure.
  • 21 is a schematic structural diagram of a second source-drain metal layer of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 22 is a schematic structural diagram of a semiconductor layer in a stretchable region according to an embodiment of the present disclosure.
  • FIG. 23 is a schematic structural diagram of the first gate layer of the stretchable region according to an embodiment of the present disclosure.
  • FIG. 24 is a schematic structural diagram of the second gate layer of the stretchable region according to an embodiment of the present disclosure.
  • FIG. 25 is a schematic structural diagram of a first source-drain metal layer of a stretchable region according to an embodiment of the present disclosure.
  • 26 is a schematic structural diagram of a second source-drain metal layer of a stretchable region according to an embodiment of the present disclosure.
  • FIG. 27 is a schematic structural diagram of a pixel electrode layer in a stretchable region according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • the present disclosure provides a flexible array substrate, the flexible array substrate includes at least one stretchable area; as shown in FIG. 1 , the flexible array substrate is provided with a plurality of through holes 010 in the stretchable area, and the plurality of through holes 010
  • the stretchable area is divided into a pixel island area 020 for display and a bridge area 030 for transmitting signals; wherein, the bridge area 030 includes a source-drain bridge area 031; as shown in FIG. 2 and FIG.
  • the substrate includes a base substrate 100 , a first source-drain metal layer 200 , a first insulating material layer 300 , a second source-drain metal layer 400 , a second insulating material layer 500 and an encapsulation layer 600 in any source-drain bridge region 031 .
  • the first source-drain metal layer 200 is disposed on one side of the base substrate 100 and includes a plurality of first source-drain leads 201 ; the first insulating material layer 300 is disposed on a side of the first source-drain metal layer 200 away from the base substrate 100 .
  • the second source-drain metal layer 400 is disposed on the side of the first insulating material layer 300 away from the base substrate 100; the second source-drain metal layer 400 includes a plurality of second source-drain leads 401, and the second source-drain leads 401 The number is less than the number of the first source-drain leads 201; the second insulating material layer 500 is provided on the side of the second source-drain metal layer 400 away from the base substrate 100; referring to FIG. 6 and FIG. 12, the second insulating material layer 500 A plurality of isolation trenches 503 (filled by the encapsulation layer 600 in FIG. 2 and FIG.
  • two source-drain metal layers are provided in the source-drain bridge region 031, which can increase the width of each source-drain lead 040 formed by the source-drain metal layer and the distance between the source-drain leads 040, and reduce the The crosstalk between the source-drain leads 040 reduces the impedance of the source-drain leads 040 , improves the bendability of the source-drain leads 040 and further improves the tensile properties and electrical stability of the stretchable region.
  • the number of the second source-drain leads 401 is less than the number of the first source-drain leads 201 , which can increase the distance between the second source-drain leads 401 and the isolation trench 503 and reduce the intrusion of water vapor into the second source-drain lead 401 through the isolation trench 503 .
  • the risk of the source-drain leads 401 increases the reliability of the package in the stretchable region, and further improves the electrical stability of the stretchable region.
  • the width of a structure in the source-drain bridge region 031 refers to the orthographic projection of the structure on the base substrate 100 , in the plane of the base substrate 100 and perpendicular to the width of the source-drain leads 040 Dimensions in the extension direction.
  • the width of the source-drain lead refers to the orthographic projection of the source-drain lead 040 in the source-drain bridge region 031 on the base substrate 100 , in the plane of the base substrate 100 and perpendicular to the source-drain lead 040 dimension in the direction of extension.
  • the width of the isolation trench 503 refers to the orthographic projection of the isolation trench 503 in the source-drain bridge region 031 on the base substrate 100 , in the plane of the base substrate 100 and perpendicular to the source-drain leads 040 dimension in the direction of extension.
  • the flexible array substrate provided by the present disclosure has at least one stretchable region, and the stretchable region can adapt to a curved surface through stretching and deformation, and can still achieve a display function after stretching.
  • the stretchable area may be located in a local area such as the edge and corner of the flexible array substrate, or may cover the entire display area of the flexible array substrate, which is not specifically limited in the present disclosure.
  • the flexible array substrate may have four stretchable regions, and the four stretchable regions are located at four top corners of the flexible array substrate; thus, the flexible array The substrate can be applied to a four-curved display.
  • the stretchable area of the flexible array substrate covers at least the display area of the flexible array substrate, that is, the display areas of the flexible array substrate are all stretchable areas;
  • the flexible array substrate can be used to prepare a head-mounted display helmet.
  • the flexible array substrate may be provided with a plurality of through holes 010 to improve the stretchability of the stretchable region.
  • the through hole 010 can divide the stretchable area into interconnected island bridge areas, the island bridge area includes a pixel island area 020 for display and a bridge area 030 for signal transmission, between adjacent pixel island areas 020 Connected through the bridging area 030.
  • the shape and arrangement of the through holes 010 can be selected and determined according to requirements, which can be I-shaped holes, elongated holes or through holes 010 of other shapes.
  • the flexible array substrate is also provided with isolation grooves 503, which are arranged around each through hole 010, so as to block the passage of water and oxygen invading from the through hole 010 to the island bridge area, so as to achieve the protection of the pixel island area 020 and the bridge area 030 .
  • the through hole 010 may be an elongated hole.
  • the through hole 010 may include a first elongated hole 011 extending along the row direction A and a second elongated hole 012 extending along the column direction B; wherein, two adjacent first elongated holes 011 in the same row There is a second elongated hole 012 between them, and the first elongated holes 011 in two adjacent rows are staggered; a first elongated hole 011 is arranged between two adjacent second elongated holes 012 in the same column. , and two adjacent rows of second elongated holes 012 are staggered.
  • one pixel island area 020 has two first elongated holes 011 and two second elongated holes 012 around it.
  • the elongated holes 012 are used to divide the pixel island regions 020 of two adjacent rows.
  • the bridge region 030 includes a gate bridge region 032 and a source-drain bridge region 031, wherein the gate bridge region 032 is located between the side of the first elongated hole 011 and the end of the second elongated hole 012, It is used to connect two pixel island regions 020 arranged adjacently in the same row; the source-drain bridge region 031 is located between the end of the first elongated hole 011 and the side of the second elongated hole 012, and is used to connect adjacent to the same column Set the two pixel island area 020.
  • the pixel island area 020 may include a pixel distribution area 021 and two pixel wiring areas 022 on both sides of the pixel distribution area 021 .
  • the pixel distribution area 021 may be provided with one or more pixels, and each pixel may include one or more sub-pixels.
  • each sub-pixel may be a self-luminous light-emitting element, for example, may have an OLED (organic electroluminescent diode), a Micro LED (micro light-emitting diode), and the like.
  • each pixel may include multiple sub-pixels of different colors, so as to realize color display by color mixing of the sub-pixels of different colors.
  • one pixel island region 020 may include four pixels, and each pixel includes one red sub-pixel, one green sub-pixel and one blue sub-pixel.
  • any pixel island 020 is located between two adjacent first elongated holes 011 and between two adjacent second elongated holes 012; any pixel island 020 includes four pixels, Any one pixel includes a red sub-pixel, a green sub-pixel and a blue sub-pixel.
  • the size of any sub-pixel along the row direction A is the first size; in the source-drain bridge region 031, the distance between two adjacent second source-drain leads 401 is equal to the second size; the first size is greater than second size.
  • the pixel wiring region 022 is located on the side of the pixel distribution region 021 close to the first elongated hole 011 , and is connected to the source-drain bridge region 031 and the gate bridge region 032 .
  • the pixel distribution region 022 in the pixel island region 020, along the column direction B, the pixel wiring region 022, the pixel distribution region 021, and the pixel wiring region 022 are sequentially arranged.
  • the pixel distribution area 021 can gather each source-drain wire 040 to the source-drain bridge area 031 through the pixel wiring area 022
  • the pixel distribution area 021 can gather each gate wire to the gate bridge area 032 through the pixel wiring area 022 .
  • the gate bridge region 032 may be provided with gate leads, so as to provide the pixel island region 020 with one or more gate signals such as scan signals, enable signals, reset signals, initialization signals, etc.; of course , the gate leads of the gate bridge region 032 can also be used to provide one or more gate signals such as scan signals, enable signals, reset signals, initialization signals and the like for pixels in other regions of the flexible array substrate.
  • the source-drain bridge region 031 may be provided with a source-drain lead 040 , and the source-drain lead 040 includes a first source-drain lead 201 located in the first source-drain metal layer 200 and a second source-drain lead 401 located in the second source-drain metal layer 400 .
  • the source-drain leads 040 are used for providing data signals and power supply voltages to the pixel island region 020, or for transmitting sensing signals of the pixel island region 020, and the like.
  • the source-drain leads 040 of the source-drain bridge region 031 can also provide data signals, Power supply voltage, etc., or sensing signals of pixels in other regions can also be transmitted.
  • the extending direction of the first source-drain lead 201 is parallel or perpendicular to the extending direction of the through hole 010 ; the extending direction of the second source-drain lead 401 is parallel or perpendicular to the extending direction of the through hole 010 . .
  • the extending direction of the first source-drain lead 201 and the second source-drain lead 401 is parallel to the extending direction of the second elongated hole 012 . That is, in the source-drain bridge region 031 , the extending direction of the first source-drain lead 201 and the second source-drain lead 401 is the column direction B. As shown in FIG.
  • the extending direction of the first source-drain lead 201 and the second source-drain lead 401 is parallel or perpendicular to the extending direction of the through hole 010 .
  • the first source-drain leads 201 or the second source-drain leads 401 in the pixel wiring region 022, it may extend along the row direction A, may also extend along the column direction B, or may partially extend along the row direction A and The remainder extends in the column direction B.
  • the flexible array substrate is further provided with pixels outside the stretchable area, the source and drain leads 040 of the first part of these pixels do not pass through the stretchable area, and the second part of these pixels can be
  • the source-drain leads 040 are shared with the pixels in the pixel island region 020, and the source-drain leads 040 of the third part of these pixels can pass through the source-drain bridge region 031 of the stretchable region and are not used for driving the pixels of the pixel island region 020 .
  • the source-drain lead 040 includes a power lead 041 for loading a power supply voltage and a data lead 042 for loading a data signal.
  • a power lead 041 for loading a power supply voltage
  • a data lead 042 for loading a data signal.
  • FIG. 1 is only used to illustrate the existence of the power supply lead 041 and the data lead 042 , rather than the quantity of the power supply lead 041 and the number of data leads 042.
  • only one power supply lead 041 may be provided, and the power supply lead 041 may provide power supply voltage to each sub-pixel in the pixel island region 020 by bridging or the like.
  • the number of source-drain leads 040 in the source-drain bridge region 031 can be reduced, thereby facilitating the improvement of the distance between the source-drain leads 040 and the width of the source-drain leads 040, thereby improving the bendability of the source-drain leads 040 and further improving the pullability of the source-drain leads 040.
  • the distance between the source-drain leads 040 from the through hole 010 and the isolation trench 503 can also be made farther, which can improve the reliability of the package in the stretchable area.
  • the reduction in the number of source-drain leads 040 in the source-drain bridge region 031 facilitates reducing the width of the source-drain bridge region 031 and the area ratio of the source-drain bridge region 031, thereby increasing the size of the pixel island region 020 and area ratio, thereby increasing the pixel density or light-emitting area of the flexible array substrate in the stretchable area, and improving the display effect.
  • the width of the power lead 041 is greater than the width of the data lead 042 to reduce the voltage drop of the power lead 041 .
  • the width of the power lead 041 is 1.5 to 3 times the width of the data lead 042 .
  • the number of power leads 041 is one, and the power lead 041 is a second source-drain lead 401 .
  • the pixel island area 020 includes 4 pixels, each pixel includes 3 sub-pixels that emit light independently, and the 3 sub-pixels are red sub-pixels, green sub-pixels and blue sub-pixels respectively. subpixel.
  • a source-drain bridge region 031 nine source-drain leads 040 may be provided, and the nine source-drain leads 040 include five first source-drain leads 201 and four second source-drain leads 401 .
  • One of the second source-drain leads 401 is used as a power supply lead 041 for loading power supply voltages to each sub-pixel in the pixel island region 020 ; Loading data signals; the two root-drain leads 040 are used as data leads 042 to provide data signals to sub-pixels outside the stretchable area, and are not used to provide data signals to sub-pixels in the pixel island region 020 .
  • this embodiment can reduce the total wiring width of the source and drain leads 040 by 43%, and can ensure the packaging effect of each source and drain lead 040 .
  • the minimum value of the distance between the orthographic projection of the second source-drain lead 401 on the second insulating material layer 500 and the isolation trench 503 is not less than two adjacent second sources. Spacing between drain leads 401 . In this way, a sufficiently large distance can be ensured between the second source-drain lead 401 and the isolation trench 503 , so that it is difficult for water vapor to penetrate into the second source-drain lead 401 through the isolation trench 503 , thereby avoiding electrical performance degradation of the second source-drain lead 401 .
  • the minimum value of the distance between the orthographic projection of the second source-drain lead 401 on the second insulating material layer 500 and the isolation trench 503 is equal to two adjacent second source-drain leads 1.5 to 2.0 times the spacing between 401.
  • the distance between two adjacent second source-drain leads 401 is equal to 3 micrometers, and the second source-drain leads 401 are located in the second insulation
  • the minimum value of the distance between the orthographic projection on the material layer 500 and the isolation trench 503 is equal to 4.5 ⁇ 6.0 ⁇ m.
  • the width of the isolation trench 503 is not greater than twice the distance between two adjacent second source-drain leads 401 . In this way, it can be avoided that the width of the isolation trench 503 is too large to compress the distance between the second source-drain lead 401 and the isolation trench 503, and the distance between the second source-drain lead 401 and the isolation trench 503 is ensured to be large enough to prevent the water vapor from being difficult to The second source-drain lead 401 is penetrated through the isolation trench 503 . Not only that, by reducing the width of the isolation trenches 503 , it is convenient to provide more isolation trenches 503 to further improve the packaging stability of the source-drain bridge region 031 .
  • the number of isolation trenches 503 is multiple, and the number of isolation trenches 503 between two adjacent isolation trenches 503 is multiple.
  • the spacing is not greater than twice the spacing between two adjacent second source-drain leads 401 .
  • isolation trenches 503 when a plurality of isolation trenches 503 are provided on one side of the source-drain bridge region 031, it can avoid that the distance between the isolation trenches 503 is too large and the distance between the second source-drain lead 401 and the isolation trench 503 is compressed, so as to ensure that the second source There is a sufficiently large distance between the drain lead 401 and the isolation trench 503 , so that it is difficult for water vapor to penetrate into the second source-drain lead 401 through the isolation trench 503 . Not only that, by reducing the spacing of the isolation trenches 503 , it is also convenient to provide more isolation trenches 503 to further improve the packaging stability of the source-drain bridge region 031 .
  • the width of the isolation trench 503 is equal to 0.9-1.1 times the distance between two adjacent second source-drain leads 401; Between the through holes 010 , the number of isolation trenches 503 is multiple, and the distance between two adjacent isolation trenches 503 is equal to 0.9 ⁇ 1.1 times of the distance between two adjacent second source-drain leads 401 . In this way, the width of the isolation trenches 503 and the spacing between the isolation trenches 503 can be further compressed, so that more isolation trenches 503 can be provided in the source-drain bridge region 031 and the spacing between the isolation trenches 503 and the second source-drain leads 401 can be further increased.
  • the distance between two adjacent second source-drain leads 401 is equal to 3 microns
  • the width of the isolation trench 503 is equal to 2.7-3.3 microns
  • the distance between two adjacent isolation trenches 503 on the same side of the source-drain bridge region 031 is equal to 2.7-3.3 microns.
  • the distance between two adjacent second source-drain leads 401 is not greater than twice the minimum value of the width of the second source-drain leads 401 .
  • the distance is such that it is difficult for water vapor to penetrate into the second source-drain lead 401 through the isolation groove 503 .
  • the distance between two adjacent second source-drain leads 401 is equal to 0.9-1.1 times the minimum width of the second source-drain leads 401 .
  • the minimum value of the width of the second source-drain leads 401 is 3 micrometers, and the distance between two adjacent second source-drain leads 401 is 2.7-3.3 micrometers.
  • the alignment accuracy of the exposure machine during the preparation of the flexible array substrate can also be used to determine the distance between the two adjacent second source-drain leads 401 in the source-drain bridge region 031 . Spacing; under the condition that the crosstalk of two adjacent second source-drain leads 401 is controllable, the distance between two adjacent second source-drain leads 401 in the source-drain bridge region 031 can be reduced within the scope allowed by the preparation process spacing between.
  • the distance between the source-drain bridge region 031 and the second source-drain lead 401 may be equal to 2-4 microns.
  • the spacing between the second source-drain leads 401 may be equal to 3 microns.
  • a plurality of second source-drain leads 401 are arranged at equal intervals; the two through holes 010 adjacent to the source-drain bridge region 031 The minimum distances between the second source-drain leads 401 in the source-drain bridge region 031 are equal.
  • the second source-drain leads 401 of the second source-drain metal layer 400 are arranged symmetrically in the center, which can ensure that the source-drain bridge region 031 is adjacent to the through hole 010 on both sides of the space to set the isolation trenches 503 , thereby ensuring a sufficiently large distance between each second source-drain lead 401 and the isolation trench 503 , so that it is difficult for water vapor to penetrate into the second source-drain leads 401 through the isolation trench 503 .
  • the distance between two adjacent first source-drain leads 201 is not greater than the distance between two adjacent second source-drain leads 401 .
  • the distance between the first source-drain leads 201 is too large and the width of the source-drain bridge region 031 is increased, which is convenient to increase the area ratio of the pixel island region 020 and improve the pixel density of the stretchable region or luminous area.
  • the distance between two adjacent first source-drain leads 201 is equal to 0.9-1.0 times the distance between two adjacent second source-drain leads 401 .
  • the distance between two adjacent second source-drain leads 401 is equal to 3 micrometers
  • the distance between two adjacent first source-drain leads 201 is equal to 3 micrometers. The spacing between them is equal to 2.7 to 3.0 microns.
  • the minimum distance between the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500 and the isolation trench 503 is not greater than the first The minimum value of the distance between the orthographic projection of the two source-drain leads 401 on the second insulating material layer 500 and the isolation trench 503 . Since the isolation trenches 503 are formed in the second insulating material layer 500 , the first source-drain leads 201 are completely covered by the first insulating material layer 300 , and it is difficult for moisture to penetrate into the first source-drain leads 201 through the isolation trenches 503 .
  • reducing the distance between the first source-drain lead 201 and the isolation trench 503 will not cause the stability of the electrical performance of the first source-drain lead 201 to decrease.
  • reducing the distance between the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500 and the isolation trench 503 can also reduce the width of the source-drain bridge region 031, thereby facilitating the increase of the pixel island Area 020 accounts for the area and increases the pixel density of the stretchable area.
  • the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500 does not overlap the isolation trench 503 at all .
  • the orthographic projection of the isolation trench 503 on the first source-drain metal layer 200 is located between the first source-drain lead 201 and the through hole 010, which can ensure that the first source-drain lead There is a sufficient distance between 201 and the through hole 010 .
  • the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500, the minimum distance from the isolation trench 503 is 1.5-2.7 ⁇ m; the second source-drain lead
  • the minimum value of the distance between the orthographic projection of 401 on the second insulating material layer 500 and the isolation trench 503 is 4.5 ⁇ 6.0 ⁇ m.
  • the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500, the minimum distance from the isolation trench 503 is 2.1 microns;
  • the minimum value of the distance between the orthographic projections on the two insulating material layers 500 and the isolation trench 503 is 5.2 ⁇ m.
  • the orthographic projection of the second source-drain lead 401 on the second insulating material layer 500 is the same as The minimum value of the distance between the isolation trenches 503 is increased by 148%, so that the second source-drain leads 401 are kept away from the isolation trenches 503 , and the packaging effect of the second source-drain leads 401 is improved.
  • the orthographic projection of the first source-drain lead 201 on the second source-drain metal layer 400 is spaced apart from each second source-drain lead 401 and not mutually overlap. In this way, the parasitic capacitance between the source-drain leads 040 can be reduced, and the crosstalk between the source-drain leads 040 can be reduced.
  • the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500 at least partially overlaps the isolation trench 503 .
  • part of the first source-drain leads 201 for example, the outermost first source-drain leads 201 , may be partially located below the isolation trench 503 .
  • the distance between the orthographic projection of the first source-drain lead 201 on the second insulating material layer 500 and the isolation trench 503 has a minimum value of 0 ⁇ m; this can further reduce the width of the source-drain bridge region 031 , thereby facilitating further
  • the area ratio of the pixel island region 020 is increased and the pixel density or light-emitting area of the stretchable region is increased.
  • the number of the first source-drain leads 201 is greater than that of the second source-drain leads 401 by 1 or 2. In this way, it is avoided that the number of the first source-drain leads 201 greatly exceeds the number of the second source-drain leads 401 and the source-drain bridge region 031 is too wide.
  • the number of the source-drain leads 040 is an even number, and the number of the first source-drain leads 201 is larger than the number of the second source-drain leads 401 by 2.
  • the number of the source-drain leads 040 is an odd number, and the number of the first source-drain leads 201 is greater than the number of the second source-drain leads 401 by one.
  • the width of the end of the isolation trench 503 away from the base substrate 100 is smaller than the width of the end of the isolation trench 503 close to the base substrate 100 .
  • the organic light-emitting layer 703 and the common electrode layer 704 of the flexible array substrate are formed by evaporation, the organic light-emitting layer 703 and the common electrode layer 704 are in the isolation groove 503 is discontinuous at the side walls.
  • the isolation groove 503 may penetrate through the second insulating material layer 500 , so that the isolation groove 503 can more effectively block the water and oxygen intrusion route and improve the resistance to the second insulating material layer 500 .
  • the packaging effect of the two source-drain leads 401 may be applied to the isolation groove 503 .
  • the isolation trench 503 does not penetrate the second insulating material layer 500 , that is, the size of the isolation trench 503 in the direction perpendicular to the base substrate 100 is smaller than that of the second insulating material layer 500 .
  • the dimension of the insulating material layer 500 in the direction perpendicular to the base substrate 100 is disposed between the first source-drain lead 201 and the isolation trench 503 , which can improve the protection effect of the first source-drain lead 201 and prevent water vapor from invading the first source. Drain lead 201 .
  • the base substrate 100 is a flexible base substrate 100 to ensure the stretchability of the flexible array substrate.
  • the material of the base substrate 100 may be a flexible material, such as polyimide.
  • the base substrate 100 may also be a composite of multi-layer materials.
  • the base substrate 100 may include a base film layer, a pressure-sensitive adhesive layer, and a first polyamide layer that are stacked in sequence. an imine layer and a second polyimide layer.
  • the first source-drain metal layer 200 may include one layer of conductive material, or may include multiple layers of stacked conductive materials.
  • the first source-drain metal layer 200 may include a titanium layer, an aluminum layer, and a titanium layer that are sequentially stacked.
  • the flexible array substrate may further include a shielding layer 701 and a third insulating material layer 702 .
  • a shielding layer 701 is provided between the first source-drain metal layer 200 and the base substrate 100 to shield light to prevent external light from irradiating the source-drain leads 040;
  • a third insulating material layer 702 It is located between the shielding layer 701 and the first source-drain metal layer 200 and is used to isolate the first source-drain metal layer 200 and the shielding layer 701 .
  • the material of the third insulating material layer 702 may be silicon oxide, silicon nitride, silicon oxynitride or other inorganic insulating materials.
  • the first insulating material layer 300 may include a first passivation layer 301 and a first planarization layer 302 .
  • the first passivation layer 301 covers the surface of the first source-drain metal layer 200 away from the base substrate 100 to protect the first source-drain metal layer 200 .
  • the material of the first passivation layer 301 may be silicon oxide, silicon nitride, silicon oxynitride or other dense inorganic insulating materials.
  • the first planarization layer 302 is located on the side of the first passivation layer 301 away from the base substrate 100 , and is used to provide a planarized surface for the second source-drain metal layer 400 .
  • the first planarization layer 302 may be an organic insulating material, so as to balance the stress distribution of the first source-drain metal layer 200 and the second source-drain metal layer 400 while providing a planarized surface, so as to improve the source-drain bridge region 031 deformability.
  • the material of the first planarization layer 302 may include polyimide.
  • the second source-drain metal layer 400 is disposed on the side of the first planarization layer 302 away from the base substrate 100 , which may include one layer of conductive material, or may include multiple layers of stacked conductive materials.
  • the second source-drain metal layer 400 may include a titanium layer, an aluminum layer, and a titanium layer that are sequentially stacked. It can be understood that, the materials of the first source-drain metal layer and the second source-drain metal layer 400 may be the same or different, which are not limited in the present disclosure.
  • the second insulating material layer 500 may include a second planarization layer 501 and a second passivation layer 502 that are stacked.
  • the second planarization layer 501 covers the side of the second source-drain metal layer 400 away from the base substrate 100 , and the material thereof may be an organic material, such as polyimide.
  • the second planarization layer 501 may also extend to other regions of the flexible array substrate, such as extending to the pixel island region 020 of the flexible array substrate, and provide a flat surface for the pixel electrodes in the pixel island region 020 surface.
  • the second planarization layer 501 may also extend to other regions of the flexible array substrate, for example, extend to the pixel island region 020 region of the flexible array substrate, and be patterned in the pixel island region 020 Define layers for pixels.
  • the second planarization layer 501 may also be a stack of multiple organic layers.
  • the second planarization layer 501 includes a first organic insulating layer and a second organic insulating layer sequentially stacked on a side of the second source-drain metal layer 400 away from the base substrate 100 layer, wherein the first organic insulating layer and the second organic insulating layer can extend to other regions of the flexible array substrate, such as extending to the pixel island region 020 of the flexible array substrate, where the first organic insulating layer can be a pixel in the pixel island region 020
  • the electrodes provide a planarized surface, and the second organic insulating layer may be patterned as a pixel definition layer in the pixel island region 020 .
  • the second passivation layer 502 is disposed on the side of the second planarization layer 501 away from the base substrate 100 , and can be made of silicon nitride, silicon oxynitride, silicon oxide or other inorganic insulating materials. In one embodiment of the present disclosure, the second passivation layer 502 is used as a mask layer so as to realize the patterning of the second planarization layer 501 .
  • the second insulating material layer 500 may be prepared by the following method: firstly forming a second planarization material layer and a second passivation material layer on the side of the second source/drain metal layer 400 away from the base substrate 100 in sequence, and then The second passivation material layer is patterned, so that the second passivation material layer forms an opening for exposing the second planarization material layer, and the patterned second passivation material layer is used as the second passivation layer 502; The second passivation layer 502 is used as a mask to etch the second planarization material layer to realize trenches on the second planarization material layer, and the patterned second planarization material layer is used as the second planarization layer 501.
  • the second insulating material layer 500 can include the stacked second planarization layer 501 and the second passivation layer 502, and the grooves of the second planarization layer 501 and the openings of the second passivation layer 502 together form the second insulating layer Isolation trenches 503 of material layer 500 .
  • a wet etching process can be used to etch the second planarizing material layer, so that the width of the groove on the second planarizing layer 501 is greater than the width of the opening of the second passivation layer 502, thereby making the isolation groove 503
  • the width of the end away from the base substrate 100 is smaller than the width of the end of the isolation trench 503 close to the base substrate 100 , or the second passivation layer 502 cannot be supported by the second planarization layer 501 near the opening.
  • a complete and unhollowed initial substrate substrate may be used to prepare the flexible array substrate; during the process of forming the isolation trenches 503 , or after forming the isolation trenches 503 , the flexible array substrate may be prepared Through holes 010 of the flexible array substrate are formed, so that the initial flexible array substrate is also patterned to form the base substrate 100 of the flexible array substrate.
  • the light-emitting elements of the flexible array substrate may be organic electroluminescent diodes.
  • an open mask may be used to vapor-deposit all or part of the materials of the organic light-emitting layer and the material of the common electrode layer to form the organic light-emitting layer 703 and the common electrode layer 704 .
  • the material of the organic light-emitting layer and the material of the common electrode layer are discontinuous at the sidewall of the isolation trench 503, thereby avoiding the formation of continuous water and oxygen intrusion channels.
  • the flexible array substrate may further include an organic light emitting layer stacked on a side of the second insulating material layer 500 away from the base substrate 100 .
  • layer 703 and the common electrode layer 704 , and the organic light-emitting layer 703 and the common electrode layer 704 are discontinuous at the position of the isolation trench 503 .
  • the encapsulation layer 600 may be disposed on the surface of the common electrode layer 704 away from the base substrate 100 .
  • the encapsulation layer 600 may be a thin film encapsulation layer 600, which may include alternately arranged inorganic material layers and organic material layers.
  • the preparation method of the flexible array substrate may include the following steps:
  • Step S110 as shown in FIG. 7 , a flexible base substrate 100 is provided on the support substrate 050 ; a first source-drain metal layer 200 is formed on the side of the base substrate 100 away from the support substrate 050 , and the first source-drain metal layer 200 is formed.
  • the metal layer 200 includes a plurality of first source-drain leads 201 in the source-drain bridge region 031 .
  • the supporting substrate 050 may be a glass substrate.
  • Step S120 as shown in FIG. 8 , a first insulating material layer 300 is formed on the side of the first source-drain metal layer 200 away from the base substrate 100 , and the first insulating material layer 300 covers each of the first source-drain bridge regions 031 .
  • Step S130 as shown in FIG. 9 , a second source-drain metal layer 400 is formed on the side of the first insulating material layer 300 away from the base substrate 100 ; in the source-drain bridge region 031 , the second source-drain metal layer 400 includes multiple two second source-drain leads 401, and the number of the second source-drain leads 401 is less than the number of the first source-drain leads 201;
  • Step S140 as shown in FIG. 10 and FIG. 11 , a second planarization layer 501 and a second passivation layer 502 are sequentially formed on the side of the second source-drain metal layer 400 away from the base substrate 100 , and then formed on the source-drain bridge.
  • the connecting region 031 covers the second insulating material layer 500 of each second source-drain lead 401;
  • Step S150 as shown in FIG. 12 , patterning the second insulating material layer 500 to form at least two isolation trenches 503 ; in the source-drain bridge region 031 , the isolation trenches 503 are on the second source-drain metal layer 400
  • the orthographic projection isolates the second source-drain lead 401 and the opening region 010 a on both sides of the source-drain bridge region 031 .
  • the opening area 010a may also be opened to form the through hole 010 in the opening area 010a.
  • Step S160 as shown in FIG. 13 , an encapsulation layer 600 is formed on the side of the second insulating material layer 500 away from the base substrate 100 .
  • step S170 the support substrate 050 is peeled off.
  • an organic light emitting layer 703 and a common electrode layer 704 may also be formed; the organic light emitting layer 703 and the common electrode layer 704 are discontinuous at the isolation trench 503 .
  • an encapsulation layer 600 may also be formed on the side of the common electrode layer 704 away from the base substrate 100 .
  • a structure of the pixel island region 020 is exemplarily introduced, so as to exemplarily show the connection method of each source-drain lead 040 of the source-drain bridge region 031 and the pixel island region 020, so as to explain and illustrate the source and drain more clearly.
  • the pixel island region 020 includes four pixels, each pixel includes three sub-pixels such as a red sub-pixel, a green sub-pixel and a blue sub-pixel, and each sub-pixel includes a pixel driving circuit and a The pixel electrode to which the driving circuit is electrically connected.
  • any pixel row includes two pixels arranged along the row direction A; as shown in FIG. 27 , in any pixel row, the pixel electrode 7053 of the blue sub-pixel and the pixel of the red sub-pixel
  • the electrodes 7051 are arranged along the row direction A, and are located on the side of the pixel electrode 7052 of the green sub-pixel away from another pixel row.
  • two pixel rows are formed with four pixel electrode rows, and the two pixel electrode rows in the middle each include two pixel electrodes 7052 of green sub-pixels arranged along the row direction A;
  • the pixel electrodes 7053 of the two blue sub-pixels and the pixel electrodes 7051 of the two red sub-pixels are arranged in the row direction A.
  • the four pixels also form two pixel columns, and any one pixel column includes two pixels arranged along the row direction B; wherein, in any one pixel column, the pixel electrodes 7053 of the two blue sub-pixels are arranged along the column direction, and the two pixel electrodes 7053 are arranged along the column direction.
  • the pixel electrodes 7051 of the red sub-pixels are arranged in the column direction, and the pixel electrodes 7052 of the two green sub-pixels are arranged in the column direction.
  • the pixel electrode 7051 of the red subpixel is located on the side of the setting direction C of the pixel electrode 7053 of the blue subpixel, and the setting direction C is a direction parallel to the row direction A.
  • the pixel island region 020 is provided with twelve pixel driving circuits connected to the twelve pixel electrodes in a one-to-one correspondence, and these pixel driving circuits are arranged in two rows, that is, the first row of pixels close to the source-drain bridge region 031 is included.
  • the driver circuit and the second row of pixel driver circuits far away from the source-drain bridge region 031 .
  • These pixel drive circuits are also distributed in six columns, which include a first column of pixel drive circuits, a second column of pixel drive circuits, a third column of pixel drive circuits, a fourth column of pixel drive circuits, a fifth column of pixel drive circuits, and a fifth column of pixel drive circuits arranged in sequence along the set direction C A column pixel driver circuit and a sixth column pixel driver circuit.
  • the pixel driving circuits in the pixel driving circuit in the first column and the pixel driving circuit in the fourth column are connected to the pixel electrode 7053 of the blue sub-pixel
  • the pixel driving circuit in the pixel driving circuit in the second column and the pixel driving circuit in the fifth column is connected to the pixel electrode 7053 of the blue sub-pixel.
  • the pixel electrode 7052 of the green sub-pixel is connected
  • the pixel driving circuits in the pixel driving circuit in the third column and the pixel driving circuit in the sixth column are connected with the pixel electrode 7051 of the red sub-pixel.
  • any one pixel driving circuit may be a 7T1C (7 thin film transistors, 1 storage capacitor Cst) structure.
  • the third thin film transistor T3 is used as a driving transistor, its first end is electrically connected to the second end of the fifth thin film transistor T5, its second end is electrically connected to the first end of the sixth thin film transistor T6, and its control end is connected to the storage
  • the first electrode plates of the capacitor Cst are electrically connected.
  • the first end of the first thin film transistor T1 is used for loading the initial signal (V init ), the second end is electrically connected to the first electrode plate of the storage capacitor Cst, and the control end is used for loading the reset signal (Reset).
  • the first end of the second thin film transistor T2 is electrically connected to the second end of the third thin film transistor T3, the second end is electrically connected to the first electrode plate of the storage capacitor Cst, and the control end is used for loading scan signals.
  • the first end of the fourth thin film transistor T4 is used to load the data signal (V data ), the second end is electrically connected to the first end of the third thin film transistor T3 , and the control end is used to load the scan signal (Gate).
  • the first end of the fifth thin film transistor T5 is used to load the power supply voltage (V DD ), the second end is electrically connected to the first end of the third thin film transistor T3, and the control end is used to load the enable signal (EM, Emission).
  • the first end of the sixth thin film transistor T6 is electrically connected to the second end of the third thin film transistor T3, the second end is used for electrical connection with the pixel electrode, and the control end is used for loading an enable signal (EM, Emission).
  • the first end of the seventh thin film transistor T7 is used for loading the initial signal (V init ), the second end is used for being electrically connected with the pixel electrode, and the control end is used for loading the reset signal.
  • the first electrode plate of the storage capacitor Cst is electrically connected to the control terminal of the third thin film transistor T3, and the second electrode plate is used for loading the power supply voltage (V DD ).
  • the flexible array substrate in the pixel island region 020 may include a base substrate, a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, and a second gate layer that are stacked in sequence. , an interlayer dielectric layer, a first source-drain metal layer, a first insulating material layer, a second source-drain metal layer, a second planarization layer, a pixel electrode layer, an organic light-emitting layer, a common electrode layer and an encapsulation layer. in,
  • the semiconductor layer 810 may be formed with a first channel region 8111 serving as a channel region of the first thin film transistor T1 and a channel serving as the second thin film transistor T2
  • the fifth channel region 8115 which is the channel region of T5, the sixth channel region 8116 which is the channel region of the sixth thin film transistor T6, the seventh channel region 8117 which is the channel region of the seventh thin film transistor T7, and
  • the first conductive segment 8121 is connected to the first end of the fourth channel region 8114 and is provided with a first via region 8131 in the semiconductor layer; the second conductive segment 8122 is connected to the second end of the fourth channel region 8114 and the fifth channel The first end of the region 8115, the first end of the third channel region 8113; the third conductive segment 8123 is connected to the second end of the fifth channel region 8115, and a sixth via region 8136 of the semiconductor layer is provided; the fourth conductive segment 8124 is connected The second end of the third channel region 8113, the first end of the sixth channel region 8116, the second end of the second channel region 8112; the fifth conductive segment 8125 is connected to the second end of the sixth channel region 8116, and the next pixel is driven The second end of the seventh channel region 8117 and the second end of the second channel region 8112 of the circuit are provided with a seventh via region 8137 of the semiconductor layer; the sixth conductive segment 8126 is connected to the first end of the second channel region 8112, The second end of the
  • the first gate layer may include a first gate lead 8211 , a second gate lead 8212 , a third gate lead 8213 , and a first gate structure including a pixel driving circuit.
  • the first gate lead 8211, the second gate lead 8212, and the third gate lead 8213 pass through the gate bridge region 032 and extend to the pixel wiring region.
  • the first gate structure of the pixel driving circuit includes a scan lead 8221 , an enable lead 8222 , a reset lead 8223 and a first electrode plate 0681 of a storage capacitor.
  • the reset lead 8223 segment includes a first lead region 8231 and a seventh lead region 8237; the orthographic projection of the first lead region 8231 on the semiconductor layer 810 coincides with the first channel region 8111 to serve as the gate of the first thin film transistor T1; The orthographic projection of the seventh lead region 8237 on the semiconductor layer 810 coincides with the seventh channel region 8117 to serve as the gate of the seventh thin film transistor T7.
  • the scanning lead 8221 segment includes a second lead region 8232 and a fourth lead region 8234; the orthographic projection of the second lead region 8232 on the semiconductor layer 810 is coincident with the second channel region 8112 to serve as the gate of the second thin film transistor T2; The orthographic projection of the fourth lead region 8234 on the semiconductor layer 810 coincides with the fourth channel region 8114 to serve as the gate of the fourth thin film transistor T4.
  • the enabling lead 8222 segment includes a fifth lead region 8235 and a sixth lead region 8236; the orthographic projection of the fifth lead region 8235 on the semiconductor layer 810 coincides with the fifth channel region 8115 to serve as the gate of the fifth thin film transistor T5 ; The orthographic projection of the sixth lead region 8236 on the semiconductor layer 810 coincides with the sixth channel region 8116 to serve as the gate of the sixth thin film transistor T6.
  • the orthographic projection of the first electrode plate 0681 of the storage capacitor on the semiconductor layer 810 completely covers the third channel region 8113, so that the first electrode plate 0681 of the storage capacitor can also serve as the gate of the third thin film transistor T3.
  • the first electrode plate 0681 of the storage capacitor is also provided with a fifth via region 8245 in the gate layer.
  • the second gate layer may include a fourth gate lead 8311 , a fifth gate lead 8312 , a sixth gate lead 8313 , and a second gate structure including a pixel driving circuit.
  • the fourth gate lead 8311, the fifth gate lead 8312, and the sixth gate lead 8313 pass through the gate bridge 032 region and extend to the pixel wiring region.
  • the second gate structure of the pixel driving circuit includes an initialization lead 8321, an auxiliary electrode plate 8322 and a second electrode plate 0682 of the storage capacitor.
  • the second electrode plate 0682 of the storage capacitor overlaps with the orthographic projection of the first electrode plate 0681 of the storage capacitor on the base substrate, and the orthographic projection of the fifth via region 8245 of the gate layer on the base substrate is located on the base plate of the storage capacitor. Outside the orthographic projection of the second electrode plate 0682 on the base substrate; the second electrode plate 0682 of the storage capacitor is provided with a fourth via area 8334 in the gate layer.
  • the third gate lead 8213 is provided with an eighth via region 8338 in the gate layer.
  • the auxiliary electrode plate 8322 is used to cover part of the sixth conductive segment 8126 and part of the first conductive segment 8121, and is provided with a ninth via area 8339 in the gate layer.
  • the sixth gate lead 8313 in the pixel wiring area is connected to the initialization lead 8321 of the pixel driving circuit close to the pixel wiring area.
  • the first source-drain metal layer includes a plurality of source-drain leads and a first source-drain conductive structure of the pixel driving circuit.
  • the first source-drain conductive structure of the pixel driving circuit includes a data lead structure 0421 , a power lead structure 0411 , a first connection lead 211 , a second connection lead 212 and a third connection lead 213 .
  • the power lead structure 0411 is arranged on one side of the set direction C of the data lead structure 0421, and the first connection lead 211, the second connection lead 212 and the third connection lead 213 are arranged on the side of the set direction C of the power lead structure 0411. side.
  • the data lead structure 0421 is provided with a source-drain first via region 221, and the source-drain first via region 221 is connected with the first via region 8131 of the semiconductor layer to form a first metallized via.
  • the power supply lead structure 0411 is provided with a fourth source-drain via region 224, a sixth source-drain via region 226 and a ninth source-drain via region 229; the source-drain fourth via region 224 and the gate layer fourth via region 8334 is connected to form a fourth metallized via, the source-drain sixth via region 226 is connected to the semiconductor layer sixth via region 8136 to form a sixth metallized via, the source-drain ninth via region 229 is connected to the gate layer The ninth via region 8339 is connected to form a ninth metallized via.
  • the first connection lead 211 is provided with a source-drain eighth via region 228 and a source-drain second via region 222, and the source-drain eighth via region 228 is connected to the gate layer eighth via region 8338 to form an eighth metallization Via, source and drain second via area 222 is connected with the second via area 8132 of the semiconductor layer to form a second metallized via;
  • the second connection lead 212 is provided with a source/drain third via area 223 and a source/drain fifth via area
  • the via area 225, the source/drain third via area 223 and the semiconductor layer third via area 8133 are connected to form a third metallized via area, the source/drain fifth via area 225 and the gate layer fifth via area 8245 connected to form a fifth metallization via;
  • the third connection lead 213 is provided with a source-drain seventh via region 227, and the source-drain seventh via region 227 is connected to the semiconductor layer seventh via region 8137 to form a seventh metallization via
  • the source-drain leads located in the first source-drain metal layer include the first source-drain leads 201 of the array substrate and a plurality of wiring leads located in the pixel island region 020 .
  • the first source-drain lead 201 includes a first metal lead 231 , a second metal lead 232 , a third metal lead 233 , a fourth metal lead 234 and a fifth metal lead 231 , which are sequentially arranged in the source-drain bridge region 031 along the set direction C.
  • Metal lead 235 wherein, the first metal lead 231, the second metal lead 232, the third metal lead 233, and the fourth metal lead 234 extend to the pixel wiring area 021; One side of a column of pixel driving circuits passes through the pixel island region.
  • the wiring leads include sixth metal leads 246 to twelfth metal leads 2412 located between two columns of pixels; wherein, the third metal leads 233 and the twelfth metal leads 2412 are connected.
  • the first metal lead 231 is connected to the data lead structure 0421 of the pixel driver circuit in the first column
  • the second metal lead 232 is connected to the data lead structure 0421 of the pixel drive circuit in the second column
  • the fourth metal lead 234 is connected to the fifth column of pixels.
  • the data lead structure 0421 of the driver circuit is connected.
  • the sixth metal lead 246 is connected to the enable lead 8222 of the pixel driving circuit of the second row through a via hole, and is connected to the first gate lead 8211 through a via hole.
  • the seventh metal lead 247 is connected to the scan lead 8221 of the pixel driving circuit of the second row through the via hole, and is connected to the fourth gate lead 8311 through the via hole.
  • the eighth metal lead 248 is connected to the enable lead 8222 of the pixel driving circuit of the first row through the via hole, and is connected to the second gate lead 8212 through the via hole.
  • the ninth metal lead 249 is connected to the scan lead 8221 of the pixel driving circuit of the first row through the via hole, and is connected to the reset lead 8223 of the pixel driver circuit of the second row through the via hole, and is connected to the fifth gate lead 8312 through the via hole.
  • the tenth metal lead 2410 is connected to the reset lead 8223 of the pixel driving circuit of the first row through a via hole, and is connected to the third gate lead 8213 through a via hole.
  • the eleventh metal lead 2411 is connected to the initialization leads 8321 of the pixel driving circuits of the first row through via holes, and is connected to the initialization leads 8321 of the pixel driver circuits of the second row through the via holes.
  • the second source-drain metal layer includes a plurality of source-drain leads and a second source-drain conductive structure of the pixel driving circuit.
  • the second source-drain conductive structure of the pixel driving circuit includes a column-direction power supply lead 411, a row-direction power supply lead 412, and a transfer pad 413, wherein the column-direction power supply lead 411 and the row-direction power supply lead 412 are connected to each other and are connected to each other through via holes.
  • the power lead structure 0411 of the pixel driving circuit is electrically connected.
  • the transfer pad 413 is connected to the third connection lead 213 of the pixel driving circuit through a via hole.
  • the source-drain lead located in the second source-drain metal layer includes a second source-drain lead 401, and the second source-drain lead 401 includes a thirteenth metal lead 4313, a thirteenth metal lead 4313, a third metal lead 4313, a Fourteen metal leads 4314 , fifteenth metal leads 4315 , and sixteenth metal leads 4316 .
  • the thirteenth metal lead 4313 extends to the pixel wiring area 022 and is connected to the column direction power lead 411 of the pixel driving circuit.
  • the fourteenth metal wire 4314 extends to the pixel wiring area 022 and is connected to the data wire structure 0421 of the pixel driving circuit in the third column through via holes.
  • the fifteenth metal wire 4315 extends to the pixel wiring area 020, and is connected to the data wire structure 0421 of the fourth column of pixel driving circuits through via holes.
  • the sixteenth metal wire 4316 extends to the pixel wiring area 022 and is connected to the data wire structure 0421 of the sixth column of pixel driving circuits through via holes.
  • the first metal wire 231 is used to load the data signal (V data ) to the data wire structure 0421 of the pixel driving circuit of the first column; the second metal wire 232 is used to load data to the data wire structure 0421 of the pixel driving circuit of the second column signal (V data ); the fourth metal lead 234 is used to load the data signal (V data ) to the data lead structure 0421 of the pixel drive circuit in the fifth column; the thirteenth metal lead 4313 is used to supply the power lead of the pixel drive circuit of each column
  • the structure 0411 loads the power supply voltage; the fourteenth metal wire 4314 is used to load the data signal (V data ) to the data wire structure 0421 of the pixel driver circuit of the third column;
  • the data lead structure 0421 is used to load the data signal (V data ); the sixteenth metal lead 4316 is used to load the data signal (V data ) to the data lead structure 0421 of the pixel driving circuit in the sixth column.
  • the pixel electrode layer is provided with twelve pixel electrodes, each pixel electrode is disposed correspondingly to the transfer pad 413 of each pixel driving circuit, and the pixel electrode is electrically connected to the corresponding transfer pad 413 through a via hole.
  • Embodiments of the present disclosure further provide a display device, where the display device includes any one of the flexible array substrates described in the flexible array substrate embodiments above.
  • the display device may be a helmet display, a quad-curved mobile phone or other types of display devices. Since the display device has any one of the flexible array substrates described in the above-mentioned embodiments of the flexible array substrate, it has the same beneficial effects, which will not be repeated in the present disclosure.

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Abstract

一种柔性阵列基板和显示装置，该柔性阵列基板包括至少一个可拉伸区域；可拉伸区域被多个贯穿孔(010)划分出像素岛区(020)和桥连区(030)，桥连区(030)包括源漏桥连区(031)。柔性阵列基板在任意一个源漏桥连区(031)包括依次层叠设置的衬底基板(100)、多个第一源漏引线(201)、第一绝缘材料层(300)、多个第二源漏引线(401)、第二绝缘材料层(500)和封装层(600)；第二源漏引线(401)的数量少于第一源漏引线(201)的数量；第二绝缘材料层(500)设置有多个隔离槽(503)，隔离槽(503)在第二源漏金属层(400)上的正投影隔离第二源漏引线(401)和贯穿孔(010)。该柔性阵列基板能够提高可拉伸区域的封装效果。

Description

柔性阵列基板和显示装置
交叉引用
本公开要求于2020年7月22日提交的申请号为202010711869.2名称为“柔性阵列基板和显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种柔性阵列基板和显示装置。
背景技术
柔性可拉伸(Stretchable)显示面板广泛应用于具有弯曲显示面的显示装置中。在柔性可拉伸显示面板中，可拉伸区域可以采用挖孔设计以形成像素岛区和桥连区组成的岛桥区。在岛桥区周围可以设置有隔离槽，以避免水汽侵入像素岛区和桥连区。然而，隔离槽的设置使得桥连区的信号引线密度变大且使得信号引线与隔离槽距离更小，水汽容易从隔离槽侵入信号引线而导致桥连区的电气性能降低。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种柔性阵列基板和显示装置，提高可拉伸区域的封装效果。
为实现上述发明目的，本公开采用如下技术方案：
根据本公开的第一个方面，提供一种柔性阵列基板，包括至少一个可拉伸区域；所述柔性阵列基板在所述可拉伸区域内设置有多个贯穿孔，多个所述贯穿孔将所述可拉伸区域划分出用于显示的像素岛区和用于传输信号的桥连区；所述桥连区包括源漏桥连区，所述柔性阵列基板在任意一个所述源漏桥连区包括：
衬底基板；
第一源漏金属层，设于所述衬底基板的一侧，且包括多个第一源漏引线；
第一绝缘材料层，设于所述第一源漏金属层远离所述衬底基板的一侧；
第二源漏金属层，设于所述第一绝缘材料层远离所述衬底基板的一侧；所述第二源漏金属层包括多个第二源漏引线，且所述第二源漏引线的数量少于所述第一源漏引线的数量；
第二绝缘材料层，设于所述第二源漏金属层远离所述衬底基板的一侧；所述第二绝缘材料层设置有多个隔离槽，所述隔离槽在所述第二源漏金属层上的正投影隔离所 述第二源漏引线和所述贯穿孔；
封装层，设于所述第二绝缘材料层远离所述衬底基板的一侧。
在本公开的一种示例性实施例中，在所述源漏桥连区，所述第二源漏引线在所述第二绝缘材料层上的正投影与所述隔离槽之间的距离的最小值，不小于相邻两个所述第二源漏引线之间的间距。
在本公开的一种示例性实施例中，在所述源漏桥连区，所述隔离槽的宽度，不大于相邻两个所述第二源漏引线之间的间距的2倍。
在本公开的一种示例性实施例中，在所述源漏桥连区，所述隔离槽的宽度，等于相邻两个所述第二源漏引线之间的间距的0.9～1.1倍；在所述第二源漏引线与一个相邻的所述贯穿孔之间，所述隔离槽的数量为多个，且相邻两个所述隔离槽之间的间距等于相邻两个所述第二源漏引线之间的间距的0.9～1.1倍。
在本公开的一种示例性实施例中，在所述源漏桥连区，相邻两个所述第二源漏引线之间的间距，不大于所述第二源漏引线的宽度的2倍。
在本公开的一种示例性实施例中，在所述源漏桥连区，多个所述第二源漏引线等间距排布；所述源漏桥连区相邻的两个所述贯穿孔，与所述第二源漏引线之间的最小距离相等。
在本公开的一种示例性实施例中，在所述源漏桥连区，相邻两个所述第一源漏引线之间的间距，不大于相邻两个所述第二源漏引线之间的间距。
在本公开的一种示例性实施例中，在所述源漏桥连区，所述第一源漏引线在所述第二绝缘材料层上的正投影与所述隔离槽之间的距离的最小值，不大于所述第二源漏引线在所述第二绝缘材料层上的正投影与所述隔离槽之间的距离的最小值。
在本公开的一种示例性实施例中，在所述源漏桥连区，所述第一源漏引线在所述第二绝缘材料层上的正投影，与所述隔离槽至少部分交叠。
在本公开的一种示例性实施例中，在所述源漏桥连区，所述第一源漏引线在所述第二绝缘材料层上的正投影与所述隔离槽之间的距离的最小值为1.5～2.7微米；所述第二源漏引线在所述第二绝缘材料层上的正投影与所述隔离槽之间的距离的最小值为4.5～6.0微米。
在本公开的一种示例性实施例中，所述第一源漏引线的数量比所述第二源漏引线的数量大1或2。
在本公开的一种示例性实施例中，所述隔离槽远离所述衬底基板的一端的宽度，小于所述隔离槽靠近所述衬底基板的一端的宽度。
在本公开的一种示例性实施例中，在所述源漏桥连区，所述第一源漏引线的延伸方向与所述贯穿孔的延伸方向平行或者垂直；所述第二源漏引线的延伸方向与所述贯穿孔的延伸方向平行或者垂直。
在本公开的一种示例性实施例中，所述像素岛区包括多个子像素，任意一个所述 子像素沿行方向的尺寸为第一尺寸；在所述源漏桥连区，相邻两个所述第二源漏引线之间的间距等于第二尺寸；所述第一尺寸大于所述第二尺寸。
在本公开的一种示例性实施例中，所述贯穿孔包括沿行方向延伸的第一长条孔和沿列方向延伸的第二长条孔；所述源漏桥连区位于所述第一长条孔的端部与所述第二长条孔的侧边之间。
在本公开的一种示例性实施例中，任意一个所述像素岛区位于相邻的两个所述第一长条孔之间，且位于相邻的两个所述第二长条孔之间；任意一个所述像素岛区包括四个像素，任意一个所述像素包括红色子像素、绿色子像素和蓝色子像素。
在本公开的一种示例性实施例中，在任意一个所述像素岛区，四个所述像素形成两个像素行，任意一个所述像素行包括沿所述行方向排列的两个所述像素；
其中，任意一个所述像素行中，所述蓝色子像素的像素电极和所述红色子像素的像素电极沿所述行方向排列，且位于所述绿色子像素的像素电极远离另一个所述像素行的一侧。
在本公开的一种示例性实施例中，所述柔性阵列基板在任意一个所述像素岛区包括阵列设置的多个子像素，任意一个所述子像素包括像素驱动电路和与所述像素驱动电路电连接的像素电极；任意一个所述像素驱动电路包括存储电容、第一薄膜晶体管至第七薄膜晶体管；其中，
所述第一薄膜晶体管的第一端用于加载初始信号，所述第一薄膜晶体管的第二端与所述存储电容的第一电极板电连接，所述第一薄膜晶体管的控制端用于加载复位信号；
所述第二薄膜晶体管的第一端与所述第三薄膜晶体管的第二端、所述第六薄膜晶体管的第一端电连接，所述第二薄膜晶体管的第二端与所述存储电容的第一电极板电连接，所述第二薄膜晶体管的控制端用于加载扫描信号；
所述第三薄膜晶体管的第一端与所述第四薄膜晶体管的第二端、所述第五薄膜晶体管的第二端电连接，所述第三薄膜晶体管的控制端与所述存储电容的第一电极板电连接；
所述第四薄膜晶体管的第一端用于加载数据信号，所述第四薄膜晶体管的控制端用于加载所述扫描信号；
所述第五薄膜晶体管的第一端用于加载电源电压，所述第五薄膜晶体管的控制端用于加载使能信号；
所述第六薄膜晶体管的第二端用于与所述像素电极电连接，所述第六薄膜晶体管的控制端用于加载所述使能信号；
所述第七薄膜晶体管的第一端用于加载所述初始信号，所述第七薄膜晶体管的第二端用于与所述像素电极电连接，所述第七薄膜晶体管的控制端用于加载所述复位信号；
所述存储电容的第二电极板用于加载所述电源电压。
在本公开的一种示例性实施例中，任意一个所述像素岛区包括沿设定方向依次排列的第一列像素驱动电路至第六列像素驱动电路，任意一列像素驱动电路包括沿列方向排列的多个所述像素驱动电路；其中，所述设定方向为平行于行方向的一个方向；
在所述源漏桥连区，所述第一源漏引线的数量为五个；沿所述设定方向的第一个所述第一源漏引线用于向所述第一列像素驱动电路加载所述数据信号；沿所述设定方向的第二个所述第一源漏引线用于向所述第二列像素驱动电路加载所述数据信号；沿所述设定方向的第四个所述第一源漏引线用于向所述第五列像素驱动电路加载所述数据信号。
在本公开的一种示例性实施例中，在所述源漏桥连区，所述第二源漏引线的数量为四个；沿所述设定方向的第一个所述第二源漏引线用于向所述第一列像素驱动电路至所述第六列像素驱动电路加载所述电源电压；沿所述设定方向的第二个所述第二源漏引线用于向所述第三列像素驱动电路加载所述数据信号；沿所述设定方向的第三个所述第二源漏引线用于向所述第四列像素驱动电路加载所述数据信号；沿所述设定方向的第四个所述第二源漏引线用于向所述第六列像素驱动电路加载所述数据信号。
根据本公开的第二个方面，提供一种显示装置，包括上述的柔性阵列基板。
本公开提供的柔性阵列基板和显示装置，在源漏桥连区设置有两层源漏金属层，可以提高源漏金属层形成的各个源漏引线的宽度和源漏引线之间的间距，降低源漏引线之间的串扰并降低源漏引线的阻抗，提升源漏引线的可弯折性能并进而提高可拉伸区域的拉伸性能和电气稳定性。不仅如此，第二源漏引线的数量少于第一源漏引线的数量，可以使得第二源漏引线与隔离槽之间的间距增大，降低水汽通过隔离槽侵入第二源漏引线的风险，提高可拉伸区域的封装的可靠性，进一步提高可拉伸区域的电气稳定性。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是本公开一种实施方式的可拉伸区域的结构示意图。
图2是本公开一种实施方式的柔性阵列基板在源漏桥连区的结构示意图。
图3是本公开一种实施方式的柔性阵列基板在源漏桥连区的结构示意图。
图4是本公开一种实施方式的柔性阵列基板在源漏桥连区的结构示意图。
图5是本公开一种实施方式的柔性阵列基板在源漏桥连区的结构示意图。
图6是本公开一种实施方式的柔性阵列基板在源漏桥连区的俯视结构示意图；其中，图6仅仅示出了贯穿孔、第一源漏引线、第二源漏引线和隔离槽的相对位置关系。
图7是本公开一种实施方式的在源漏桥连区形成第一源漏引线的结构示意图。
图8是本公开一种实施方式的在源漏桥连区形成第一绝缘材料层的结构示意图。
图9是本公开一种实施方式的在源漏桥连区形成第二源漏引线的结构示意图。
图10是本公开一种实施方式的在源漏桥连区形成第二平坦化层的结构示意图。
图11是本公开一种实施方式的在源漏桥连区形成第二钝化层的结构示意图。
图12是本公开一种实施方式的在源漏桥连区形成隔离槽的结构示意图。
图13是本公开一种实施方式的在源漏桥连区形成封装层的结构示意图。
图14是本公开一种实施方式的在源漏桥连区形成有机发光层和公共电极层的结构示意图。
图15是本公开一种实施方式的在源漏桥连区形成封装层的结构示意图。
图16是本公开一种实施方式的像素驱动电路的等效电路图。
图17是本公开一种实施方式的像素驱动电路的半导体层的结构示意图。
图18是本公开一种实施方式的像素驱动电路的第一栅极层的结构示意图。
图19是本公开一种实施方式的像素驱动电路的第二栅极层的结构示意图。
图20是本公开一种实施方式的像素驱动电路的第一源漏金属层的结构示意图。
图21是本公开一种实施方式的像素驱动电路的第二源漏金属层的结构示意图。
图22是本公开一种实施方式的可拉伸区域的半导体层的结构示意图。
图23是本公开一种实施方式的可拉伸区域的第一栅极层的结构示意图。
图24是本公开一种实施方式的可拉伸区域的第二栅极层的结构示意图。
图25是本公开一种实施方式的可拉伸区域的第一源漏金属层的结构示意图。
图26是本公开一种实施方式的可拉伸区域的第二源漏金属层的结构示意图。
图27是本公开一种实施方式的可拉伸区域的像素电极层的结构示意图。
图中主要元件附图标记说明如下：
A、行方向；B、列方向；C、设定方向；010、贯穿孔；010a、开孔区；011、第一长条孔；012、第二长条孔；020、像素岛区；021、像素分布区；022、像素布线区；030、桥连区；031、源漏桥连区；032、栅极桥连区；040、源漏引线；041、电源引线；042、数据引线；050、支撑基板；0681、存储电容的第一电极板；0682、存储电容的第二电极板；100、衬底基板；200、第一源漏金属层；201、第一源漏引线；211、第一连接引线；212、第二连接引线；213、第三连接引线；221、源漏第一过孔区；222、源漏第二过孔区；223、源漏第三过孔区；224、源漏第四过孔区；225、源漏第五过孔区；226、源漏第六过孔区；227、源漏第七过孔区；228、源漏第八过孔区；229、源漏第九过孔区；231、第一金属引线；232、第二金属引线；233、第三金属引线；234、第四金属引线；235、第五金属引线；246、第六金属引线；247、第七金属引线；248、第八金属引线；249、第九金属引线；2410、第十金属引线；2411、第十一金属引线；2412、第十二金属引线；300、第一绝缘材料层；301、第一钝化层；302、第一平坦化层；400、第二源漏金属层；401、第二源漏引线；411、列向电源引线；412、行向电 源引线；413、转接焊盘；4313、第十三金属引线；4314、第十四金属引线；4315、第十五金属引线；4316、第十六金属引线；500、第二绝缘材料层；501、第二平坦化层；502、第二钝化层；503、隔离槽；600、封装层；701、屏蔽层；702、第三绝缘材料层；703、有机发光层；704、公共电极层；7051、红色子像素的像素电极；7052、绿色子像素的像素电极；7053、蓝色子像素的像素电极；810、半导体层；8111、第一沟道区；8112、第二沟道区；8113、第三沟道区；8114、第四沟道区；8115、第五沟道区；8116、第六沟道区；8117、第七沟道区；8121、第一导电段；8122、第二导电段；8123、第三导电段；8124、第四导电段；8125、第五导电段；8126、第六导电段；8127、第七导电段；8131、半导体层第一过孔区；8132、半导体层第二过孔区；8133、半导体层第三过孔区；8136、半导体层第六过孔区；8137、半导体层第七过孔区；8211、第一栅极引线；8212、第二栅极引线；8213、第三栅极引线；8221、扫描引线；8222、使能引线；8223、复位引线；8231、第一引线区；8232、第二引线区；8234、第四引线区；8235、第五引线区；8236、第六引线区；8237、第七引线区；8245、栅极层第五过孔区；8311、第四栅极引线；8312、第五栅极引线；8313、第六栅极引线；8321、初始化引线；8322、辅助电极板；8334、栅极层第四过孔区；8338、栅极层第八过孔区；8339、栅极层第九过孔区。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
本公开提供一种柔性阵列基板，该柔性阵列基板包括至少一个可拉伸区域；如图 1所示，柔性阵列基板在可拉伸区域内设置有多个贯穿孔010，多个贯穿孔010将可拉伸区域划分出用于显示的像素岛区020和用于传输信号的桥连区030；其中，桥连区030包括源漏桥连区031；如图2和图3所示，柔性阵列基板在任意一个源漏桥连区031包括衬底基板100、第一源漏金属层200、第一绝缘材料层300、第二源漏金属层400、第二绝缘材料层500和封装层600。第一源漏金属层200设于衬底基板100的一侧，且包括多个第一源漏引线201；第一绝缘材料层300设于第一源漏金属层200远离衬底基板100的一侧；第二源漏金属层400设于第一绝缘材料层300远离衬底基板100的一侧；第二源漏金属层400包括多个第二源漏引线401，且第二源漏引线401的数量少于第一源漏引线201的数量；第二绝缘材料层500设于第二源漏金属层400远离衬底基板100的一侧；参见图6和图12，第二绝缘材料层500设置有多个隔离槽503(图2和图3中被封装层600填充)，隔离槽503在第二源漏金属层400上的正投影隔离第二源漏引线401和贯穿孔010；封装层600设于第二绝缘材料层500远离衬底基板100的一侧。
本公开提供的柔性阵列基板，在源漏桥连区031设置有两层源漏金属层，可以提高源漏金属层形成的各个源漏引线040的宽度和源漏引线040之间的间距，降低源漏引线040之间的串扰并降低源漏引线040的阻抗，提升源漏引线040的可弯折性能并进而提高可拉伸区域的拉伸性能和电气稳定性。不仅如此，第二源漏引线401的数量少于第一源漏引线201的数量，可以使得第二源漏引线401与隔离槽503之间的间距增大，降低水汽通过隔离槽503侵入第二源漏引线401的风险，提高可拉伸区域的封装的可靠性，进一步提高可拉伸区域的电气稳定性。
在本公开中，源漏桥连区031内的某一结构的宽度指的是，该结构在衬底基板100上的正投影，在衬底基板100的平面内且垂直于源漏引线040的延伸方向上的尺寸。举例而言，源漏引线的宽度指的是，在源漏桥连区031的源漏引线040在衬底基板100上的正投影，在衬底基板100的平面内且垂直于源漏引线040的延伸方向上的尺寸。再举例而言，隔离槽503的宽度指的是，在源漏桥连区031的隔离槽503在衬底基板100上的正投影，在衬底基板100的平面内且垂直于源漏引线040的延伸方向上的尺寸。
下面，结合附图对本公开提供的柔性阵列基板的结构、原理和效果做进一步的解释和说明。
本公开提供的柔性阵列基板具有至少一个可拉伸区域，该可拉伸区域可以通过拉伸形变而适应弯曲表面，并在拉伸后依然能够实现显示功能。可拉伸区域可以位于柔性阵列基板的边缘、角部等局部区域，也可以覆盖整个柔性阵列基板的显示区，本公开对此不做特殊的限定。举例而言，在本公开的一种实施方式中，柔性阵列基板可以具有四个可拉伸区域，且该四个可拉伸区域位于柔性阵列基板的四个顶角处；如此，该柔性阵列基板可以应用于四曲面显示屏。再举例而言，在本公开的另一种实施方式 中，该柔性阵列基板的可拉伸区域至少覆盖该柔性阵列基板的显示区，即该柔性阵列基板的显示区均为可拉伸区域；如此，该柔性阵列基板可以用于制备头戴式显示头盔。
在可拉伸区域，如图1所示，柔性阵列基板可以设置有多个贯穿孔010，以提高可拉伸区域的拉伸性能。贯穿孔010可以将可拉伸区域划分为相互连接的岛桥区域，该岛桥区域包括用于显示的像素岛区020和用于传输信号的桥连区030，相邻像素岛区020之间通过桥连区030连接。贯穿孔010的形状和设置方式可以根据需求进行选择和确定，其可以为工字型孔、长条孔或者其他形状的贯穿孔010。柔性阵列基板还设置有隔离槽503，隔离槽503环绕各个贯穿孔010设置，以便阻断水氧从贯穿孔010向岛桥区域入侵的通道，达成对像素岛区020和桥连区030的保护。
可选地，贯穿孔010可以为长条形孔。参见图1，贯穿孔010可以包括沿行方向A延伸的第一长条孔011和沿列方向B延伸的第二长条孔012；其中，同一行的相邻两个第一长条孔011之间设置有一个第二长条孔012，相邻两行第一长条孔011交错排布；同一列的相邻两个第二长条孔012之间设置有一个第一长条孔011，且相邻两列第二长条孔012交错排布。如此，一个像素岛区020周围具有两个第一长条孔011和两个第二长条孔012，一个第一长条孔011用于分割相邻的两列像素岛区020，一个第二长条孔012用于分割相邻的两行像素岛区020。桥连区030包括栅极桥连区032和源漏桥连区031，其中，栅极桥连区032位于第一长条孔011的侧边与第二长条孔012的端部之间，用于连接同行相邻设置的两个像素岛区020；源漏桥连区031位于第一长条孔011的端部与第二长条孔012的侧边之间，用于连接同列相邻设置的两个像素岛区020。
进一步地，像素岛区020可以包括像素分布区021和像素分布区021两侧的两个像素布线区022。像素分布区021可以设置有一个或者多个像素，每个像素可以包括一个或者多个子像素。可选地，各个子像素可以为自发光的发光元件，例如可以具有OLED(有机电致发光二极管)、Micro LED(微发光二极管)等。可选地，每个像素可以包括多种不同颜色的子像素，以便通过不同颜色的子像素的混色实现彩色显示。举例而言，在本公开的一种实施方式中，一个像素岛区020可以包括四个像素，每个像素包括一个红色子像素、一个绿色子像素和一个蓝色子像素。换言之，任意一个像素岛区020位于相邻的两个第一长条孔011之间，且位于相邻的两个第二长条孔012之间；任意一个像素岛区020包括四个像素，任意一个像素包括红色子像素、绿色子像素和蓝色子像素。
可选地，任意一个子像素沿行方向A的尺寸为第一尺寸；在源漏桥连区031，相邻两个第二源漏引线401之间的间距等于第二尺寸；第一尺寸大于第二尺寸。
如图1所示，像素布线区022位于像素分布区021靠近第一长条孔011的一侧，且与源漏桥连区031、栅极桥连区032连接。换言之，在像素岛区020内，沿列方向B，依次设置有像素布线区022、像素分布区021和像素布线区022。如此，像素分布区 021可以通过像素布线区022将各个源漏引线040汇聚至源漏桥连区031，像素分布区021可以通过像素布线区022将各个栅极引线汇聚至栅极桥连区032。
可选地，栅极桥连区032可以设置有栅极引线，以便为像素岛区020提供扫描信号、使能信号、复位信号、初始化信号等栅极信号中的一种或者多种；当然的，栅极桥连区032的栅极引线还可以用于为柔性阵列基板的其他区域的像素提供扫描信号、使能信号、复位信号、初始化信号等栅极信号中的一种或者多种。
源漏桥连区031可以设置有源漏引线040，源漏引线040包括位于第一源漏金属层200的第一源漏引线201和位于第二源漏金属层400的第二源漏引线401。源漏引线040用于为像素岛区020提供数据信号、电源电压，或者用于传输像素岛区020的感测信号等。当然的，如果柔性阵列基板的可拉伸区域以外还设置有子像素，在一些情形下，源漏桥连区031的源漏引线040还可以为柔性阵列基板的其他区域的像素提供数据信号、电源电压等，或者还可以传输其他区域的像素的感测信号等。
优选地，在源漏桥连区031，第一源漏引线201的延伸方向与贯穿孔010的延伸方向平行或者垂直；第二源漏引线401的延伸方向与贯穿孔010的延伸方向平行或者垂直。进一步的地，在源漏桥连区031，第一源漏引线201和第二源漏引线401的延伸方向与第二长条孔012的延伸方向平行。即，在源漏桥连区031，第一源漏引线201和第二源漏引线401的延伸方向为列方向B。
可选地，在像素布线区022，第一源漏引线201和第二源漏引线401的延伸方向与贯穿孔010的延伸方向平行或者垂直。换言之，对于任意一个第一源漏引线201或者第二源漏引线401，在像素布线区022，其可以沿行方向A延伸，也可以沿列方向B延伸，还可以局部沿行方向A延伸且其余部分沿列方向B延伸。
在本公开的一种实施方式中，柔性阵列基板在可拉伸区域以外还设置有像素，这些像素中的第一部分的源漏引线040不经过可拉伸区域，这些像素中的第二部分可以与像素岛区020中的像素共用源漏引线040，这些像素中的第三部分的源漏引线040可以穿过可拉伸区域的源漏桥连区031且不用于驱动像素岛区020的像素。
如图1所示，在源漏桥连区031，源漏引线040包括用于加载电源电压的电源引线041和用于加载数据信号的数据引线042。其中，图1中仅仅示例性地画出了一根电源引线041和一根数据引线042，该图1仅用于示意存在电源引线041和数据引线042，而非用于示意电源引线041的数量和数据引线042的数量。
可选地，在一个源漏桥连区031，可以仅设置一条电源引线041，该电源引线041在像素岛区020可以通过桥接等方式向各个子像素提供电源电压。如此，可以减少源漏桥连区031的源漏引线040数量，进而便于提高源漏引线040的间距和源漏引线040的宽度，进而提高源漏引线040的可弯折性能并进而提高可拉伸区域的拉伸性能和电气稳定性。不仅如此，由于源漏引线040的数量减少，还可以使得源漏引线040距离贯穿孔010和隔离槽503的距离更远，能够提高可拉伸区域的封装的可靠性。尤其是， 在源漏桥连区031的源漏引线040数量的减少，便于减小源漏桥连区031的宽度并减少源漏桥连区031的面积占比，提高像素岛区020的尺寸和面积占比，进而提高柔性阵列基板在可拉伸区域的像素密度或者发光面积，提高显示效果。
可选地，电源引线041的宽度大于数据引线042的宽度，以降低电源引线041的压降。优选地，电源引线041的宽度为数据引线042的宽度的1.5～3倍。
在本公开的一种实施方式中，在一个源漏桥连区031，电源引线041的数量为一个，且该电源引线041为一根第二源漏引线401。
示例性地，在本公开的一种实施方式中，像素岛区020包括4个像素，每个像素包括3个独立发光的子像素，3个子像素分别为红色子像素、绿色子像素和蓝色子像素。在一个源漏桥连区031，可以设置有9根源漏引线040，该9根源漏引线040包括5根第一源漏引线201和4根第二源漏引线401。其中1根第二源漏引线401作为电源引线041，用于向像素岛区020的各个子像素加载电源电压；6根源漏引线040作为数据引线042，用于向像素岛区020的各个子像素加载数据信号；2根源漏引线040作为数据引线042，用于向可拉伸区域以外的子像素提供数据信号，且不用于向像素岛区020的子像素提供数据信号。相较于将所有源漏引线040设置于同一源漏金属层的方案，该实施方式可以将源漏引线040的总布线宽度降低43％，且能够保证各个源漏引线040的封装效果。
可选地，在源漏桥连区031，第二源漏引线401在第二绝缘材料层500上的正投影与隔离槽503之间的距离的最小值，不小于相邻两个第二源漏引线401之间的间距。如此，可以保证第二源漏引线401与隔离槽503之间具有足够大的距离，使得水汽难以通过隔离槽503侵入第二源漏引线401，进而避免第二源漏引线401的电气性能下降。
优选地，在源漏桥连区031，第二源漏引线401在第二绝缘材料层500上的正投影与隔离槽503之间的距离的最小值，等于相邻两个第二源漏引线401之间的间距的1.5～2.0倍。举例而言，在本公开的一种实施方式中，在源漏桥连区031，相邻两根第二源漏引线401之间的间距等于3微米，第二源漏引线401在第二绝缘材料层500上的正投影与隔离槽503之间的距离的最小值等于4.5～6.0微米。
可选地，隔离槽503的宽度，不大于相邻两个第二源漏引线401之间的间距的2倍。如此，可以避免隔离槽503的宽度太大而压缩第二源漏引线401与隔离槽503之间的距离，保证第二源漏引线401与隔离槽503之间具有足够大的距离，使得水汽难以通过隔离槽503侵入第二源漏引线401。不仅如此，通过减小隔离槽503的宽度，还便于设置更多个隔离槽503以进一步提高源漏桥连区031的封装稳定性。
可选地，在源漏桥连区031，在第二源漏引线401与一个相邻的贯穿孔010之间，隔离槽503的数量为多个，且相邻两个隔离槽503之间的间距不大于相邻两个第二源漏引线401之间的间距的2倍。如此，当源漏桥连区031的单侧设置多个隔离槽503 时，可以避免隔离槽503的间距过大而压缩第二源漏引线401与隔离槽503之间的距离，保证第二源漏引线401与隔离槽503之间具有足够大的距离，使得水汽难以通过隔离槽503侵入第二源漏引线401。不仅如此，通过减小隔离槽503的间距，还便于设置更多个隔离槽503以进一步提高源漏桥连区031的封装稳定性。
优选地，在源漏桥连区031，隔离槽503的宽度，等于相邻两个第二源漏引线401之间的间距的0.9～1.1倍；在第二源漏引线401与一个相邻的贯穿孔010之间，隔离槽503的数量为多个，且相邻两个隔离槽503之间的间距等于相邻两个第二源漏引线401之间的间距的0.9～1.1倍。如此，可以进一步压缩隔离槽503的宽度以及隔离槽503的间距，进而可以在源漏桥连区031设置更多的隔离槽503且使得隔离槽503与第二源漏引线401之间的间距更大，进一步提高源漏桥连区031的封装稳定性和源漏引线040的的电气性能的稳定。举例而言，在本公开的一种实施方式中，在源漏桥连区031，相邻两个第二源漏引线401之间的间距等于3微米，隔离槽503的宽度等于2.7～3.3微米，在源漏桥连区031同侧的相邻两个隔离槽503的间距等于2.7～3.3微米。
可选地，在源漏桥连区031，相邻两个第二源漏引线401之间的间距，不大于第二源漏引线401的宽度的最小值的2倍。如此，可以避免第二源漏引线401之间的间距太大而压缩第二源漏引线401与隔离槽503之间的距离，可以保证第二源漏引线401与隔离槽503之间具有足够大的距离，使得水汽难以通过隔离槽503侵入第二源漏引线401。不仅如此，通过减小相邻两个第二源漏引线401之间的间距，还便于设置更多个隔离槽503以进一步提高源漏桥连区031的封装稳定性。
优选地，在源漏桥连区031，相邻两个第二源漏引线401之间的间距，等于第二源漏引线401的宽度的最小值的0.9～1.1倍。举例而言，在本公开的一种实施方式中，第二源漏引线401的宽度的最小值为3微米，相邻两个第二源漏引线401之间的间距为2.7～3.3微米。
当然的，在本公开的另一种实施方式中，还可以根据柔性阵列基板制备过程中曝光机的对准精度等来确定相邻两个第二源漏引线401在源漏桥连区031的间距；在满足相邻两个第二源漏引线401的串扰可控的条件下，可以在制备工艺允许的范围内减小源漏桥连区031中相邻两个第二源漏引线401之间的间距。示例性地，在本公开的一种实施方式中，根据曝光机的对准和曝光精度，在源漏桥连区031，第二源漏引线401之间的间距可以等于2～4微米。优选地，在源漏桥连区031，第二源漏引线401之间的间距可以等于3微米。
可选地，如图2～5所示，在源漏桥连区031，多个第二源漏引线401等间距排布；源漏桥连区031相邻的两个贯穿孔010，与在源漏桥连区031中的第二源漏引线401之间的最小距离相等。如此，在源漏桥连区031，第二源漏金属层400的各个第二源漏引线401呈中心对称排布，能够保证源漏桥连区031临近贯穿孔010的两侧均能够获得足够的空间以设置隔离槽503，进而保证各个第二源漏引线401与隔离槽503之 间具有足够大的距离，使得水汽难以通过隔离槽503侵入第二源漏引线401。
可选地，在源漏桥连区031，相邻两个第一源漏引线201之间的间距，不大于相邻两个第二源漏引线401之间的间距。如此，可以避免第一源漏引线201之间的间距太大而导致源漏桥连区031的宽度增大，便于增大像素岛区020的面积占比并提高可拉伸区域的像素密度或者发光面积。
优选地，在源漏桥连区031，相邻两个第一源漏引线201之间的间距，等于相邻两个第二源漏引线401之间的间距的0.9～1.0倍。举例而言，在本公开的一种实施方式中，在源漏桥连区031，相邻两个第二源漏引线401之间的间距等于3微米，相邻两个第一源漏引线201之间的间距等于2.7～3.0微米。
可选地，如图6所示，在源漏桥连区031，第一源漏引线201在第二绝缘材料层500上的正投影与隔离槽503之间的距离的最小值，不大于第二源漏引线401在第二绝缘材料层500上的正投影与隔离槽503之间的距离的最小值。由于隔离槽503开设于第二绝缘材料层500，因此第一源漏引线201被第一绝缘材料层300完全覆盖，水汽难以通过隔离槽503侵入第一源漏引线201。因此，减小第一源漏引线201与隔离槽503之间的距离不会导致第一源漏引线201的电性性能的稳定性下降。不仅如此，减小第一源漏引线201在第二绝缘材料层500上的正投影与隔离槽503之间的距离，还可以减小源漏桥连区031的宽度，进而便于增大像素岛区020的面积占比并提高可拉伸区域的像素密度。
在本公开的一种实施方式中，如图6所示，源漏桥连区031中，第一源漏引线201在第二绝缘材料层500上的正投影，与隔离槽503完全不交叠。在该实施方式中，在源漏桥连区031，隔离槽503在第一源漏金属层200上的正投影位于第一源漏引线201和贯穿孔010之间，可以保证第一源漏引线201与贯穿孔010之间具有足够的距离。举例而言，在源漏桥连区031，第一源漏引线201在第二绝缘材料层500上的正投影，与隔离槽503的距离的最小值为1.5～2.7微米；第二源漏引线401在第二绝缘材料层500上的正投影与隔离槽503之间的距离的最小值为4.5～6.0微米。
优选地，在源漏桥连区031，第一源漏引线201在第二绝缘材料层500上的正投影，与隔离槽503的距离的最小值为2.1微米；第二源漏引线401在第二绝缘材料层500上的正投影与隔离槽503之间的距离的最小值为5.2微米。如此，相较于第一源漏引线201在第二绝缘材料层500上的正投影与隔离槽503的距离的最小值，第二源漏引线401在第二绝缘材料层500上的正投影与隔离槽503之间的距离的最小值增大了148％，使得第二源漏引线401远离隔离槽503，提高了对第二源漏引线401的封装效果。
在本公开的一种实施方式中，在源漏桥连区031，第一源漏引线201在第二源漏金属层400上的正投影，与各个第二源漏引线401间隔设置且相互不交叠。如此，可以减少源漏引线040之间的寄生电容，降低源漏引线040之间的串扰。
在本公开的另一种实施方式中，在源漏桥连区031，第一源漏引线201在第二绝缘材料层500上的正投影，与隔离槽503至少部分交叠。在该实施方式中，在源漏桥连区031，部分第一源漏引线201，例如最外侧的第一源漏引线201，可以部分位于隔离槽503下方。如此，第一源漏引线201在第二绝缘材料层500上的正投影，与隔离槽503的距离的最小值为0微米；这可以进一步减小源漏桥连区031的宽度，进而便于进一步增大像素岛区020的面积占比并提高可拉伸区域的像素密度或者发光面积。
可选地，第一源漏引线201的数量比第二源漏引线401的数量大1或2。如此，避免第一源漏引线201的数量大大超过第二源漏引线401的数量而导致源漏桥连区031过宽。在本公开的一种实施方式中，源漏引线040的数量为偶数，第一源漏引线201的数量比第二源漏引线401的数量大2。在本公开的另一种实施方式中，源漏引线040的数量为奇数，第一源漏引线201的数量比第二源漏引线401的数量大1。
可选地，隔离槽503远离衬底基板100的一端的宽度，小于隔离槽503靠近衬底基板100的一端的宽度。如此，对于发光元件为有机电发光二极管的柔性阵列基板，在通过蒸镀的方法形成柔性阵列基板的有机发光层703和公共电极层704时，有机发光层703和公共电极层704在隔离槽503的侧壁处不连续。如此，可以避免水氧沿着有机发光层703与第二绝缘层之间的界面处侵入源漏桥连区031和像素岛区020，阻断水氧入侵通道，保证源漏桥连区031和像素岛区020的封装的稳定性。
在本公开的一种实施方式中，如图2和图3所示，隔离槽503可以贯穿第二绝缘材料层500，以使得隔离槽503能够更有效地阻断水氧入侵路线，提高对第二源漏引线401的封装效果。
在本公开的另一种实施方式中，如图4和图5所示，隔离槽503未贯穿第二绝缘材料层500，即隔离槽503在垂直于衬底基板100的方向的尺寸小于第二绝缘材料层500在垂直于衬底基板100的方向的尺寸。如此，第一源漏引线201与隔离槽503之间设置有第一绝缘材料层300和部分第二绝缘材料层500，能够提高对第一源漏引线201的保护效果，避免水汽侵入第一源漏引线201。
可选地，衬底基板100为柔性衬底基板100，以保证柔性阵列基板的可拉伸性能。衬底基板100的材料可以为柔性材料，例如可以为聚酰亚胺。衬底基板100还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板100可以包括依次层叠设置的底膜层、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
可选地，第一源漏金属层200可以包括一层导电材料，也可以包括层叠的多层导电材料。举例而言，在本公开的一种实施方式中，第一源漏金属层200可以包括依次层叠的钛层、铝层和钛层。
可选地，如图2～5所示，柔性阵列基板还可以包括有屏蔽层701和第三绝缘材料层702。其中，在源漏桥连区031，屏蔽层701设于第一源漏金属层200和衬底基板100之间，用于遮光以避免外部光线照射至源漏引线040；第三绝缘材料层702位于屏 蔽层701与第一源漏金属层200之间，用于隔离第一源漏金属层200和屏蔽层701。在本公开的一种实施方式中，第三绝缘材料层702的材料可以为氧化硅、氮化硅、氮氧化硅或者其他无机绝缘材料。
可选的，如图2～5所示，第一绝缘材料层300可以包括第一钝化层301和第一平坦化层302。其中，第一钝化层301覆盖第一源漏金属层200远离衬底基板100的表面，用以保护第一源漏金属层200。在本公开的一种实施方式中，第一钝化层301的材料可以为氧化硅、氮化硅、氮氧化硅或者其他致密的无机绝缘材料。第一平坦化层302位于第一钝化层301远离衬底基板100的一侧，用于为第二源漏金属层400提供平坦化表面。进一步地，第一平坦化层302可以为有机绝缘材料，以便在提供平坦化表面的同时平衡第一源漏金属层200和第二源漏金属层400的应力分布，提高源漏桥连区031的形变能力。在本公开的一种实施方式中，第一平坦化层302的材料可以包括聚酰亚胺。
可选地，第二源漏金属层400设于第一平坦化层302远离衬底基板100的一侧，其可以包括一层导电材料，也可以包括层叠的多层导电材料。举例而言，在本公开的一种实施方式中，第二源漏金属层400可以包括依次层叠的钛层、铝层和钛层。可以理解的是，第一源漏金属和第二源漏金属层400的材料可以相同，也可以不同，本公开对此不做限制。
可选地，如图2～5所示，第二绝缘材料层500可以包括层叠设置的第二平坦化层501和第二钝化层502。其中，第二平坦化层501覆盖第二源漏金属层400远离衬底基板100的一侧，其材料可以为有机材料，例如可以包括聚酰亚胺。在本公开的一种实施方式中，第二平坦化层501还可以延伸至柔性阵列基板的其他区域，例如延伸至柔性阵列基板的像素岛区020，并在像素岛区020为像素电极提供平坦化表面。在本公开的另一种实施方式中，第二平坦化层501还可以延伸至柔性阵列基板的其他区域，例如延伸至柔性阵列基板的像素岛区020域，并在像素岛区020被图案化为像素定义层。当然的，第二平坦化层501还可以是多层有机层的层叠。举例而言，在本公开的另一种实施方式中，第二平坦化层501包括依次层叠于第二源漏金属层400远离衬底基板100一侧的第一有机绝缘层和第二有机绝缘层，其中，第一有机绝缘层和第二有机绝缘层可以延伸至柔性阵列基板的其他区域，例如延伸至柔性阵列基板的像素岛区020，第一有机绝缘层在像素岛区020可以为像素电极提供平坦化表面，第二有机绝缘层在像素岛区020可以被图案化为像素定义层。
第二钝化层502设于第二平坦化层501远离衬底基板100的一侧，其可以采用氮化硅、氮氧化硅、氧化硅或者其他的无机绝缘材料。在本公开的一种实施方式中，第二钝化层502用于作为掩膜层，以便实现第二平坦化层501的图案化。
示例性地，可以通过如下方法制备第二绝缘材料层500：先在第二源漏金属层400远离衬底基板100的一侧依次形成第二平坦化材料层和第二钝化材料层，然后对第二 钝化材料层进行图案化，使得第二钝化材料层形成暴露第二平坦化材料层的开口，图案化后的第二钝化材料层作为第二钝化层502；然后再以第二钝化层502作为掩膜板，对第二平坦化材料层进行刻蚀，实现在第二平坦化材料层上挖槽，图案化后的第二平坦化材料层作为第二平坦化层501。如此，可以使得第二绝缘材料层500包括层叠的第二平坦化层501和第二钝化层502，第二平坦化层501的槽和第二钝化层502的开口共同形成了第二绝缘材料层500的隔离槽503。
进一步地，可以采用湿法刻蚀工艺对第二平坦化材料层进行刻蚀，使得第二平坦化层501上的槽的宽度大于第二钝化层502的开口的宽度，进而使得隔离槽503远离衬底基板100的一端的宽度，小于隔离槽503靠近衬底基板100的一端的宽度，或者使得第二钝化层502在开口附近得不到第二平坦化层501的支撑。
可选地，在形成第二钝化层502之前，可以采用完整且未镂空的初始衬底基板来制备柔性阵列基板；在形成隔离槽503的过程中，或者在形成隔离槽503之后，可以制备出柔性阵列基板的贯穿孔010，使得初始的柔性阵列基板也被图案化而形成柔性阵列基板的衬底基板100。
可选地，柔性阵列基板的发光元件可以为有机电致发光二极管。为了便于有机电致发光二极管的制备，可以采用开放式掩膜蒸镀全部或者部分有机发光层的材料和公共电极层的材料，以形成有机发光层703和公共电极层704。在蒸镀过程中，有机发光层的材料和公共电极层的材料在隔离槽503的侧壁处不连续，进而可以避免形成连续的水氧入侵通道。
换言之，在一些实施方式中，如图3和图5所示，在源漏桥连区031，柔性阵列基板还可以包括层叠于第二绝缘材料层500远离衬底基板100的一侧的有机发光层703和公共电极层704，且有机发光层703和公共电极层704在隔离槽503位置不连续。封装层600可以设于公共电极层704远离衬底基板100的表面。
可选地，封装层600可以为薄膜封装层600，其可以包括交替设置的无机材料层和有机材料层。
示例性地，该柔性阵列基板的制备方法可以包括如下步骤：
步骤S110，如图7所示，提供一位于支撑基板050上的柔性的衬底基板100；在衬底基板100远离支撑基板050的一侧形成第一源漏金属层200，该第一源漏金属层200在源漏桥连区031包括多个第一源漏引线201。可选地，该支撑基板050可以为玻璃基板。
步骤S120，如图8所示，在第一源漏金属层200远离衬底基板100的一侧形成第一绝缘材料层300，第一绝缘材料层300在源漏桥连区031覆盖各个第一源漏引线201；
步骤S130，如图9所示，在第一绝缘材料层300远离衬底基板100的一侧形成第二源漏金属层400；在源漏桥连区031，第二源漏金属层400包括多个第二源漏引线401，且第二源漏引线401的数量少于第一源漏引线201的数量；
步骤S140，如图10和图11所示，在第二源漏金属层400远离衬底基板100的一侧依次形成第二平坦化层501和第二钝化层502，进而形成在源漏桥连区031覆盖各个第二源漏引线401的第二绝缘材料层500；
步骤S150，如图12所示，对第二绝缘材料层500进行图案化处理，以便形成至少两个隔离槽503；在源漏桥连区031，隔离槽503在第二源漏金属层400上的正投影隔离第二源漏引线401和源漏桥连区031两侧的开孔区010a。
可选地，在形成隔离槽503时，还可以对开孔区010a进行开孔，以在开孔区010a形成贯穿孔010。
步骤S160，如图13所示，在第二绝缘材料层500远离衬底基板100的一侧形成封装层600。
步骤S170，剥离支撑基板050。
在一些实施方式中，如图14所示，在形成隔离槽503之后，还可以形成有机发光层703和公共电极层704；有机发光层703和公共电极层704在隔离槽503处不连续。如图15所示，在形成有机发光层703和公共电极层704后，还可以在公共电极层704远离衬底基板100的一侧形成封装层600。
下面，示例性地介绍一种像素岛区020的结构，以便示例性地展示源漏桥连区031的各个源漏引线040与像素岛区020的连接方式，以更清晰地解释和说明源漏桥连区031的结构。
该像素岛区的示例中，像素岛区020包括四个像素，每个像素包括红色子像素、绿色子像素和蓝色子像素等三个子像素，每个子像素包括像素驱动电路和与所述像素驱动电路电连接的像素电极。
四个像素形成两个像素行，任意一个像素行包括沿行方向A排列的两个像素；如图27所示，任意一个像素行中，蓝色子像素的像素电极7053和红色子像素的像素电极7051沿行方向A排列，且位于绿色子像素的像素电极7052远离另一个像素行的一侧。如此，两个像素行形成有四个像素电极行，中间的两个像素电极行各包括两个沿行方向A排列的绿色子像素的像素电极7052；两侧的任意一个像素电极行各包括沿行方向A排列的两个蓝色子像素的像素电极7053和两个红色子像素的像素电极7051。
四个像素还形成两个像素列，任意一个像素列包括沿行方向B排列的两个像素；其中，任意一个像素列中，两个蓝色子像素的像素电极7053沿列方向排列，两个红色子像素的像素电极7051沿列方向排列，且两个绿色子像素的像素电极7052沿列方向排列。任意一个像素列中，红色子像素的像素电极7051位于蓝色子像素的像素电极7053的设定方向C一侧，设定方向C为平行于行方向A的一个方向。
对应地，像素岛区020设置有与十二个像素电极一一对应连接的十二个像素驱动电路，这些像素驱动电路呈两排设置，即包括靠近源漏桥连区031的第一排像素驱动电路和远离源漏桥连区031的第二排像素驱动电路。这些像素驱动电路还呈六列分布， 其包括沿设定方向C依次排列的第一列像素驱动电路、第二列像素驱动电路、第三列像素驱动电路、第四列像素驱动电路、第五列像素驱动电路和第六列像素驱动电路。其中，第一列像素驱动电路和第四列像素驱动电路中的像素驱动电路与蓝色子像素的像素电极7053连接，第二列像素驱动电路和第五列像素驱动电路中的像素驱动电路与绿色子像素的像素电极7052连接，第三列像素驱动电路和第六列像素驱动电路中的像素驱动电路与红色子像素的像素电极7051连接。
在该示例中，如图16所示，任意一个像素驱动电路可以为7T1C(7个薄膜晶体管，1个存储电容Cst)架构。其中，第三薄膜晶体管T3作为驱动晶体管，其第一端与第五薄膜晶体管T5的第二端电连接，其第二端与第六薄膜晶体管T6的第一端电连接，其控制端与存储电容Cst的第一电极板电连接。第一薄膜晶体管T1的第一端用于加载初始信号(V init)，第二端与存储电容Cst的第一电极板电连接，控制端用于加载复位信号(Reset)。第二薄膜晶体管T2的第一端与第三薄膜晶体管T3的第二端电连接，第二端与存储电容Cst的第一电极板电连接，控制端用于加载扫描信号。第四薄膜晶体管T4的第一端用于加载数据信号(V data)，第二端与第三薄膜晶体管T3的第一端电连接，控制端用于加载扫描信号(Gate)。第五薄膜晶体管T5的第一端用于加载电源电压(V DD)，第二端与第三薄膜晶体管T3的第一端电连接，控制端用于加载使能信号(EM，Emission)。第六薄膜晶体管T6的第一端与第三薄膜晶体管T3的第二端电连接，第二端用于与像素电极电连接，控制端用于加载使能信号(EM，Emission)。第七薄膜晶体管T7的第一端用于加载初始信号(V init)，第二端用于与像素电极电连接，控制端用于加载复位信号。存储电容Cst的第一电极板与第三薄膜晶体管T3的控制端电连接，第二电极板用于加载电源电压(V DD)。
该示例中，柔性阵列基板在像素岛区020可以包括依次层叠设置的衬底基板、半导体层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间电介质层、第一源漏金属层、第一绝缘材料层、第二源漏金属层、第二平坦化层、像素电极层、有机发光层、公共电极层和封装层。其中，
半导体层的材料可以为多晶硅，其可以通过掺杂等工艺改变不同位置处的导电性能，进而形成多个沟道区和导电段。如图17和图22所示，在任意一个像素驱动电路中，半导体层810可以形成有作为第一薄膜晶体管T1的沟道区的第一沟道区8111、作为第二薄膜晶体管T2的沟道区的第二沟道区8112、作为第三薄膜晶体管T3的沟道区的第三沟道区8113、作为第四薄膜晶体管T4的沟道区的第四沟道区8114、作为第五薄膜晶体管T5的沟道区的第五沟道区8115、作为第六薄膜晶体管T6的沟道区的第六沟道区8116、作为第七薄膜晶体管T7的沟道区的第七沟道区8117，以及形成有第一导电段8121、第二导电段8122、第三导电段8123、第四导电段8124、第五导电段8125、第六导电段8126、第七导电段8127。其中，第一导电段8121连接第四沟道区8114第一端，且设置有半导体层第一过孔区8131；第二导电段8122连接第四沟道区 8114第二端、第五沟道区8115第一端、第三沟道区8113第一端；第三导电段8123连接第五沟道区8115第二端，且设置有半导体层第六过孔区8136；第四导电段8124连接第三沟道区8113第二端、第六沟道区8116第一端、第二沟道区8112第二端；第五导电段8125连接第六沟道区8116第二端、下一像素驱动电路的第七沟道区8117第二端、第二沟道区8112第二端，且设置有半导体层第七过孔区8137；第六导电段8126连接第二沟道区8112第一端、第一沟道区8111第二端，且设置有半导体层第三过孔区8133；第七导电段8127连接第一沟道区8111第一端、第七沟道区8117第一端，且设置有半导体层第二过孔区8132。
如图18和图23所示，第一栅极层可以包括第一栅极引线8211、第二栅极引线8212、第三栅极引线8213，以及包括像素驱动电路的第一栅极结构。其中，第一栅极引线8211、第二栅极引线8212、第三栅极引线8213穿过栅极桥连区032并延伸至像素布线区。
如图18所示，像素驱动电路的第一栅极结构包括有扫描引线8221、使能引线8222、复位引线8223和存储电容的第一电极板0681。复位引线8223段包括第一引线区8231和第七引线区8237；第一引线区8231在半导体层810上的正投影与第一沟道区8111重合，以作为第一薄膜晶体管T1的栅极；第七引线区8237在半导体层810上的正投影与第七沟道区8117重合，以作为第七薄膜晶体管T7的栅极。扫描引线8221段包括第二引线区8232和第四引线区8234；第二引线区8232在半导体层810上的正投影与第二沟道区8112重合，以作为第二薄膜晶体管T2的栅极；第四引线区8234在半导体层810上的正投影与第四沟道区8114重合，以作为第四薄膜晶体管T4的栅极。使能引线8222段包括第五引线区8235和第六引线区8236；第五引线区8235在半导体层810上的正投影与第五沟道区8115重合，以作为第五薄膜晶体管T5的栅极；第六引线区8236在半导体层810上的正投影与第六沟道区8116重合，以作为第六薄膜晶体管T6的栅极。存储电容的第一电极板0681在半导体层810上的正投影完全覆盖第三沟道区8113，使得存储电容的第一电极板0681还可以作为第三薄膜晶体管T3的栅极。存储电容的第一电极板0681还设置有栅极层第五过孔区8245。
如图19和图24所示，第二栅极层可以包括第四栅极引线8311、第五栅极引线8312、第六栅极引线8313，以及包括像素驱动电路的第二栅极结构。其中，第四栅极引线8311、第五栅极引线8312、第六栅极引线8313穿过栅极桥连032区并延伸至像素布线区。像素驱动电路的第二栅极结构包括初始化引线8321、辅助电极板8322和存储电容的第二电极板0682。存储电容的第二电极板0682与存储电容的第一电极板0681在衬底基板上的正投影部分重合，且栅极层第五过孔区8245在衬底基板上的正投影位于存储电容的第二电极板0682在衬底基板上的正投影以外；存储电容的第二电极板0682设置有栅极层第四过孔区8334。第三栅极引线8213设置有栅极层第八过孔区8338。辅助电极板8322用于覆盖部分第六导电段8126和部分第一导电段8121，且设置有栅极 层第九过孔区8339。其中，像素布线区中的第六栅极引线8313与靠近该像素布线区的像素驱动电路的初始化引线8321连接。
如图20和图25所示，第一源漏金属层包括多个源漏引线和像素驱动电路的第一源漏导电结构。
如图20所示，像素驱动电路的第一源漏导电结构包括数据引线结构0421、电源引线结构0411、第一连接引线211、第二连接引线212和第三连接引线213。其中，电源引线结构0411设于数据引线结构0421的设定方向C的一侧，第一连接引线211、第二连接引线212和第三连接引线213设于电源引线结构0411的设定方向C的一侧。数据引线结构0421设置有源漏第一过孔区221，源漏第一过孔区221与半导体层第一过孔区8131连接而形成第一金属化过孔。电源引线结构0411设置有源漏第四过孔区224、源漏第六过孔区226和源漏第九过孔区229；源漏第四过孔区224与栅极层第四过孔区8334连接而形成第四金属化过孔，源漏第六过孔区226与半导体层第六过孔区8136连接而形成第六金属化过孔，源漏第九过孔区229与栅极层第九过孔区8339连接而形成第九金属化过孔。第一连接引线211设置有源漏第八过孔区228和源漏第二过孔区222，源漏第八过孔区228与栅极层第八过孔区8338连接而形成第八金属化过孔，源漏第二过孔区222与半导体层第二过孔区8132连接而形成第二金属化过孔；第二连接引线212设置有源漏第三过孔区223和源漏第五过孔区225，源漏第三过孔区223与半导体层第三过孔区8133连接而形成第三金属化过孔，源漏第五过孔区225与栅极层第五过孔区8245连接而形成第五金属化过孔；第三连接引线213设置有源漏第七过孔区227，源漏第七过孔区227与半导体层第七过孔区8137连接而形成第七金属化过孔。
位于第一源漏金属层的源漏引线包括阵列基板的第一源漏引线201和位于像素岛区020的多个布线引线。其中，第一源漏引线201包括在源漏桥连区031沿设定方向C依次设置的第一金属引线231、第二金属引线232、第三金属引线233、第四金属引线234和第五金属引线235；其中，第一金属引线231、第二金属引线232、第三金属引线233、第四金属引线234延伸至像素布线区021；第五金属引线235沿第六列像素驱动电路远离第一列像素驱动电路的一侧穿过像素岛区。布线引线包括位于两列像素之间的第六金属引线246至第十二金属引线2412；其中，第三金属引线233和第十二金属引线2412连接。
其中，第一金属引线231与第一列像素驱动电路的数据引线结构0421连接，第二金属引线232与第二列像素驱动电路的数据引线结构0421连接，第四金属引线234与第五列像素驱动电路的数据引线结构0421连接。第六金属引线246通过过孔与第二行像素驱动电路的使能引线8222连接，以及通过过孔与第一栅极引线8211连接。第七金属引线247通过过孔与第二行像素驱动电路的扫描引线8221连接，以及通过过孔与第四栅极引线8311连接。第八金属引线248通过过孔与第一行像素驱动电路的使能 引线8222连接，以及通过过孔与第二栅极引线8212连接。第九金属引线249通过过孔与第一行像素驱动电路的扫描引线8221连接，以及通过过孔与第二行像素驱动电路的复位引线8223连接，以及通过过孔与第五栅极引线8312连接。第十金属引线2410通过过孔与第一行像素驱动电路的复位引线8223连接，以及通过过孔与第三栅极引线8213连接。第十一金属引线2411通过过孔与第一行像素驱动电路的初始化引线8321连接，以及通过过孔与第二行像素驱动电路的初始化引线8321连接。
如图21和图26所示，第二源漏金属层包括多个源漏引线和像素驱动电路的第二源漏导电结构。
像素驱动电路的第二源漏导电结构包括列向电源引线411、行向电源引线412和转接焊盘413，其中，列向电源引线411和行向电源引线412相互连接，且通过过孔与像素驱动电路的电源引线结构0411电连接。转接焊盘413通过过孔与像素驱动电路的第三连接引线213连接。
位于第二源漏金属层的源漏引线包括第二源漏引线401，该第二源漏引线401包括在源漏桥连区031沿设定方向C依次设置的第十三金属引线4313、第十四金属引线4314、第十五金属引线4315、第十六金属引线4316。第十三金属引线4313延伸至像素布线区022，且与像素驱动电路的列向电源引线411连接。第十四金属引线4314延伸至像素布线区022，且通过过孔与第三列像素驱动电路的数据引线结构0421连接。第十五金属引线4315延伸至像素布线区020，且通过过孔与第四列像素驱动电路的数据引线结构0421连接。第十六金属引线4316延伸至像素布线区022，且通过过孔与第六列像素驱动电路的数据引线结构0421连接。
如此，第一金属引线231用于向第一列像素驱动电路的数据引线结构0421加载数据信号(V data)；第二金属引线232用于向第二列像素驱动电路的数据引线结构0421加载数据信号(V data)；第四金属引线234用于向第五列像素驱动电路的数据引线结构0421加载数据信号(V data)；第十三金属引线4313用于向各列像素驱动电路的电源引线结构0411加载电源电压；第十四金属引线4314用于向第三列像素驱动电路的数据引线结构0421加载数据信号(V data)；第十五金属引线4315用于向第四列像素驱动电路的数据引线结构0421加载数据信号(V data)；第十六金属引线4316用于向第六列像素驱动电路的数据引线结构0421加载数据信号(V data)。
像素电极层设置有十二个像素电极，各像素电极与各像素驱动电路的转接焊盘413对应设置，且像素电极通过过孔与对应的转接焊盘413电连接。
本公开实施方式还提供一种显示装置，该显示装置包括上述柔性阵列基板实施方式所描述的任意一种柔性阵列基板。该显示装置可以为头盔显示器、四曲面手机或者其他类型的显示装置。由于该显示装置具有上述柔性阵列基板实施方式所描述的任意一种柔性阵列基板，因此具有相同的有益效果，本公开在此不再赘述。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置 方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (21)

  1. 一种柔性阵列基板，包括至少一个可拉伸区域；所述柔性阵列基板在所述可拉伸区域内设置有多个贯穿孔，多个所述贯穿孔将所述可拉伸区域划分出用于显示的像素岛区和用于传输信号的桥连区；所述桥连区包括源漏桥连区，所述柔性阵列基板在任意一个所述源漏桥连区包括：
    衬底基板；
    第一源漏金属层，设于所述衬底基板的一侧，且包括多个第一源漏引线；
    第一绝缘材料层，设于所述第一源漏金属层远离所述衬底基板的一侧；
    第二源漏金属层，设于所述第一绝缘材料层远离所述衬底基板的一侧；所述第二源漏金属层包括多个第二源漏引线，且所述第二源漏引线的数量少于所述第一源漏引线的数量；
    第二绝缘材料层，设于所述第二源漏金属层远离所述衬底基板的一侧；所述第二绝缘材料层设置有多个隔离槽，所述隔离槽在所述第二源漏金属层上的正投影隔离所述第二源漏引线和所述贯穿孔；
    封装层，设于所述第二绝缘材料层远离所述衬底基板的一侧。
  2. 根据权利要求1所述的柔性阵列基板，其中，在所述源漏桥连区，所述第二源漏引线在所述第二绝缘材料层上的正投影与所述隔离槽之间的距离的最小值，不小于相邻两个所述第二源漏引线之间的间距。
  3. 根据权利要求1所述的柔性阵列基板，其中，在所述源漏桥连区，所述隔离槽的宽度，不大于相邻两个所述第二源漏引线之间的间距的2倍。
  4. 根据权利要求1所述的柔性阵列基板，其中，在所述源漏桥连区，所述隔离槽的宽度，等于相邻两个所述第二源漏引线之间的间距的0.9～1.1倍；在所述第二源漏引线与一个相邻的所述贯穿孔之间，所述隔离槽的数量为多个，且相邻两个所述隔离槽之间的间距等于相邻两个所述第二源漏引线之间的间距的0.9～1.1倍。
  5. 根据权利要求1所述的柔性阵列基板，其中，在所述源漏桥连区，相邻两个所述第二源漏引线之间的间距，不大于所述第二源漏引线的宽度的2倍。
  6. 根据权利要求1所述的柔性阵列基板，其中，在所述源漏桥连区，多个所述第二源漏引线等间距排布；所述源漏桥连区相邻的两个所述贯穿孔，与所述第二源漏引线之间的最小距离相等。
  7. 根据权利要求1所述的柔性阵列基板，其中，在所述源漏桥连区，相邻两个所述第一源漏引线之间的间距，不大于相邻两个所述第二源漏引线之间的间距。
  8. 根据权利要求1所述的柔性阵列基板，其中，在所述源漏桥连区，所述第一源漏引线在所述第二绝缘材料层上的正投影与所述隔离槽之间的距离的最小值，不大于所述第二源漏引线在所述第二绝缘材料层上的正投影与所述隔离槽之间的距离的最小值。
  9. 根据权利要求1所述的柔性阵列基板，其中，在所述源漏桥连区，所述第一源漏引线在所述第二绝缘材料层上的正投影，与所述隔离槽至少部分交叠。
  10. 根据权利要求1所述的柔性阵列基板，其中，在所述源漏桥连区，所述第一源漏引线在所述第二绝缘材料层上的正投影与所述隔离槽之间的距离的最小值为1.5～2.7微米；所述第二源漏引线在所述第二绝缘材料层上的正投影与所述隔离槽之间的距离的最小值为4.5～6.0微米。
  11. 根据权利要求1所述的柔性阵列基板，其中，所述第一源漏引线的数量比所述第二源漏引线的数量大1或2。
  12. 根据权利要求1所述的柔性阵列基板，其中，所述隔离槽远离所述衬底基板的一端的宽度，小于所述隔离槽靠近所述衬底基板的一端的宽度。
  13. 根据权利要求1～12任意一项所述的柔性阵列基板，其中，在所述源漏桥连区，所述第一源漏引线的延伸方向与所述贯穿孔的延伸方向平行或者垂直；所述第二源漏引线的延伸方向与所述贯穿孔的延伸方向平行或者垂直。
  14. 根据权利要求1～12任意一项所述的柔性阵列基板，其中，所述像素岛区包括多个子像素，任意一个所述子像素沿行方向的尺寸为第一尺寸；在所述源漏桥连区，相邻两个所述第二源漏引线之间的间距等于第二尺寸；所述第一尺寸大于所述第二尺寸。
  15. 根据权利要求1～12任意一项所述的柔性阵列基板，其中，所述贯穿孔包括沿行方向延伸的第一长条孔和沿列方向延伸的第二长条孔；所述源漏桥连区位于所述第一长条孔的端部与所述第二长条孔的侧边之间。
  16. 根据权利要求15所述的柔性阵列基板，其中，任意一个所述像素岛区位于相邻的两个所述第一长条孔之间，且位于相邻的两个所述第二长条孔之间；任意一个所述像素岛区包括四个像素，任意一个所述像素包括红色子像素、绿色子像素和蓝色子像素。
  17. 根据权利要求16所述的柔性阵列基板，其中，在任意一个所述像素岛区，四个所述像素形成两个像素行，任意一个所述像素行包括沿所述行方向排列的两个所述像素；
    其中，任意一个所述像素行中，所述蓝色子像素的像素电极和所述红色子像素的像素电极沿所述行方向排列，且位于所述绿色子像素的像素电极远离另一个所述像素行的一侧。
  18. 根据权利要求1～12任意一项所述的柔性阵列基板，其中，所述柔性阵列基板在任意一个所述像素岛区包括阵列设置的多个子像素，任意一个所述子像素包括像素驱动电路和与所述像素驱动电路电连接的像素电极；任意一个所述像素驱动电路包括存储电容、第一薄膜晶体管至第七薄膜晶体管；其中，
    所述第一薄膜晶体管的第一端用于加载初始信号，所述第一薄膜晶体管的第二端 与所述存储电容的第一电极板电连接，所述第一薄膜晶体管的控制端用于加载复位信号；
    所述第二薄膜晶体管的第一端与所述第三薄膜晶体管的第二端、所述第六薄膜晶体管的第一端电连接，所述第二薄膜晶体管的第二端与所述存储电容的第一电极板电连接，所述第二薄膜晶体管的控制端用于加载扫描信号；
    所述第三薄膜晶体管的第一端与所述第四薄膜晶体管的第二端、所述第五薄膜晶体管的第二端电连接，所述第三薄膜晶体管的控制端与所述存储电容的第一电极板电连接；
    所述第四薄膜晶体管的第一端用于加载数据信号，所述第四薄膜晶体管的控制端用于加载所述扫描信号；
    所述第五薄膜晶体管的第一端用于加载电源电压，所述第五薄膜晶体管的控制端用于加载使能信号；
    所述第六薄膜晶体管的第二端用于与所述像素电极电连接，所述第六薄膜晶体管的控制端用于加载所述使能信号；
    所述第七薄膜晶体管的第一端用于加载所述初始信号，所述第七薄膜晶体管的第二端用于与所述像素电极电连接，所述第七薄膜晶体管的控制端用于加载所述复位信号；
    所述存储电容的第二电极板用于加载所述电源电压。
  19. 根据权利要求18所述的柔性阵列基板，其中，任意一个所述像素岛区包括沿设定方向依次排列的第一列像素驱动电路至第六列像素驱动电路，任意一列像素驱动电路包括沿列方向排列的多个所述像素驱动电路；其中，所述设定方向为平行于行方向的一个方向；
    在所述源漏桥连区，所述第一源漏引线的数量为五个；沿所述设定方向的第一个所述第一源漏引线用于向所述第一列像素驱动电路加载所述数据信号；沿所述设定方向的第二个所述第一源漏引线用于向所述第二列像素驱动电路加载所述数据信号；沿所述设定方向的第四个所述第一源漏引线用于向所述第五列像素驱动电路加载所述数据信号。
  20. 根据权利要求19所述的柔性阵列基板，其中，在所述源漏桥连区，所述第二源漏引线的数量为四个；沿所述设定方向的第一个所述第二源漏引线用于向所述第一列像素驱动电路至所述第六列像素驱动电路加载所述电源电压；沿所述设定方向的第二个所述第二源漏引线用于向所述第三列像素驱动电路加载所述数据信号；沿所述设定方向的第三个所述第二源漏引线用于向所述第四列像素驱动电路加载所述数据信号；沿所述设定方向的第四个所述第二源漏引线用于向所述第六列像素驱动电路加载所述数据信号。
  21. 一种显示装置，包括上述的柔性阵列基板。
PCT/CN2021/099842 2020-07-22 2021-06-11 柔性阵列基板和显示装置 WO2022017058A1 (zh)

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