WO2022016637A1 - 感光传感器、阵列基板及电子设备 - Google Patents

感光传感器、阵列基板及电子设备 Download PDF

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Publication number
WO2022016637A1
WO2022016637A1 PCT/CN2020/109244 CN2020109244W WO2022016637A1 WO 2022016637 A1 WO2022016637 A1 WO 2022016637A1 CN 2020109244 W CN2020109244 W CN 2020109244W WO 2022016637 A1 WO2022016637 A1 WO 2022016637A1
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WIPO (PCT)
Prior art keywords
electrode
layer
array substrate
gate
semiconductor layer
Prior art date
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PCT/CN2020/109244
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English (en)
French (fr)
Inventor
袁剑峰
龚帆
艾飞
宋继越
宋德伟
龙时宇
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to KR1020217025649A priority Critical patent/KR102640599B1/ko
Priority to EP20883673.4A priority patent/EP4187434A4/en
Priority to US17/052,110 priority patent/US12033424B2/en
Priority to JP2021534390A priority patent/JP7403544B2/ja
Publication of WO2022016637A1 publication Critical patent/WO2022016637A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G02F1/13318—Circuits comprising a photodetector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/112—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor
    • H01L31/113—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor being of the conductor-insulator-semiconductor type, e.g. metal-insulator-semiconductor field-effect transistor
    • H01L31/1136—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor being of the conductor-insulator-semiconductor type, e.g. metal-insulator-semiconductor field-effect transistor the device being a metal-insulator-semiconductor field-effect transistor
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
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    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • G—PHYSICS
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    • G06V10/14—Optical characteristics of the device performing the acquisition or on the illumination arrangements
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    • G—PHYSICS
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    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
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    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1324—Sensors therefor by using geometrical optics, e.g. using prisms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0376—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
    • H01L31/03762—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors including only elements of Group IV of the Periodic Table
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Definitions

  • the present application relates to the field of display technology, and in particular, to a photosensitive sensor, an array substrate and an electronic device.
  • optical fingerprint technology is one of the main directions at present. Its principle is to use the different strengths of light reflected by the valleys and ridges of the fingerprint to the sensing area of the display panel, thereby converting different optical signals into The electrical signal is extracted by the chip to form a key fingerprint pattern to achieve the purpose of fingerprint identification.
  • Photosensitive sensors currently used in display panels have poor anti-noise capability and sensitivity, thus reducing the accuracy of fingerprint recognition.
  • Embodiments of the present application provide a photosensitive sensor, an array substrate, and an electronic device, which can enhance the anti-noise capability and sensitivity of the photosensitive sensor, thereby improving the accuracy of fingerprint recognition.
  • An embodiment of the present application provides a photosensitive sensor, which includes:
  • a third metal layer including a second gate
  • the second semiconductor layer is disposed on the second insulating layer; the second semiconductor layer includes conductive parts, and the conductive parts are located at both ends of the second semiconductor layer; wherein the second semiconductor layer is set the orthographic projection on the plane partially overlaps the orthographic projection of the second grid on the set plane;
  • the fourth metal layer is disposed on the second semiconductor layer, and the fourth metal layer includes a second source electrode and a second drain electrode.
  • Embodiments of the present application provide an array substrate, which includes:
  • the substrate including the control element
  • the second drain of the photosensitive sensor is connected to the control element.
  • Embodiments of the present application further provide an electronic device, which includes the above-mentioned array substrate.
  • the photosensitive sensor, the array substrate, and the electronic device include a third metal layer including a second gate electrode; a second insulating layer disposed on the third metal layer; and a second semiconductor layer disposed on the first on two insulating layers; the second semiconductor layer includes conductive parts, and the conductive parts are located at both ends of the second semiconductor layer; wherein the second gate covers part of the second semiconductor layer; a fourth metal layer , set on the second semiconductor layer, and the fourth metal layer includes a second source electrode and a second drain electrode; because there is no gate between the second gate electrode and the second source electrode and/or the second drain electrode
  • the highly regulated gap area reduces the dark current of the photosensitive sensor, enhances the anti-noise capability and sensitivity of the device, and improves the accuracy of fingerprint identification.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
  • FIG. 2 is a top view of a photosensitive sensor according to an embodiment of the present application.
  • FIG. 3 is a top view of a photosensitive sensor provided by another embodiment of the present application.
  • FIG. 4 is a top view of a photosensitive sensor according to an embodiment of the present application.
  • FIG. 5 is a flow chart of a manufacturing process of the array substrate shown in FIG. 1 .
  • FIG. 6 is a schematic structural diagram of an array substrate provided by another embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an array substrate according to another embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be a mechanical connection, an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be a mechanical connection, an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
  • the array substrate 100 of this embodiment includes a base 10 , a third metal layer 21 , a second insulating layer 22 , a second semiconductor layer 23 and a fourth metal layer 24 .
  • the substrate 10 includes a control element T1; the control element T1 is also a thin film transistor.
  • the base 10 may include: a base substrate 11 , a first semiconductor layer 14 , a first insulating layer 15 , a first metal layer 16 and a second metal layer 18 .
  • the substrate 10 may further include at least one of a light shielding layer 12 , a buffer layer 13 , a gate insulating layer 17 and a planarization layer 19 .
  • the substrate 11 may be a glass substrate or a flexible substrate.
  • the material of the base substrate 11 includes one or more of glass, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide or polyurethane.
  • the light shielding layer 12 is disposed on the base substrate 11 , and the material of the light shielding layer 12 can be a metal material.
  • the buffer layer 13 is disposed on the light shielding layer 12, and the material of the buffer layer 13 includes but not limited to silicon nitride or silicon oxide.
  • the first semiconductor layer 14 is disposed on the buffer layer 13 ; in a preferred embodiment, the first semiconductor layer 14 may include a first semiconductor portion 141 .
  • the first insulating layer 15 is disposed on the first semiconductor layer 14; the material of the first insulating layer 15 may include at least one of silicon nitride, silicon oxide and organic photoresist.
  • the first metal layer 16 is disposed on the first insulating layer 15 ; the first metal layer 16 includes a first gate electrode 161 .
  • the material of the first metal layer 16 may include at least one of copper, aluminum and titanium.
  • the gate insulating layer 17 is disposed on the first metal layer 16, and the material of the gate insulating layer 17 may include at least one of silicon nitride, silicon oxide and organic photoresist.
  • the second metal layer 18 is disposed on the gate insulating layer 17, and the second metal layer 18 includes a first source electrode 181 and a first drain electrode 182; the material of the second metal layer 18 can be the same as that of the first metal layer 16 is the same material.
  • the flat layer 19 is disposed on the second metal layer 18 , and the material of the flat layer 19 can be the same as that of the gate insulating layer 17 .
  • the array substrate further includes a photosensitive sensor S, and the photosensitive sensor S includes a second gate electrode 211 , a second semiconductor layer 23 , and a second source electrode 241 and a second drain electrode 242 .
  • this embodiment also provides a photosensitive sensor S, which includes:
  • the third metal layer 21 is disposed on the flat layer 19 ; the third metal layer 21 includes a second gate electrode 211 and a first metal portion 212 .
  • the material of the third metal layer 21 may be the same as the material of the second metal layer 18 .
  • the second insulating layer 22 is disposed on the third metal layer 21 ; the material of the second insulating layer 22 may include at least one of silicon nitride, silicon oxide, and organic photoresist.
  • the second semiconductor layer 23 is disposed on the second insulating layer 22; the second semiconductor layer 23 includes conductive parts 231, and the conductive parts 231 are located at both ends of the second semiconductor layer 23; as shown in FIG. 1 and FIG. 2, wherein the orthographic projection of the second semiconductor layer 23 on the set plane partially overlaps with the orthographic projection of the second gate 211 on the set plane, and the set plane is also a horizontal plane. That is, from bottom to top, the second gate electrode 211 covers part of the second semiconductor layer 23 .
  • the material of the second semiconductor layer 23 may be amorphous silicon, and the material of the first semiconductor layer 14 may be polysilicon.
  • the second semiconductor layer 23 may cover the first semiconductor portion 141 .
  • the fourth metal layer 24 is disposed on the second semiconductor layer 23, the fourth metal layer 24 includes a second source electrode 241 and a second drain electrode 242, and the second drain electrode 242 is connected to the control element T1 , which is specifically connected to the drain of the control element T1 (ie, the first drain 182 ).
  • the second drain 242 may be connected to the first drain 182 through the first metal portion 212 .
  • the second source electrode 241 may cover part of the second gate electrode 211 .
  • the gate of the photosensitive sensor (amorphous silicon thin film transistor) is not fully covered, there is a gap region 101 without gate regulation between the second gate 211 and the second source 241 .
  • the region 101 is used to reduce the dark current of the photosensitive sensor, enhance the anti-noise capability of the device, and the sensitivity of the device can be enhanced by adjusting the gate voltage.
  • the position of the gap region 101 is not specifically limited.
  • the second source electrode 241 includes a first sub-connection portion 51 and a second sub-connection portion 52 .
  • the second sub-connection portion 52 is arc-shaped, and one end of the first sub-connecting portion 51 is connected to the second sub-connecting portion 52;
  • the shape of the set end portion 53 of the second drain electrode 242 is arc-shaped, and the shape of the second sub-connection portion 52 matches the shape of the set end portion of the second drain electrode 242; wherein the The set end portion is the end portion close to the second source electrode 241 side.
  • the shape of the set end portion 54 of the second gate 211 is also arc-shaped, and the area of the orthographic projection of the second gate 211 on the substrate 10 is larger than that of the second drain 242 on the substrate 10; the second sub-connection part 52 is wrapped outside the set end 54 of the second grid 211; that is, the second sub-connection part 52 is arranged on the second Outside the set end portion 54 of the gate electrode 211 .
  • the second source electrode 241 includes a first common terminal 61, a first trunk portion 62 and a plurality of first branch portions 63;
  • the first trunk portion 62 is respectively connected with one end of the first branch portion 63 and the first common end 61, and the first common end 61 and the first branch portion 63 are arranged along the first direction;
  • the first trunk portion 62 is arranged along the second direction; wherein the first direction intersects the second direction;
  • the second drain 242 includes a second common terminal 64, a second trunk portion 65 and a plurality of second branch portions 66; the second trunk portion 65 is connected to the second common terminal 64 and the second branch portion 66 respectively.
  • One end of the branch portion 66 is connected, the second common end 64 and the second branch portion 66 are arranged along the first direction; the second trunk portion 65 is arranged along the second direction; and the first branch portion 63 and The second branch portions 65 are staggered;
  • the second gate 211 covers the second trunk portion 65 , the second branch portion 66 and a part of the second common terminal 64 .
  • the shape of the second gate 211 matches the shape of the second drain 242, the second gate 211 may include a third trunk portion and a plurality of third branch portions, one end of the third branch portion is connected to the The third backbone connection is described.
  • the third metal layer 21 further includes first touch electrodes 213 .
  • the array substrate 100 may further include:
  • the first conductive layer 30 is disposed on the second insulating layer 22 ; the first conductive layer 30 includes a second touch electrode 31 , and the position of the first touch electrode 213 is the same as that of the second touch electrode 31 corresponding position.
  • the first touch electrodes 213 and the second touch electrodes 31 are both grid-shaped, and the second touch electrodes 31 are connected to the first touch electrodes 213 . It can be understood that the structures of the first touch electrodes 213 and the second touch electrodes 31 are not limited to this.
  • the material of the first conductive layer 30 includes, but is not limited to, indium tin oxide.
  • the substrate 10 further includes a switching element T2 , and the switching element includes a third drain electrode 183 .
  • the array substrate 100 further includes a second conductive layer 40, and the second conductive layer 40 is disposed on the first conductive layer 30; the second conductive layer 40 includes a pixel electrode 41; the pixel electrode 41 is connected to the drain electrode 183 of the switching element T2.
  • the material of the second conductive layer 40 may be the same as the material of the first conductive layer 30 .
  • the first conductive layer 30 further includes a first electrode plate 32
  • the second conductive layer 40 further includes a second electrode plate 42, wherein the second electrode plate 42 is connected to the first electrode plate 42.
  • the positions of the electrode plates 32 correspond to each other to form the pixel capacitance.
  • the third drain electrode 183 is located in the second metal layer 18 . That is, the drain and source of the switching element T2 are fabricated in the same layer as the source and drain of the control element T1, respectively.
  • the gate of the switching element T2 can be fabricated in the same layer as the gate of the control element T1, and the semiconductor of the switching element T2 can be fabricated in the same layer. The layer may also be fabricated in the same layer as the semiconductor layer of the control element T1.
  • the manufacturing method of the array substrate of this embodiment includes:
  • the light shielding layer 12 is patterned by means of exposure etching or the like, so that the light shielding layer 12 shields the first semiconductor portion 141 .
  • the buffer layer 13 and the first semiconductor layer 14 are sequentially prepared on the light shielding layer 12 .
  • the material of the first semiconductor layer 14 is polysilicon, and the first semiconductor layer 14 is exposed and etched to form the first semiconductor part 141 and the second semiconductor part 142 respectively, and the first semiconductor part 141 and the second semiconductor part are respectively formed.
  • 142 is doped with P ions to form N+, so that the first semiconductor part 141 and the second semiconductor part 142 are easy to make ohmic contact.
  • the first gate electrode 161 and the third gate electrode 162 are formed by patterning the first metal layer 16 . Then, N- ions are implanted into the first semiconductor portion 141 and the second semiconductor portion 142 using a self-aligned process, respectively.
  • the gate insulating layer 17 can be a stacked structure of SiNx/SiOx.
  • rapid thermal annealing can be used for hydrogenation and activation, and then the gate insulating layer 17 is exposed and etched, A source and drain connection hole is formed, and the connection hole is connected to the first semiconductor portion 141 or the second semiconductor portion 142 .
  • the second metal layer 18 is patterned to form the first source electrode 181 and the first drain electrode 182 , and the third drain electrode 183 and the third source electrode 184 .
  • connection hole is provided on the flat layer, and the first metal part 212 is used for connecting with the first drain electrode 182 through the connection hole.
  • the third metal layer 21 is patterned to form the second gate electrode 211 , the first metal portion 212 and the first touch electrode 213 .
  • the material of the second semiconductor layer 23 is a-Si, the surface of which is processed to form N+-a-Si, and then the patterning process is performed.
  • the third insulating layer 25 is provided with a connection hole for connecting the pixel electrode 41 and the third drain electrode 183 .
  • the second conductive layer 40 is patterned to form the pixel electrode 41 and the second electrode plate 42 .
  • the photosensitive sensor S is fabricated on the control element T1
  • the related metal wirings connected to the photosensitive sensor can be reduced, thereby increasing the aperture ratio; in addition, the light absorption coefficient of the photosensitive layer of amorphous silicon is much better than that of polysilicon, thereby increasing the photosensitive Sensitivity of the sensor.
  • FIG. 6 is a schematic structural diagram of an array substrate according to another embodiment of the present application.
  • the difference between the photosensitive sensor of this embodiment and the photosensitive sensor of the previous embodiment is that the second gate electrode 211 of this embodiment is connected to the second source electrode 241 .
  • the impedance is further reduced, thereby improving the sensitivity of the photosensitive sensor.
  • Embodiments of the present application further provide an array substrate, which includes the above-mentioned photosensitive sensor.
  • FIG. 7 is a schematic structural diagram of an array substrate according to another embodiment of the present application.
  • the difference between the photosensitive sensor of this embodiment and the photosensitive sensor of the first embodiment is that the area of the second gate electrode 211 in this embodiment is larger.
  • the second drain electrode 242 partially covers the second gate electrode 211 . That is, the area of the orthographic projection of the second gate electrode 211 on the base substrate 11 is larger than the area of the orthographic projection of the second drain electrode 242 on the base substrate 11 , and the second gate electrode 211 is on the base substrate 11 .
  • the orthographic projection of is also partially overlapped with the orthographic projection of the second semiconductor layer 23 on the base substrate 11 .
  • the second gate 211 also covers part of the first drain 182 , that is, the second gate is also used as a first metal portion.
  • Embodiments of the present application further provide an array substrate, which includes the above-mentioned photosensitive sensor.
  • FIG. 2 to FIG. 7 only show schematic structural diagrams of one of the embodiments, but do not limit the present invention.
  • the array substrate in the above-mentioned embodiment includes all the technical solutions of the above-mentioned photosensitive sensor, so all the above-mentioned technical effects can be achieved, which will not be repeated here.
  • this embodiment further provides a display panel 200 , which includes any one of the array substrates 100 described above.
  • the display panel 200 may further include a second substrate 201 , and the second substrate 201 is disposed opposite to the array substrate 100 .
  • the display panel 200 may be a liquid crystal display panel.
  • a liquid crystal layer (not shown in the figure) is also disposed between the array substrate 100 and the second substrate 201 .
  • a sealant may be disposed between the array substrate 100 and the second substrate 201 for attaching the array substrate 100 and the second substrate 201 .
  • the second substrate 201 may include a second base substrate 71 and a second electrode 72 .
  • the second substrate 201 may be a color filter substrate, that is, the second substrate 201 may further include a color filter layer. It can be understood that the structure of the second substrate 201 is not limited to this.
  • FIG. 9 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device 300 may include a display panel 200 , a control circuit 80 and a housing 90 . It should be noted that the electronic device 300 shown in FIG. 9 is not limited to the above contents, and may also include other components, such as a camera, an antenna structure, a fingerprint unlocking module, and the like.
  • the display panel 200 is disposed on the casing 90 .
  • the display panel 200 may be fixed to the casing 90 , and the display panel 200 and the casing 90 form a closed space to accommodate devices such as the control circuit 80 .
  • the casing 90 may be made of a flexible material, such as a plastic casing or a silicone casing.
  • control circuit 80 is installed in the casing 90, the control circuit 80 can be the main board of the electronic device 300, and the control circuit 80 can be integrated with a battery, an antenna structure, a microphone, a speaker, a headphone interface, a universal serial bus interface, One, two or more of functional components such as camera, distance sensor, ambient light sensor, receiver, and processor.
  • the display panel 200 is installed in the casing 90 , and at the same time, the display panel 200 is electrically connected to the control circuit 80 to form a display surface of the electronic device 300 .
  • the display panel 200 may include a display area and a non-display area.
  • the display area may be used to display the screen of the electronic device 300 or for the user to perform touch manipulation and the like. This non-display area can be used to set various functional components.
  • the electronic devices include but are not limited to mobile phones, tablet computers, computer monitors, game consoles, televisions, display screens, wearable devices, and other household appliances or household appliances with display functions.
  • the photosensitive sensor, the array substrate, and the electronic device include a third metal layer including a second gate electrode; a second insulating layer disposed on the third metal layer; and a second semiconductor layer disposed on the first on two insulating layers; the second semiconductor layer includes conductive parts, and the conductive parts are located at both ends of the second semiconductor layer; wherein the second gate covers part of the second semiconductor layer; a fourth metal layer , set on the second semiconductor layer, and the fourth metal layer includes a second source electrode and a second drain electrode; because there is no gate between the second gate electrode and the second source electrode and/or the second drain electrode
  • the highly regulated gap area reduces the dark current of the photosensitive sensor, enhances the anti-noise capability of the device and the sensitivity of the device, thereby improving the accuracy of fingerprint identification.

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Abstract

本申请实施例公开了一种感光传感器、阵列基板及电子设备，该感光传感器包括第三金属层；所述第三金属层包括第二栅极；所述第二半导体层包括导电部，所述导电部位于所述第二半导体层的两端；第四金属层，设于所述第二半导体层上，所述第四金属层包括第二源极和第二漏极。

Description

感光传感器、阵列基板及电子设备 技术领域
本申请涉及显示技术领域，具体涉及一种感光传感器、阵列基板及电子设备。
 背景技术
光学指纹技术与显示面板相结合是目前主要的方向之一，它的原理是利用指纹的谷和脊反射到显示面板的传感区域内的光的强弱不同，从而将不同的光信号转换成电信号，通过芯片提取出来，形成关键的指纹图样，达到指纹识别的目的。
 技术问题
目前应用于显示面板中的感光传感器的抗噪能力和灵敏度较差，因此降低了指纹识别的准确性。
 技术解决方案
本申请实施例提供一种感光传感器、阵列基板及电子设备，可以增强感光传感器的抗噪能力和灵敏度，进而提高指纹识别的准确性。
本申请实施例提供一种感光传感器，其包括：
第三金属层，包括第二栅极；
第二绝缘层，设于所述第三金属层上；
第二半导体层，设于所述第二绝缘层上；所述第二半导体层包括导电部，所述导电部位于所述第二半导体层的两端；其中所述第二半导体层在设定平面上的正投影与所述第二栅极在所述设定平面上的正投影部分重叠；
第四金属层，设于所述第二半导体层上，所述第四金属层包括第二源极和第二漏极。
本申请实施例提供一种阵列基板，其包括：
基底，包括控制元件；
上述感光传感器，所述感光传感器的第二漏极与所述控制元件连接。
本申请实施例还提供一种电子设备，其包括上述阵列基板。
 有益效果
本申请实施例的感光传感器、阵列基板及电子设备，包括第三金属层包括第二栅极；第二绝缘层，设于所述第三金属层上；第二半导体层，设于所述第二绝缘层上；所述第二半导体层包括导电部，所述导电部位于所述第二半导体层的两端；其中所述第二栅极覆盖部分所述第二半导体层；第四金属层，设于所述第二半导体层上，所述第四金属层包括第二源极和第二漏极；由于第二栅极与第二源极和/或第二漏极之间存在没有栅极调控的间隙区域，从而减少感光传感器的暗电流、增强器件的抗噪能力和灵敏度，进而提高了指纹识别的准确性。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例提供的阵列基板的结构示意图。
图2为本申请一实施例提供的感光传感器的俯视图。
图3为本申请另一实施例提供的感光传感器的俯视图。
图4为本申请有一实施例提供的感光传感器的俯视图。
图5为图1所示的阵列基板的制备工艺流程图。
图6为本申请另一实施例提供的阵列基板的结构示意图。
图7为本申请又一实施例提供的阵列基板的结构示意图。
图8为本申请一实施例提供的显示面板的结构示意图。
图9为本申请一实施例提供的电子设备的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参阅图1，图1为本申请一实施例提供的阵列基板的结构示意图。
如图1所示，本实施例的阵列基板100包括基底10、第三金属层21、第二绝缘层22、第二半导体层23以及第四金属层24。
基底10包括控制元件T1；该控制元件T1也即为薄膜晶体管。在一实施方式中，基底10可包括：衬底基板11、第一半导体层14、第一绝缘层15、第一金属层16以及第二金属层18。此外该基底10还可包括遮光层12、缓冲层13、栅绝缘层17以及平坦层19中的至少一种。
衬底基板11可为玻璃基板或者柔性衬底。衬底基板11的材质包括玻璃、二氧化硅、聚乙烯、聚丙烯、聚苯乙烯、聚乳酸、聚对苯二甲酸乙二醇酯、聚酰亚胺或聚氨酯中的一种或多种。
遮光层12设于衬底基板11上，遮光层12的材料可为金属材料。
缓冲层13设于遮光层12上，所述缓冲层13的材料包括但不限于氮化硅或氧化硅。
第一半导体层14设于所述缓冲层13上；在一优选实施方式中，第一半导体层14可包括第一半导体部141。
第一绝缘层15设于所述第一半导体层14上；第一绝缘层15的材料可包括氮化硅、氧化硅以及有机光阻中的至少一种。
第一金属层16设于所述第一绝缘层15上；所述第一金属层16包括第一栅极161。第一金属层16的材料可包括铜、铝以及钛中的至少一种。
栅绝缘层17设于第一金属层16上，栅绝缘层17的材料可包括氮化硅、氧化硅以及有机光阻中的至少一种。
第二金属层18设于所述栅绝缘层17上，所述第二金属层18包括第一源极181和第一漏极182；所述第二金属层18的材料可与第一金属层16的材料相同。
平坦层19设于第二金属层18上，平坦层19的材料可与栅绝缘层17的材料相同。
此外阵列基板还包括感光传感器S，感光传感器S包括第二栅极211、第二半导体层23以及第二源极241和第二漏极242。
在一实施方式中，本实施例还提供一种感光传感器S，其包括：
第三金属层21设于所述平坦层19上；所述第三金属层21包括第二栅极211和第一金属部212。所述第三金属层21的材料可与第二金属层18的材料相同。
第二绝缘层22设于所述第三金属层21上；第二绝缘层22的材料可包括氮化硅、氧化硅、有机光阻中的至少一种。
第二半导体层23设于所述第二绝缘层22上；所述第二半导体层23包括导电部231，所述导电部231位于所述第二半导体层23的两端；如图1和图2所示，其中所述第二半导体层23在设定平面上的正投影与所述第二栅极211在所述设定平面上的正投影部分重叠，设定平面也即为水平面。也即从下至上，第二栅极211覆盖部分所述第二半导体层23。在一优选实施方式中，所述第二半导体层23的材料可为非晶硅，第一半导体层14的材料为多晶硅。由于非晶硅可以制作的比较厚，因此利于光的吸收，便于形成高性能的感光传感器，因此提高了指纹识别的准确性。为了进一步提高开口率，在一实施方式中，所述第二半导体层23可覆盖所述第一半导体部141。
第四金属层24设于所述第二半导体层23上，所述第四金属层24包括第二源极241和第二漏极242，所述第二漏极242与所述控制元件T1连接，具体与控制元件T1的漏极（也即第一漏极182）连接。在一实施方式中，为了降低阻抗，所述第二漏极242可通过所述第一金属部212与所述第一漏极182连接。在一优选实施方式中，所述第二源极241可覆盖部分所述第二栅极211。
如图2所示，由于感光传感器（非晶硅薄膜晶体管）的栅极未全部覆盖，因此使得第二栅极211与第二源极241之间存在没有栅极调控的间隙区域101，该间隙区域101用于减少感光传感器的暗电流、增强器件的抗噪能力，并且可以通过调控栅极电压，以增强器件的灵敏度。该间隙区域101的位置具体不作限定。
在一优选实施方式中，为了进一步提高感光传感器的灵敏度，如图3所示，所述第二源极241包括第一子连接部51和第二子连接部52，所述第二子连接部52的形状为弧形，所述第一子连接部51的一端与所述第二子连接部52连接；
所述第二漏极242的设定端部53的形状为弧形，且所述第二子连接部52的形状和所述第二漏极242的设定端部的形状匹配；其中所述设定端部为靠近所述第二源极241一侧的端部。
所述第二栅极211的设定端部54的形状也为弧形，所述第二栅极211在所述基底10上的正投影的面积大于所述第二漏极242在所述基底10上的正投影的面积；所述第二子连接部52包覆在所述第二栅极211的设定端部54外；也即所述第二子连接部52设于所述第二栅极211的设定端部54外。
在另一实施方式中，为了进一步提高感光传感器的灵敏度，如图4所示，所述第二源极241包括第一公共端61、第一主干部62和多个第一分支部63；所述第一主干部62分别与所述第一分支部63的一端以及所述第一公共端61连接，所述第一公共端61和所述第一分支部63均沿第一方向排列；所述第一主干部62沿第二方向排列；其中第一方向与所述第二方向相交；
所述第二漏极242包括第二公共端64、第二主干部65和多个第二分支部66；所述第二主干部65分别与所述第二公共端64以及所述第二分支部66的一端连接，所述第二公共端64和所述第二分支部66均沿第一方向排列；所述第二主干部65沿第二方向排列；且所述第一分支部63与所述第二分支部65交错设置；
所述第二栅极211覆盖所述第二主干部65、所述第二分支部66以及部分所述第二公共端64。在一实施方式中，第二栅极211的形状与第二漏极242的形状匹配，第二栅极211可包括第三主干部和多个第三分支部，第三分支部的一端与所述第三主干部连接。
在一实施方式中，返回图1，为了进一步提高阵列基板的集成度，减小整体厚度，所述第三金属层21还包括第一触控电极213。
在一实施方式中，为了进一步提高阵列基板的集成度，减小整体厚度，所述阵列基板100还可包括：
第一导电层30设于所述第二绝缘层22上；所述第一导电层30包括第二触控电极31，所述第一触控电极213的位置与所述第二触控电极31的位置对应。在一实施方式中，所述第一触控电极213和所述第二触控电极31均为网格状，所述第二触控电极31与所述第一触控电极213连接。可以理解的，第一触控电极213和第二触控电极31的结构不限于此。在一实施方式中，第一导电层30的材料包括但不限于氧化铟锡。
在一实施方式中，为了简化制程工艺，降低生产成本，所述基底10还包括开关元件T2，所述开关元件包括第三漏极183。
在一实施方式中，为了简化制程工艺，降低生产成本，所述阵列基板100还包括第二导电层40，第二导电层40设于所述第一导电层30上；所述第二导电层40包括像素电极41；所述像素电极41与所述开关元件T2的漏极183连接。第二导电层40的材料可与第一导电层30的材料相同。
在一实施方式中，为了简化制程工艺，降低生产成本，第一导电层30还包括第一极板32，第二导电层40还包括第二极板42，其中第二极板42与第一极板32的位置对应，以形成像素电容。
其中在一优选实施方式中，第三漏极183位于第二金属层18。也即开关元件T2的漏极和源极分别与控制元件T1的源极和漏极同层制作，此外开关元件T2的栅极可与控制元件T1的栅极同层制作，开关元件T2的半导体层也可与控制元件T1的半导体层同层制作。
如图5所示，在一实施方式中，本实施例的阵列基板的制作方法包括：
S101、在衬底基板11上制备遮光层12；
例如，采用曝光蚀刻等方式对遮光层12进行图案化，以使遮光层12遮挡第一半导体部141。
S102、在遮光层12上依次制备缓冲层13和第一半导体层14。
例如，第一半导体层14的材料为多晶硅，对第一半导体层14进行曝光、蚀刻，分别形成第一半导体部141和第二半导体部142，并分别对第一半导体部141和第二半导体部142进行P离子掺杂形成N+，使第一半导体部141和第二半导体部142易于欧姆接触。
S103、在第一半导体部和第二半导体部上依次沉积第一绝缘层15以及第一金属层16。
例如，对第一金属层16进行图案化处理形成第一栅极161和第三栅极162。然后采用自对准工艺分别对第一半导体部141和第二半导体部142进行N-离子注入。
S104、在第一金属层16上沉积一层栅绝缘层17。
例如，在一实施方式中，栅绝缘层17可为SiNx/SiOx的叠层结构，在一实施方式中，可采用快速热退火进行氢化和活化，然后对该栅绝缘层17进行曝光、蚀刻，形成源极和漏极的连接孔，该连接孔与第一半导体部141或者第二半导体部142连接。
S105、在连接孔内以及栅绝缘层17沉积第二金属层。
例如，对第二金属层18进行图案化处理形成第一源极181和第一漏极182、以及第三漏极183和第三源极184。
S106、在第二金属层上制备平坦层19。
例如，平坦层上设置有连接孔，第一金属部212用于通过该连接孔与第一漏极182连接。
S107、在平坦层19沉积第三金属层21。
例如，对所述第三金属层21进行图案化处理形成第二栅极211、第一金属部212以及第一触控电极213。
S108、在第三金属层21沉积第二绝缘层22，并在第二绝缘层22上制作一金属部212与第二漏极242之间的连接孔、以及与第一触控电极213与第二触控电极31之间的连接孔。
S109、在第二绝缘层22上沉积第二半导体层23。
第二半导体层23的材料为a-Si，对其进行处理表面形成N+-a-Si，然后对其进行图形化处理。
S110、在第二半导体层23上制作第四金属层24，对第四金属层24进行图案化处理形成第二源极241和第二漏极242。
S111、在第二绝缘层22上沉积第一导电层30，对其进行图案化处理形成第二触控电极31和第一极板32。
S112、在第一导电层30上依次沉积第三绝缘层25和第二导电层40。
例如，第三绝缘层25上设置有连接孔，该连接孔用于连接像素电极41和第三漏极183。
对第二导电层40进行图案化处理形成像素电极41和第二极板42。
由于在控制元件T1上制作感光传感器S，因此可以减少与感光传感器连接的相关金属走线，从而提高了开口率；此外由于非晶硅的感光层的吸光系数大大优于多晶硅，从而增大感光传感器的灵敏度。
请参阅图6，图6为本申请另一实施例提供的阵列基板的结构示意图。
如图6所示，本实施例的感光传感器与上一实施例的感光传感器的区别在于：本实施例的第二栅极211与所述第二源极241连接。
由于所述第二栅极211与所述第二源极241连接，因此进一步降低阻抗，进而提高了感光传感器的灵敏度。
本申请实施例还提供一种阵列基板，其包括上述感光传感器。
请参阅图7，图7为本申请又一实施例提供的阵列基板的结构示意图。
本实施例的感光传感器与第一实施例的感光传感器的区别在于：本实施例中的第二栅极211的面积较大。
如图7所示，为了简化制程工艺，降低生产成本，所述第二漏极242覆盖部分所述第二栅极211。也即第二栅极211在衬底基板11上的正投影的面积大于所述第二漏极242在衬底基板11上的正投影的面积，此外第二栅极211在衬底基板11上的正投影还与第二半导体层23在衬底基板11上的正投影部分重叠。此外所述第二栅极211还覆盖部分所述第一漏极182，也即第二栅极还作为第一金属部使用。
本申请实施例还提供一种阵列基板，其包括上述感光传感器。
可以理解的，图2至图7仅示出其中一种实施方式的结构示意图，但是并不能对本发明构成限定。上述实施例中的阵列基板包括了上述感光传感器的全部技术方案，因此能实现上述全部技术效果，此处不再赘述。
如图8所示，本实施例还提供一种显示面板200，其包括上述任意一种阵列基板100，此外该显示面板200还可以包括第二基板201，第二基板201与阵列基板100相对设置。该显示面板200可为液晶显示面板。阵列基板100和第二基板201之间还设置有液晶层（图中未示出）。此外阵列基板100和第二基板201之间还可设置有框胶，用于贴合阵列基板100和第二基板201。在一实施方式中，第二基板201可包括第二衬底基板71和第二电极72。在另一实施方式中，第二基板201可为彩膜基板，也即第二基板201还可包括彩膜层。可以理解的，第二基板201的结构不限于此。
请参阅图9，图9为本申请实施例提供的电子设备的结构示意图。
该电子设备300可以包括显示面板200、控制电路80以及壳体90。需要说明的是，图9所示的电子设备300并不限于以上内容，其还可以包括其他器件，比如还可以包括摄像头、天线结构、指纹解锁模块等。
其中，显示面板200设置于壳体90上。
在一些实施例中，显示面板200可以固定到壳体90上，显示面板200和壳体90形成密闭空间，以容纳控制电路80等器件。
在一些实施例中，壳体90可以为由柔性材料制成，比如为塑胶壳体或者硅胶壳体等。
其中，该控制电路80安装在壳体90中，该控制电路80可以为电子设备300的主板，控制电路80上可以集成有电池、天线结构、麦克风、扬声器、耳机接口、通用串行总线接口、摄像头、距离传感器、环境光传感器、受话器以及处理器等功能组件中的一个、两个或多个。
其中，该显示面板200安装在壳体90中，同时，该显示面板200电连接至控制电路80上，以形成电子设备300的显示面。该显示面板200可以包括显示区域和非显示区域。该显示区域可以用来显示电子设备300的画面或者供用户进行触摸操控等。该非显示区域可用于设置各种功能组件。
所述电子设备包括但不限定于手机、平板电脑、计算机显示器、游戏机、电视机、显示屏幕、可穿戴设备及其他具有显示功能的生活电器或家用电器等。
本申请实施例的感光传感器、阵列基板及电子设备，包括第三金属层包括第二栅极；第二绝缘层，设于所述第三金属层上；第二半导体层，设于所述第二绝缘层上；所述第二半导体层包括导电部，所述导电部位于所述第二半导体层的两端；其中所述第二栅极覆盖部分所述第二半导体层；第四金属层，设于所述第二半导体层上，所述第四金属层包括第二源极和第二漏极；由于第二栅极与第二源极和/或第二漏极之间存在没有栅极调控的间隙区域，从而减少感光传感器的暗电流、增强了器件的抗噪能力和器件的灵敏度，进而提高了指纹识别的准确性。
以上对本申请实施例提供的感光传感器、阵列基板及电子设备进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种感光传感器，其包括：
    第三金属层，包括第二栅极；
    第二绝缘层，设于所述第三金属层上；
    第二半导体层，设于所述第二绝缘层上；所述第二半导体层包括导电部，所述导电部位于所述第二半导体层的两端；其中所述第二半导体层在设定平面上的正投影与所述第二栅极在所述设定平面上的正投影部分重叠；
    第四金属层，设于所述第二半导体层上，所述第四金属层包括第二源极和第二漏极。
  2. 根据权利要求1所述的感光传感器，其中
    所述第二源极覆盖部分所述第二栅极。
  3. 根据权利要求2所述的感光传感器，其中
    所述第二栅极与所述第二源极连接。
  4. 根据权利要求2所述的感光传感器，其中
    所述第二漏极在所述设定平面上的正投影与所述第二栅极在所述设定平面上的正投影不重叠。
  5. 根据权利要求1所述的感光传感器，其中
    所述第二漏极覆盖部分所述第二栅极。
  6. 根据权利要求5所述的感光传感器，其中
    所述第二源极在所述设定平面上的正投影与所述第二栅极在所述设定平面上的正投影不重叠。
  7. 根据权利要求1所述的感光传感器，其中
    所述第二源极包括第一子连接部和第二子连接部，所述第二子连接部的形状为弧形，所述第一子连接部的一端与所述第二子连接部连接；
    所述第二漏极的设定端部的形状为弧形，且所述第二子连接部的形状和所述第二漏极的设定端部的形状匹配；其中所述设定端部为靠近所述第二源极一侧的端部；
    所述第二栅极的设定端部的形状也为弧形，所述第二栅极在所述基底上的正投影的面积大于所述第二漏极在所述基底上的正投影的面积；所述第二子连接部包覆在所述第二栅极的设定端部外。
  8. 根据权利要求1所述的感光传感器，其中
    所述第二源极包括第一公共端、第一主干部和多个第一分支部；所述第一主干部分别与所述第一公共端和所述第一分支部的一端连接，所述第一公共端和所述第一分支部均沿第一方向排列；所述第一主干部沿第二方向排列；
    所述第二漏极包括第二公共端、第二主干部和多个第二分支部；所述第二主干部分别与所述第二公共端以及所述第二分支部的一端连接，所述第二公共端和所述第二分支部均沿所述第一方向排列；所述第二主干部沿所述第二方向排列；且所述第一分支部与所述第二分支部交错设置；
    所述第二栅极覆盖所述第二主干部、所述第二分支部以及部分所述第二公共端，所述第一方向和所述第二方向相交。
  9. 一种阵列基板，其包括：
    基底，包括控制元件；
    感光传感器，所述感光传感器包括：
    第三金属层，包括第二栅极；
    第二绝缘层，设于所述第三金属层上；
    第二半导体层，设于所述第二绝缘层上；所述第二半导体层包括导电部，所述导电部位于所述第二半导体层的两端；其中所述第二半导体层在设定平面上的正投影与所述第二栅极在所述设定平面上的正投影部分重叠；
    第四金属层，设于所述第二半导体层上，所述第四金属层包括第二源极和第二漏极；所述感光传感器的第二漏极与所述控制元件连接。
  10. 根据权利要求9所述的阵列基板，其中
    所述控制元件包括第一漏极；
    所述第三金属层还包括第一金属部；所述第二漏极通过所述第一金属部与所述第一漏极连接。
  11. 根据权利要求9所述的阵列基板，其中
    所述第二半导体层覆盖所述控制元件的半导体层。
  12. 根据权利要求9所述的阵列基板，其中
    所述控制元件的半导体层的材料为多晶硅，所述第二半导体层的材料为非晶硅。
  13. 根据权利要求9所述的阵列基板，其中
    所述第三金属层还包括第一触控电极；
    所述阵列基板还包括：
    第一导电层，设于所述第二绝缘层上；所述第一导电层包括第二触控电极，所述第二触控电极的位置与所述第一触控电极的位置对应。
  14. 根据权利要求13所述的阵列基板，其中
    所述基底还包括开关元件；
    所述阵列基板还包括：
    第二导电层，设于所述第一导电层上；所述第二导电层包括像素电极；所述像素电极与所述开关元件的漏极连接。
  15. 根据权利要求14所述的阵列基板，其中
    所述第一导电层还包括第一极板；
    所述第二导电层还包括第二极板，所述第一极板的位置与所述第二极板的位置对应。
  16. 根据权利要求9所述的阵列基板，其中
    所述第二源极覆盖部分所述第二栅极。
  17. 根据权利要求9所述的阵列基板，其中
    所述第二栅极与所述第二源极连接。
  18. 根据权利要求9所述的阵列基板，其中
    所述第二漏极覆盖部分所述第二栅极。
  19. 根据权利要求18所述的阵列基板，其中
    所述第二源极在所述设定平面上的正投影与所述第二栅极在所述设定平面上的正投影不重叠。
  20. 一种电子设备，其包括如权利要求9所述的阵列基板。
PCT/CN2020/109244 2020-07-21 2020-08-14 感光传感器、阵列基板及电子设备 WO2022016637A1 (zh)

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